LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Rev. 1.5 Rev. 1.6 Rev. 1.7 Description Initial Issue Added ISB Spec. Revised ICC1/ISB1/VDR/IDR Spec. Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Revised PACKAGE OUTLINE DIMENSION in page 11 Revised VIH to 0.7*Vcc Revised ORDERING INFORMATION in page 11 Deleted E grade Added SL grade Revised VIH in page 3 Revised TEST CONDITION of VIH in page 4 Revised PACKAGE OUTLINE DIMENSION in page 10 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Issue Date Jan.10.2008 Feb.1.2008 Mar.2.2009 May.7.2010 Aug.25.2010 Apr.25.2011 May.13.2011 Jul.27.2011 LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 FEATURES GENERAL DESCRIPTION Fast access time : 55/70ns Low power consumption: Operating current : 30/20mA (TYP.) Standby current : 6A (TYP.) LL-version 3A (TYP.) SL-version Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 1.5V (MIN.) Green package available Package : 44-pin 400 mil TSOP-II 48-ball 6mm x 8mm TFBGA The LY62W10248 is a 8,388,608-bit low power CMOS static random access memory organized as 1,048,576 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY62W10248 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY62W10248 operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY62W10248 LY62W10248(I) Operating Temperature 0 ~ 70 -40 ~ 85 Vcc Range Speed 2.7 ~ 5.5V 2.7 ~ 5.5V 55/70ns 55/70ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A19 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# CE2 WE# OE# CONTROL CIRCUIT Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 6A(LL)/3A(SL) 30/20mA 6A(LL)/3A(SL) 30/20mA 1024Kx8 MEMORY ARRAY SYMBOL DESCRIPTION A0 - A19 Address Inputs DQ0 - DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection COLUMN I/O Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 PIN CONFIGURATION 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 CE2 CE# 6 39 A8 NC 7 38 NC NC 8 37 NC 36 DQ7 35 DQ6 34 Vss 33 Vcc 32 DQ5 31 DQ4 30 DQ0 9 DQ1 10 Vcc 11 Vss 12 DQ2 13 DQ3 14 NC 15 LY62W10248 A4 A NC OE# A0 A1 A2 CE2 B NC NC A3 A4 CE# NC NC C DQ0 NC A5 A6 NC DQ4 NC 16 29 NC D Vss DQ1 A17 A7 WE# 17 28 A9 E Vcc DQ2 NC A16 DQ6 Vss A19 18 27 A10 A18 19 26 A11 F DQ3 NC A14 A15 A17 20 25 A12 G NC NC A12 A13 WE# NC A16 21 24 A13 H A18 A8 A9 A10 A11 A19 A15 22 23 A14 1 2 3 4 TFBGA 5 6 TSOP-II Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 DQ5 Vcc NC DQ7 LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V W mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby CE# CE2 OE# WE# H X X X I/O OPERATION High-Z SUPPLY CURRENT ISB,ISB1 X L X X High-Z ISB,ISB1 Output Disable L H H H High-Z ICC,ICC1 Read L H L H DOUT ICC,ICC1 L H X L DIN ICC,ICC1 Write Note: H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Voltage SYMBOL VCC Input High Voltage VIH Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIL ILI *1 VCC = 2.7 ~ 3.6V VCC = 4.5 ~ 5.5V *2 ILO VOH VOL ICC Average Operating Power supply Current ICC1 ISB Standby Power Supply Current TEST CONDITION ISB1 VCC VIN VSS VCC VOUT VSS Output Disabled IOH = -1mA IOL = 2mA Cycle time = Min. - 55 CE# = VIL and CE2 = VIH II/O = 0mA - 70 Other pins at VIL or VIH Cycle time = 1 s CE#0.2V and CE2VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL Other pins at VIL or VIH LL LLI CE# VCC-0.2V *5 25 SL or CE20.2V *5 SLI Other pins at 0.2V 40 or VCC-0.2V SL SLI MIN. 2.7 2.2 2.4 - 0.2 -1 TYP. 3.0 - *4 MAX. 5.5 VCC+0.5 VCC+0.5 0.6 1 UNIT V V V V A -1 - 1 A 2.4 - 2.7 - 0.4 V V - 30 60 mA - 20 50 mA - 4 12 mA - 0.15 2 mA - 6 6 3 3 3 3 30 50 10 10 20 25 A A A A A A Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25 CAPACITANCE (TA = 25, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 UNIT pF pF LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* LY62W10248-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 - LY62W10248-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 - UNIT LY62W10248-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 LY62W10248-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 UNIT *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. VCC for Data Retention VDR 1.5 CE# VCC - 0.2V or CE20.2V LL LLI VCC = 1.5V 25 SL Data Retention Current IDR CE# VCC-0.2V or CE20.2V SLI 40 Other pins at 0.2V or VCC-0.2V SL SLI Chip Disable to Data See Data Retention tCDR 0 Retention Time Waveforms (below) Recovery Time tR tRC* tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tCDR CE2 tR CE2 0.2V VIL VIL Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 TYP. 4 4 3 3 3 3 MAX. 5.5 30 50 10 10 20 25 UNIT V A A A A A A - - ns - - ns LY62W10248 1024K X 8 BIT LOW POWER CMOS SRAM Rev. 1.7 PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP-II Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 0 3 6 DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 LY62W10248 Rev. 1.7 1024K X 8 BIT LOW POWER CMOS SRAM 48-ball 6mm x 8mm TFBGA Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 LY62W10248 Rev. 1.7 1024K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION LY62W10248 U V - WW XX Y Z Z : Packing Type Blank : Tube or Tray Tray : 44-pin 400 mil TSOP-II 48-ball 6 mm x 8 mm TFBGA T : Tape Reel Y : Temperature Range Blank : (Commercial) 0C ~ 70C I : (Industrial) -40C ~ +85C XX : Power Type LL : Ultra Low Power SL : Special Ultra Low Power WW : Access Time(Speed) V : Lead Information L : Green Package U : Package Type M : 44-pin 400 mil TSOP-II G : 48-ball 6 mm x 8 mm TFBGA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 LY62W10248 Rev. 1.7 1024K X 8 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12