DR-11525DX-404 - Data Device Corporation

DR-11525

16-BIT HIGH FREQUENCY HYBRID

DIGITAL-TO-RESOLVER D/R CONVERTER

DESCRIPTION

The DR-11525 is a versatile multiply-

ing digital-to-resolver converter. The

digital input represents an angle, and

the output is resolver type, sin/cos.

The reference input will accept any

waveform, even a sawtooth for CRT

drive. Because the reference is dc-

coupled to the output, the DR-11525

can be used as: a digital-to-resolver

converter using a sinusoidal refer-

ence as an input; a digital-to-sin/cos

dc converter using a dc reference; or

a polar-to-rectangular converter using

a reference input proportional to the

radius vector; or a rotating cartwheel

sweep generator for PPI displays

using a sawtooth reference.

Packaged in a 36-pin DDIP, the DR-

11525 is a complete D/R conver ter in

one hybrid module. Hybrid technology

results in low weight, low power con-

sumption, very high reliability, and a

wide operating temperature range. The

DR-11525 circuit design allows f or high-

er accuracy and reduces the output

scale factor variation so that the output

can drive displays directly. The output

line-to-ground voltage can be scaled by

external resistors. The DR-11525 also

includes high ac and dc common mode

rejection at the reference input

APPLICATIONS

Because of its high reliability, small size

and low power consumption, the hybrid

DR-11525 is ideal f or the most stringent

and severe industrial and military

ground or a vionics applications.All units

are available with MIL-PRF-38534 pro-

cessing as a standard option.

Among the many possible applica-

tions are computer-based systems in

which digital angle information is

processed, such as synchro/resolver

simulators, flight trainers, flight instru-

mentation, fire control systems, IR,

radar and na vigation systems.In addi-

tion, the DR-11525 is ideal for motor

and robotic control test systems.

FEATURES

•

Accuracy Up to 1 Minute

•

Operational Up to 10 kHz

•

2 Vrms, 6.81 Vrms, 11.8 V

,or

Scalable Resolver Outputs

•

2 mA rms Output

•

16-Bit Resolution

•

8-Bit/2-Byte Double Buffered

Transparent Latches

•

DC-Coupled Reference Accepts

Any W avef orm

•

High-Rel CMOS D/R Chip

•

No +5 V Supply Required

TEST POINT - R

D/R CONVERTER

HIGH ACCURACY

LOW SCALE FACTOR

VARIATION

RESOLVER SCALING

OUTPUT AMPLIFIERS

TRANSPARENT

LATCH

TRANSPARENT

LATCH

REFERENCE

CONDITIONER

DIGITAL INPUT

BITS 1-8 BITS 9-16

49.92 k

49.92 k36.71 k

36.71 k13.37 k

13.37 k

26 V

REFERENCE INPUTS

LA LM LL

+C S1

S426 V

4.4 V

DIFFERENTIAL

(NOTE 1)

SINGLE-ENDED

(NOTE 2)

ADJUSTABLE

(NOTE 3)

BITS 1-16

RESOLVER

OUTPUTS

NOTES: 1) 26 VRMS REFERENCE IN = 11.8 VL-L DIFFERENTIAL OUTPUT

2) 26 VRMS REFERENCE IN = 6.8 VRMS SINGLE-ENDED OUTPUT

3) 4.4 VRMS REFERENCE IN = 2 VRMS SINGLE-ENDED OUTPUT

FIGURE 2. LL, LM, LA TIMING DIAGRAM

INTRODUCTION

As shown in FIGURE 1, the signal con v ersion in the DR-11525 is

perf ormed b y a high-accuracy digital-to-resolv er conv erter whose

sin and cos outputs have a low scale factor variation as a func-

tion of the digital input angle.This resolver output is amplified by

scaling amplifiers f or resolver output.The output line currents can

be 2 mA rms max, which is sufficient for driving R/D conver ters,

solid-state control transformers, and displays. Output power

amplifiers will be required, howe v er , f or driving electromechanical

devices such as synchros and resolvers.

The ref erence conditioner has a differential input with high ac and

dc common mode rejection, so that a reference isolation trans-

for mer will seldom be required.There are three sets of reference

inputs which provide three different input/output ratios. The RH-

RL input provides a 0.45 ratio between the reference input and

the signal output and is designed to provide 11.8 VL-Ldifferential

output for a 26 Vrms reference input. The RH2-RL2 input pro-

vides a 0.52 ratio between the reference input and the signal out-

put and is designed to provide a 6.81 Vrms single-ended output

for a 26 Vrms reference input. The RH3-RL3 input provides a

0.91 ratio between the reference input and the signal output and

is designed to provide a 2 Vrms single-ended output for a 4.4

Vrms reference input. Series resistors can be added to accom-

modate higher reference levels or to reduce the output level.

The reference conditioner output -R is intended for test purpos-

es. For a 26 Vrms nominal input to RH, RL, -R should be 5.9

Vrms.

The timing relationship of LL, LM, and LA is shown in FIGURE 2

as a design reference.

OUTPUT SCALING AND REF. LEVEL ADJUSTMENT

The DR-11525 operates like a multiplying D/A converter in that

the voltage of each output line is directly proportional to the ref-

erence voltage. Reference FIGURE 3.

The magnitude of the resistors, R', in ohms is calculated as fol-

lows:

For RH-RL:VOUTL-L45.38k

VIN 100k + R'

,,,

DATA 1-16 BITS

200 ns MIN

LATCHED

TRANSPARENT

100 ns MIN50 ns MIN

Notes: 1) Maximum reference input RH-RL = 26 V +10%; RH2-RL2 = 26 V +10%;

RH3-RL3 = 16.4 V.

2) Minumum voltage output (when using scalable reference input) is 1 V

differential or 0.5 V single ended.

3) Differential is line-to-line (L-L); single ended is line-to-ground (L-gnd).

TABLE 1. DR-11525 SPECIFICATIONS

Apply over temperature range, power supply range, reference voltage and

frequency range, and 10% harmonic distor tion in the reference.

PARAMETER UNIT VALUE

16BitsRESOLUTION

Natural binary angle, parallel positive

logic CMOS and TTL compatible.

Inputs are CMOS transient protected.

Logic 0 = 0 to +1 V

Logic 1 = +2.2 V to +5 V

20 max to GND (bits 1-16)

20 max to +5 V (LL, LM, LA)

See Timing Diagram (FIGURE 2.).

µA

DIGITAL INPUT

Logic Type

Load Current

REFERENCE INPUT

Type

Frequency Range

Standard Input

Voltage (Note 1)

RH3-RL3

RH2-RL2

RH-RL

Input Impedance

Single-Ended:RH-gnd

Differential: RH to RL

k ohm

Resolver

2 max

(Tracks Reference Input Voltage)

11.8 nominal

6.81 (single ended)

2.0 nominal (single ended)

±0.5 max

±0.1 max

±15 max Var ies with input angle.

mA rms

VrmsL-L

Vrms

ANALOG OUTPUT

Type

Output Current

Standard Output

Voltage (Note 2)

RH-RL

RH2-RL2

RH3-RL3

Transf orm. Ratio Tol.

Scale Factor Variation

DC Offset

Single ended

mAmax

-15 ±5%

-18 V

35+ load current

-55 to +125

0 to +70

-55 to +135

°C

Operation

-1 Option

-3 Option

Storage

Type

Size

Weight in.(mm)

oz (g)

36 pin DDIP

0.78 x 1.9 x 0.21 (19.7 x 48.1 x 5.3)

0.85 (24)

±4 to ±1 min. (See Ordering info.)

1 minute part: 1 min up to 1 kHz, 1.5 min

for 1 to 5 kHz, and 3 min for 5 to 10 kHz

(guaranteed by design - tested at 5 kHz)

±1 max

Less than 20 for any digital step change

Minutes

LSB

µsec

Three differential solid-state inputs: two

for standard 26 V, one programmable.

DC to 10 k

4.4

100 ±0.5%

200 ±0.5%

+15 ±5%

+18 V

35+ load current

POWER SUPPLIES

Voltage

Current or Impedance

Max voltage without damage

TEMPERATURE RANGES (CASE)

PHYSICAL CHARACTERISTICS

ACCURACY and

Output Accuracy

Differential Linearity

Output Setting Time

DYNAMICS

*For RH2-RL2:VOUTL-L45.38k

VIN 86.63k + R'

*For RH3-RL3:VOUTL-L45.38k

VIN 49.92k + R'

*Note: For RH2, RL2 and RH3, RL3:VOUT(single-ended) = 1/2 VOUTL-L.

OUTPUT PHASING AND OUTPUT SCALE FACTOR

The analog output signals have the following phasing:

Resolver output:

S3—S1 = (RH - RL)Ao(1 + A(θ)) sin θ

S2—S4 = (RH - RL)Ao(1 + A(θ)) cos θ

The output amplifiers simultaneously track reference voltage

fluctuations because they are proportional to (RH - RL). The

transformation ratio Aois 11.8/26 for 11.8 VrmsL-Loutput. The

maximum v ariation in Aofrom all causes is ± 0.2%.The term A(θ)

represents the variation of the amplitude with the digital signal

input angle. A(θ), which is called the scale factor variation, is a

S3 S3

S1 S1

DR-11525 36

S2 S2

S4 S4

FIGURE 4. DIFFERENTIAL RESOLVER OUTPUT

35 (+SIN)

S3 S3

DR-11525 36 (+COS)

S2 S2

GND

FIGURE 5. SINGLE-ENDED RESOLVER OUTPUT

TABLE 2. PIN CONNECTION TABLE

PINPINNAME NAMENAME

+15V

GND

-15V

RH2 (6.81V)

RL2 (6.81V)

-R

RL (11.8V)

RL3 (2V)

RH (11.8V)

RH3 (2V)

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 (MSB)

Bit 15

Bit 16 (LSB)

S4 (-COS)

S1 (-SIN)

S3 (+SIN)

S2 (+COS)

Notes:

1. -R (Pin 7) can be used for test purposes to detect whether a reference signal

is present. See block diagram.

2. Functions LL, LA, and LM may be left unconnected when not used.

3. Exter nal scaling resistor pin 11 RH3 output pins (31, 32, 35, 36).

4. RH and RL (pins 10, 8) 26 V reference with differential outputs on pins 35, 36,

32, 31.

5. RH2 and RL2 (pins 5, 6) 26 V reference with single-ended output on pins 35,

36.

6. RH3 and RL3 (pins 11, 9) 4.4 V reference with single-ended outputs on pins

35, 36.

FIGURE 3. REFERENCE LEVEL ADJUSTMENT

49.92k

49.92k36.71k

36.71k13.37k

13.37k

REFERENCE

INPUTS

V (RH-RL)

V (RH2-RL2)

V (RH3-RL3)

8.703k

45.38k

VOUT L-L

R′

smooth function of (θ) without discontinuities and is less than

±0.05% for all values of (θ). The total maximum variation in

Ao[1 + A(θ)] is therefore ± 0.25%.

Because the amplitude f actor (RH - RL)Ao(1 + A(θ)) varies simul-

taneously on all output lines, it will not be a source of error when

the DR-11525 is to drive a ratiometric system such as a synchro

or resolver. However, if the outputs are used independently, as in

x-y plotters, the amplitude variations must be tak en into account.

ORDERING INFORMATION

DR-11525D X-X X X Accuracy:

3 = ±4 minutes

4 = ±2 minutes

5 = ±1 minute*

Reliability:

0 = Standard DDC procedures

1 = Fully Compliant with MIL-PRF-38534

2 = Screened to MIL-PRF-38534 but

without QCI testing

3 = Fully Compliant with MIL-PRF-38534

+ PIND Testing

4 = Fully Compliant with MIL-PRF-38534

+ Solder Dip

5 = Fully Compliant with MIL-PRF-38534

+ PIND Testing + Solder Dip

6 = Screened to MIL-PRF-38534 + PIND

Testing but without QCI Testing

7 = Screened to MIL-PRF-38534 + Solder

Dip but without QCI Testing

8 = Screened to MIL-PRF-38534 + PIND

Testing + Solder Dip but without QCI

Testing

Operating T emperature Range:

1 = -55 to +125°C (Case)

3 = 0 to +70°C (Case)

4 = -55 to +125°C (Case) + Variables Data

8 = 0 to +70°C (Case) + Variables Data

Options:

X = NONE

Package:

D = DIP Package

* Consult factory for availability of ±1 minute par ts.

A-09/96-2M PRINTED IN THE U.S.A.

The information provided in this data sheet is believed to be accurate; however, no responsibility

is assumed by Data Device Cor poration for its use, and no license or rights

are granted by implication or otherwise in connection therewith.

Specifications are subject to change without notice.

Notes:

1. Dimensions shown are in inches (millimeters).

2. Lead identification numbers are for referenced only.

3. Lead cluster shall be centered within ±0.005 of outline dimensions. Lead spac-

ing dimensions apply only at seating plane.

4. Pin mater ial meets solderability requirements of MIL-STD-202E, Method 208C.

FIGURE 6. DR-11525 MECHANICAL OUTLINE

36 PIN DDIP (CERAMIC)

0.210 MAX

(5.33)

0.250 MIN

(6.35)

0.018 ±0.002 DIA TYP

(0.46 ±0.05)

17 EQ. SP. @ 0.100 = 1.700

TOL NONCUM

(@ 2.54 = 43.18)

1.900 MAX

(48.26)

0.800

MAX

(20.32)

0.010 TYP

(0.25)

SIDE VIEW

BOTTOM VIEW

0.100 TYP

(2.54)

0.600

(15.24)

PIN NUMBERS FOR

REFERENCE ONLY

ILC DATA DEVICE CORPORATION

REGISTERED TO ISO 9001

FILE NO. A5976

105 Wilbur Place, Bohemia, New Yor k 11716-2482

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