Ss = =a" CYPRESS SRECININA SY fax id: 1106 CY7C1326 128K x 18 Synchronous-Pipelined Cache RAM Features * * . e . . . . * * Low (1.65 mW) standby power (f=0, L version) Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states Fully registered inputs and outputs for pipelined operation 128K x 18 common I/O architecture Single 3.3V power supply Fast clock-to-output times 3.5 ns (for 166-MHz device) 4.0 ns (for 133-MHz device} 4.5 ns (for 117-MHz device) 5.5 ns (for 100-MHz device) User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100-pin TQFP pinout ZZ Sleep Mode option and Stop Clock option Logic Block Diagram CLK BURST ADV COUNTER ADSC ADSP ADDRESS Aneo REGISTER Gw BW D_ ENABLE CE REGISTER CLK SLEEP CONTROL Intel and Pentium are trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation + 3901 North First Street + Functional Description The CY7C1326 is a 3.3V 128K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max- imum access delay from the clock rise is 3.5 ns (166-MHz device). A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. The GY7C1326 supports either the interleaved burst se- quence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the processor address strobe (ADSP) or the controller address strobe (ADSC) at clock rise. Address advancement through the burst sequence is con- trolled by the ADV input. Byte write operations are qualified with the two Byte Write Se- lect (BW)-1)) inputs. A Global Write Enable (GW) overrides the byte write inputs and writes data to both bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE,, CE, CE3) and an asyn- chrenous output enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. 128KX18 MEMORY ARRAY INPUT REGISTERS CLK CLK OUTPUT. REGISTERS 408-943-2600 Auaust 24, 1998 SanJose + GA 95134 +Se <vpress PSELIANNASY CY7C1326 Pin Configuration 100-Lead TQFP we LL B I> 2 O my ou =| wld | is erbde CREM SSIEEMEES 22 NOOR OOHOHOOUHOOUR OOOO SCoOwor-uont IOAN r oOgorwnotanaAr So Oooraoooroaoanrnwndwononwmwwon wow wo NCC 1 80 Ajo NCC 2 738 NC NCD3 78 NC Vppq i 4 Tim Vopa Vgg 5 7614 Veg NCC6 75 NC Ncc7 74/2 DPy 7 DQ,-48 73) Da, Da,-] 9 72/9 DQ, Ves S| 10 71 Veg Vppe S 14 70 Fo Vopa DQ,) = 12 694 DO, DQ,,-4 13 68 DQ, NCC 14 67) Veg Vpp 15 66 9) NC BYTEO NCO 416 65 V, BYTE1 DD DQ, 18 63 [A DQ, DQ,,-7 19 62 A DQ, Vppq 20 614 Vppa Veg J 21 60 FI Ves DQ,, 22 53 Da, DQ,, 23 58 DQ, | DP,C424 57 NC NCO 25 56 fo NC Veg 26 55 Ves Vppqo 27 541 Vppa NCL 28 53 [oO NCO 23 52D NC NCC 30 5ifo nc T-~TN OTHO OMmMODOOoOeT A YT Hoon WoO a Onmnmnononanrnnntat ttt Tt wo UUUUU UU UU UUUU UU UU lo + ON Tr OnD YAaxnS = Nowryeg G= SSS SERS ZA cee cd + Selection Guide 701326-166 | 701326-133 | 7C1326-117 | 7C1326-100 Maximum Access Time (ns) 3.5 4.0 45 5.5 Maximum Operating Current (mA) 420 375 350 325 Maximum Standby Current (mA) 2.0 2.0 2.0 2.0Sy cvpnsss Pin Definitions PSELININASY CY7C1326 Pin Number Name 0 Description 49-44, 81,82, | Areo] Input- Address Inputs used to select one of the 128K address locations. Sampled at the 99, 100, Synchronous | rising edge of the CLK if ADSP or ADSC is active LOW, and CE,, CEs, and CE; 32-37 are sampled active. Ag and A, feed the 2-bit counter. 94-93 BWr-o) | Input Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes Synchronous | to the SRAM. Sampled on the rising edge of CLK. 88 GW Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of Synchronous | CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWi1-0) and BWE). a7 BWE Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous | signal must be asserted LOW to conduct a byte write. ag CLK Input-Glock Glock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. 98 CE, Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous | conjunction with CE, and CE; to select/deselect the device. ADSP is ignored if CE, is HIGH. 97 CEs Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous | conjunction with CE, and CE, to select/deselect the device. 92 CE Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous | conjunction with CE, and CE to select/deselect the device. 86 OE Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O Asynchronous | pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. 83 ADV Input- Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto- Synchronous =| matically increments the address in a burst cycle. 84 ADSP Input- Address Strobe from Processcr, sampled on the rising edge of CLK. When assert- Synchronous =| ed LOW, Arje.n] is captured in the address registers. Ay and A, are also loaded into the burst cbunter. When ADSP and ADSC are both asserted, only ADSP is recog- nized. ASDP is ignored when CE, is deasserted HIGH. 85 ADSC Input- Address Strobe from Controller, sampled on the rising edge of CLK. When assert- Synchronous | ed LOW, Arie:o] is captured in the address registers. Ap and A; are also loaded into the burst cbunter. When ADSP and ADSC are both asserted, only ADSP is recog- nized. 64 ZZ Input- 77 sleep Input. This active HIGH input places the device in a non-time critical Asynchronous | sleep condition with data integrity preserved. 29, 28, DQiH 5:9), | /O- Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that 25-22, 19, DPi1:9] Synchronous | is triggered by the rising edge of CLK. As outputs, they deliver the data contained 18,13,12, in the memory location specified by Aryg.9) during the previous clock rise of the 9-6, 3, 2, 79, read cycle. The direction of the pins is controlled by OE. When OE is asserted 78, 75-72, LOW, the pins behave as outputs. When HIGH, DOhs.9, and DP), .9, are placed in 69, 68, 63,62 a three- state condition. 59-56, 53, 52 15, 41, 65,91] Vop Power Supply | Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 17, 40, 67, 90 | Vss Ground Ground for the core of the device. Should be connected to ground of the system. 4,11, 20,27, | Vope OQ Power Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. 54,61, 70, 77 Supply 5, 10,21, 26, | Vssq 0 Ground Ground for the I/O circuitry. Should be connected to ground of the system. 55, 60,71, 76 34 MODE Input- Selects burst order. When tied to GND selects linear burst sequence. When tied Static to Vppqg oF left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. 1,14, 16,30, | NC No Connects. 38,39, 42,43, 49,50,51,66, 80PSELININASY CY7C1326 Sy cvpnsss Introduction Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max- imum access delay from the clock rise (too) is 3.5 ns (166-MHz device). A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically incre- ments the address for the rest of the burst access. The C7C1326 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is de- termined by sampling the MODE input. Accesses can be initi- ated with either the processor address strobe (ADSP} or the controller address strobe (ADSC}). Address advancement through the burst sequence is controlled by the ADV input. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWig.4)) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchro- nous self-timed write circuitry. Three synchronous chip selects (CE,, CE, CE3) and an asyn- chronous output enable (GE) provide for easy bank selection and output three-state control. ADSP is ignored if CE, is HIGH. Single Read Accesses This access is initiated when the following conditions are sat- isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE,, , CEs, CE, are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE, is HIGH. The address presented to the address inputs (ApAj4g) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-MHz device} if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE,, CEs, CE; are all asserted active. The address presented to ApAj., is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, BW, and BW,}) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ)DQ,5 and DP inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BW, 1:0] Signals. The CY7C1326 provides byte write capability that is described in the Write Cycle Descriptions table. Assert- ing the Byte Write Enable input (BWE) with the selected Byte Write (BWpy, BW} input will selectively write to only the de- sired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mecha- nism has been provided to simplify the write operations. Because the CY7C1326 is a common I/O device, the Output Enable (GE} must be deasserted HIGH before presenting data to the DQ,-DQ,. and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQg-DQ,5 and DP are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following condi- tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE,, CEs, CE; are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW,, BW} are asserted active to conduct a write to the desired byte(s}. ADSC triggered write accesses require a single clock cycle to complete. The address presented to Ag-Ai, is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is con- ducted, the data presented to the DQ,-DQ,, and DP are writ ten into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1326 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ,-DQ,.5 and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ@,-DQ,15 and DP are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The GY7C 1326 provides a two-bit wraparound counter, fed by Ag and A,, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specif- ically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a lin- ear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Interleaved Burst Sequence First Second Third Fourth Address Address Address Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax oo 01 10 11 01 oo 11 10 10 11 00 01 11 10 01 ooSy cvpnsss PSELININASY CY7C1326 Linear Burst Sequence Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ plac- First Second Third Fourth es the SRAM in a power conservation sleep mode. Two clock Address Address Address Address cycles are required to enter inte or exit from this sleep mode. Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered 00 01 10 im valid nor is the completion of the operation guaranteed. The of 11 00 device must be deselected prior to entering the sleep mode. CE,, CEs, CE3, ADSP, and ADSC must remain inactive for the 10 00 01 duration of tzzRec after the ZZ input returns LOW. 11 00 01 10 Cycle Descriptions" 2"! Next Cycle Add.Used | ZZ CE, | CE, | CE, | ADSP | ADSC | ADV | OE DQ | Write Unselected None L x x 1 Xx 0 Xx Xx Hi-Z x Unselected None L 1 Xx 0 0 Xx X X Hi-Z Xx Unselected None L x 0 0 0 x Xx Xx Hi-Z x Unselected None L 1 x 0 1 0 Xx Xx Hi-Z x Unselected None L x 0 0 1 0 X X Hi-Z x Begin Read External L 0 1 0 0 x Xx xX Hi-Z x Begin Read External L 0 1 0 1 0 x x Hi-Z read Continue Read | Next L x x x 1 1 0 1 Hi-7 read Continue Read | Next L x x x 1 1 0 0 DQ read Continue Read | Next L x x 1 Xx 1 0 1 Hi-Z read Gontinue Read | Next L x x 1 x 1 0 0 DQ read Suspend Read | Current L x x x 1 1 1 1 Hi-Z read Suspend Read | Current L x x x 1 1 1 0 DQ read Suspend Read | Current L x x 1 x 1 1 1 Hi-7 read Suspend Read | Current L x x 1 x 1 1 0 DQ read Begin Write Current L x x x 1 1 1 Xx Hi-Z write Begin Write Current L x x 1 X 1 1 Xx Hi-Z write Begin Write External L 0 1 0 1 0 Xx Xx Hi-Z write Continue Write | Next L x x x 1 1 0 x Hi-Z write Continue Write | Next L x x 1 x 1 0 x Hi-7 write Suspend Write | Current L Xx Xx Xx 1 1 1 x Hi-Z write Suspend Write | Current L xX xX 1 x 1 1 X Hi-Z write ZZ sleep None H x x x X x X X Hi-Z x Notes: 1. X=Don't Care, 1=HIGH, 0=LOW. _ 2. Write is defined by BWE, BW[1:0], and GW. See Write Cycle Descriptions table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.Se <vpress PSELININASY CY7C1326 Write Cycle Descriptions! ="! Function Gw BWE BW, BW) Read 1 1 x xX Read 1 0 1 1 Write Byte 0 - DQjz.9), BP ta 1 0 1 0 Write Byte 1 - DQi5-8), DPty 1 0 0 1 Write Both Bytes 1 0 0 0 Write Both Bytes 0 x x x Maximum Ratings Current into Outputs (LOW)... eee 20 mA Static Discharge Voltage oo... eeeeereteeeeees >2001V nee not tested) useful life may be impaired. For user quide- (per MIL-STD-883, Method 3015) Storage Temperature sricsesn:scsnsnusnsuennen 65C to +150C Lateh-Up Current... cece tne eneete >200 mA Ambient Temperature with Operating Range Power Applied onesies terres Oo G fo +125C Supply Voltage on Vpp Relative to GND O0.5V to +4.6V Ambient [5] 5G Vol Applied oo reenene eM , Range Temperature Vop oltage Applied to Outputs ; in High Z Stately oa sesssseseessssseeeee 0.5V to Vppq + 0.5V Com'| 0G to +70G 3.3V 5%/+10% DC Input Voltage). ee -O.5V to Vppag + 0.5V Notes: 4. Minimum voltage equals 2.0V for pulse durations of less than 20 ns. 5. T,is the instant on case temperatureSe <vpress PREUIMINASY CY7C1326 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit Vee Power Supply Voltage 3.135 3.6 Vv Vopa lO Supply Veltage 3.135 3.6 Vv Vou Output HIGH Voltage | Vpp = Min., Igy =-4.0 mA 2.4 Vv VoL Output LOW Voltage = | Vpp = Min., Ip, = 8.0 MA 0.4 Vv Vin Input HIGH Voltage 20 |Vppq+O0.3V] V Vi Input LOW Voltage!) 0.3 0.8 V ly Input Load Current GND <V<Vppe aa) 5 HA except 77 and MODE Input Current of MODE | Input = Vg -30 LA Input = Vope 5 HA Input Current of 27 Input = Ves -5 HA Input = Vopq 30 HA loz Output Leakage GND < V| <= Vppaq, Output Disabled +5 5 HA Current lec Vpp Operating Supply | Vpp = Max., lout = 0 MA, 6-ns cycle, 166 MHz 420 mA Current f= fax = ove 7.5-ns cycle, 133 MHz 375 mA 8.5-ns cycle, 117 MHz 350 mA 10-ns cycle, 100 MHz 325 mA Ispi Automatic CS Max. Vpp, Device Deselected, 6-ns cycle, 166 MHz 35 mA Coren TIL Inputs pe MNS vn 7-5-ns cycle, 133 MHz 80 mA 8.5-ns cycle, 117 MHz 25 mA 10-ns cycle, 100 MHz 25 mA Ispe Automatic GS Max. Vpp, Device Deselected, 2.5 mA Isp3 Automatic CS Max. Vpp, Device Deselected, or | 6-ns cycle, 166 MHz 10 mA 8.5-ns cycle, 117 MHz 10 mA 10-ns cycle, 100 MHz 10 mA Ispa Automatic CS Max. Vpp, Device Deselected, 18 mA Power-Down Vin = Vin or Vin = Viv,f = 0 CurrentTTL Inputs 2Z Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit leezz Snooze mode 22 > Vpp- 0.2V 3 mA standby current loezz (L Version) Snooze mode ZZ >Vpop- 0.2V 800 LA standby current tzzs Device operationto | ZZ > Vpp 0.2V Zteve ns ZZ tzz7REC ZZ recovery time 27 <0.2V 2tove nsSe <vpress PRELIMINARY CY7C1326 Capacitance! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, pF . Vop = 3.3V Cok Clock Input Capacitance Vppa = 3.3V pF Cio Input/Output Capacitance pF AC Test Loads and Waveforms 3.35V R=3170 OUTPUT _ OUTPUT ALL INPUT PULSES! Note: INCLUDING JIG AND (a) SCOPE > (b) 6. Tested initially and after any design or process changes that may affect these parameters. 7. Input waveform should have a slew rate of 1V/ns. P $ R=3510 GNDSe <vpress PSELININASY CY7C1326 Switching Characteristics Over the Operating Range?.'9 -166 -133 -117 -100 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit teye Clock Cycle Time 6 75 8.5 10 ns tcH Glock HIGH 17 1.9 2.5 3.5 ns teL Clock LOW 1.7 1.9 25 3.5 ns tas Address Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns tan Address Hold After CLK Rise 05 05 05 0.5 ns teo Data Output Valid After CLK Rise 3.5 4 4.5 5.5 ns tpou Data Output Hold After CLK Rise 15 2.0 2.0 2.0 ns taps ADSP, ADSC Set-Up Before CLK Rise | 2.0 25 25 25 ns tADH ADSP ADSC Hold After CLK Rise 05 05 05 0.5 ns twes BWE, GW, BW[1:0] Set-Up Before CLK | 2.0 25 25 2.5 ns Rise tweH BWE, GW, BW[1:C] Hold After CLK 0.5 0.5 0.5 0.5 ns Rise tapvs ADV Set-Up Before CLK Rise 2.0 25 25 25 ns tapvH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tps Data Input Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns tbH Data Input Hold After CLK Rise 05 05 05 0.5 ns tces Chip Select Set-Up 2.0 25 25 2.5 ns tcEH Chip Select Hold After GLK Rise 05 0.5 0.5 0.5 ns tcuz Clock to High-z!? 1% 3.5 3.5 35 3.5 | ns toLz Clock to Low-z/: 14 0 0 0 0 ns tEOHZ OE HIGH to Output High-Z!: 19 3.5 3.5 3.5 3.5 | ns tEoLz OE LOW to Output Low-zI: 10] 0 0 0 0 6 ns teov OE LOW to Output Valid!! 3.5 3.5 3.5 3.5 | ns Notes: 8. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5, input pulse levels of 9 to 3.0V, and output loading of the specified |, 4,4, and load capacitance. Shown in {a) and (b) of AC test loads. 9. toyz. tocz. teoy. tegiz, and tro yz are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured + 200 m from steady-state voltage. 10. At any given voltage and temperature, te gy; is less than ted, 7 and toyz is less than ty, z.Se <vpress PSELININASY CY7C1326 Switching Waveforms Write Cycle Timing a, | | | " = |, WE is the combination of BWE_& BW, to define a write cycle (see Write Cycle Descriptions table). Bee] = UNDEFINED Re = DON'T CARESe <vpress PSSLIMINASY CY7C1326 Switching Waveforms (continued) Read Cycle Timing WE is the combination of BWE & BW, to define a write cycle (see Write Cycle Descriptions table). j= DONT CARE = UNDEFINED 11 evensss. PSELIMINASY CY7C1326 Switching Waveforms (continued) Read/Write Cycle Timing WE is the combination of BWE & BW, to defin es - cycle (se 8 Wiite Cycle Des cription s table). = DON'T CARE fq = UNDEFINED Note: Write data forwarded to wipe, ead immediately following a writeCY7C1326 PSELININASY Sy cvpnsss Switching Waveforms (continued) Pipeline Timing : A Ee Device originally deselected WE is the combination of BWE, BWS)1.9) and GW to define a write cycle (see Write Cycle Descriptions table). CE is the combination of CE, and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. UNDEFINED DON'T CARE BSS = - 13CY7C1326 PSELININASY Sy cvpnsss Switching Waveforms (continued) Device must be deselected when entering 22 mode. See Cycle Description for all possible signal conditions to deselect the device. Os are in three-state when exiting 22 sleep mode. ZZ Mode Timing !"'-121 Note: 11. 12. 14= ;-vpress PRELIMINARY CY7C1326 Ordering Information Speed Package Operating (MHz) Ordering Code Name Package Type Range 166 CY7C1326-166AG A101 100-Lead Thin Quad Flat Pack Commercial 166 CY7C1326L-166AC A101 100-Lead Thin Quad Flat Pack Commercial 133 CY7C1326-133AC A101 100-Lead Thin Quad Flat Pack Commercial 133 CY7C1326L-133AC A101 100-Lead Thin Quad Flat Pack Commercial 117 CY7C1326-117AC A101 100-Lead Thin Quad Flat Pack Commercial 117 CY7C1326L-117AC A101 100-Lead Thin Quad Flat Pack Commercial 100 CY7C1326-100AG A101 100-Lead Thin Quad Flat Pack Commercial 100 CY7C1326L-100AC A101 100-Lead Thin Quad Flat Pack Commercial Document #: 38-00720 Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. re 16.0020.20 14,0020.10 1.400.05 0.3020.0B 22.0040.20 70.00+0.10 0.65 le*s1* TYP. eax? st = SEE DETAIL A i 0.20 MAX. R 0.08 MIN. 020 Han O MIN. a] 1.60 MAX. f ) STAND-OF F iS 005 MN SEATING PLANE a GAUGE PLANE \ A ) 3 \ R 0.08 MIN. or-7" O20 MAX. 0.602015 4 be 0.20 MIN. 1.00 REF. | DETAIL A 51-85050-A Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility tor the use ofany circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical componenis in life-support systems where a maliunction or failure may reasonably be expecied to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that ine manutacturer assumes all risk of Such Use and in doing so indemnifies Cypress Semiconductor against all charges.