KSZ8091MNX/RNB 10BASE-T/100BASE-TX Physical Layer Transceiver Features Target Applications * Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver * MII Interface Support (KSZ8091MNX) * RMII v1.2 interface support with a 50 MHz reference clock output to MAC, and an option to input a 50 MHz reference clock (KSZ8091RNB) * Back-to-Back Mode Support for a 100 Mbps Copper Repeater * MDC/MDIO Management Interface for PHY Register Configuration * Programmable Interrupt Output * LED Outputs for Link and Activity Status Indication, plus speed indication for KSZ8091RNB * On-Chip Termination Resistors for the Differential Pairs * Baseline Wander Correction * HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option * Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full) * Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage (MII Version Only) for 100BASE-TX and Transmit Amplitude Reduction with 10BASE-Te Option * Wake-on-LAN (WOL) Support with Either Magic Packet, Link Status Change, or Robust CustomPacket Detection * HBM ESD Rating (6 kV) * Power-Down and Power-Saving Modes * LinkMD(R) TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling * Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board * Loopback Modes for Diagnostics * Single 3.3V Power Supply with VDD I/O Options for 1.8V, 2.5V, or 3.3V * Built-In 1.2V Regulator for Core * Available in 32-pin 5 mm x 5 mm QFN Package * * * * * * 2016 Microchip Technology Inc. Game Consoles IP Phones IP Set-Top Boxes IP TVs LOM Printers DS00002275A-page 1 KSZ8091MNX/RNB TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00002275A-page 2 2016 Microchip Technology Inc. KSZ8091MNX/RNB Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Description .................................................................................................................................................................. 15 4.0 Register Descriptions .................................................................................................................................................................... 40 5.0 Operational Characteristics ........................................................................................................................................................... 57 6.0 Electrical Characteristics ............................................................................................................................................................... 58 7.0 Timing Diagrams ........................................................................................................................................................................... 60 8.0 Reset Circuit ................................................................................................................................................................................. 69 9.0 Reference Circuits -- LED Strap-In Pins ...................................................................................................................................... 70 10.0 Reference Clock - Connection and Selection ............................................................................................................................. 71 11.0 Magnetic - Connection and Selection ......................................................................................................................................... 72 12.0 Package Outline .......................................................................................................................................................................... 74 Appendix A: Data Sheet Revision History ........................................................................................................................................... 75 The Microchip Web Site ...................................................................................................................................................................... 76 Customer Change Notification Service ............................................................................................................................................... 76 Customer Support ............................................................................................................................................................................... 76 Product Identification System ............................................................................................................................................................. 77 2016 Microchip Technology Inc. DS00002275A-page 3 KSZ8091MNX/RNB 1.0 INTRODUCTION 1.1 General Description The KSZ8091 is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ8091 is a highly integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs, by integrating a low-noise regulator to supply the 1.2V core, and by offering a flexible 1.8/2.5/3.3V digital I/O interface. The KSZ8091MNX offers the Media Independent Interface (MII) and the KSZ8091RNB offers the Reduced Media Independent Interface (RMII) for direct connection with MII/RMII-compliant Ethernet MAC processors and switches. Energy Efficient Ethernet (EEE) provides further power saving during idle traffic periods and Wake-on-LAN (WOL) provides a mechanism for the KSZ8091 to wake up a system that is in standby power mode. The KSZ8091 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ8091 I/Os and the board. LinkMD(R) TDR-based cable diagnostics identify faulty copper cabling. The KSZ8091MNX and KSZ8091RNB are available in 32-pin, lead-free QFN packages. SYSTEM BLOCK DIAGRAM 10/100Mbps MII/RMII MAC MII/RMII ON-CHIP TERMINATION RESISTORS MDC/MDIO MANAGEMENT KSZ8091MNX/ KSZ8091RNB 50MHz (KSZ8091RNB) REF_CLK PME_N (SYSTEM POWER CIRCUIT) RJ-45 CONNECTOR MEDIA TYPES: 10BASE-T 100BASE-TX XI XO 25MHz XTAL 22pF DS00002275A-page 4 MAGNETICS FIGURE 1-1: 22pF 2016 Microchip Technology Inc. KSZ8091MNX/RNB PIN DESCRIPTION AND CONFIGURATION 32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8091MNX (TOP VIEW) RST# TXER LED0/PME_N1/NWAYEN CRS/CONFIG1 COL/CONFIG0 TXD3 TXD2 FIGURE 2-1: TXD1 2.0 32 31 30 29 28 27 26 25 GND VDD_1.2 VDDA_3.3 RXM RXP TXM 1 24 2 23 6 19 TXD0 TXEN TXC/PME_EN INTRP/PME_N2/NAND_TREE# RXER/ISO RXC/B-CAST_OFF TXP XO 7 18 RXDV/CONFIG2 8 17 VDDIO 22 4 PADDLE GROUND 5 (ON BOTTOM OF CHIP) 10 11 12 13 14 TABLE 2-1: 20 15 16 XI REXT MDIO MDC RXD3/PHYAD0 RXD2/PHYAD1 RXD1/PHYAD2 9 21 RXD0/DUPLEX 3 SIGNALS - KSZ8091MNX Pin Number Pin Name Type Note 2-1 1 GND GND 2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8091MNX) Decouple with 2.2 F and 0.1 F capacitors to ground. 3 VDDA_3.3 P 3.3V analog VDD 4 RXM I/O Physical receive or transmit signal (- differential) 5 RXP I/O Physical receive or transmit signal (+ differential) 2016 Microchip Technology Inc. Description Ground. DS00002275A-page 5 KSZ8091MNX/RNB TABLE 2-1: SIGNALS - KSZ8091MNX (CONTINUED) Pin Number Pin Name Type Note 2-1 6 TXM I/O Physical transmit or receive signal (- differential) 7 TXP I/O Physical transmit or receive signal (+ differential) 8 XO O Crystal feedback for 25 MHz crystal This pin is a no connect if an oscillator or external clock source is used. 9 XI I Crystal/Oscillator/External Clock input 25 MHz 50 ppm 10 REXT I Set PHY transmit output current Connect a 6.49 k resistor to ground on this pin. 11 MDIO Ipu/ Opu Management Interface (MII) Data I/O This pin has a weak pull-up, is open-drain, and requires an external 1.0 k pull-up resistor. 12 MDC Ipu Management Interface (MII) Clock input This clock pin is synchronous to the MDIO data pin. 13 RXD3/ PHYAD0 14 RXD2/ PHYAD1 15 RXD1/ PHYAD2 Description Ipu/O MII mode: MII Receive Data Output[3] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de assertion of reset. See the Strap-In Options - KSZ8091MNX section for details. Ipd/O MII mode: MII Receive Data Output[2] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[1] at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. Ipd/O MII mode: MII Receive Data Output[1] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de assertion of reset. See the Strap-In Options - KSZ8091MNX section for details. 16 RXD0/ DUPLEX Ipu/O MII mode: MII Receive Data Output[0] (Note 2-2) Config mode: The pull-up/pull-down value is latched as DUPLEX at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. 17 VDDIO P 18 RXDV/ CONFIG2 19 RXC/ B-CAST_OFF 20 RXER/ISO DS00002275A-page 6 3.3V, 2.5V, or 1.8V digital VDD Ipd/O MII mode: MII Receive Data Valid output Config mode: The pull-up/pull-down value is latched as CONFIG2 at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. Ipd/O MII mode: MII Receive Clock output Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de assertion of reset. See the Strap-In Options - KSZ8091MNX section for details. Ipd/O MII mode: MII Receive Error output Config mode: The pull-up/pull-down value is latched as ISOLATE at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 2-1: Pin Number 21 SIGNALS - KSZ8091MNX (CONTINUED) Pin Name INTRP/ PME_N2/ NAND_Tree# Type Note 2-1 Description Ipu/ Opu Interrupt output: Programmable interrupt output, with Register 1Bh as the Interrupt Control/Status register, for programming the interrupt conditions and reading the interrupt status. Register 1Fh, bit [9] sets the interrupt output to active low (default) or active high. PME_N output: Programmable PME_N output (pin option 2). When asserted low, this pin signals that a WOL event has occurred. Config mode: The pull-up/pull-down value is latched as NAND Tree# at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. This pin has a weak pull-up and is an open-drain. For Interrupt (when active low) and PME functions, this pin requires an external 1.0 k pull-up resistor to VDDIO (digital VDD). MII mode: MII Transmit Clock output MII back-to-back mode: No connection Config mode: The pull-up/pull-down value is latched as PME_EN at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. 22 TXC/ PME_EN Ipd/O 23 TXEN I MII mode: MII Transmit Enable input 24 TXD0 I MII mode: MII Transmit Data Input[0] (Note 2-3) 25 TXD1 I MII mode: MII Transmit Data Input[1] (Note 2-3) 26 TXD2 I MII mode: MII Transmit Data Input[2] (Note 2-3) 27 TXD3 I MII Mode: MII Transmit Data Input[3] (Note 2-3) 28 COL/ CONFIG0 29 CRS/ CONFIG1 Ipd/O MII mode: MII Collision Detect output Config mode: The pull-up/pull-down value is latched as CONFIG0 at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. Ipd/O MII mode: MII Carrier Sense output Config mode: The pull-up/pull-down value is latched as CONFIG1 at the deassertion of reset. See the Strap-In Options - KSZ8091MNX section for details. 2016 Microchip Technology Inc. DS00002275A-page 7 KSZ8091MNX/RNB TABLE 2-1: Pin Number SIGNALS - KSZ8091MNX (CONTINUED) Pin Name Type Note 2-1 Description LED output: Programmable LED0 output PME_N Output: Programmable PME_N Output (pin option 1) In this mode, this pin has a weak pull-up, is an open-drain, and requires an external 1.0 k pull-up resistor to VDDIO (digital VDD). Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the de-assertion of reset. See the Strap-In Options - KSZ8091MNX section for details. The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows. LED Mode = [00] 30 LED0/ PME_N1/ NWAYEN Ipu/O Link/Activity Pin State LED Definition No Link High OFF Link Low ON Activity Toggle Blinking Link Pin State LED Definition No Link High OFF Link Low ON LED Mode = [01] LED Mode = [10], [11]: Reserved 31 TXER Ipd MII mode: MII Transmit Error input For EEE mode, this pin is driven by the EEEMAC to pull up this pin for KSZ8091MNX transmit into the LPI state. For non-EEE mode, this pin is not defined for error transmission from MAC to KSZ8091MNX and can be left as a no connect. For NAND Tree testing, this pin should be pulled high by a pull-up resistor. 32 RST# Ipu Chip reset (active low) PADDLE GND GND Ground Note 2-1 P = power supply GND = ground I = input O = output I/O = bi-directional Ipu = Input with internal pull-up (see Electrical Characteristics for value). Ipd = Input with internal pull-down (see Electrical Characteristics for value). Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). Note 2-2 MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC. DS00002275A-page 8 2016 Microchip Technology Inc. KSZ8091MNX/RNB Note 2-3 MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7 k) or pull-downs (1.0 k) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly. TABLE 2-2: Pin Number STRAP-IN OPTIONS - KSZ8091MNX Pin Name Type Note 2-4 15 PHYAD2 Ipd/O 14 PHYAD1 Ipd/O 13 PHYAD0 Ipu/O 18 CONFIG2 29 CONFIG1 28 CONFIG0 22 20 16 30 19 21 Note 2-4 PME_EN ISO DUPLEX NWAYEN B-CAST_OFF Description PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to 7 with PHY Address 1 as the default value. PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a `1' to Register 16h, bit [9]. PHY Address bits [4:3] are set to 00 by default. The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset. CONFIG[2:0] Mode Ipd/O 000 MII (default) 110 MII back-to-back 001 - 101, 111 Reserved, not used Ipd/O PME output for Wake-on-LAN Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 16h, bit [15]. Ipd/O Isolate mode Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 0h, bit [10]. Ipu/O Duplex Mode: Pull-up (default) = Half-duplex Pull-down = Full-duplex At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8]. Ipu/O Nway Auto-Negotiation Enable: Pull-up (default) = Enable auto-negotiation Pull-down = Disable auto-negotiation At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12]. Ipd/O Broadcast Off - for PHY Address 0: Pull-up = PHY Address 0 is set as an unique PHY address Pull-down (default) = PHY Address 0 is set as a broadcast PHY address At the de-assertion of reset, this pin value is latched by the chip. NAND Tree Mode: Pull-up (default) = Disable NAND_Tree# Ipu/Opu Pull-down = Enable At the de-assertion of reset, this pin value is latched by the chip. Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up and output with internal pull-up. 2016 Microchip Technology Inc. DS00002275A-page 9 KSZ8091MNX/RNB TXD1 32-PIN 5 MM X 5 MM QFN ASSIGNMENT, KSZ8091RNB (TOP VIEW) RST# LED1/SPEED LED0/PME_N1/NWAYEN CONFIG1 CONFIG0 NC NC FIGURE 2-2: 32 31 30 29 28 27 26 25 GND VDD_1.2 VDDA_3.3 RXM RXP TXM 1 24 2 23 6 19 TXD0 TXEN PME_EN INTRP/PME_N2/NAND_TREE# RXER/ISO REF_CLK/B-CAST_OFF TXP XO 7 18 CRS_DV/CONFIG2 17 VDDIO 3 22 4 PADDLE GROUND 5 (ON BOTTOM OF CHIP) 21 8 15 16 RXD0/DUPLEX 10 11 12 13 14 XI REXT MDIO MDC PHYAD0 PHYAD1 RXD1/PHYAD2 9 TABLE 2-3: 20 SIGNALS - KSZ8091RNB Pin Number Pin Name Type Note 2-1 1 GND GND 2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8091RNB) Decouple with 2.2 F and 0.1 F capacitors to ground. 3 VDDA_3.3 P 3.3V analog VDD 4 RXM I/O Physical receive or transmit signal (- differential) 5 RXP I/O Physical receive or transmit signal (+ differential) 6 TXM I/O Physical transmit or receive signal (- differential) 7 TXP I/O Physical transmit or receive signal (+ differential) 8 XO O Crystal feedback for 25 MHz crystal This pin is a no connect if an oscillator or external clock source is used. DS00002275A-page 10 Description Ground. 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 2-3: SIGNALS - KSZ8091RNB (CONTINUED) Pin Number Pin Name Type Note 2-1 9 XI I 25 MHz Mode:25 MHz 50 ppm Crystal/Oscillator/External Clock Input 50 MHz Mode: 50 MHz 50 ppm Oscillator/External Clock Input 10 REXT I Set PHY transmit output current Connect a 6.49 k resistor to ground on this pin. 11 MDIO 12 MDC Ipu 13 PHYAD0 Ipu/O The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. 14 PHYAD1 Ipd/O The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. 15 RXD1/ PHYAD2 Ipd/O RMII mode: RMII Receive Data Output[1] (Note 2-2) Config mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. 16 RXD0/ DUPLEX Ipu/O RMII mode: RMII Receive Data Output[0] (Note 2-2) Config mode: The pull-up/pull-down value is latched as DUPLEX at the deassertion of reset. See the Strap-In Options - KSZ8091RNB section for details. 17 VDDIO P 18 CRS_DV/ CONFIG2 19 20 21 Management Interface (MII) Data I/O Ipu/Opu This pin has a weak pull-up, is open-drain, and requires an external 1.0 k pull-up resistor. REF_CLK/ B-CAST_OFF RXER/ISO INTRP/ PME_N2/ NAND_Tree# Description Management Interface (MII) Clock input This clock pin is synchronous to the MDIO data pin. 3.3V, 2.5V, or 1.8V digital VDD Ipd/O RMII mode: RMII Carrier Sense/Receive Data Valid output Config mode: The pull-up/pull-down value is latched as CONFIG2 at the deassertion of reset. See the Strap-In Options - KSZ8091RNB section for details. Ipd/O RMII mode: 25 MHz mode: This pin provides the 50 MHz RMII reference clock output to the MAC. See also XI (pin 9). 50 MHz mode: This pin is a no connect. See also XI (pin 9). Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. Ipd/O RMII mode: RMII Receive Error output Config mode: The pull-up/pull-down value is latched as ISOLATE at the deassertion of reset. See the Strap-In Options - KSZ8091RNB section for details. Interrupt output: Programmable interrupt output, with Register 1Bh as the Interrupt Control/Status register, for programming the interrupt conditions and reading the interrupt status. Register 1Fh, bit [9] sets the interrupt output to active low (default) or active high. PME_N output: Programmable PME_N output (pin option 2). When asserted low, this pin signals that a WOL event has occurred. Ipu/Opu Config mode: The pull-up/pull-down value is latched as NAND Tree# at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. This pin has a weak pull-up and is an open-drain. For Interrupt (when active low) and PME functions, this pin requires an external 1.0 k pull-up resistor to VDDIO (digital VDD). 2016 Microchip Technology Inc. DS00002275A-page 11 KSZ8091MNX/RNB TABLE 2-3: SIGNALS - KSZ8091RNB (CONTINUED) Pin Number Pin Name Type Note 2-1 22 PME_EN Ipd/O 23 TXEN I RMII Transmit Enable input 24 TXD0 I RMII Transmit Data Input[0] (Note 2-3) 25 TXD1 I 26 NC NC 27 NC NC Description The pull-up/pull-down value is latched as PME_EN at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. RMII Transmit Data Input[1] (Note 2-3) No connect - This pin is not bonded and can be left floating. No connect - This pin is not bonded and can be left floating. 28 CONFIG0 Ipd/O The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. 29 CONFIG1 Ipd/O The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. LED output: Programmable LED0 output PME_N Output: Programmable PME_N Output (pin option 1). In this mode, this pin has a weak pull-up, is an open-drain, and requires an external 1.0 k pull-up resistor to VDDIO (digital VDD). Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows. 30 LED0/ PME_N1/ NWAYEN LED Mode = [00] Ipu/O Link/Activity Pin State LED Definition No Link High OFF Link Low ON Activity Toggle Blinking Link Pin State LED Definition No Link High OFF Link Low ON LED Mode = [01] LED Mode = [10], [11]: Reserved LED output: Programmable LED1 output Config mode: Latched as SPEED (Register 0h, bit [13]) at the de-assertion of reset. See the Strap-In Options - KSZ8091RNB section for details. The LED1 pin is programmable using Register 1Fh bits [5:4], and is defined as follows. LED Mode = [00] 31 LED1/ SPEED Ipu/O Speed Pin State LED Definition 10BASE-T High OFF 100BASE-TX Low ON Activity Pin State LED Definition No Activity High OFF Activity Toggle Blinking LED Mode = [01] LED Mode = [10], [11]: Reserved DS00002275A-page 12 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 2-3: SIGNALS - KSZ8091RNB (CONTINUED) Pin Number Pin Name Type Note 2-1 32 RST# Ipu PADDLE GND GND Description Chip reset (active low) Ground Note 2-1 P = Power supply. GND = Ground. I = Input. O = Output. I/O = Bi-directional. Ipu = Input with internal pull-up (see Electrical Characteristics for value). Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). NC = Pin is not bonded to the die. Note 2-2 RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC. Note 2-3 RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC. The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7 k) or pull-downs (1.0 k) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly. TABLE 2-4: Pin Number STRAP-IN OPTIONS - KSZ8091RNB Pin Name Type Note 2-4 15 PHYAD2 Ipd/O 14 PHYAD1 Ipd/O 13 PHYAD0 Ipu/O 18 CONFIG2 29 CONFIG1 28 CONFIG0 22 PME_EN 2016 Microchip Technology Inc. Description PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0 to 7 with PHY Address 1 as the default value. PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or writing a `1' to Register 16h, bit [9]. PHY Address bits [4:3] are set to 00 by default. The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset. CONFIG[2:0] Mode Ipd/O Ipd/O 000 RMII (default) 110 RMII back-to-back 001 - 101, 111 Reserved, not used PME output for Wake-on-LAN Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 16h, bit [15]. DS00002275A-page 13 KSZ8091MNX/RNB TABLE 2-4: Pin Number STRAP-IN OPTIONS - KSZ8091RNB (CONTINUED) Pin Name 20 31 16 30 19 21 Note 2-4 ISO SPEED DUPLEX NWAYEN B-CAST_OFF NAND_Tree# Type Note 2-4 Description Ipd/O Isolate mode Pull-up = Enable Pull-down (default) = Disable At the de-assertion of reset, this pin value is latched into Register 0h, bit [10]. Ipu/O Speed mode Pull-up (default) = 100 Mbps Pull-down = 10 Mbps At the de-assertion of reset, this pin value is latched into Register 0h, bit [13] as the speed select, and also is latched into Register 4h (auto-negotiation advertisement) as the speed capability support. Ipu/O Duplex Mode: Pull-up (default) = Half-duplex Pull-down = Full-duplex At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8]. Ipu/O Nway Auto-Negotiation Enable: Pull-up (default) = Enable auto-negotiation Pull-down = Disable auto-negotiation At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12]. Ipd/O Broadcast Off - for PHY Address 0: Pull-up = PHY Address 0 is set as an unique PHY address Pull-down (default) = PHY Address 0 is set as a broadcast PHY address At the de-assertion of reset, this pin value is latched by the chip. Ipu/Opu NAND Tree Mode: Pull-up (default) = Disable Pull-down = Enable At the de-assertion of reset, this pin value is latched by the chip. Ipu/O = Input with internal pull-up during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down during power-up/reset; output pin otherwise. Ipu/Opu = Input with internal pull-up and output with internal pull-up. DS00002275A-page 14 2016 Microchip Technology Inc. KSZ8091MNX/RNB 3.0 FUNCTIONAL DESCRIPTION The KSZ8091 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3 Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core. On the copper media side, the KSZ8091 supports 10BASE-T and 100BASE-TX for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. On the MAC processor side, the KSZ8091MNX offers the Media Independent Interface (MII) and the KSZ8091RNB offers the Reduced Media Independent Interface (RMII) for direct connection with MII and RMII compliant Ethernet MAC processors and switches, respectively. The MII management bus option gives the MAC processor complete access to the KSZ8091 control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change. The KSZ8091MNX/RNB is used to refer to both KSZ8091MNX and KSZ8091RNB versions in this data sheet. 3.1 3.1.1 10BASE-T/100BASE-TX Transceiver 100BASE-TX TRANSMIT The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI conversion, and MLT3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the MII/RMII data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 6.49 k 1% resistor for the 1:1 transformer ratio. The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 3.1.2 100BASE-TX RECEIVE The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as temperature variations. Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit converts MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder. Finally, the NRZ serial data is converted to MII/RMII format and provided as the input data to the MAC. 3.1.3 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY) The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and baseline wander. The de-scrambler recovers the scrambled signal. 3.1.4 10BASE-T TRANSMIT The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output 10BASE-T signals with a typical amplitude of 2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASET/10BASE-Te signals have harmonic contents that are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal. 2016 Microchip Technology Inc. DS00002275A-page 15 KSZ8091MNX/RNB 3.1.5 10BASE-T RECEIVE On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8091MNX/RNB decodes a data frame. The receive clock is kept active during idle periods between data receptions. 3.1.6 SQE AND JABBER FUNCTION (10BASE-T ONLY) In 10BASE-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE test is needed to test the 10BASE-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the 10BASE-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10BASE-T transmitter is re-enabled and COL is de-asserted (returns to low). 3.1.7 PLL CLOCK SYNTHESIZER The KSZ8091MNX/RNB generates all internal clocks and all external clocks for system timing from an external 25 MHz crystal, oscillator, or reference clock. For the KSZ8091RNB in RMII 50 MHz clock mode, these clocks are generated from an external 50 MHz oscillator or system clock. 3.1.8 AUTO-NEGOTIATION The KSZ8091MNX/RNB conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. The following list shows the speed and duplex operation mode from highest to lowest priority. * * * * Priority 1: 100BASE-TX, full-duplex Priority 2: 100BASE-TX, half-duplex Priority 3: 10BASE-T, full-duplex Priority 4: 10BASE-T, half-duplex If auto-negotiation is not supported or the KSZ8091MNX/RNB link partner is forced to bypass auto-negotiation, then the KSZ8091MNX/RNB sets its operating mode by observing the signal at its receiver. This is known as parallel detection, which allows the KSZ8091MNX/RNB to establish a link by listening for a fixed signal protocol in the absence of the autonegotiation advertisement protocol. Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, pin 30) or software (Register 0h, bit [12]). By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or disabled by Register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, bit [13], and the duplex is set by Register 0h, bit [8]. The auto-negotiation link-up process is shown in Figure 3-1. DS00002275A-page 16 2016 Microchip Technology Inc. KSZ8091MNX/RNB FIGURE 3-1: AUTO-NEGOTIATION FLOW CHART START AUTO-NEGOTIATION FORCE LINK SETTING NO PARALLEL OPERATION YES BYPASS AUTO-NEGOTIATION AND SET LINK MODE ATTEMPT AUTONEGOTIATION LISTEN FOR 100BASE-TX IDLES LISTEN FOR 10BASE-T LINK PULSES NO JOIN FLOW LINK MODE SET? YES LINK MODE SET 3.2 MII Data Interface (KSZ8091MNX Only) The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface between MII PHYs and MACs, and has the following key characteristics: * Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication). * 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex. * Data transmission and reception are independent and belong to separate signal groups. * Transmit data and receive data are each 4 bits wide, a nibble. By default, the KSZ8091MNX is configured to MII mode after it is powered up or hardware reset with the following: * A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI. * The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting). 2016 Microchip Technology Inc. DS00002275A-page 17 KSZ8091MNX/RNB 3.2.1 MII SIGNAL DEFINITION Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information. TABLE 3-1: MII SIGNAL DEFINITION MII Signal Name Direction with Respect to PHY, KSZ8091MNX Signal Direction with Respect to MAC TXC Output Input Description Transmit Clock (2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps) TXEN Input Output Transmit Enable TXD[3:0] Input Output Transmit Data[3:0] TXER Input Output or not implemented RXC Output Input Transmit Error (KSZ8091MNX implements only the EEE function for this pin. See Transmit Error (TXER) for details.) Receive Clock (2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps) RXDV Output Input Receive Data Valid RXD[3:0] Output Input Receive Data[3:0] RXER Output CRS Output Input Carrier Sense COL Output Input Collision Detection 3.2.1.1 Input or not required Receive Error Transmit Clock (TXC) TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN, TXD[3:0], and TXER. TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation. 3.2.1.2 Transmit Enable (TXEN) TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated before the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC. 3.2.1.3 Transmit Data[3:0] (TXD[3:0]) When TXEN is asserted, TXD[3:0] are the data nibbles presented by the MAC and accepted by the PHY for transmission. When TXEN is de-asserted, the MAC drives TXD[3:0] to either 0000 for the idle state (non-EEE mode) or 0001 for the LPI state (EEE mode). TXD[3:0] transitions synchronously with respect to TXC. 3.2.1.4 Transmit Error (TXER) TXER is implemented only for the EEE function. For EEE mode, this pin is driven by the EEE-MAC to put the KSZ8091MNX transmit into the LPI state. For non-EEE mode, this pin is not defined for error transmission from MAC to KSZ8091MNX and can be left as a no connect. TXER transitions synchronously with respect to TXC. 3.2.1.5 Receive Clock (RXC) RXC provides the timing reference for RXDV, RXD[3:0], and RXER. In 10 Mbps mode, RXC is recovered from the line while the carrier is active. When the line is idle or the link is down, RXC is derived from the PHY's reference clock. DS00002275A-page 18 2016 Microchip Technology Inc. KSZ8091MNX/RNB In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY's reference clock. RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation. 3.2.1.6 Receive Data Valid (RXDV) RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0]. In 10 Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted until the end of the frame. In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame. RXDV transitions synchronously with respect to RXC. 3.2.1.7 Receive Data[3:0] (RXD[3:0]) For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY. When RXDV is de-asserted, the PHY drives RXD[3:0] to either 0000 for the idle state (non-EEE mode) or 0001 for the LPI state (EEE mode). RXD[3:0] transitions synchronously with respect to RXC. 3.2.1.8 Receive Error (RXER) When RXDV is asserted, RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected somewhere in the frame that is being transferred from the PHY to the MAC. In EEE mode only, when RXDV is de-asserted, RXER is driven by the PHY to inform the MAC that the KSZ8091MNX receive is in the LPI state. RXER transitions synchronously with respect to RXC. 3.2.1.9 Carrier Sense (CRS) CRS is asserted and de-asserted as follows: * In 10 Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the reception of an end-of-frame (EOF) marker. * In 100 Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts CRS if IDLE symbols are received without /T/R. 3.2.1.10 Collision Detection (COL) COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This informs the MAC that a collision has occurred during its transmission to the PHY. COL transitions asynchronously with respect to TXC and RXC. 2016 Microchip Technology Inc. DS00002275A-page 19 KSZ8091MNX/RNB 3.2.2 MII SIGNAL DIAGRAM The KSZ8091MNX MII pin connections to the MAC are shown in Figure 3-2. FIGURE 3-2: KSZ8091MNX MII INTERFACE ' KSZ8091MNX TXC TX_EN TXD[3:0] TXC TX_EN TXD[3:0] TXER TXER RXC RXC RXDV RXDV RXD[3:0] RXER 3.3 MII ETHERNET MAC RXD[3:0] RXER CRS CRS COL COL RMII Data Interface (KSZ8091RNB Only) The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: * Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference clock). * 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex. * Data transmission and reception are independent and belong to separate signal groups. * Transmit data and receive data are each 2 bits wide, a dibit. 3.3.1 RMII - 25 MHZ CLOCK MODE The KSZ8091RNB is configured to RMII - 25 MHz clock mode after it is powered up or hardware reset with the following: * A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI. * The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001. * Register 1Fh, bit [7] is set to 0 (default value) to select 25 MHz clock mode. 3.3.2 RMII - 50 MHZ CLOCK MODE The KSZ8091RNB is configured to RMII - 50 MHz clock mode after it is powered up or hardware reset with the following: * An external 50 MHz clock source (oscillator) connected to XI (pin 9). * The CONFIG[2:0] strap-in pins (pins 18, 29, 28) set to 001. * Register 1Fh, bit [7] is set to 1 to select 50 MHz clock mode. DS00002275A-page 20 2016 Microchip Technology Inc. KSZ8091MNX/RNB 3.3.3 RMII SIGNAL DEFINITION Table 3-2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information. TABLE 3-2: RMII SIGNAL DEFINITION RMII Signal Name Direction with Respect to PHY KSZ8091RNB Signal Direction with Respect to MAC REF_CLK Output (25 MHz clock mode)/<no connect> (50 MHz clock mode) Input/Input or <no connect> Description Synchronous 50 MHz reference clock for receive, transmit, and control interface TXEN Input Output Transmit Enable TXD[1:0] Input Output Transmit Data[1:0] CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Data[1:0] RXER Output 3.3.4 Input or not required Receive Error REFERENCE CLOCK (REF_CLK) REF_CLK is a continuous 50 MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0] and RX_ER. For 25 MHz clock mode, the KSZ8091RNB generates and outputs the 50 MHz RMII REF_CLK to the MAC at REF_CLK (pin 19). For 50 MHz clock mode, the KSZ8091RNB takes in the 50 MHz RMII REF_CLK from the MAC or system board at XI (pin 9) and leaves the REF_CLK (pin 19) as a no connect. 3.3.5 TRANSMIT ENABLE (TXEN) TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated before the first REF_CLK following the final dibit of a frame. TXEN transitions synchronously with respect to REF_CLK. 3.3.6 TRANSMIT DATA[1:0] (TXD[1:0]) When TXEN is asserted, TXD[1:0] are the data dibits presented by the MAC and accepted by the PHY for transmission. When TXEN is de-asserted, the MAC drives TXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI state (EEE mode). TXD[1:0] transitions synchronously with respect to REF_CLK. 3.3.7 CARRIER SENSE/RECEIVE DATA VALID (CRS_DV) The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is detected. This happens when squelch is passed in 10 Mbps mode, and when two non-contiguous 0s in 10 bits are detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV. While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded. 3.3.8 RECEIVE DATA[1:0] (RXD[1:0]) For each clock period in which CRS_DV is asserted, RXD[1:0] transfers a dibit of recovered data from the PHY. When CRS_DV is de-asserted, the PHY drives RXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI state (EEE mode). RXD[1:0] transitions synchronously with respect to REF_CLK. 2016 Microchip Technology Inc. DS00002275A-page 21 KSZ8091MNX/RNB 3.3.9 RECEIVE ERROR (RXER) When CRS_DV is asserted, RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected somewhere in the frame that is being transferred from the PHY to the MAC. RXER transitions synchronously with respect to REF_CLK. 3.3.10 COLLISION DETECTION (COL) The MAC regenerates the COL signal of the MII from TXEN and CRS_DV. 3.3.11 RMII SIGNAL DIAGRAM The KSZ8091RNB RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-3. The connections for 50 MHz clock mode are shown in Figure 3-4. FIGURE 3-3: KSZ8091RNB RMII INTERFACE (25 MHZ CLOCK MODE) KSZ8091RNB RMII MAC CRS_DV CRS_DV RXD[1:0] RXD[1:0] RXER RX_ER TXEN TX_EN TXD[1:0] REF_CLK TXD[1:0] REF_CLK XI XO 25MHz XTAL 22pF DS00002275A-page 22 22pF 2016 Microchip Technology Inc. KSZ8091MNX/RNB FIGURE 3-4: KSZ8091RNB RMII INTERFACE (50 MHZ CLOCK MODE) RMII MAC KSZ8091RNB CRS_DV CRS_DV RXD[1:0] RXD[1:0] RXER RX_ER TXEN TX_EN TXD[1:0] TXD[1:0] REF_CLK XI 50MHz OSC 3.4 Back-to-Back Mode - 100 Mbps Copper Repeater Two KSZ8091MNX/RNB devices can be connected back-to-back to form a 100BASE-TX copper repeater. FIGURE 3-5: KSZ8091MNX/RNB TO KSZ8091MNX/RNB BACK-TO-BACK COPPER REPEATER RxD RXP/RXM TXP/TXM KSZ8091MNX/RNB (COPPER MODE) TxD 25MHz/ 50MHz XI OSC XI TXP/TXM RXP/RXM 2016 Microchip Technology Inc. KSZ8091MNX/RNB (COPPER MODE) TxD RxD DS00002275A-page 23 KSZ8091MNX/RNB 3.4.1 MII BACK-TO-BACK MODE (KSZ8091MNX ONLY) In MII back-to-back mode, a KSZ8091MNX interfaces with another KSZ8091MNX to provide a complete 100 Mbps copper repeater solution. The KSZ8091MNX devices are configured to MII back-to-back mode after power-up or reset with the following: * Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 110. * A common 25 MHz reference clock connected to XI (Pin 9) of both KSZ8091MNX devices. * MII signals connected as shown in Table 3-3. TABLE 3-3: MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE (100BASE-TX COPPER REPEATER) KSZ8091MNX (100BASE-TX Copper) [Device 1] Pin Name 3.4.2 Pin Number KSZ8091MNX (100BASE-TX Copper) [Device 2] Pin Type Pin Name Pin Number Pin Type RXDV 18 Output TXEN 23 Input RXD3 13 Output TXD3 27 Input RXD2 14 Output TXD2 26 Input RXD1 15 Output TXD1 25 Input RXD0 16 Output TXD0 24 Input TXEN 23 Input RXDV 18 Output TXD3 27 Input RXD3 13 Output TXD2 26 Input RXD2 14 Output TXD1 25 Input RXD1 15 Output TXD0 24 Input RXD0 16 Output RMII BACK-TO-BACK MODE (KSZ8091RNB ONLY) In RMII back-to-back mode, a KSZ8091RNB interfaces with another KSZ8091RNB to provide a complete 100 Mbps copper repeater solution. The KSZ8091RNB devices are configured to RMII back-to-back mode after power-up or reset with the following: * Strap-in pin CONFIG[2:0] (pins 18, 29, 28) set to 101. * A common 50 MHz reference clock connected to XI (pin 9) of both KSZ8091RNB devices. * RMII signals connected as shown in Table 3-4. TABLE 3-4: RMII SIGNAL CONNECTION FOR RMII BACK-TO-BACK MODE (100BASE-TX COPPER REPEATER) KSZ8091RNB (100BASE-TX Copper) [Device 1] Pin Name Pin Number KSZ8091RNB (100BASE-TX Copper) [Device 2] Pin Type Pin Name Pin Number Pin Type CRSDV 18 Output TXEN 23 Input RXD1 15 Output TXD1 25 Input RXD0 16 Output TXD0 24 Input TXEN 23 Input CRSDV 18 Output TXD1 25 Input RXD1 15 Output TXD0 24 Input RXD0 16 Output DS00002275A-page 24 2016 Microchip Technology Inc. KSZ8091MNX/RNB 3.5 MII Management (MIIM) Interface The KSZ8091MNX/RNB supports the IEEE 802.3 MII management interface, also known as the Management Data Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and control the state of the KSZ8091MNX/RNB. An external device with MIIM capability is used to read the PHY status and/ or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification. The MIIM interface consists of the following: * A physical connection that incorporates the clock line (MDC) and the data line (MDIO). * A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more PHY devices. * A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indirect access to MMD addresses and registers. See the Register Descriptions section. As the default, the KSZ8091MNX/RNB supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8091MNX/RNB device, or write to multiple KSZ8091MNX/RNB devices simultaneously. PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, pin 19) or software (Register 16h, bit [9]), and assigned as a unique PHY address. The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8091MNX/RNB device. The MIIM interface can operates up to a maximum clock speed of 10 MHz MAC clock. Table 3-5 shows the MII management frame format for the KSZ8091MNX/RNB. TABLE 3-5: MII MANAGEMENT FRAME FORMAT FOR THE KSZ8091MNX/RNB Preamble Start of Frame Read/ Write OP Code PHY Address Bits[4:0] REG Address Bits[4:0] TA Data Bits[15:0] Idle Read 32 1's 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1's 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z 3.6 Interrupt (INTRP) INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8091MNX/RNB PHY Register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh. Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low. The MII management bus option gives the MAC processor complete access to the KSZ8091MNX/RNB control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change. 3.7 HP Auto MDI/MDI-X HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable between the KSZ8091MNX/RNB and its link partner. This feature allows the KSZ8091MNX/RNB to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8091MNX/RNB accordingly. HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a `1' to Register 1Fh, bit [13]. MDI and MDI-X mode is selected by Register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled. An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X. Table 3-6 shows how the IEEE 802.3 Standard defines MDI and MDI-X. 2016 Microchip Technology Inc. DS00002275A-page 25 KSZ8091MNX/RNB TABLE 3-6: MDI/MDI-X PIN DESCRIPTION MDI 3.7.1 MDI-X RJ-45 Pin Signal RJ-45 Pin Signal 1 2 TX+ 1 RX+ TX- 2 RX- 3 6 RX+ 3 TX+ RX- 6 TX- STRAIGHT CABLE A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-6 shows a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device). FIGURE 3-6: TYPICAL STRAIGHT CABLE CONNECTION 10/100 ETHERNET MEDIA DEPENDENT INTERFACE 10/100 ETHERNET MEDIA DEPENDENT INTERFACE 1 1 2 2 TRANSMIT PAIR RECEIVE PAIR 3 STRAIGHT CABLE 3 4 4 5 5 6 6 7 7 8 8 RECEIVE PAIR TRANSMIT PAIR MODULAR CONNECTOR (RJ-45) NIC 3.7.2 MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) CROSSOVER CABLE A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 3-7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). DS00002275A-page 26 2016 Microchip Technology Inc. KSZ8091MNX/RNB FIGURE 3-7: TYPICAL CROSSOVER CABLE CONNECTION 10/100 ETHERNET MEDIA DEPENDENT INTERFACE 1 RECEIVE PAIR 10/100 ETHERNET MEDIA DEPENDENT INTERFACE CROSSOVER CABLE 1 RECEIVE PAIR 2 2 3 3 4 4 5 5 6 6 7 7 8 8 TRANSMIT PAIR TRANSMIT PAIR MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) 3.8 MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) Loopback Mode The KSZ8091MNX/RNB supports the following loopback operations to verify analog and/or digital data paths. * Local (digital) loopback * Remote (analog) loopback 3.8.1 LOCAL (DIGITAL) LOOPBACK This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8091MNX/RNB and the external MAC, and is supported for both speeds (10/100 Mbps) at full-duplex. The loopback data path is shown in Figure 3-8. 1. 2. 3. 4. The MII/RMII MAC transmits frames to the KSZ8091MNX/RNB. Frames are wrapped around inside the KSZ8091MNX/RNB. The KSZ8091MNX/RNB transmits frames back to the MII/RMII MAC. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port. 2016 Microchip Technology Inc. DS00002275A-page 27 KSZ8091MNX/RNB FIGURE 3-8: LOCAL (DIGITAL) LOOPBACK KSZ8091MNX/RNB AFE PCS (ANALOG) (DIGITAL) MII/ RMII MII/RMII MAC The following programming action and register settings are used for local loopback mode: For 10/100 Mbps loopback: Set Register 0h, Bit [14] = 1 // Enable local loopback mode Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed Bit [12] = 0 // Disable auto-negotiation Bit [8] = 1 // Select full-duplex mode 3.8.2 REMOTE (ANALOG) LOOPBACK This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive data paths between the KSZ8091MNX/RNB and its link partner, and is supported for 100BASE-TX full-duplex mode only. The loopback data path is shown in Figure 3-9. 1. 2. 3. The Fast Ethernet (100BASE-TX) PHY link partner transmits frames to the KSZ8091MNX/RNB. Frames are wrapped around inside the KSZ8091MNX/RNB. The KSZ8091MNX/RNB transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner. DS00002275A-page 28 2016 Microchip Technology Inc. KSZ8091MNX/RNB FIGURE 3-9: REMOTE (ANALOG) LOOPBACK KSZ8091MNX/RNB RJ-45 AFE (ANALOG) PCS (DIGITAL) MII/ RMII CAT-5 (UTP) RJ-45 100BASE-TX LINK PARTNER The following programming steps and register settings are used for remote loopback mode: 1. Set Register 0h, Bits [13] = 1 // Select 100 Mbps speed Bit [12] = 0 // Disable auto-negotiation Bit [8] = 1 // Select full-duplex mode Or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner. 2. Set Register 1Fh, Bit [2] = 1 // Enable remote loopback mode LinkMD(R) Cable Diagnostic 3.9 The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems. These include open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a numerical value that can be translated to a cable distance. LinkMD is initiated by accessing register 1Dh, the LinkMD Cable Diagnostic register, in conjunction with Register 1Fh, the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the cable differential pair for testing. 3.9.1 USAGE The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh: 1. 2. 3. 4. Disable auto MDI/MDI-X by writing a `1' to Register 1Fh, bit [13]. Start cable diagnostic test by writing a `1' to Register 1Dh, bit [15]. This enable bit is self-clearing. Wait (poll) for Register 1Dh, bit [15] to return a `0', and indicating cable diagnostic test is completed. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 2016 Microchip Technology Inc. DS00002275A-page 29 KSZ8091MNX/RNB 11 = cable diagnostic test failed (invalid test) The `11' case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38. The distance to the cable fault can be determined by the following formula: EQUATION 3-1: * D Dis tan ce to cable fault in meters = 0.38 Register 1Dh, bits[8:0] Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38. The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. 3.10 NAND Tree Support The KSZ8091MNX/RNB provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND tree is a chain of nested NAND gates in which each KSZ8091MNX/RNB digital I/O (NAND tree input) pin is an input to one NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the nested NAND gates. The NAND tree test process includes: * * * * Enabling NAND tree mode Pulling all NAND tree input pins high Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input driven low Table 3-7 and Table 3-8 list the NAND tree pin orders for KSZ8091MNX and KSZ8091RNB, respectively. TABLE 3-7: NAND TREE TEST PIN ORDER FOR KSZ8091MNX Pin Number Pin Name NAND Tree Description 11 MDIO Input 12 MDC Input 13 RXD3 Input 14 RXD2 Input 15 RXD1 Input 16 RXD0 Input 18 RXDV Input 18 RXC Input 20 RXER Input 21 INTRP Input 22 TXC Input 23 TXEN Input 24 TXD0 Input 25 TXD1 Input 26 TXD2 Input 27 TXD3 Input DS00002275A-page 30 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 3-7: Pin Number Pin Name NAND Tree Description 30 LED0 Input TABLE 3-8: 3.10.1 NAND TREE TEST PIN ORDER FOR KSZ8091MNX (CONTINUED) 28 COL Input 29 CRS Output NAND TREE TEST PIN ORDER FOR KSZ8091RNB Pin Number Pin Name NAND Tree Description 11 MDIO Input 12 MDC Input 15 RXD1 Input 16 RXD0 Input 18 CRS_DV Input 19 REF_CLK Input 20 RXER Input 21 INTRP Input 22 PME_EN Input 23 TXEN Input 24 TXD0 Input 25 TXD1 Input 30 LED0 Input 31 LED1 Input 28 CONFIG0 Input 29 CONFIG1 Output NAND TREE I/O TESTING Use the following procedure to check for faults on the KSZ8091MNX/RNB digital I/O pin connections to the board: 1. 2. 3. Enable NAND tree mode using either a hardware strap-in pin (NAND_Tree#, Pin 21) or software (Register 16h, Bit [5]). Use board logic to drive all KSZ8091MNX/RNB NAND tree input pins high. Use board logic to drive each NAND tree input pin, in KSZ8091MNX/RNB NAND tree pin order, as follows: a) Toggle the first pin (MDIO) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to indicate that the first pin is connected properly. b) Leave the first pin (MDIO) low. c) Toggle the second pin (MDC) from high to low, and verify that the CRS/CONFIG1 pin switches from low to high to indicate that the second pin is connected properly. d) Leave the first pin (MDIO) and the second pin (MDC) low. e) Toggle the third pin (RXD3/PHYAD0) from high to low, and verify that the CRS/CONFIG1 pin switches from high to low to indicate that the third pin is connected properly. f) Continue with this sequence until all KSZ8091MNX/RNB NAND tree input pins have been toggled. Each KSZ8091MNX/RNB NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or lowto-high to indicate a good connection. If the CRS/CONFIG1 pin fails to toggle when the KSZ8091MNX/RNB input pin toggles from high to low, the input pin has a fault. 3.11 Power Management The KSZ8091MNX/RNB incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections. 2016 Microchip Technology Inc. DS00002275A-page 31 KSZ8091MNX/RNB 3.11.1 POWER-SAVING MODE Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by writing a `1' to Register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). In this mode, the KSZ8091MNX/RNB shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL circuits. By default, power-saving mode is disabled after power-up. 3.11.2 ENERGY-DETECT POWER-DOWN MODE Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is unplugged. It is enabled by writing a `0' to Register 18h, bit [11], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). EDPD mode works with the PLL off (set by writing a `1' to Register 10h, bit [4] to automatically turn the PLL off in EDPD mode) to turn off all KSZ8091MNX/RNB transceiver blocks except the transmitter and energy-detect circuits. Power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8091MNX/RNB and its link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable is connected between them. By default, energy-detect power-down mode is disabled after power-up. 3.11.3 POWER-DOWN MODE Power-down mode is used to power down the KSZ8091MNX/RNB device when it is not in use after power-up. It is enabled by writing a `1' to Register 0h, bit [11]. In this mode, the KSZ8091MNX/RNB disables all internal functions except the MII management interface. The KSZ8091MNX/RNB exits (disables) power-down mode after Register 0h, bit [11] is set back to `0'. 3.11.4 SLOW-OSCILLATOR MODE Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (pin 9) and select the on-chip slow oscillator when the KSZ8091MNX/RNB device is not in use after power-up. It is enabled by writing a `1' to Register 11h, bit [5]. Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8091MNX/RNB device in the lowest power state, with all internal functions disabled except the MII management interface. To properly exit this mode and return to normal PHY operation, use the following programming sequence: 1. 2. 3. Disable slow-oscillator mode by writing a `0' to Register 11h, Bit [5]. Disable power-down mode by writing a `0' to Register 0h, Bit [11]. Initiate software reset by writing a `1' to Register 0h, Bit [15]. DS00002275A-page 32 2016 Microchip Technology Inc. KSZ8091MNX/RNB 3.12 Energy Efficient Ethernet (EEE) The KSZ8091MNX implements Energy Efficient Ethernet (EEE) for the Media Independent Interface (MII) as described in IEEE Standard 802.3az. The Standard is defined around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that support special signaling associated with EEE. EEE saves power by keeping the AC signal on the copper Ethernet cable at approximately 0V peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up status. This is referred to as low-power idle (LPI) mode or state. Similarly, the KSZ8091RNB implements EEE for the Reduced Media Independent Interface (RMII) as described in IEEE Standard 802.3az for line signaling by the two differential pairs (analog side) and according to the multi-source agreement (MSA) of collaborating Fast Ethernet chip vendors for the RMII (digital side). This agreement is based on the IEEE Standard's EEE implementation for MII (100 Mbps). During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation immediately, without blockage of traffic or loss of packet. This involves exiting LPI mode and returning to normal 100 Mbps operating mode. Wake-up time is <30 s for 100BASE-TX. The LPI state is controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for: * Transmit cable path only * Receive cable path only * Both transmit and receive cable paths The KSZ8091MNX/RNB has the EEE function disabled as the power-up default setting. To enable the EEE function for 100 Mbps mode, use the following programming sequence: 1. 2. Enable 100 Mbps EEE mode advertisement by writing a `1' to MMD address 7h, Register 3Ch, bit [1]. Restart auto-negotiation by writing a `1' to standard Register 0h, bit [9]. For standard (non-EEE) 10BASE-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are used to maintain the link during the idle period when there is no traffic activity. To save more power, the KSZ8091MNX/ RNB provides the option to enable 10BASE-Te mode, which saves additional power by reducing the transmitted signal amplitude from 2.5V to 1.75V. To enable 10BASE-Te mode, write a `1' to standard Register 13h, bit [4]. During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approximately every 20 to 22 milliseconds, a refresh transmission of 200 to 220 microseconds is sent to the link partner. The refresh transmissions and quiet periods are shown in Figure 3-10. LPI MODE (REFRESH TRANSMISSIONS AND QUIET PERIODS) TR DATA/ IDLE TQ QUIET IDLE TS QUIET ACTIVE WAKE QUIET REFRESH LOW-POWER SLEEP DATA/ IDLE ACTIVE REFRESH FIGURE 3-10: TW_PHY TW_SYSTEM 3.12.1 TRANSMIT DIRECTION CONTROL (MAC-TO-PHY) The KSZ8091MNX enters LPI mode for the transmit direction when its attached EEE-compliant MII MAC de-asserts TXEN, asserts TXER, and sets TXD[3:0] to 0001. The KSZ8091MNX remains in the LPI transmit state while the MAC maintains the states of these signals. When the MAC changes any of the TXEN, TXER, or TX data signals from their LPI state values, the KSZ8091MNX exits the LPI transmit state. The TXC clock is not stopped, because it is sourced from the PHY and is used by the MAC for MII transmit. Figure 3-11 shows the LPI transition for MII (100 Mbps) transmit. 2016 Microchip Technology Inc. DS00002275A-page 33 KSZ8091MNX/RNB FIGURE 3-11: LPI TRANSITION - MII (100 MBPS) TRANSMIT TXC TXEN 0001 TXD[3:0] WAKE TIME ENTER LOW POWER STATE TXER EXIT LOW POWER STATE Similarly, the KSZ8091RNB enters LPI mode for the transmit direction when its attached EEE-compliant RMII MAC deasserts TXEN and sets TXD [1:0] to 01. The KSZ8091RNB remains in the LPI transmit state while the RMII MAC maintains the states of these signals. When the RMII MAC changes any of the TXEN or TX data signals from their LPI state values, the KSZ8091RNB exits the LPI transmit state. Figure 3-12 shows the LPI transition for RMII (100 Mbps) transmit. FIGURE 3-12: LPI TRANSITION - RMII (100 MBPS) TRANSMIT REF_CLK TXEN TXD[1:0] XX XX 00 01 00 01 DATA IDLE ASSERT LPI IDLE PREAMBLE WAKE TIME 3.12.2 RECEIVE DIRECTION CONTROL (PHY-TO-MAC) The KSZ8091MNX enters LPI mode for the receive direction when it receives the /P/ code bit pattern (Sleep/Refresh) from its EEE-compliant link partner. It then de-asserts RXDV, asserts RXER, and drives RXD[3:0] to 0001. The KSZ8091MNX remains in the LPI receive state while it continues to receive the refresh from its link partner, so it will continue to maintain and drive the LPI output states for the MII receive signals to inform the attached EEE-compliant MII MAC that it is in the LPI receive state. When the KSZ8091MNX receives a non /P/ code bit pattern (non-refresh), it exits the LPI receive state and sets the RXDV, RXER, and RX data signals to set a normal frame or normal idle. The KSZ8091MNX stops the RXC clock output to the MAC after nine or more RXC clock cycles have occurred in the LPI receive state, to save more power. By default, RXC clock stoppage is enabled. It is disabled by writing a `0' to MMD address 3h, Register 0h, Bit [10]. Figure 3-13 shows the LPI transition for MII (100 Mbps) receive. DS00002275A-page 34 2016 Microchip Technology Inc. KSZ8091MNX/RNB FIGURE 3-13: LPI TRANSITION - MII (100 MBPS) RECEIVE 9 CYCLES RXC RX_DV RXD[3:0] XX XX XX 0001 XX XX XX XX ENTER LOW POWER STATE RXER EXIT LOW POWER STATE Similarly, the KSZ8091RNB enters LPI mode for the receive direction when it receives the /P/ code bit pattern (Sleep/ Refresh) from its EEE-compliant link partner. It then de-asserts CRS_DV and drives RXD[1:0] to 01. The KSZ8091RNB remains in the LPI receive state while it continues to receive the refresh from its link partner, so it will continue to maintain and drive the LPI output states for the RMII receive signals to inform the attached EEE-compliant RMII MAC that it is in the LPI receive state. When the KSZ8091RNB receives a non /P/ code bit pattern (non-refresh), it exits the LPI receive state and sets the CRS_DV and RX data signals to set a normal frame or normal idle. Figure 3-14 shows the LPI transition for RMII (100 Mbps) receive. FIGURE 3-14: LPI TRANSITION - RMII (100 MBPS) RECEIVE REF_CLK CRS_DV RXD[1:0] 3.12.3 XX XX 00 01 00 01 DATA IDLE ASSERT LPI IDLE PREAMBLE REGISTERS ASSOCIATED WITH EEE The following registers are provided for EEE configuration and management: * * * * * * Standard Register 13h - AFE Control 4 (to enable 10BASE-Te mode) MMD address 1h, Register 0h - PMA/PMD Control 1 (to enable LPI) MMD address 1h, Register 1h - PMA/PMD Status 1 (for LPI status) MMD address 3h, Register 0h - EEE PCS Control 1 (to stop RXC clock for KSZ8091MNX only) MMD address 7h, Register 3Ch - EEE Advertisement MMD address 7h, Register 3Dh - EEE Link Partner Advertisement 2016 Microchip Technology Inc. DS00002275A-page 35 KSZ8091MNX/RNB 3.13 Wake-On-LAN Wake-On-LAN (WOL) is normally a MAC-based function to wake up a host system (for example, an Ethernet end device, such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet (commonly referred to as the "magic packet") that is sent by the remote link partner. The KSZ8091MNX/RNB can perform the same WOL function if the MAC address of its associated MAC device is entered into the KSZ8091MNX/RNB PHY registers for magic-packet detection. When the KSZ8091MNX/RNB detects the magic packet, it wakes up the host by driving its power management event (PME) output pin low. By default, the WOL function is disabled. It is enabled by setting the enabling bit and configuring the associated registers for the selected PME wake-up detection method. The KSZ8091MNX/RNB provides three methods to trigger a PME wake-up: * Magic-packet detection * Customized-packet detection * Link status change detection 3.13.1 MAGIC-PACKET DETECTION The magic packet's frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of its associated MAC device (local MAC device). When the magic packet is detected from its link partner, the KSZ8091MNX/RNB asserts its PME output pin low. The following MMD address 1Fh registers are provided for magic-packet detection: * Magic-packet detection is enabled by writing a `1' to MMD address 1Fh, Register 0h, bit [6] * The MAC address (for the local MAC device) is written to and stored in MMD address 1Fh, Registers 19h - 1Bh The KSZ8091MNX/RNB does not generate the magic packet. The magic packet must be provided by the external system. 3.13.2 CUSTOMIZED-PACKET DETECTION The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet to use in the CRC calculation. After the KSZ8091MNX/RNB receives the packet from its link partner, the selected bytes for the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that was previously written to and stored in the KSZ8091MNX/RNB PHY Registers. If there is a match, the KSZ8091MNX/RNB asserts its PME output pin low. Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used to configure and enable each customized packet. The following MMD Registers are provided for customized-packet detection: * Each of the four customized packets is enabled via MMD address 1Fh, Register 0h, - Bit [2] // For customized packets, type 0 - Bit [3] // For customized packets, type 1 - Bit [4] // For customized packets, type 2 - Bit [5] // For customized packets, type 3 * Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in: - MMD address 1Fh, Registers 1h - 4h // For customized packets, type 0 - MMD address 1Fh, Registers 7h - Ah // For customized packets, type 1 - MMD address 1Fh, Registers Dh - 10h // For customized packets, type 2 - MMD address 1Fh, Registers 13h - 16h // For customized packets, type 3 * 32-bit expected CRCs are written to and stored in: - MMD address 1Fh, Registers 5h - 6h // For customized packets, type 0 - MMD address 1Fh, Registers Bh - Ch // For customized packets, type 1 - MMD address 1Fh, Registers 11h - 12h // For customized packets, type 2 - MMD address 1Fh, Registers 17h - 18h // For customized packets, type 3 DS00002275A-page 36 2016 Microchip Technology Inc. KSZ8091MNX/RNB 3.13.3 LINK STATUS CHANGE DETECTION If link status change detection is enabled, the KSZ8091MNX/RNB asserts its PME output pin low whenever there is a link status change, using the following MMD address 1Fh register bits and their enabled (1) or disabled (0) settings: * MMD address 1Fh, Register 0h, bit [0] // For link-up detection * MMD address 1Fh, Register 0h, bit [1] // For link-down detection The PME output signal is available on either INTRP/PME_N2 (pin 21) or LED0/PME_N1 (pin 30), and is enabled using standard Register 16h, bit [15]. MMD address 1Fh, Register 0h, bits [15:14] defines and selects the output functions for pins 21 and 30. The PME output is active low and requires a 1 k pull-up to the VDDIO supply. When asserted, the PME output is cleared by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status change). 3.14 Reference Circuit for Power and Ground Connections The KSZ8091MNX/RNB is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and ground connections are shown in Figure 3-15 and Table 3-9 for 3.3V VDDIO. FIGURE 3-15: KSZ8091MNX/RNB POWER AND GROUND CONNECTIONS FERRITE BEAD 2 3 22F VDD_1.2 2.2F 0.1F VDDA_3.3 0.1F KSZ8091MNX/RNB 3.3V 17 22F VDDIO 0.1F GND 1 PADDLE TABLE 3-9: KSZ8091MNX/RNB POWER PIN DESCRIPTION Power Pin Pin Number Description VDD_1.2 2 Decouple with 2.2 F and 0.1 F capacitors to ground. VDDA_3.3 3 Connect to board's 3.3V supply through a ferrite bead. Decouple with 22 F and 0.1 F capacitors to ground. VDDIO 17 Connect to board's 3.3V supply for 3.3V VDDIO. Decouple with 22 F and 0.1 F capacitors to ground. 2016 Microchip Technology Inc. DS00002275A-page 37 KSZ8091MNX/RNB 3.15 Typical Current/Power Consumption Table 3-10, Table 3-11, and Table 3-12 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O (VDDIO) power pins, and typical values for power consumption by the KSZ8091MNX/RNB device for the indicated nominal operating voltages. These current and power consumption values include the transmit driver current and on-chip regulator current for the 1.2V core. TABLE 3-10: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V) Condition 3.3V Transceiver (VDDA_3.3) 3.3V Digital I/Os (VDDIO) 100BASE-TX Link-up (no traffic) 34 mA 12 mA 152 mW 100BASE-TX Full-duplex @ 100% utilization 34 mA 13 mA 155 mW Total Chip Power 10BASE-T Link-up (no traffic) 14 mA 11 mA 82.5 mW 10BASE-T Full-duplex @ 100% utilization 30 mA 11 mA 135 mW EEE 100 Mbps Link-up mode (transmit and receive in LPI state with no traffic) 13 mA 10 mA 75.9 mW Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 mA 10 mA 75.9 mW EDPD mode (Reg. 18h, Bit [11] = 0) 10 mA 10 mA 66 mW EDPD mode (Reg. 18h, Bit [11] = 0) and PLL off (Reg. 10h, Bit [4] = 1) 3.77 mA 1.54 mA 17.5 mW Software power-down mode (Reg. 0h, Bit [11] =1) 2.59 mA 1.51 mA 13.5 mW Software power-down mode (Reg. 0h, Bit [11] =1) and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.36 mA 0.45 mA 5.97 mW TABLE 3-11: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V) Condition 3.3V Transceiver (VDDA_3.3) 2.5V Digital I/Os (VDDIO) Total Chip Power 100BASE-TX Link-up (no traffic) 34 mA 11 mA 140 mW 100BASE-TX Full-duplex @ 100% utilization 34 mA 12 mA 142 mW 10BASE-T Link-up (no traffic) 15 mA 10 mA 74.5 mW 10BASE-T Full-duplex @ 100% utilization 27 mA 10 mA 114 mW EEE 100 Mbps Link-up mode (transmit and receive in LPI state with no traffic) 13 mA 10 mA 67.9 mW Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 mA 10 mA 67.9 mW EDPD mode (Reg. 18h, Bit [11] = 0) 11 mA 10 mA 61.3 mW EDPD mode (Reg. 18h, Bit [11] = 0) and PLL off (Reg. 10h, Bit [4] = 1) 3.55 mA 1.35 mA 15.1 mW Software power-down mode (Reg. 0h, Bit [11] =1) 2.29 mA 1.34 mA 10.9 mW Software power-down mode (Reg. 0h, Bit [11] =1) and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.15 mA 0.29 mA 4.52 mW TABLE 3-12: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V) Condition 3.3V Transceiver (VDDA_3.3) 1.8V Digital I/Os (VDDIO) Total Chip Power 100BASE-TX Link-up (no traffic) 100BASE-TX Full-duplex @ 100% utilization 34 mA 11 mA 132 mW 34 mA 12 mA 134 mW 10BASE-T Link-up (no traffic) 15 mA 9 mA 65.7 mW 10BASE-T Full-duplex @ 100% utilization 27 mA 9 mA 105 mW DS00002275A-page 38 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 3-12: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V) 3.3V Transceiver (VDDA_3.3) 1.8V Digital I/Os (VDDIO) Total Chip Power EEE 100 Mbps Link-up mode (transmit and receive in LPI state with no traffic) 13 mA 9 mA 59.1 mW Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 mA 9 mA 59.1 mW Condition EDPD mode (Reg. 18h, Bit [11] = 0) 11 mA 9 mA 52.5 mW EDPD mode (Reg. 18h, Bit [11] = 0) and PLL off (Reg. 10h, Bit [4] = 1) 4.05 mA 1.21 mA 15.5 mW Software power-down mode (Reg. 0h, Bit [11] =1) 2.79 mA 1.21 mA 11.4 mW Software power-down mode (Reg. 0h, Bit [11] =1) and slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.65 mA 0.19 mA 5.79 mW 2016 Microchip Technology Inc. DS00002275A-page 39 KSZ8091MNX/RNB 4.0 REGISTER DESCRIPTIONS The register space within the KSZ8091MNX/RNB consists of two distinct areas. * Standard registers * MDIO manageable device (MMD) registers // Direct register access // Indirect register access The KSZ8091MNX/RNB supports the following standard registers. 4.1 Register Map TABLE 4-1: STANDARD REGISTERS SUPPORTED BY KSZ8091MNX/RNB Register Number (hex) Description IEEE Defined Registers 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Auto-Negotiation Link Partner Next Page Ability 9h - Ch Reserved Dh MMD Access - Control Eh MMD Access - Register/Data Fh Reserved Vendor Specific Registers 10h Digital Reserved Control 11h AFE Control 1 12h Reserved 13h AFE Control 4 14h Reserved 15h RXER Counter 16h Operation Mode Strap Override 17h Operation Mode Strap Status 18h Expanded Control 19h - 1Ah Reserved 1Bh Interrupt Control/Status 1Ch Reserved 1Dh LinkMD Cable Diagnostic 1Eh PHY Control 1 1Fh PHY Control 2 DS00002275A-page 40 2016 Microchip Technology Inc. KSZ8091MNX/RNB The KSZ8091MNX/RNB supports the following MMD device addresses and their associated register addresses, which make up the indirect MMD registers. TABLE 4-2: MMD REGISTERS SUPPORTED BY KSZ8091MNX/RNB Device Address (Hex) 1h 3h 7h 1Fh Register Address (Hex) Description 0h PMA/PMD Control 1 1h PMA/PMD Status 1 0h EEE PCS Control 1 3Ch EEE Advertisement 3Dh EEE Link Partner Advertisement 0h Wake-On-LAN - Control 1h Wake-On-LAN - Customized Packet, Type 0, Mask 0 2h Wake-On-LAN - Customized Packet, Type 0, Mask 1 3h Wake-On-LAN - Customized Packet, Type 0, Mask 2 4h Wake-On-LAN - Customized Packet, Type 0, Mask 3 5h Wake-On-LAN - Customized Packet, Type 0, Expected CRC 0 6h Wake-On-LAN - Customized Packet, Type 0, Expected CRC 1 7h Wake-On-LAN - Customized Packet, Type 1, Mask 0 8h Wake-On-LAN - Customized Packet, Type 1, Mask 1 9h Wake-On-LAN - Customized Packet, Type 1, Mask 2 Ah Wake-On-LAN - Customized Packet, Type 1, Mask 3 Bh Wake-On-LAN - Customized Packet, Type 1, Expected CRC 0 Ch Wake-On-LAN - Customized Packet, Type 1, Expected CRC 1 Dh Wake-On-LAN - Customized Packet, Type 2, Mask 0 Eh Wake-On-LAN - Customized Packet, Type 2, Mask 1 Fh Wake-On-LAN - Customized Packet, Type 2, Mask 2 10h Wake-On-LAN - Customized Packet, Type 2, Mask 3 11h Wake-On-LAN - Customized Packet, Type 2, Expected CRC 0 12h Wake-On-LAN - Customized Packet, Type 2, Expected CRC 1 13h Wake-On-LAN - Customized Packet, Type 3, Mask 0 14h Wake-On-LAN - Customized Packet, Type 3, Mask 1 15h Wake-On-LAN - Customized Packet, Type 3, Mask 2 16h Wake-On-LAN - Customized Packet, Type 3, Mask 3 17h Wake-On-LAN - Customized Packet, Type 3, Expected CRC 0 18h Wake-On-LAN - Customized Packet, Type 3, Expected CRC 1 19h Wake-On-LAN - Magic Packet, MAC-DA-0 1Ah Wake-On-LAN - Magic Packet, MAC-DA-1 1Bh Wake-On-LAN - Magic Packet, MAC-DA-2 2016 Microchip Technology Inc. DS00002275A-page 41 KSZ8091MNX/RNB 4.2 Standard Registers Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE 802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor. TABLE 4-3: Address IEEE DEFINED REGISTER DESCRIPTIONS Name Description Mode Note 4-1 Default Register 0h - Basic Control 0.15 Reset 1 = Software reset 0 = Normal operation This bit is self-cleared after a `1' is written to it. RW/SC 0 0.14 Loopback 1 = Loopback mode 0 = Normal operation RW 0 RW Set by the SPEED strapping pin (KSZ8091RNB only). See the Strap-In Options KSZ8091RNB section for details. 0.13 1 = 100 Mbps 0 = 10 Mbps Speed Select This bit is ignored if auto-negotiation is enabled (Register 0.12 = 1). Set by the NWAYEN strapping pin. See the Strap-In Options KSZ8091MNX section for details. 1 = Enable auto-negotiation process 0 = Disable auto-negotiation process RW If enabled, the auto-negotiation result overrides the settings in Registers 0.13 and 0.8. 0.12 Auto-Negotiation Enable 0.11 1 = Power-down mode 0 = Normal operation If software reset (Register 0.15) is used to exit power-down mode (Register 0.11 = 1), two softPower-Down ware reset writes (Register 0.15 = 1) are required. The first write clears power-down mode; the second write resets the chip and re-latches the pin strapping pin values. 1 = Electrical isolation of PHY from MII 0 = Normal operation 0.10 Isolate 0.9 1 = Restart auto-negotiation process Restart Auto0 = Normal operation. Negotiation This bit is self-cleared after a `1' is written to it. RW 0 RW Set by the ISO strapping pin. See the Strap-In Options KSZ8091MNX section for details. RW/SC 0 0.8 Duplex Mode 1 = Full-duplex 0 = Half-duplex RW The inverse of the DUPLEX strapping pin value. See the Strap-In Options KSZ8091MNX section for details. 0.7 Collision Test 1 = Enable COL test 0 = Disable COL test RW 0 0.6:0 Reserved Reserved RO 000_0000 DS00002275A-page 42 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 4-3: Address IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default Register 1h - Basic Status 1.15 100BASE-T4 1.14 1 = T4 capable 0 = Not T4 capable RO 0 100BASE-TX 1 = Capable of 100 Mbps full-duplex Full-Duplex 0 = Not capable of 100 Mbps full-duplex RO 1 1.13 100BASE-TX 1 = Capable of 100 Mbps half-duplex Half-Duplex 0 = Not capable of 100 Mbps half-duplex RO 1 1.12 10BASE-T Full-Duplex 1 = Capable of 10 Mbps full-duplex 0 = Not capable of 10 Mbps full-duplex RO 1 1.11 10BASE-T Half-Duplex 1 = Capable of 10 Mbps half-duplex 0 = Not capable of 10 Mbps half-duplex RO 1 1.10:7 Reserved Reserved RO 000_0 1.6 1 = Preamble suppression No Preamble 0 = Normal preamble RO 1 1.5 Auto-Negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RO 0 1.4 Remote Fault 1 = Remote fault 0 = No remote fault RO/LH 0 1.3 Auto-Negotiation Ability 1 = Can perform auto-negotiation 0 = Cannot perform auto-negotiation RO 1 1.2 Link Status 1 = Link is up 0 = Link is down RO/LL 0 1.1 Jabber Detect 1 = Jabber detected 0 = Jabber not detected (default is low) RO/LH 0 1.0 Extended Capability 1 = Supports extended capability registers RO 1 Register 2h - PHY Identifier 1 2.15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI). KENDIN ComRO munication's OUI is 0010A1 (hex). 0022h Register 3h - PHY Identifier 2 3.15:10 Assigned to the 19th through 24th bits of the OrgaPHY ID Numnizationally Unique Identifier (OUI). KENDIN Com- RO ber munication's OUI is 0010A1 (hex). 0001_01 3.9:4 Model Number Six-bit manufacturer's model number RO 01_0110 3.3:0 Revision Number Four-bit manufacturer's revision number RO Indicates silicon revision. Register 4h - Auto-Negotiation Advertisement 4.15 Next Page 1 = Next page capable 0 = No next page capability RW 1 4.14 Reserved Reserved RO 0 4.13 Remote Fault 1 = Remote fault supported 0 = No remote fault RW 0 4.12 Reserved Reserved RO 0 2016 Microchip Technology Inc. DS00002275A-page 43 KSZ8091MNX/RNB TABLE 4-3: Address IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description 4.11:10 Pause [00] = No pause [10] = Asymmetric pause [01] = Symmetric pause [11] = Asymmetric and symmetric pause RW 00 4.9 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 RW Set by the SPEED strapping pin (KSZ8091RNB only). See the Strap-In Options KSZ8091RNB section for details. 4.8 100BASE-TX 1 = 100 Mbps full-duplex capable Full-Duplex 0 = No 100 Mbps full-duplex capability Default 4.7 100BASE-TX 1 = 100 Mbps half-duplex capable Half-Duplex 0 = No 100 Mbps half-duplex capability RW Set by the SPEED strapping pin (KSZ8091RNB only). See the Strap-In Options KSZ8091RNB section for details. 4.6 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capability RW 1 4.5 10BASE-T Half-Duplex 1 = 10 Mbps half-duplex capable 0 = No 10 Mbps half-duplex capability RW 1 4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001 Register 5h - Auto-Negotiation Link Partner Ability 5.15 Next Page 1 = Next page capable 0 = No next page capability RO 0 5.14 Acknowledge 1 = Link code word received from partner 0 = Link code word not yet received RO 0 5.13 Remote Fault 1 = Remote fault detected 0 = No remote fault RO 0 5.12 Reserved Reserved RO 0 5.11:10 Pause [00] = No pause [10] = Asymmetric pause [01] = Symmetric pause [11] = Asymmetric and symmetric pause RO 00 5.9 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 5.8 100BASE-TX 1 = 100 Mbps full-duplex capable Full-Duplex 0 = No 100 Mbps full-duplex capability RO 0 5.7 100BASE-TX 1 = 100 Mbps half-duplex capable Half-Duplex 0 = No 100 Mbps half-duplex capability RO 0 5.6 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capability RO 0 5.5 10BASE-T Half-Duplex 1 = 10 Mbps half-duplex capable 0 = No 10 Mbps half-duplex capability RO 0 5.4:0 Selector Field [00001] = 802.3 after AN completes. RO 0_0000 DS00002275A-page 44 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 4-3: Address IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default Register 6h - Auto-Negotiation Expansion 6.15:5 Reserved Reserved RO 0000_0000_000 6.4 Parallel Detection Fault 1 = Fault detected by parallel detection 0 = No fault detected by parallel detection RO/LH 0 6.3 Link Partner Next Page Able 1 = Link partner has next page capability RO 0 = Link partner does not have next page capability 0 6.2 Next Page Able 1 = Local device has next page capability 0 = Local device does not have next page capability RO 1 6.1 Page Received 1 = New page received 0 = New page not received yet RO/LH 0 6.0 Link Partner Auto-Negotiation Able 1 = Link partner has auto-negotiation capability 0 = Link partner does not have auto-negotiation capability RO 0 Register 7h - Auto-Negotiation Next Page 7.15 Next Page 1 = Additional next pages will follow 0 = Last page RW 0 7.14 Reserved Reserved RO 0 7.13 Message Page 1 = Message page 0 = Unformatted page RW 1 7.12 Acknowledge2 1 = Will comply with message 0 = Cannot comply with message RW 0 7.11 Toggle 1 = Previous value of the transmitted link code word equaled logic 1 0 = Logic 0 RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 000_0000_0001 Register 8h - Link Partner Next Page Ability 8.15 Next Page 1 = Additional next pages will follow 0 = Last page RO 0 8.14 Acknowledge 1 = Successful receipt of link word 0 = No successful receipt of link word RO 0 8.13 Message Page 1 = Message page 0 = Unformatted page RO 0 8.12 Acknowledge2 1 = Can act on the information 0 = Cannot act on the information RO 0 8.11 Toggle 1 = Previous value of transmitted link code word equal to logic 0 0 = Previous value of transmitted link code word equal to logic 1 RO 0 8.10:0 Message Field 11-bit wide field to encode 2048 messages RO 000_0000_0000 2016 Microchip Technology Inc. DS00002275A-page 45 KSZ8091MNX/RNB TABLE 4-3: Address IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default Register Dh - MMD Access - Control D.15:14 MMD - Operation Mode For the selected MMD device address (bits [4:0] of this register), these two bits select one of the following register or data operations and the usage for MMD Access - Register/Data (Reg. Eh). RW 00 = Register 01 = Data, no post increment 10 = Data, post increment on reads and writes 11 = Data, post increment on writes only D.13:5 Reserved Reserved RW 00_0000_000 D.4:0 MMD - Device Address These five bits set the MMD device address. RW 0_0000 RW 0000_0000_0000_ 0000 00 Register Eh - MMD Access - Register/Data E.15:0 Note 4-1 TABLE 4-4: Address MMD - Register/ Data For the selected MMD device address (Reg. Dh, bits [4:0]), When Reg. Dh, bits [15:14] = 00, this register contains the read/write register address for the MMD device address. Otherwise, this register contains the read/write data value for the MMD device address and its selected register address. See also Reg. Dh, bits [15:14], for descriptions of post increment reads and writes of this register for data operation. RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low. VENDOR SPECIFIC REGISTER DESCRIPTIONS Name Description Mode Note 4-1 Default Register 10h - Digital Reserved Control 10.15:5 Reserved Reserved RW 0000_0000_000 10.4 PLL Off 1 = Turn PLL off automatically in EDPD mode 0 = Keep PLL on in EDPD mode. See also Register 18h, Bit [11] for EDPD mode RW 0 10.3:0 Reserved Reserved RW 0000 RW 0000_0000_00 Register 11h - AFE Control 1 11.15:6 Reserved 11.5 Slow-oscillator mode is used to disconnect the input reference crystal/clock on the XI pin and select the on-chip slow oscillator when the Slow-Oscilla- KSZ8091MNX/RNB device is not in use after tor Mode power-up. RW Enable 1 = Enable 0 = Disable This bit automatically sets software power-down to the analog side when enabled. 0 11.4:0 Reserved 0_0000 DS00002275A-page 46 Reserved Reserved RW 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 4-4: Address VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Note 4-1 Default Register 15h - RXER Counter 15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h PME Enable PME for Wake-on-LAN 1 = Enable 0 = Disable This bit works in conjunction with MMD Address 1Fh, Reg. 0h, Bits [15:14] to define the output for pins 21 and 30. RW Set by the PME_EN strapping pin. See the Strap-In Options KSZ8091MNX section for details. 16.14:11 Reserved Reserved RW 000_0 16.10 Reserved Reserved RO 0 16.9 BCAST_OFF Override 1 = Override strap-in for B-CAST_OFF If bit is `1', PHY Address 0 is non-broadcast. RW 0 16.8 Reserved Reserved RW 0 16.7 MII B-to-B Override 1 = Override strap-in for MII back-to-back mode (also set bit 0 of this register to `1') This bit applies only to KSZ8091MNX. RW 0 16.6 RMII B-to-B Override 1 = Override strap-in for RMII back-to-back mode (also set bit 1 of this register to `1') This bit applies only to KSZ8091RNB. RW 0 16.5 NAND Tree Override 1 = Override strap-in for NAND tree mode RW 0 16.4:2 Reserved Reserved RW 0_00 16.1 RMII Override 1 = Override strap-in for RMII mode This bit applies only to KSZ8091RNB. RW 0 16.0 MII Override 1 = Override strap-in for MII mode This bit applies only to KSZ8091MNX. RW 1 PHYAD[2:0] Strap-In Status [000] = Strap to PHY Address 0 [001] = Strap to PHY Address 1 [010] = Strap to PHY Address 2 [011] = Strap to PHY Address 3 [100] = Strap to PHY Address 4 [101] = Strap to PHY Address 5 [110] = Strap to PHY Address 6 [111] = Strap to PHY Address 7 RO -- 17.12:10 Reserved Reserved RO -- 17.9 BCAST_OFF Strap-In Status 1 = Strap to B-CAST_OFF If bit is `1', PHY Address 0 is non-broadcast. RO -- 17.8 Reserved Reserved RO -- 17.7 MII B-to-B Strap-In Status 1 = Strap to MII back-to-back mode This bit applies only to KSZ8091MNX. RO -- 17.6 RMII B-to-B Strap-In Status 1 = Strap to RMII back-to-back mode This bit applies only to KSZ8091RNB. RO -- Register 16h - Operation Mode Strap Override 16.15 Register 17h - Operation Mode Strap Status 17.15:13 2016 Microchip Technology Inc. DS00002275A-page 47 KSZ8091MNX/RNB TABLE 4-4: Address VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description 17.5 NAND Tree Strap-In Status 1 = Strap to NAND tree mode RO -- 17.4:2 Reserved Reserved RO -- 17.1 RMII Strap-In 1 = Strap to RMII mode Status This bit applies only to KSZ8091RNB. RO -- 17.0 MII Strap-In Status RO -- 1 = Strap to MII mode This bit applies only to KSZ8091MNX. Default Register 18h - Expanded Control 18.15:12 Reserved Reserved RW 0000 18.11 EDPD Disabled Energy-detect power-down mode 1 = Disable 0 = Enable See also Register 10h, Bit [4] for PLL off. RW 1 18.10 1 = MII output is random latency 0 = MII output is fixed latency 100BASE-TX For both settings, all bytes of received preamble Latency are passed to the MII output. This bit applies only to the KSZ8091MNX. RW 0 18.9:7 Reserved Reserved RW 00_0 18.6 10BASE-T Preamble Restore 1 = Restore received preamble to MII output 0 = Remove all seven bytes of preamble before sending frame (starting with SFD) to MII output This bit applies only to the KSZ8091MNX. RW 0 18.5:0 Reserved Reserved RW 00_0001 Register 1Bh - Interrupt Control/Status 1B.15 Jabber Interrupt Enable 1 = Enable jabber interrupt 0 = Disable jabber interrupt RW 0 1B.14 Receive Error Interrupt Enable 1 = Enable receive error interrupt 0 = Disable receive error interrupt RW 0 1B.13 Page Received Interrupt Enable 1 = Enable page received interrupt 0 = Disable page received interrupt RW 0 1B.12 Parallel Detect Fault Interrupt Enable 1 = Enable parallel detect fault interrupt 0 = Disable parallel detect fault interrupt RW 0 1B.11 Link Partner Acknowledge Interrupt Enable 1 = Enable link partner acknowledge interrupt 0 = Disable link partner acknowledge interrupt RW 0 1B.10 Link-Down Interrupt Enable 1= Enable link-down interrupt 0 = Disable link-down interrupt RW 0 1B.9 Remote Fault 1 = Enable remote fault interrupt Interrupt 0 = Disable remote fault interrupt Enable RW 0 DS00002275A-page 48 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 4-4: Address VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description 1B.8 Link-Up Interrupt Enable 1 = Enable link-up interrupt 0 = Disable link-up interrupt RW 0 1B.7 Jabber Interrupt 1 = Jabber occurred 0 = Jabber did not occur RO/SC 0 1B.6 Receive Error Interrupt 1 = Receive error occurred 0 = Receive error did not occur RO/SC 0 1B.5 Page Receive Interrupt 1 = Page receive occurred 0 = Page receive did not occur RO/SC 0 1B.4 Parallel Detect Fault Interrupt 1 = Parallel detect fault occurred 0 = Parallel detect fault did not occur RO/SC 0 1B.3 Link Partner Acknowledge Interrupt 1 = Link partner acknowledge occurred 0 = Link partner acknowledge did not occur RO/SC 0 1B.2 Link-Down Interrupt 1 = Link-down occurred 0 = Link-down did not occur RO/SC 0 1B.1 Remote Fault 1 = Remote fault occurred Interrupt 0 = Remote fault did not occur RO/SC 0 1B.0 Link-Up Interrupt RO/SC 0 1 = Link-up occurred 0 = Link-up did not occur Default Register 1Dh - LinkMD Control/Status 1D.15 Cable Diagnostic Test Enable 1 = Enable cable diagnostic test. After test has completed, this bit is self-cleared. 0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. RW/SC 0 1D.14:13 Cable Diagnostic Test Result [00] = Normal condition [01] = Open condition has been detected in cable [10] = Short condition has been detected in cable [11] = Cable diagnostic test has failed RO 00 1D.12 Short Cable Indicator 1 = Short cable (<10 meter) has been detected by LinkMD RO 0 1D.11:9 Reserved Reserved RW 000 1D.8:0 Cable Fault Counter Distance to fault RO 0_0000_0000 Register 1Eh - PHY Control 1 1E.15:10 Reserved Reserved RO 0000_00 1E.9 Enable Pause (Flow Control) 1 = Flow control capable 0 = No flow control capability RO 0 1E.8 Link Status 1 = Link is up 0 = Link is down RO 0 1E.7 Polarity Status 1 = Polarity is reversed 0 = Polarity is not reversed RO -- 1E.6 Reserved Reserved RO 0 2016 Microchip Technology Inc. DS00002275A-page 49 KSZ8091MNX/RNB TABLE 4-4: Address VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description 1E.5 MDI/MDI-X State 1 = MDI-X 0 = MDI RO -- 1E.4 Energy Detect 1 = Signal present on receive differential pair 0 = No signal detected on receive differential pair RO 0 1E.3 PHY Isolate 1 = PHY in isolate mode 0 = PHY in normal operation RW 0 Operation Mode Indication [000] = Still in auto-negotiation [001] = 10BASE-T half-duplex [010] = 100BASE-TX half-duplex [011] = Reserved [100] = Reserved [101] = 10BASE-T full-duplex [110] = 100BASE-TX full-duplex [111] = Reserved RO 000 1E.2:0 Default Register 1Fh - PHY Control 2 HP_MDIX 1 = HP Auto MDI/MDI-X mode 0 = Microchip Auto MDI/MDI-X mode RW 1 1F.14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 1 = MDI-X mode Transmit on RXP, RXM (Pins 5, 4) and Receive on TXP, TXM (Pins 7, 6) 0 = MDI mode Transmit on TXP, TXM (Pins 7, 6) and Receive on RXP, RXM (Pins 5, 4) RW 0 1F.13 Pair Swap Disable 1 = Disable Auto MDI/MDI-X 0 = Enable Auto MDI/MDI-X RW 0 1F.12 Reserved Reserved RW 0 1F.11 Force Link 1 = Force link pass 0 = Normal link operation RW This bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. 0 1F.10 Power Saving 1 = Enable power saving 0 = Disable power saving RW 0 1F.9 Interrupt Level 1 = Interrupt pin active high 0 = Interrupt pin active low RW 0 1F.8 Enable Jabber 1 = Enable jabber counter 0 = Disable jabber counter RW 1 1F.7 RMII Reference Clock Select 1 = RMII 50 MHz clock mode; clock input to XI (pin 9) is 50 MHz 0 = RMII 25 MHz clock mode; clock input to XI (pin RW 9) is 25 MHz This bit applies only to KSZ8091RNB. 0 1F.6 Reserved Reserved RW 0 1F.5:4 LED Mode [00] = LED1: Speed LED0: Link/Activity [01] = LED1: Activity LED0: Link [10], [11] = Reserved The LED1 pin applies only to the KSZ8091RNB. RW 00 1F.3 Disable Transmitter 1 = Disable transmitter 0 = Enable transmitter RW 0 1F.15 DS00002275A-page 50 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 4-4: Address VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED) Mode Note 4-1 Name Description 1F.2 Remote Loopback 1 = Remote (analog) loopback is enabled 0 = Normal mode RW 0 1F.1 Enable SQE Test 1 = Enable SQE test 0 = Disable SQE test RW 0 1F.0 Disable Data 1 = Disable scrambler Scrambling 0 = Enable scrambler RW 0 Note 4-1 4.3 Default RW = Read/Write; RO = Read Only; SC = Self-Cleared. MMD Registers MMD registers provide indirect read/write access to up to 32 MMD Device Addresses with each device supporting up to 65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. The KSZ8091MNX/RNB, however, uses only a small fraction of the available registers. See the Register Descriptions section for a list of supported MMD device addresses and their associated register addresses. The following two standard registers serve as the portal registers to access the indirect MMD registers. * Standard register Dh - MMD Access - Control * Standard register Eh - MMD Access - Register/Data TABLE 4-5: Address PORTAL REGISTERS (ACCESS TO INDIRECT MMD REGISTERS) Name Description Mode Default Register Dh - MMD Access - Control D.15:14 MMD - Operation Mode For the selected MMD device address (bits [4:0] of this register), these two bits select one of the following register or data operations and the usage for MMD Access - Register/Data (Reg. Eh). RW 00 = Register 01 = Data, no post increment 10 = Data, post increment on reads and writes 11 = Data, post increment on writes only D.13:5 Reserved Reserved RW 00_0000_000 D.4:0 MMD - Device Address These five bits set the MMD device address. RW 0_0000 RW 0000_0000_0000_ 0000 00 Register Eh - MMD Access - Register/Data E.15:0 MMD - Register/ Data For the selected MMD device address (Reg. Dh, bits [4:0]), When Reg. Dh, bits [15:14] = 00, this register contains the read/write register address for the MMD device address. Otherwise, this register contains the read/write data value for the MMD device address and its selected register address. See also Reg. Dh, bits [15:14], for descriptions of post increment reads and writes of this register for data operation. Examples: MMD Register Write Write MMD - Device Address 1Fh, Register 0h = 0001h to enable link-up detection to trigger PME for WOL. 2016 Microchip Technology Inc. DS00002275A-page 51 KSZ8091MNX/RNB 1. 2. 3. 4. Write Register Dh with 001Fh Write Register Eh with 0000h Write Register Dh with 401Fh Write Register Eh with 0001h // Set up register address for MMD - Device Address 1Fh. // Select register 0h of MMD - Device Address 1Fh. // Select register data for MMD - Device Address 1Fh, Register 0h. // Write value 0001h to MMD - Device Address 1Fh, Register 0h. MMD Register Read Read MMD - Device Address 1Fh, Register 19h - 1Bh for the magic packet's MAC address 1. 2. 3. Write Register Dh with 001Fh Write Register Eh with 0019h Write Register Dh with 801Fh 4. 5. 6. Read Register Eh Read Register Eh Read Register Eh TABLE 4-6: Address // Set up register address for MMD - Device Address 1Fh. // Select Register 19h of MMD - Device Address 1Fh. // Select register data for MMD - Device Address 1Fh, Register 19h // with post increments // Read data in MMD - Device Address 1Fh, Register 19h. // Read data in MMD - Device Address 1Fh, Register 1Ah. // Read data in MMD - Device Address 1Fh, Register 1Bh. MMD REGISTER DESCRIPTIONS Name Description Mode Default MMD Address 1h, Register 0h - PMA/PMD Control 1 1.0.15:13 Reserved Reserved RW 000 1.0.12 LPI enable Lower Power Idle enable RW 0 1.0.11:0 Reserved Reserved RW 0000_0000_0000 MMD Address 1h, Register 1h - PMA/PMD Status 1 1.1.15:9 Reserved Reserved RO 0000_000 1.1.8 LPI State Entered 1 = PMA/PMD has entered LPI state 0 = PMA/PMD has not entered LPI state RO/LH 0 1.1.7:4 Reserved Reserved RO 0000 1.1.3 LPI State Indication 1 = PMA/PMD is currently in LPI state 0 = PMA/PMD is currently not in LPI state RO 0 1.1.2:0 Reserved Reserved RO 000 MMD Address 3h, Register 0h - EEE PCS Control 1 3.0.15:12 Reserved Reserved RO 0000 3.0.11 Reserved Reserved RW 1 3.0.10 During receive lower-power idle mode, 100BASE-TX 1 = RXC clock is stoppable for 100BASE-TX RXC Clock 0 = RXC clock is not stoppable for 100BASE-TX Stoppable This bit applies only to KSZ8091MNX. RW 1 3.0.9:4 Reserved Reserved RW 00_0001 3.0.3:2 Reserved Reserved RO 00 3.0.1:0 Reserved Reserved RW 00 RO 0000_0000_0000_0 MMD Address 7h, Register 3Ch - EEE Advertisement 7.3C.15:3 Reserved Reserved 7.3C.2 1000BASE-T 0 = 1000 Mbps EEE is not supported EEE Capable RO 0 7.3C.1 1 = 100 Mbps EEE capable 0 = No 100 Mbps EEE capability 100BASE-TX This bit is set to `0' as the default after power-up or RW EEE Capable reset. Set this bit to `1' to enable 100 Mbps EEE mode. 0 7.3C.0 Reserved RO 0 RO 0000_0000_0000_0 Reserved MMD Address 7h, Register 3Dh - EEE Link Partner Advertisement 7.3D.15:3 Reserved DS00002275A-page 52 Reserved 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 7.3D.2 1000BASE-T 1 = 1000 Mbps EEE capable EEE Capable 0 = No 1000 Mbps EEE capability RO 0 7.3D.1 100BASE-TX 1 = 100 Mbps EEE capable EEE Capable 0 = No 100 Mbps EEE capability RO 0 7.3D.0 Reserved RO 0 Reserved MMD Address 1Fh, Register 0h - Wake-On-LAN - Control 1F.0.15:14 PME Output Select These two bits work in conjunction with Reg. 16h, Bit [15] for PME enable to define the output for pins 21 and 30. INTRP/PME_N2 (pin 21) 00 = INTRP output 01 = PME_N2 output 10 = INTRP and PME_N2 output RW 11 = Reserved LED0/PME_N1 (pin 30) 00 = PME_N1 output 01 = LED0 output 10 = LED0 output 11 = PME_N1 output 1F.0.13:7 Reserved Reserved 1F.0.6 Magic Packet 1 = Enable magic-packet detection Detect 0 = Disable magic-packet detection Enable RW 0 1F.0.5 CustomPacket Type 3 Detect Enable 1 = Enable custom-packet, Type 3 detection 0 = Disable custom-packet, Type 3 detection RW 0 1F.0.4 CustomPacket Type 2 Detect Enable 1 = Enable custom-packet, Type 2 detection 0 = Disable custom-packet, Type 2 detection RW 0 1F.0.3 CustomPacket Type 1 Detect Enable 1 = Enable custom-packet, Type 1 detection 0 = Disable custom-packet, Type 1 detection RW 0 1F.0.2 CustomPacket Type 0 Detect Enable 1 = Enable custom-packet, Type 0 detection 0 = Disable custom-packet, Type 0 detection RW 0 1F.0.1 Link-Down Detect Enable 1 = Enable link-down detection 0 = Disable link-down detection RW 0 1F.0.0 Link-Up Detect Enable 1 = Enable link-up detection 0 = Disable link-up detection RW 0 2016 Microchip Technology Inc. 00 RO 00_0000_0 DS00002275A-page 53 KSZ8091MNX/RNB TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default MMD Address 1Fh, Register 1h - Wake-On-LAN - Customized Packet, Type 0, Mask 0 MMD Address 1Fh, Register 7h - Wake-On-LAN - Customized Packet, Type 1, Mask 0 MMD Address 1Fh, Register Dh - Wake-On-LAN - Customized Packet, Type 2, Mask 0 MMD Address 1Fh, Register 13h - Wake-On-LAN - Customized Packet, Type 3, Mask 0 1F.1.15:0 1F.7.15:0 1F.D.15:0 1F.13.15:0 Custom Packet Type X Mask 0 This register selects the bytes in the first 16 bytes of the packet (bytes 1 thru 16) that will be used for CRC calculation. For each bit in this register, 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation The register-bit to packet-byte mapping is as follows: Bit [15]: byte-16 ... : ... Bit [1]: byte-2 Bit [0]: byte-1 0000_0000_0000_ 0000 RW MMD Address 1Fh, Register 2h - Wake-On-LAN - Customized Packet, Type 0, Mask 1 MMD Address 1Fh, Register 8h - Wake-On-LAN - Customized Packet, Type 1, Mask 1 MMD Address 1Fh, Register Eh - Wake-On-LAN - Customized Packet, Type 2, Mask 1 MMD Address 1Fh, Register 14h - Wake-On-LAN - Customized Packet, Type 3, Mask 1 1F.2.15:0 1F.8.15:0 1F.E.15:0 1F.14.15:0 Custom Packet Type X Mask 1 This register selects the bytes in the second 16 bytes of the packet (bytes 17 thru 32) that will be used for CRC calculation. For each bit in this register, 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation The register-bit to packet-byte mapping is as follows: Bit [15]: byte-32 ... : ... Bit [1]: byte-18 Bit [0]: byte-17 0000_0000_0000_ 0000 RW MMD Address 1Fh, Register 3h - Wake-On-LAN - Customized Packet, Type 0, Mask 2 MMD Address 1Fh, Register 9h - Wake-On-LAN - Customized Packet, Type 1, Mask 2 MMD Address 1Fh, Register Fh - Wake-On-LAN - Customized Packet, Type 2, Mask 2 MMD Address 1Fh, Register 15h - Wake-On-LAN - Customized Packet, Type 3, Mask 2 1F.3.15:0 1F.9.15:0 1F.F.15:0 1F.15.15:0 Custom Packet Type X Mask 2 DS00002275A-page 54 This register selects the bytes in the third 16 bytes of the packet (bytes 33 thru 48) that will be used for CRC calculation. For each bit in this register, 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation RW The register-bit to packet-byte mapping is as follows: Bit [15]: byte-48 ... : ... Bit [1]: byte-34 Bit [0]: byte-33 0000_0000_0000_ 0000 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default MMD Address 1Fh, Register 4h - Wake-On-LAN - Customized Packet, Type 0, Mask 3 MMD Address 1Fh, Register Ah - Wake-On-LAN - Customized Packet, Type 1, Mask 3 MMD Address 1Fh, Register 10h - Wake-On-LAN - Customized Packet, Type 2, Mask 3 MMD Address 1Fh, Register 16h - Wake-On-LAN - Customized Packet, Type 3, Mask 3 1F.4.15:0 1F.A.15:0 1F.10.15:0 1F.16.15:0 Custom Packet Type X Mask 3 This register selects the bytes in the fourth 16 bytes of the packet (bytes 49 thru 64) that will be used for CRC calculation. For each bit in this register, 1 = Byte is selected for CRC calculation 0 = Byte is not selected for CRC calculation RW The register-bit to packet-byte mapping is as follows: Bit [15]: byte-64 ... : ... Bit [1]: byte-50 Bit [0]: byte-49 0000_0000_0000_ 0000 MMD Address 1Fh, Register 5h - Wake-On-LAN - Customized Packet, Type 0, Expected CRC 0 MMD Address 1Fh, Register Bh - Wake-On-LAN - Customized Packet, Type 1, Expected CRC 0 MMD Address 1Fh, Register 11h - Wake-On-LAN - Customized Packet, Type 2, Expected CRC 0 MMD Address 1Fh, Register 17h - Wake-On-LAN - Customized Packet, Type 3, Expected CRC 0 1F.5.15:0 1F.B.15:0 1F.11.15:0 1F.17.15:0 Custom Packet Type X CRC 0 This register stores the lower two bytes for the expected CRC. Bit [15:8] = Byte 2 (CRC [15:8]) Bit [7:0] = Byte 1 (CRC [7:0]) The upper two bytes for the expected CRC are stored in the following register. RW 0000_0000_0000_ 0000 MMD Address 1Fh, Register 6h - Wake-On-LAN - Customized Packet, Type 0, Expected CRC 1 MMD Address 1Fh, Register Ch - Wake-On-LAN - Customized Packet, Type 1, Expected CRC 1 MMD Address 1Fh, Register 12h - Wake-On-LAN - Customized Packet, Type 2, Expected CRC 1 MMD Address 1Fh, Register 18h - Wake-On-LAN - Customized Packet, Type 3, Expected CRC 1 1F.6.15:0 1F.C.15:0 1F.12.15:0 1F.18.15:0 Custom Packet Type X CRC 1 This register stores the upper two bytes for the expected CRC. Bit [15:8] = Byte 4 (CRC [31:24]) Bit [7:0] = Byte 3 (CRC [23:16]) The lower two bytes for the expected CRC are stored in the previous register. RW 0000_0000_0000_ 0000 This register stores the lower two bytes of the destination MAC address for the magic packet. Magic Packet Bit [15:8] = Byte 2 (MAC Address [15:8]) RW MAC-DA-0 Bit [7:0] = Byte 1 (MAC Address [7:0]) The upper four bytes of the destination MAC address are stored in the following two registers. 0000_0000_0000_ 0000 MMD Address 1Fh, Register 19h - Wake-On-LAN - Magic Packet, MAC-DA-0 1F.19.15:0 MMD Address 1Fh, Register 1Ah - Wake-On-LAN - Magic Packet, MAC-DA-1 1F.1A.15:0 This register stores the middle two bytes of the destination MAC address for the magic packet. Bit [15:8] = Byte 4 (MAC Address [31:24]) Magic Packet Bit [7:0] = Byte 3 (MAC Address [23:16]) RW MAC-DA-1 The lower two bytes and upper two bytes of the destination MAC address are stored in the previous and following registers, respectively. 2016 Microchip Technology Inc. 0000_0000_0000_ 0000 DS00002275A-page 55 KSZ8091MNX/RNB TABLE 4-6: Address MMD REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default MMD Address 1Fh, Register 1Bh - Wake-On-LAN - Magic Packet, MAC-DA-2 1F.1B.15:0 Note 4-1 This register stores the upper two bytes of the destination MAC address for the magic packet. Magic Packet Bit [15:8] = Byte 6 (MAC Address [47:40]) RW MAC-DA-2 Bit [7:0] = Byte 5 (MAC Address [39:32]) The lower four bytes of the destination MAC address are stored in the previous two registers. 0000_0000_0000_ 0000 RW = Read/Write; RO = Read Only; LH = Latch High. DS00002275A-page 56 2016 Microchip Technology Inc. KSZ8091MNX/RNB 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VIN) (VDD_1.2).................................................................................................................................................... -0.5V to +1.8V (VDDIO, VDDA_3.3) ...................................................................................................................................... -0.5V to +5.0V Input Voltage (all inputs)............................................................................................................................ -0.5V to +5.0V Output Voltage (all outputs)....................................................................................................................... -0.5V to +5.0V Lead Temperature (soldering, 10s) ....................................................................................................................... +260C Storage Temperature (TS) ...................................................................................................................... -55C to +150C *Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. 5.2 Operating Ratings** Supply Voltage (VDDIO_3.3, VDDA_3.3) ........................................................................................................................ +3.135V to +3.465V (VDDIO_2.5) ........................................................................................................................................ +2.375V to +2.625V (VDDIO_1.8) ........................................................................................................................................ +1.710V to +1.890V Ambient Temperature (TA Commercial)........................................................................................................................................... 0C to +70C (TA Industrial) ........................................................................................................................................... -40C to +85C Maximum Junction Temperature (TJ max.) ........................................................................................................... +125C Thermal Resistance (JA)..............................................................................................................................+45.87C/W Thermal Resistance (JC) .............................................................................................................................+15.85C/W **The device is not guaranteed to function outside its operating ratings. Note: Do not drive input signals without power supplied to the device. 2016 Microchip Technology Inc. DS00002275A-page 57 KSZ8091MNX/RNB 6.0 ELECTRICAL CHARACTERISTICS TA = 25C. Specification is for packaged product only. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Note Supply Current (VDDIO, VDDA_3.3 = 3.3V), Note 6-1 10BASE-T IDD1_3.3V -- 41 -- mA Full-duplex traffic @ 100% utilization 100BASE-TX IDD2_3.3V -- 47 -- mA Full-duplex traffic @ 100% utilization EEE (100 Mbps) Mode IDD3_3.3V -- 23 -- mA TX and RX paths in LPI state with no traffic EDPD Mode IDD4_3.3V -- 20 -- mA Ethernet cable disconnected (Reg. 18h.11 = 0) Power-Down Mode IDD5_3.3V -- 4 -- mA Software power-down (Reg. 0h.11 = 1) 2.0 -- -- V VDDIO = 3.3V VIH 1.8 -- -- V VDDIO = 2.5V 1.3 -- -- V VDDIO = 1.8V -- -- 0.8 V VDDIO = 3.3V -- -- 0.7 V VDDIO = 2.5V -- -- 0.5 V VDDIO = 1.8V |IIN| -- -- 10 A VIN = GND ~ VDDIO 2.4 -- -- V VDDIO = 3.3V VOH 2.0 -- -- V VDDIO = 2.5V 1.5 -- -- V VDDIO = 1.8V -- -- 0.4 V VDDIO = 3.3V -- -- 0.4 V VDDIO = 2.5V -- -- 0.3 V VDDIO = 1.8V |IOZ| -- -- 10 A -- ILED -- 8 -- mA Each LED pin (LED0, LED1) CMOS Level Inputs Input High Voltage Input Low Voltage Input Current VIL CMOS Level Outputs Output High Voltage Output Low Voltage Output Tri-State Leakage VOL LED Output Output Drive Current All Pull-Up/Pull-Down Pins (including Strap-In Pins) Internal Pull-Up Resistance Internal Pull-Down Resistance pu pd 30 45 73 k VDDIO = 3.3V 39 61 102 k VDDIO = 2.5V 48 99 178 k VDDIO = 1.8V 26 43 79 k VDDIO = 3.3V 34 59 113 k VDDIO = 2.5V 53 99 200 k VDDIO = 1.8V 100BASE-TX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage VO 0.95 -- 1.05 V 100 termination across differential output Output Voltage Imbalance VIMB -- -- 2 % 100 termination across differential output Rise/Fall Time tr/tf 3 -- 5 ns -- Rise/Fall Time Imbalance -- 0 -- 0.5 ns -- Duty Cycle Distortion -- -- -- 0.25 ns -- Overshoot -- -- -- 5 % -- DS00002275A-page 58 2016 Microchip Technology Inc. KSZ8091MNX/RNB TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Parameters Symbol Min. Typ. Max. Units Note Output Jitter -- -- 0.7 -- ns Peak-to-peak 10BASE-T Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage VP 2.2 -- 2.8 V 100 termination across differential output Jitter Added -- -- -- 3.5 ns Peak-to-peak Rise/Fall Time tr/tf -- 25 -- ns -- VSQ -- 400 -- mV 5 MHz square wave VSET -- 0.65 -- V R(ISET) = 6.49 k -- -- 300 -- ps Peak-to-peak (Applies only to KSZ8091RNB in RMII - 25 MHz Clock Mode) ns XI (25 MHz clock input) to MII TXC (25 MHz clock output) delay, referenced to rising edges of both clocks. (Applies only to KSZ8091MNX in MII mode) s Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 00 (KSZ8091RNB only), Speed LED output changes from low (100 Mbps) to high (10 Mbps, default state for link-down). 2. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 3. INTRP pin asserts for link-down status change. 10BASE-T Receive Squelch Threshold Transmitter - Drive Setting Reference Voltage of ISET REF_CLK Output 50 Mhz RMII Clock Output Jitter 100 Mbps Mode - Industrial Applications Parameters Clock Phase Delay - XI Input to MII TXC Output Link Loss Reaction (Indication) Time Note 6-1 -- tllr 15 -- 20 4.4 25 -- Current consumption is for the single 3.3V supply KSZ8091MNX/RNB device only, and includes the transmit driver current and the 1.2V supply voltage (VDD_1.2) that are supplied by the KSZ8091MNX/ RNB. 2016 Microchip Technology Inc. DS00002275A-page 59 KSZ8091MNX/RNB 7.0 TIMING DIAGRAMS 7.1 MII SQE Timing (10BASE-T) FIGURE 7-1: MII SQE TIMING (10BASE-T) tWL TXC tWH tP TXEN tSQE COL TABLE 7-1: tSQEP MII SQE TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP TXC period -- 400 -- ns tWL TXC pulse width low -- 200 -- ns tWH TXC pulse width high -- 200 -- ns tSQE COL (SQE) delay after TXEN de-asserted -- 2.2 -- s tSQEP COL (SQE) pulse duration -- 1.0 -- s DS00002275A-page 60 2016 Microchip Technology Inc. KSZ8091MNX/RNB 7.2 MII Transmit Timing (10BASE-T) FIGURE 7-2: MII TRANSMIT TIMING (10BASE-T) tP tWL TXC tWH tSU2 TXEN TXD[3:0] tHD2 tSU1 tHD1 tCRS1 CRS TABLE 7-2: tCRS2 MII TRANSMIT TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP TXC period -- 400 -- ns tWL TXC pulse width low -- 200 -- ns tWH TXC pulse width high -- 200 -- ns tSU1 TXD[3:0] setup to rising edge of TXC 120 -- -- ns tSU2 TXEN setup to rising edge of TXC 120 -- -- ns tHD1 TXD[3:0] hold from rising edge of TXC 0 -- -- ns tHD2 TXEN hold from rising edge of TXC 0 -- -- ns tCRS1 TXEN high to CRS asserted latency -- 600 -- ns tCRS2 TXEN low to CRS de-asserted latency -- 1.0 -- s 2016 Microchip Technology Inc. DS00002275A-page 61 KSZ8091MNX/RNB 7.3 MII Receive Timing (10BASE-T) FIGURE 7-3: MII RECEIVE TIMING (10BASE-T) CRS tRLAT RXDV tOD RXD[3:0] RXER tP tWL RXC tWH TABLE 7-3: MII RECEIVE TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP RXC period -- 400 -- ns tWL RXC pulse width low -- 200 -- ns tWH RXC pulse width high -- 200 -- ns tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC -- 205 -- tRLAT CRS to (RXDV, RXD[3:0]) latency -- 7.2 -- DS00002275A-page 62 ns s 2016 Microchip Technology Inc. KSZ8091MNX/RNB 7.4 MII Transmit Timing (100BASE-TX) FIGURE 7-4: MII TRANSMIT TIMING (100BASE-TX) tWL TXC tSU2 TXEN tSU1 TXD[3:0] tHD2 tWH tP tHD1 DATA IN tCRS2 tCRS1 CRS TABLE 7-4: MII TRANSMIT TIMING (100BASE-TX) PARAMETERS Parameter Description Min. Typ. Max. Units tP TXC period -- 40 -- ns tWL TXC pulse width low -- 20 -- ns tWH TXC pulse width high -- 20 -- ns tSU1 TXD[3:0] setup to rising edge of TXC 10 -- -- ns tSU2 TXEN setup to rising edge of TXC 10 -- -- ns tHD1 TXD[3:0] hold from rising edge of TXC 0 -- -- ns tHD2 TXEN hold from rising edge of TXC 0 -- -- ns tCRS1 TXEN high to CRS asserted latency -- 72 -- ns tCRS2 TXEN low to CRS de-asserted latency -- 72 -- ns 2016 Microchip Technology Inc. DS00002275A-page 63 KSZ8091MNX/RNB 7.5 MII Receive Timing (100BASE-TX) FIGURE 7-5: MII RECEIVE TIMING (100BASE-TX) CRS tRLAT RXDV tOD RXD[3:0] RXER tWL RXC tWH tP TABLE 7-5: MII RECEIVE TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max. Units tP RXC period -- 40 -- ns tWL RXC pulse width low -- 20 -- ns tWH RXC pulse width high -- 20 -- ns tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC 16 21 25 tRLAT CRS to (RXDV, RXD[3:0]) latency -- 170 -- DS00002275A-page 64 ns ns 2016 Microchip Technology Inc. KSZ8091MNX/RNB 7.6 RMII Timing FIGURE 7-6: RMII TIMING - DATA RECEIVED FROM RMII TRANSMIT TIMING tCYC REF_CLK t1 t2 TXEN TXD[1:0] FIGURE 7-7: RMII TIMING - DATA INPUT TO RMII RECEIVE TIMING tCYC REF_CLK CRS_DV RXD[1:0] RXER tOD TABLE 7-6: RMII TIMING PARAMETERS - KSZ8091RNB (Note 7-1) Timing Parameter Description Min. Typ. Max. Units tCYC Clock cycle -- 20 -- ns t1 Setup time 4 -- -- ns t2 Hold time 2 -- -- ns tOD Note 7-1 Output delay 25 MHz input to XI pin, 50 MHz output from REF_CLK pin. 7 10 13 ns TABLE 7-7: RMII TIMING PARAMETERS - KSZ8091RNB (Note 7-1) Timing Parameter Description Min. Typ. Max. Units tCYC Clock cycle -- 20 -- ns t1 Setup time 4 -- -- ns t2 Hold time 2 -- -- ns tOD Note 7-1 Output delay 50 MHz input to XI pin. 8 11 13 ns 2016 Microchip Technology Inc. DS00002275A-page 65 KSZ8091MNX/RNB 7.7 Auto-Negotiation Timing FIGURE 7-8: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING AUTO -NEGOTIATION FAST LINK PULSE (FLP) TIMING FLP BURST FLP BURST TX+/TXtFLPW tBTB CLOCK PULSE DATA PULSE tPW tPW CLOCK PULSE DATA PULSE TX+/TX- tCTD tCTC TABLE 7-8: AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tBTB FLP burst to FLP burst 8 16 24 ms tFLPW FLP burst width -- 2 -- ms tPW Clock/Data pulse width -- 100 -- ns tCTD Clock pulse to data pulse 55.5 64 69.5 s tCTC Clock pulse to clock pulse 111 128 139 s -- Number of clock/data pulses per FLP burst 17 -- 33 -- DS00002275A-page 66 2016 Microchip Technology Inc. KSZ8091MNX/RNB 7.8 MDC/MDIO Timing FIGURE 7-9: MDC/MDIO TIMING tP MDC tMD1 MDIO (PHY INPUT) tMD2 VALID DATA VALID DATA tMD3 MDIO (PHY OUTPUT) TABLE 7-9: VALID DATA MDC/MDIO TIMING PARAMETERS Parameter Description Min. Typ. Max. Units fc MDC Clock Frequency -- 2.5 10 MHz tP MDC period -- 400 -- ns tMD1 MDIO (PHY input) setup to rising edge of MDC 10 -- -- ns tMD2 MDIO (PHY input) hold from rising edge of MDC 4 -- -- ns tMD3 MDIO (PHY output) delay from rising edge of MDC 5 222 -- ns 2016 Microchip Technology Inc. DS00002275A-page 67 KSZ8091MNX/RNB 7.9 Power-Up/Reset Timing The KSZ8091MNX/RNB reset timing requirement is summarized in Figure 7-10 and Table 7-10. FIGURE 7-10: POWER-UP/RESET TIMING SUPPLY VOLTAGES tVR tSR RST# tCS tCH STRAP-IN VALUE tRC STRAP-IN / OUTPUT PIN TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 -- -- s tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 -- -- ms tCS Configuration setup time 5 -- -- ns tCH Configuration hold time 5 -- -- ns tRC Reset to strap-in pin output 6 -- -- ns The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300 s minimum rise time is from 10% to 90%. For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500 s. The strap-in pin values are read and updated at the de-assertion of reset. After the de-assertion of reset, wait a minimum of 100 s before starting programming on the MIIM (MDC/MDIO) interface. DS00002275A-page 68 2016 Microchip Technology Inc. KSZ8091MNX/RNB 8.0 RESET CIRCUIT Figure 8-1 shows a reset circuit recommended for powering up the KSZ8091MNX/RNB if reset is triggered by the power supply. FIGURE 8-1: RECOMMENDED RESET CIRCUIT VDDIO D1: 1N4148 D1 KSZ8091MNX/RNB R 10k RST# C 10F Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2 is used if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other. If different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (for example, Vishay's BAT54, MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same VDDIO voltage. FIGURE 8-2: RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT VDDIO KSZ8091MNX/RNB R 10k D1 CPU/FPGA RST# RST_OUT_N D2 C 10F D1: 1N4148 2016 Microchip Technology Inc. DS00002275A-page 69 KSZ8091MNX/RNB 9.0 REFERENCE CIRCUITS -- LED STRAP-IN PINS The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/PME_N1/NWAYEN strapping pins are shown in Figure 9-1 for 3.3V and 2.5V VDDIO. FIGURE 9-1: REFERENCE CIRCUITS FOR LED STRAPPING PINS VDDIO = 3.3V, 2.5V PULL_UP 4.7k 220 KSZ8091MNX/RXB LED PIN VDDIO = 3.3V, 2.5V FLOAT 220 KSZ8091MNX/RXB LED PIN VDDIO = 3.3V, 2.5V PULL-DOWN 220 KSZ8091MNX/RXB LED PIN 1k For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the SPEED and NWAYEN strap-in pins are functional with a 4.7 k pull-up to 1.8V VDDIO or float for a value of `1', and with a 1.0 k pull-down to ground for a value of `0'. If using RJ45 jacks with integrated LEDs and 1.8V VDDIO, a level shifting is required from LED 3.3V to 1.8V. For example, use a bipolar transistor or a level shift device. DS00002275A-page 70 2016 Microchip Technology Inc. KSZ8091MNX/RNB 10.0 REFERENCE CLOCK - CONNECTION AND SELECTION A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8091MNX/ RNB. For the KSZ8091MNX/RNB in all operating modes and for the KSZ8091RNB in RMII - 25 MHz Clock Mode, the reference clock is 25 MHz. The reference clock connections to XI (Pin 9) and XO (Pin 8), and the reference clock selection criteria, are provided in Figure 10-1 and Table 10-1. FIGURE 10-1: 25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION 22pF XI XI 25MHz OSC 50ppm 22pF XO NC XO 25MHz XTAL 50ppm TABLE 10-1: 25 MHZ CRYSTAL/REFERENCE CLOCK SELECTION CRITERIA Characteristics Value Frequency 25 MHz Frequency Tolerance (max.); Note 10-1 50 ppm Crystal Series Resistance (typ.) 40 Crystal Load Capacitance (typ.) Note 10-1 60 ppm for overtemperature crystal. 16 pF For the KSZ8091RNB in RMII - 50 MHz Clock Mode, the reference clock is 50 MHz. The reference clock connections to XI (Pin 9), and the reference clock selection criteria are provided in Figure 10-2 and Table 10-2. FIGURE 10-2: 50 MHZ OSCILLATOR REFERENCE CLOCK CONNECTION XI 50MHz OSC 50PPM TABLE 10-2: NC XO 50 MHZ OSCILLATOR/REFERENCE CLOCK SELECTION CRITERIA Characteristics Value Frequency 50 MHz Frequency Tolerance (max.) 50 ppm 2016 Microchip Technology Inc. DS00002275A-page 71 KSZ8091MNX/RNB 11.0 MAGNETIC - CONNECTION AND SELECTION A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. The KSZ8091MNX/RNB design incorporates voltage-mode transmit drivers and on-chip terminations. With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs. Therefore, the two transformer center tap pins on the KSZ8091MNX/RNB side should not be connected to any power supply source on the board; instead, the center tap pins should be separated from one another and connected through separate 0.1 F common-mode capacitors to ground. Separation is required because the common-mode voltage is different between transmitting and receiving differential pairs. Figure 11-1 shows the typical magnetic interface circuit for the KSZ8091MNX/RNB. TYPICAL MAGNETIC INTERFACE CIRCUIT TXP 1 TXM 2 RXP 3 RXM 4 5 RJ-45 CONNECTOR KSZ8091MNX/RNB FIGURE 11-1: 6 7 8 4 x 75 (2 x 0.1F) 1000pF/2kV SIGNAL GROUND CHASSIS GROUND Table 11-1 lists recommended magnetic characteristics. TABLE 11-1: MAGNETICS SELECTION CRITERIA Parameter Value Turns Ratio 1 CT : 1 CT -- Open-Circuit Inductance (min.) 350 H 100 mV, 100 kHz, 8 mA Insertion Loss (max.) -1.1 dB 100 kHz to 100 MHz HIPOT (min.) 1500 VRMS -- DS00002275A-page 72 Test Conditions 2016 Microchip Technology Inc. KSZ8091MNX/RNB Table 11-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that can be used with the KSZ8091MNX/RNB. TABLE 11-2: COMPATIBLE SINGLE-PORT 10/100 MAGNETICS Manufacturer Part Number Temperature Range Magnetic + RJ-45 Bel Fuse S558-5999-U7 0C to 70C No Bel Fuse SI-46001-F 0C to 70C Yes Bel Fuse SI-50170-F 0C to 70C Yes Delta LF8505 0C to 70C No HALO HFJ11-2450E 0C to 70C Yes HALO TG110-E055N5 -40C to 85C No LANKom LF-H41S-1 0C to 70C No Pulse H1102 0C to 70C No Pulse H1260 0C to 70C No Pulse HX1188 -40C to 85C No Pulse J00-0014 0C to 70C Yes Pulse JX0011D21NL -40C to 85C Yes TDK TLA-6T718A 0C to 70C Yes Transpower HB726 0C to 70C No Wurth/Midcom 000-7090-37R-LF1 -40C to 85C No 2016 Microchip Technology Inc. DS00002275A-page 73 KSZ8091MNX/RNB 12.0 PACKAGE OUTLINE FIGURE 12-1: Note: 32-LEAD QFN 5 MM X 5 MM PACKAGE For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00002275A-page 74 2016 Microchip Technology Inc. KSZ8091MNX/RNB APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00002275A (09-15-16) 2016 Microchip Technology Inc. Section/Figure/Entry -- Correction Converted Micrel data sheet KSZ8091MNX/RNB to Microchip DS00002275A. Minor text changes throughout. DS00002275A-page 75 KSZ8091MNX/RNB THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support DS00002275A-page 76 2016 Microchip Technology Inc. KSZ8091MNX/RNB PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X X X XX XX Interface Package Special Temperature Media Type Attribute Device: KSZ8091 Interface: M = MII R = RMII Package: N = 32-pin QFN Special Attribute: B = 25 MHz In/50 MHz Out Clocks X = None Temperature: CA = 0C to +70C (Commercial) IA = -40C to +85C (Industrial) Media Type: blank = Tray TR = Tape & Reel Examples: a) b) c) d) e) f) g) h) 2016 Microchip Technology Inc. KSZ8091MNXCA MII Interface 32-pin QFN No Special Attribute Commercial Temperature Tray KSZ8091MNXIA MII Interface 32-pin QFN No Special Attribute Industrial Temperature Tray KSZ8091MNXCA-TR MII Interface 32-pin QFN No Special Attribute Commercial Temperature Tape & Reel KSZ8091MNXIA-TR MII Interface 32-pin QFN No Special Attribute Industrial Temperature Tape & Reel KSZ8091RNBCA RMII Interface 32-pin QFN 25 MHz In/50 MHz Out Clocks Commercial Temperature Tray KSZ8091RNBIA RMII Interface 32-pin QFN 25 MHz In/50 MHz Out Clocks Industrial Temperature Tray KSZ8091RNBCA-TR RMII Interface 32-pin QFN 25 MHz In/50 MHz Out Clocks Commercial Temperature Tape & Reel KSZ8091RNBIA-TR RMII Interface 32-pin QFN 25 MHz In/50 MHz Out Clocks Industrial Temperature Tape & Reel DS00002275A-page 77 KSZ8091MNX/RNB DS00002275A-page 78 2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0944-1 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2016 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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