AK4642EN - AKM Semiconductor, Inc.

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

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GENERAL DESCRIPTION

The AK4642 features a stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and

Speaker-Amplifier. Input c ircuits include a Mi crophon e-Amplif ier and an ALC (Auto Level Control) circ uit

that is suitable for portable application with recording/playback function. The AK4642 is available in a

32pin QFN, utilizing less board space than competitive offerings.

FEATURES

1. Recording Function

• Stereo Mic Input (Full-di fferential or Single-ended)

• Stereo Line Input

• MIC Amplifier (+32dB/+26dB/+20dB or 0dB)

• Digital ALC (Automatic Level Control)

(+36dB ∼ −54dB, 0.375dB Step, Mute)

• ADC Performance: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB)

S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB)

• Wind-noise Reduction Filter

• Stereo Separatio n Emphasis

2. Playback Function

• Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)

• Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute)

• Digital ALC (Automatic Level Control)

(+36dB ∼ −54dB, 0.375dB Step, Mute)

• Stereo Separatio n Emphasis

• Stereo Line Output

- Performance: S/(N+D): 88dB, S/N: 92dB

• Stereo Headphone-Amp

- S/(N+D): 70dB, S/N: 90dB

- Output Power: 62mW@16Ω (HVDD=3.3V)

- Pop Noise Free at Power ON/OFF

• Mono Speaker-Amp

- S/(N+D): 50dB@240mW, S/N: 90 dB

- BTL Output

- Availbable for both Dynamic and Piezo Speaker

- Output Power: 400mW@8Ω (HVDD=3.3V)

3.0Vrms@50Ω (HV DD =5V )

• Analog Mixing: Mono Input

3. Power Management

4. Master Clock:

(1) PLL Mode

• Frequencies:

11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)

1fs (LRCK pin)

32fs or 64fs (BICK pin)

(2) External Clock Mode

• Frequencies: 256fs, 512fs or 1024fs (MCKI p in)

5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs

Stereo CODEC with MIC/HP/SPK-AMP

K4642EN

ASAHI KASEI [AK4642EN]

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6. Sampling Rate:

• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz

• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz

• PLL Slave Mode (MCKI pin):

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz , 44.1kHz, 48kHz

• PLL Master Mode:

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz , 44.1kHz, 48kHz

• EXT Slave Mode:

7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)

7. µP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz High Speed Mod e)

8. Master/Slave mode

9. Audio Interface Format: MSB First, 2’s compliment

• ADC : 16bit MSB justified, I2S

• DAC : 16bit MSB justified, 16bit LSB justified, 16-24bit I2S

10. Ta = −30 ∼ 85°C (SPK-Amp=OFF)

−30 ∼ 70°C (SPK-Amp=ON)

11. Power Supply:

• AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V)

• HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V)

12. Package: 32pin QFN (5mm x 5mm, 0.5mm pitch)

13. Register Upper-Compatible with Mono CODEC (AK4 536/4630/4631)

 Block Diagram

MIC Powe

Supply

MIC-Amp A/D Wind-Noise

Reduction Stereo

Separation

HPF

PMADL

PMADR

PMMP

PMAD L or PMAD R

Audio

I/F

D/A DATT

SMUTE

PMDAC

PMHP L

PMHPR

Internal

MIC

External

MIC

Line In

Line Out

Headphone

PM SPK

Speaker

ALC

Bass

Boost

PLL

PMBP

PMP LL

Control

MPWR

LIN1

RIN1

LIN

RIN

HPL

HPR

MUTE

SPN

HVD

HVSS MIN

AVDD AVSS VCOM DVDD

CSN

PDN

CCLK

CDTI

BICK

LRCK

SDTO

SDTI

MCKO

MCKI

VCO C

PM LO

LOUT

ROU

ALC

DVSS

Stereo

Separation HPF

I2C

Figure 1. Block Diagram

ASAHI KASEI [AK4642EN]

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 Ordering Guide

AK4642EN −30 ∼ +85°C 32pin QFN (0.5mm pitch)

AKD4642 Evaluation board for AK4642

 Pin Layout

MUTET

ROUT

LOUT

MIN

RIN2 / IN2−

LIN2 / IN2+

LIN1 / IN1−

RIN1 / IN1+

HPL

HPR

HVSS

HVDD

SPP

SPN

MCKO

MCKI

MPWR

VCOM

AVSS

AVDD

VCOC

I2C

PDN

CSN / CA D0

DVSS

DVDD

BICK

LRCK

SDTO

SDTI

CDTI / SDA

CCLK / SCL

AK4642EN

Top View

ASAHI KASEI [AK4642EN]

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 Comparison wi th AK4537

Function AK4537 AK4642EN

Mic Input Single-ended Single-ended / Full-differential

Stereo Mic Input 1-Input 2-Input selectable

MIC-Power 2-Output, RL=2kΩ (min) 1-Output, RL=0.5kΩ (min)

MIC-Amp +20dB or 0dB +32dB/+26dB/+20dB or 0dB

MIC ALC +27.5dB to –8dB, 0.5dB step +36dB to –54dB, 0.375dB step, Mute

Wind-noise Reduction Filter N/A Available

Stereo Separation Emphasis N/A Available

Mono Mic Mode N/A Available

ALC for Playback SP only, +18dB to –8dB Line/HP/SP, +36dB to –54dB

DATT 0 to –127dB, Mute +12 to –115dB, Mute

Bass Boost +5.74dB/+5.94dB/+16.04dB@20Hz +5.76dB/+10.80dB/+16.06dB@20Hz

DAC Digital Filter

Stopband Attenuation 43dB 59dB

Line Output Level 1.98Vpp 1.98Vpp/2.50Vpp

Usage for Piezo Speaker N/A Available

PLL Input Frequency 11.2896MHz, 12MHz, 12.288MHz 11.2896MHz, 12MHz, 12.288MHz,

13.5MHz, 24MHz, 27MHz

µP I/F 4-wire/I2C(100kHz mode) 3-wire/I2C(400kHz m ode)

X’tal Available N/A

MCKI AC Input Available N/A

MCKI Pull-down Available N/A

Analog Loopback Available N/A

Mono Line Output Available N/A

Stereo Beep Input Available N/A

Power Supply (HVDD) 2.4 ∼ 3.6V 2.6 ∼ 5.25V

Package 52pin QFN (7.2mm x 7.2mm) 32pin QFN (5mm x 5mm)

ASAHI KASEI [AK4642EN]

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 Comparison wi th AK4631

Function AK4631 AK4642EN

Mic Input Single-ended Single-ended / Full-differential

Stereo Mic Input N/A Available

ADC Mono Stereo

MIC ALC +27.5dB to –8dB, 0.5dB step +36dB to –54dB, 0.375dB step, Mute

Wind-noise Reduction Filter N/A Available

Stereo Separation Emphasis N/A Available

ALC for Playback SP only, +18dB to –8dB Line/HP/SP, +36dB to –54dB

Soft Mute N/A Available

Bass Boost N/A Available

De-emphasis N/A Available

DAC Mono Stereo

HP-Amp N/A Available

Line Output Mono Stereo

Line Output Level 1.98Vpp 1.98Vpp/2.50Vpp

µP I/F 3-wire 3-wire/I2C

MCKI Pull-down Available N/A

Analog Loopback Available N/A

DSP Mode Available N/A

Package 28pin QFN (5.2mm x 5.2mm) 32pin QFN (5mm x 5mm)

Regester Map Upper-compatibl e (Difference: ALC

parameter, Analog Loopback & DSP

Mode Removed)

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 Register Compatibi lity with AK4631

AK4631

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Management 1 0 PMVCM PMBP PMSPK PMAO PMDAC PMMIC PMADC

01H Power Management 2 0 0 0 0 M/S MCKPD MCKO PMPLL

02H Signal Select 1 SPPS BEEPS ALC2S DACA DACM MPWR MICAD MGAIN0

03H Signal Select 2 0 AOPSN MGAIN1 SPKG1 SPKG0 BEEPA ALC1M ALC1A

04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO1 BCKO0 DIF1 DIF0

05H Mode Control 2 0 0 FS3 MSBS BCKP FS2 FS1 FS0

06H Timer Select DVTM ROTM ZTM1 ZTM0 WTM1 WTM0 LTM1 LTM0

07H ALC Mode Control 1 0 ALC2 ALC1 ZELM LMAT1 LMAT0 RATT LMTH

08H ALC Mode Control 2 0 REF6 REF5 REF4 REF3 REF2 REF1 REF0

09H Input PGA Control 0 IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 IPGA1 IPGA0

0AH Digital Volume Control DVOL7 DVOL6 DVOL5 DVOL4 DVOL3 DVOL2 DVOL1 DVOL0

0BH ALC2 Mode Cont rol 0 0 RFS5 RFS4 RFS3 RFS2 RFS1 RFS0

AK4642

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Management 1 0 PMVCM PMBP PMSPK PMLO PMDAC 0 PMADL

01H Power Management 2 0 HPMTN PMHPL PMHPR M/S 0 MCKO PMPLL

02H Signal Sel e c t 1 SPPSN BEEPS DACS DACL 0 PMMP 0 MGAIN0

03H Signal Select 2 LOVL LOPS MGAIN1 SPKG1 SPKG0 BEEPL 0 0

04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0

05H Mode Control 2 PS1 PS0 FS3 0 0 FS2 FS1 FS0

06H Timer Select DVTM 0 ZTM1 ZTM0 WTM1 WTM0 0 0

07H ALC Mode Control 1 0 0 ALC ZELMN LMAT1 LMAT0 RGAIN0 LMTH0

08H ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0

09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0

0AH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0

0BH ALC Mo de Control 3 RGAIN1 LMTH1 0 0 0 0 0 0

0CH

1FH Additional Function for AK4642 only

Bits which are not needed for AK4642

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PIN/FUNCTION

No. Pin Name I/O Function

1 MPWR O MIC Power Supply Pin

2 VCOM O Common Voltage Output Pin, 0.45 x AVDD

Bias voltage of ADC inputs and DAC outputs.

3 AVSS - Analog Ground Pin

4 AVDD - Analog Power Supply Pin

5 VCOC O Output Pin for Loop Filter of PLL Circuit

This pin should be connected to AVSS with one resistor and capacitor in series.

6 I2C I Control Mode Select Pin

“H”: I2C Bus, “L”: 3-wire Serial

7 PDN I Power-Down Mode Pin

“H”: Power-up, “L”: Power-down, reset and initializes the control register.

CSN I Chip Select Pin (I2C pin = “L”)

8 CAD0 I Chip Address 1 Select Pin (I2C pin = “H”)

CCLK I Control Data Clock Pin (I2C pin = “L”)

9 SCL I Control Data Clock Pin (I2C pin = “H”)

CDTI I Control Data Input Pin (I2C pin = “L”)

10 SDA I/O Control Data Input Pin (I2C pin = “H”)

11 SDTI I Audio Serial Data Input Pin

12 SDTO O Audio Serial Data Output Pin

13 LRCK I/O Input / Output Channel Clock Pin

14 BICK I/O Audio Serial Data Clock Pin

15 DVDD - Digital Power Supply Pin

16 DVSS - Digital Ground Pin

17 MCKI I External Master Clock Input Pin

18 MCKO O Master Clock Output Pin

19 SPN O Speaker Amp Negative Output Pin

20 SPP O Speaker Amp Positive Output Pin

21 HVDD - Headphone & Speaker Amp Power Supply Pin

22 HVSS - Headphone & Speaker Amp Ground Pin

23 HPR O Rch Headphone-Amp Output Pin

24 HPL O Lch Headphone-Amp Output Pin

25 MUTET O Mute Time Constant Control Pin

Connected to HVSS pin with a capacitor for mute time constant.

26 ROUT O Rch Stereo Line Output Pin

27 LOUT O Lch Stereo Line Output Pin

28 MIN I Mono Signal Input Pin

RIN2 I Rch Analog Input 2 Pin (MDIF2 bit = “0”)

29 IN2− I Microphone Negative Input 2 Pin (MDIF2 bit = “1”)

LIN2 I Lch Analog Input 2 Pin (MDIF2 bit = “0”)

30 IN2+ I Microphone Positive Input 2 Pin (MDIF2 bit = “1”)

LIN1 I Lch Analog Input 1 Pin (MDIF1 bit = “0”)

31 IN1− I Microphone Negative Input 1 Pin (MDIF1 bit = “1”)

RIN1 I Rch Analog Input 1 Pin (MDIF1 bit = “0”)

32 IN1+ I Microphone Positive Input 1 Pin (MDIF1 bit = “1”)

Note 1. All input pins exce pt analog input pins (MIN, LIN1, RIN1, LIN2, RIN2) should not be left floating.

Note 2. AVDD or AVSS voltage should be input to I2C pin.

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 Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

Classification Pin Name Setting

Analog MPWR, VCOC, SPN, SPP, HPR, HPL, MUTET,

ROUT, LOUT, MIN, RIN2/I N2−, LIN2/IN2+,

LIN1/IN1−, RIN1/IN1+ These pins should be open.

MCKO This pin should be open.

Digital MCKI This pin should be connected to DVSS.

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ABSOLUTE MAXIMUM RATINGS

(AVSS, DVSS, HVSS=0V; Note 3)

Parameter Symbol min max Units

Power Supplies: Analog AVDD −0.3 6.0 V

Digital DVDD

−0.3 6.0 V

Headphone-Amp / Speaker-Amp HVDD −0.3 6.0 V

|AVSS – DVSS| (Note 4) ∆GND1 - 0.3 V

|AVSS – HVSS| (Note 4) ∆GND2 - 0.3 V

Input Current, Any Pin Except Supplies IIN - ±10 mA

Analog Input Voltage (Note 5) VINA −0.3 AVDD+0.3 V

Digital Input Voltage (Note 6) VIND −0.3 DVDD+0.3 V

Ambient Temperature (powered applied) Ta −30 85 °C

Storage Temperature Tstg −65 150 °C

Maximum Power Dissipation Ta=85°C (Note 8) Pd1 - 400 mW

(Note 7) Ta=70°C (Note 9) Pd2 - 550 mW

Note 3. All voltages with respect to ground.

Note 4. AVSS, DVSS and HVSS m ust be connected to the same analog ground plane.

Note 5. I2C, MIN, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins

Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins

Pull-up resistors at SDA and SCL pins should be connected to DVDD or less voltage.

Note 7. In case that PCB wiring density is 100%. This power is the AK4642 internal dissipati on that does not include

power of externall y connected speaker and headphone .

Note 8. Speaker-Amp is not available.

Note 9. Speaker-Amp is available.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AVSS, DVSS, HVSS=0V; Note 3)

Parameter Symbol min typ Max Units

Power Supplies Analog AVDD 2.6 3.3 3.6 V

(Note 10) Digital DVDD 2.6 3.3 3.6 V

HP / SPK-Amp (Note 11) HVDD 2.6 3.3 / 5.0 5.25 V

Difference AVDD−DVDD −0.3 0 +0.3 V

Note 3. All voltages with respect to ground.

Note 10. The power-up sequence between AVDD, DVDD and HVDD is not critical. When the power supplies are

partially powered OFF, the AK4642 must be reset by bringing PDN pin “L” after these power supplies are

powered ON again.

Note 11. HVDD = 2.6 ∼ 3.6V when 8Ω dynamic speaker is connected to the AK4642.

* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

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ANALOG CHARACTERISTICS

(Ta=25°C; AVDD, DVDD, HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, BICK=64fs;

Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwi se specified)

Parameter min typ max Units

MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = “0” (Si ngle-ended inputs)

MGAIN1-0 bits = “00” 40 60 80 kΩ

Input

Resistance MGAIN1-0 bits = “01”, “10”or “11” 20 30 40 kΩ

MGAIN1-0 bits = “00” - 0 - dB

MGAIN1-0 bits = “01” - +20 - dB

MGAIN1-0 bits = “10” - +26 - dB

Gain

MGAIN1-0 bits = “11” - +32 - dB

MIC Amplifier: IN1+, IN1−, IN2+, IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differe ntial input)

Maximum Input Voltage (Note 12)

MGAIN1-0 bits = “01” - - 0.228 Vpp

MGAIN1-0 bits = “10” - - 0.114 Vpp

MGAIN1-0 bits = “11” - - 0.057 Vpp

MIC Power Supply: MPWR pin

Output Voltage (Note 13) 2.22 2.47 2.72 V

Load Resistance 0.5 - - kΩ

Load Capacitance - - 30 pF

ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pi ns → ADC → IVOL, IVOL=0dB, ALC=OFF

Resolution - - 16 Bits

(Note 15) 0.168 0.198 0.228 Vpp

Input Voltage (Note 14) (Note 16) 1.68 1.98 2.28 Vpp

(Note 15) 71 83 - dBFS

S/(N+D) (−1dBFS) (Note 16) - 88 - dBFS

(Note 15) 76 86 - dB

D-Range (−60dBFS, A-weighted) (Note 16) - 95 - dB

(Note 15) 76 86 - dB

S/N (A-weighted) (Note 16) - 95 - dB

(Note 15) 75 90 - dB

Interchannel Isolat ion (Note 16) - 100 - dB

(Note 15) - 0.1 0.8 dB

Interchannel Gain Mismatch (Note 16) - 0.1 0.8 dB

Note 12. The voltage difference between IN1/2+ a nd IN1/2− pins. AC coupling capacitor should be inserte d in se ries at

each input pin. Full-differential mic input is not available at MGAIN1-0 bits = “00”. Maximum input voltage of

IN1+, IN1−, IN2+ and IN2− pins is proportional to AVDD voltage, respectively.

Vin = 0.069 x AVDD (max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x

AVDD (max)@MGAIN1-0 bits = “11”.

When the signal larger than above value is input to IN1+, IN1−, IN2+ or IN2− pin, ADC does not operate

normally.

Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ)

Note 14. Input voltage is proport ional to AVDD voltage. Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+ 20dB),

Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB)

Note 15. MGAIN1-0 bits = “01” (+20dB)

Note 16. MGAIN1-0 bits = “00” (0dB )

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Parameter min typ max Units

DAC Characteristics:

Resolution - - 16 Bits

Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit =

“0”, RL=10kΩ

Output Voltage (Note 17) LOVL bit = “0” 1.78 1.98 2.18 Vpp

LOVL bit = “1” 2.25 2.50 2.75 Vpp

S/(N+D) (−3dBFS) 78 88 - dBFS

S/N (A-weighted) 82 92 - dB

Interchannel Isolation 80 100 - dB

Interchannel Gain Mismatch - 0.1 0.5 dB

Load Resistance 10 - - kΩ

Load Capacitanc e - - 30 pF

Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB

Output Voltage (Not e 18)

HPG bit = “0”, 0dBFS, HVDD=3. 3V, R L=22.8Ω 1.58 1.98 2.38 Vpp

HPG bit = “1”, 0dBFS, HVDD=5V, R L=100Ω 2.40 3.00 3.60 Vpp

HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) - 1.00 - Vrms

S/(N+D)

HPG bit = “0”, −3dBFS , HVDD=3.3V, RL=22.8Ω60 70 - dBFS

HPG bit = “1”, −3dBFS , HVDD=5V, RL=100Ω - 80 - dBFS

HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) - 20 - dBFS

(Note 19) 80 90 - dB

S/N (A-weighted) (Note 20) - 90 - dB

(Note 19) 65 75 - dB

Interchannel Isolat ion (Note 20) - 80 - dB

(Note 19) - 0.1 0.8 dB

Interchannel Gain Mismatch (Note 20) - 0.1 0.8 dB

Load Resistance 16 - - Ω

C1 in Figure 2 - - 30 pF

Load Capacitance C2 in Figure 2 - - 300 pF

Note 17. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”.

Note 18. Output voltage is proportional to AVDD voltage.

Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”.

Note 19. HPG bit = “0”, HVDD= 3.3V, RL=22.8Ω.

Note 20. HPG bit = “1”, HVDD= 5V, RL=100Ω.

HPL/ HPR pin

HP-Amp

47µF

C1 16Ω

6.8Ω

0.22µF

10Ω

Measurement Point

Figure 2. Headphone-Amp output circuit

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Parameter min typ max Units

Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, RL=8Ω, BTL,

HVDD=3.3V

Output Voltage (Not e 21)

SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW ) - 3.11 - Vpp

SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW ) 3.13 3.92 4.71 Vpp

SPKG1-0 bits = “10”, −2.5dBFS (Po=400mW ) - 1.79 - Vrms

S/(N+D)

SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW ) - 60 - dB

SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW ) 20 50 - dB

SPKG1-0 bits = “10”, −2.5dBFS (Po=400mW ) - 20 - dB

S/N (A-weighted) 80 90 - dB

Load Resistance 8 - - Ω

Load Capacitanc e - - 30 pF

Speaker-Amp Characteristics: DAC → SP P/SPN pins, ALC=OFF, I VOL=0dB, DVOL=0dB, CL=3µF, Rserial=10Ω x 2,

RL=50Ω, BTL, HVDD=5.0V

Output Voltage SPKG1-0 bits = “10”, 0dBFS - 6.75 - Vpp

(Note 21) SPKG1-0 bits = “11”, 0dBFS 6.80 8.50 10.20 Vpp

S/(N+D) SPKG1-0 bits = “10”, 0dBFS - 60 - dB

(Note 22) SPKG1-0 bits = “11”, 0dBFS 40 50 - dB

S/N (A-weighted) 80 90 - dB

Load Resistance (Note 23) 50 - - Ω

Load Capacitance (Note 23) - - 3 µF

Mono Input: MIN pin (External Input Resistance=20kΩ)

Maximum Input Voltage (Note 24) - 1.98 - Vpp

Gain (Note 25)

MIN Æ LOUT/ROUT LOVL bit = “0” −4.5 0 +4.5 dB

LOVL bit = “1” - +2 - dB

MIN Æ HPL/HPR HPG bit = “0” −24.5 −20 −15.5 dB

HPG bit = “1” - −16.4 - dB

MIN Æ SPP/SPN

ALC bit = “0”, SPKG1-0 bits = “ 00” −0.57 +4.43 +8.93 dB

ALC bit = “0”, SPKG1-0 bits = “01” - +6.43 - dB

ALC bit = “0”, SPKG1-0 bits = “10” - +10.65 - dB

ALC bit = “0”, SPKG1-0 bits = “11” - +12.65 - dB

ALC bit = “1”, SPKG1-0 bits = “00” - +6.43 - dB

ALC bit = “1”, SPKG1-0 bits = “01” - +8.43 - dB

ALC bit = “1”, SPKG1-0 bits = “10” - +12.65 - dB

ALC bit = “1”, SPKG1-0 bits = “11” - +14.65 - dB

Note 21. Output voltage is proportional to AVDD voltage.

Vout = 0.94 x AVDD(typ)@SPKG1-0 bits = “00”, 1.19 x AVDD(typ) @SPKG1-0 bits = “01”, 2.05 x

AVDD(typ)@SPKG1-0 bits = “10”, 2.58 x AVDD(typ)@SPKG1-0 bits = “11” at Full-differential output.

Note 22. In case of mea suring at SPP and SPN pins.

Note 23. Load im pedance is tota l impedanc e of series resist ance and piezo speaker im pedance at 1kHz i n Figure 33. Load

capacita nce is capa cit ance of piezo spea ker. When piez o speaker is used, 10 Ω or more series resi stors should be

connected at both SPP and SPN pins, respectively.

Note 24. Maxim um volt age i s in proporti on to both AVDD and exte rnal input r esistanc e (Rin). Vin = 0.6 x AVDD x Rin

/ 20kΩ (typ).

Note 25. The gain is in inverse proportion to ext ernal input resistance.

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Parameter min typ max Units

Power Supplies:

Power-Up (PDN pin = “H”)

All Circuit Power-up:

AVDD+DVDD (Note 26) - 15 23 mA

HVDD: HP-Amp Normal Operation

No Output (Note 27) - 5 8 mA

HVDD: SPK-Amp Normal Operation

No Output (Note 28) - 8 24 mA

Power-Down (PDN pin = “L”) (Note 29)

AVDD+DVDD+HVDD - 10 100 µA

Note 26. PLL Master M ode (MCKI=12.288MHz) and PMADL = PM ADR = PMDAC = PM LO = PMHPL = PM HPR =

PMSPK = PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S b its = “1 ”. MPWR pi n outpu ts 0 mA.

AVDD=11mA(typ), DVDD=4mA(typ).

EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=10mA(typ), DVDD=3mA(typ).

Note 27. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMBP bits = “1” and

PMSPK bit = “0 ”.

Note 28. PMADL = PMADR = PMDAC = PMLO = PMS PK = PMVCM = PMPLL = PMBP bits = “1” and PMH PL =

PMHPR bits = “0”.

Note 29. All digit a l input pins are fixed to DVDD or DVSS.

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FILTER CHARACTERISTICS

(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF)

Parameter Symbol min typ max Units

ADC Digital Filter (Decimation LPF):

Passband (Note 30) ±0.16dB PB 0 - 17.3 kHz

−0.66dB - 19.4 - kHz

−1.1dB - 19.9 - kHz

−6.9dB - 22.1 - kHz

Stopband SB 26.1 - - kHz

Passband Ripple PR - - ±0.1 dB

Stopband Attenuat ion SA 73 - - dB

Group Delay (Note 31) GD - 19 - 1/fs

Group Delay Distortion ∆GD - 0 -

µs

ADC Digital Filter (HPF): (Note 32)

Frequency Response (Note 30) −3.0dB FR - 0.9 - Hz

−0.5dB - 2.7 - Hz

−0.1dB - 6.0 - Hz

DAC Digital Filter (LPF):

Passband (Note 30) ±0.1dB PB 0 - 19.6 kHz

−0.7dB - 20.0 - kHz

−6.0dB - 22.05 - kHz

Stopband SB 25.2 - - kHz

Passband Ripple PR - - ±0.01 dB

Stopband Attenuat ion SA 59 - - dB

Group Delay (Note 31) GD - 22 - 1/fs

DAC Digital Filter (LPF) + SCF:

Frequency Response: 0 ∼ 20.0kHz FR -

±1.0 - dB

DAC Digital Filter (HPF): (Note 32)

Frequency Response (Note 30) −3.0dB FR - 0.9 - Hz

−0.5dB - 2.7 - Hz

−0.1dB - 6.0 - Hz

BOOST Filter: (Note 33)

MIN 20Hz FR - 5.76 - dB

100Hz - 2.92 - dB

1kHz - 0.02 - dB

MID 20Hz FR - 10.80 - dB

100Hz - 6.84 - dB

1kHz - 0.13 - dB

MAX 20Hz FR - 16.06 - dB

100Hz - 10.54 - dB

Frequency Response

1kHz - 0.37 - dB

Note 30. The passband and stopband frequencies scale with fs (system sampling rate).

For example, ADC is PB=0.454*fs (@-1.0dB). Each response refers to that of 1kHz.

Note 31. The calcul ated delay tim e caused by digital filte ring. This tim e is from the input of analog signal to setting of the

16-bit data of both channels from the input register to the output register of the ADC. This time includes the

group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input

Note 32. When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled.

When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is

disabled.

Note 33. These frequency responses sca le with fs. If a high-le vel and low frequency signal is input, the analog output clips

to the full-scale.

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DC CHARACTERISTICS

(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)

Parameter Symbol min typ Max Units

High-Level Input Voltage VIH 70%DVDD - - V

Low-Level Input Voltage VIL - - 30%DVDD V

High-Level Output Voltage (Iout=−200µA) VOH DVDD−0.2 - - V

Low-Level Output Voltage

(Except SDA pin: Iout=200µA) VOL - - 0.2 V

(SDA pin: Iout=3mA) VOL - - 0.4 V

Input Leakage Current Iin - - ±10 µA

SWITCHING CHARACTERISTICS

(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF)

Parameter Symbol min typ max Units

PLL Master Mode (PLL Ref erence Clock = MCKI pin)

MCKI Input Timing

Frequency fCLK 11.2896 - 27 MHz

Pulse Width Low tCLKL 0.4/fCLK - - ns

Pulse Width High tCLKH 0.4/fCLK - - ns

MCKO Output Timin g

Frequency fMCK 0.2352 - 12.288 MHz

Duty Cycle

Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 %

256fs at fs=32kHz, 29.4kHz dMCK - 33 - %

LRCK Output Timing

Frequency fs 7.35 - 48 kHz

Duty Cycle Duty - 50 - %

BICK Output Timing

Period BCKO bit = “0” tBCK - 1/(32fs) - ns

BCKO bit = “1” tBCK - 1/(64fs) - ns

Duty Cycle dBCK - 50 - %

PLL Slave Mode (PLL Reference Clock = MCKI pin)

MCKI Input Timing

Frequency fCLK 11.2896 - 27 MHz

Pulse Width Low tCLKL 0.4/fCLK - - ns

Pulse Width High tCLKH 0.4/fCLK - - ns

MCKO Output Timin g

Frequency fMCK 0.2352 - 12.288 MHz

Duty Cycle

Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 %

256fs at fs=32kHz, 29.4kHz dMCK - 33 - %

LRCK Input Timing

Frequency fs 7.35 - 48 kHz

Duty Duty 45 - 55 %

BICK Input Timing

Period tBCK 1/(64fs) - 1/(32fs) ns

Pulse Width Low tBCKL 0.4 x tBCK - - ns

Pulse Width High tBCKH 0.4 x tBCK - - ns

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Parameter Symbol min typ max Units

PLL Slave Mode (PLL Reference Clock = LRCK pin)

LRCK Input Timing

Frequency fs 7.35 - 48 kHz

Duty Duty 45 - 55 %

BICK Input Timing

Period tBCK 1/(64fs) - 1/(32fs) ns

Pulse Width Low tBCKL 240 - - ns

Pulse Width High tBCKH 240 - - ns

PLL Slave Mode (PLL Reference Clock = BIC K pin)

LRCK Input Timing

Frequency fs 7.35 - 48 kHz

Duty Duty 45 - 55 %

BICK Input Timing

Peri od PLL3-0 bits = “0010” tBCK - 1/(32fs) - ns

PLL3-0 bits = “0011” tBCK - 1/(64fs) - ns

Pulse Width Low tBCKL 0.4 x tBCK - - ns

Pulse Width High tBCKH 0.4 x tBCK - - ns

External Slave Mode

MCKI Input Timing

Frequency 256fs fCLK 1.8816 - 12.288 MHz

512fs fCLK 3.7632 - 13.312 MHz

1024fs fCLK 7.5264 - 13.312 MHz

Pulse Width Low tCLKL 0.4/fCLK - - ns

Pulse Width High tCLKH 0.4/fCLK - - ns

LRCK Input Timing

Frequency 256fs fs 7.35 - 48 kHz

512fs fs 7.35 - 26 kHz

1024fs fs 7.35 - 13 kHz

Duty Duty 45 - 55 %

BICK Input Timing

Period tBCK 312.5 - - ns

Pulse Width Low tBCKL 130 - - ns

Pulse Width High tBCKH 130 - - ns

Audio Interface Timing

Master Mode

BICK “↓” to LRCK Edge (Note 34) tMBLR −40 - 40 ns

LRCK Edge to SDTO (MSB)

(Except I2S mode) tLRD

−70

BICK “↓” to SDTO tBSD −70 - 70 ns

SDTI Hold Time tSDH 50 - - ns

SDTI Se tup Time tSDS 50 - - ns

Slave Mode

LRCK Edge to BICK “↑” (Note 34) tLRB 50 - - ns

BICK “↑” to LRCK Edge (Note 34) tBLR 50 - - ns

LRCK Edge to SDTO (MSB)

(Except I2S mode) tLRD

BICK “↓” to SDTO tBSD - - 80 ns

SDTI Hold Time tSDH 50 - - ns

SDTI Se tup Time tSDS 50 - - ns

Note 34. BICK rising edge must not occur at the same time as LRCK edge.

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Parameter Symbol min typ max Units

Control Interface Timing (3-wire Serial mode)

CCLK Period tCCK 200 - - ns

CC LK Pulse Width Low tCCKL 80 - - ns

Pulse Width High tCCKH 80 - - ns

CDTI Setup Time tCDS 40 - - ns

CDTI Hold Time tCDH 40 - - ns

CSN “H” Time tCSW 150 - - ns

CSN “↓” to CCLK “↑” tCSS 50 - - ns

CCLK “↑” to CSN “↑” tCSH 50 - - ns

Contr o l Interfac e Tim ing (I2C Bus mode):

SCL Clock Frequency fSCL - - 400 kHz

Bus Free Time Be tween Transmissions tBUF 1.3 - - µs

Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - µs

Clock Low Time tLOW 1.3 - - µs

Clock High Time tHIGH 0.6 - - µs

Setup Time for Repea ted Start Condition tSU:STA 0.6 - - µs

SDA Hold Time from SCL Falling (Note 35) tHD:DAT 0 - - µs

SDA Setup Time from SCL Rising tSU:DAT 0.1 - - µs

Rise Time of Both SDA and SCL Lines tR - - 0.3 µs

Fall Time of Both SDA and SCL Lines tF - - 0.3 µs

Setup Time for Stop Condition tSU:STO 0.6 - - µs

Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 ns

Power-down & Reset Timing

PDN Pulse Width (Note 36) tPD 150 - - ns

PMADL or PMADR “↑” to SDTO valid (Note 37) tPDV - 1059 - 1/fs

Note 35. Data must be held long enough to bridge the 300ns-transition time of SCL.

Note 36. The AK4642 can be reset by the PDN pin = “L”.

Note 37. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.

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 Timing Diagram

LRCK

1/fCLK

MCKI

tCLKH tCLKL

VIH

VIL

1/fMCK

MCKO

tMCKL

50%DVDD

1/fs

tLRCKH tLRCKL

50%DVDD

Duty = tLRCKH x fs x 100

tLRCKL x f s x 1 00

dMCK = tMCKL x fMCK x 100

Figure 3. Clock Timing (PLL Master mode)

LRCK 50%DVDD

BICK 50%DVDD

SDTO 50%DVDD

tBSD

tSDS

SDTI VIL

tSDH

VIH

tBLR tBCKL

tDLR

Figure 4. Audio Interface Timing (PLL Master mode)

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1/fCLK

MCKI

tCLKH tCLKL

VIH

VIL

1/fs

LRCK VIH

VIL

tBCK

BICK

tBCKH tBCKL

VIH

VIL

tLRCKH tLRCKL

fMCK

MCKO

tMCKL

50%DVDD

dMCK = tMCKL x fMCK x 100

Duty = tLRCKH x fs x 100

= tLRCKL x fs x 100

Figure 5. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)

1/fCLK

MCKI

tCLKH tCLKL

VIH

VIL

1/fs

LRCK VIH

VIL

tBCK

BICK

tBCKH tBCKL

VIH

VIL

tLRCKH tLRCKL Duty = tLRCKH x f s x 100

tLRCKL x fs x 100

Figure 6. Clock Timing (EXT Slave mode)

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LRCK VIH

VIL

tBLR

BICK VIH

VIL

tLRD

SDTO 50%DVDD

tLRB

tBSD

tSDS

SDTI VIL

tSDH

VIH

MSB

Figure 7. Audio Interface Timing (PLL/EXT Slave mode)

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CSN VIH

VIL

tCSS

CCLK

tCDS

VIH

VIL

CDTI VIH

tCCKHtCCKL

tCDH

VIL

C1 C0 R/W

tCCK

Figure 8. WRITE Command Input Timing

CSN VIH

VIL

tCSH

CCLK VIH

VIL

CDTI VIH

tCSW

VIL

D1 D0D2

Figure 9. WRITE Data Input Timing

StopStartStartStop

tHIGH

tHD:DAT

SDA

SCL

tBUF tLOW tR tF

tSU:DAT

VIH

VIL

tHD:STA tSU:STA

VIH

VIL

tSU:STO

tSP

Figure 10. I2C Bus Mode Timing

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PMADL bit

PMADR bit tPDV

SDTO 50%DVDD

Figure 11. Power Down & Reset Timing 1

tPD

PDN VIL

Figure 12. Power Down & Reset Timing 2

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OPERATION OVERVIEW

 System Clock

There are the following four clock modes to interface wi th external devices (see Table 1 and Table 2).

Mode PMPLL bit M/S bit PLL3-0 bits Figure

PLL Master Mode 1 1 See Table 4 Figure 13

PLL Slave Mode 1

(PLL Reference Clock: MCKI pin) 1 0 See Table 4 Figure 14

PLL Slave Mode 2

(PLL Reference Clock: LRCK or BICK pin) 1 0 See Table 4 Figure 15

EXT Slave Mode 0 0 x Figure 16

Don’t Care (Note 38) 0 1 x -

Note 38. If this mode is selected, the invalid clocks are output from MCKO pin when MCKO bit is “1”.

Table 1. Clock Mode Setting (x: Don’t care)

Mode MCKO bit MCKO pin MCKI pin BICK pin LRCK pin

0 “L”

PLL Master Mode 1 Select ed by

PS1-0 bits

Selected by

PLL3-0 bits

Output

(Selected by

BCKO bit)

Output

(1fs)

0 “L”

PLL Slave Mode

(PLL Reference Clock: MCKI pin) 1 Selected by

PS1-0 bits

Selected by

PLL3-0 bits

Input

(Selectet by

BCKO bit)

Input

(1fs)

PLL Slave Mode

(PLL Reference Clock: LRCK or BICK pin) 0 “L” GND

Input

(Selected by

BCKO bit)

Input

(1fs)

EXT Slave Mode 0 “L” Select ed by

FS3-0 bits Input

(≥ 32fs) Input

(1fs)

Table 2. Clock pins state in Clock Mode

 Master Mode/Slave Mode

The M/S bit sel ects either m aster or slave mode. M/ S bit = “1” sel ects master m ode and “0” selects slave mode. When the

AK4642 is power-down m ode (PDN pi n = “L”) and exits reset state , the AK4642 is slave mode. Aft er exiting rese t state ,

the AK4642 goes to master m ode by changing M/S bit = “1”.

When the AK4642 is used by master mode, LRCK a nd BICK pins are a floating state until M/S bit becomes “1”. LRCK

and BICK pins of the AK4642 shoul d be pull ed-down or pulle d-up by the resist or (about 100kΩ) externally to avoid the

floating state.

M/S bit Mode

0 Slave Mode Default

1 Master Mode

Table 3. Select Master/Slave Mode

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 PLL Mode

When PM PLL bit is “1”, a fu lly in t eg rated analog pha se locked loo p (PLL) generate s a cl o ck that is selected by th e

PLL3-0 and FS3-0 bits. The PLL lock ti me is shown i n Table 4, whenever the AK4642 i s supplied to a st able clocks after

PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.

1) Setting of PLL Mode R and C of

VCOC pin

Mode PLL3

bit PLL2

bit PLL1

bit PLL0

bit

PLL

Reference

Clock Input

Input

Frequency R[Ω]C[F]

PLL Lock

Time

(max)

0 0 0 0 0 LRCK pin 1fs 6.8k 220n 160ms Default

1 0 0 0 1 N/A - - - -

2 0 0 1 0 BICK pin 32fs 10k 4.7n 2ms

10k 10n 4ms

3 0 0 1 1 BICK pin 64fs 10k 4.7n 2ms

10k 10n 4ms

4 0 1 0 0 MCKI pin 11.2896MHz 10k 4.7n 40ms

5 0 1 0 1 MCKI pin 12.288MHz 10k 4.7n 40ms

6 0 1 1 0 MCKI pin 12MHz 10k 4.7n 40ms

7 0 1 1 1 MCKI pin 24MHz 10k 4.7n 40ms

12 1 1 0 0 MCKI pin 13.5MHz 10k 10n 40ms

13 1 1 0 1 MCKI pin 27MHz 10k 10n 40ms

Others Others N/A

Table 4. Setting of PLL Mode (*fs: Sampling Frequency)

2) Setting of sampling frequency in PLL Mode

When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as

defined in Table 5.

Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency

0 0 0 0 0 8kHz Default

1 0 0 0 1 12kHz

2 0 0 1 0 16kHz

3 0 0 1 1 24kHz

4 0 1 0 0 7.35kHz

5 0 1 0 1 11.025kHz

6 0 1 1 0 14.7kHz

7 0 1 1 1 22.05kHz

10 1 0 1 0 32kHz

11 1 0 1 1 48kHz

14 1 1 1 0 29.4kHz

15 1 1 1 1 44.1kHz

Others Others N/A

Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”

When PLL2 bit is “0” (PLL reference cl ock i nput i s LR CK or B IC K pin), t he sam pli ng freque ncy i s selec te d by FS3 and

FS1-0 bits. (See Tabl e 6). FS2 bit is “don’t care”.

Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range

0 0 Don’t care 0 0 7.35kHz ≤ fs ≤ 8kHz Default

1 0 Don’t care 0 1 8kHz < fs ≤ 12kHz

2 0 Don’t care 1 0 12kHz < fs ≤ 16kHz

3 0 Don’t care 1 1 16kHz < fs ≤ 24kHz

6 1 Don’t care 1 0 24kHz < fs ≤ 32kHz

7 1 Don’t care 1 1 32kHz < fs ≤ 48kHz

Others Others N/A

Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”

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 PLL Unlock State

1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

In this mode, LRCK and BICK pins go to “L” and irregul ar frequency clock is output from MCKO pins at MCKO bit is

“1” before the PLL goes to lo c k state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (see

Table 7).

After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state

after a period of 1/fs.

When sampling frequency is changed, BICK and LRCK pins do not output irre gular frequency clocks but go to “L” by

setting PMPLL bit to “0”.

MCKO pin

PLL State MCKO bit = “0” MCKO bit = “1” BICK pin LRCK pin

After that PMPLL bit “0” Æ “1” “L” Output Invalid “L” Output “L” Output

PLL Unlock (except above case) “L” Output Invalid Invalid Invalid

PLL Lock “L” Output See Table 9 See Table 10 1fs Output

Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

In this m ode, an invalid clock is output from MCKO pin before the PLL goes to lock state aft er PMPLL bit = “0” Æ “1”.

After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC and DAC output invalid

data when t he PLL i s unlocked. For DAC , the output si gnal should be m uted by writ ing “0” to DACL, DAC H and DACS

bits.

MCKO pin

PLL State MCKO bit = “0” MCKO b it = “1”

After that PMPLL bit “0” Æ “1” “L” Output Invalid

PLL Unlock “L” Output Invalid

PLL Lock “L” Output Output

Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

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 PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the

MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by

PS1-0 bits (see Table 9) a nd the output i s enabled by MCKO bit. The BICK output frequency is select ed between 32fs or

64fs, by BCKO bit (see Table 10).

K4642 DSP or µP

MCKO

BICK

LRCK

SDTO

SDTI

BCLK

LRCK

SDTI

SDTO

MCKI

1fs

32fs, 64fs

256fs/128fs/64fs/32fs

11.2896MHz, 12MHz, 12.288MHz

13.5MHz, 24MHz, 27MHz

MCLK

Figure 13. PLL Master Mode

Mode PS1 bit PS0 bit MCKO pin

0 0 0 256fs Default

1 0 1 128fs

2 1 0 64fs

3 1 1 32fs

Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)

BCKO bit BICK Output

Frequency

0 32fs Default

1 64fs

Table 10. BICK Output Frequency at Master Mode

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 PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the

AK4642 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4).

a) PLL reference clock: MCKI pin

BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not

matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the out put is enabled by MCKO bit.

Sampling frequency can be selected by FS3-0 bits (see Table 5).

K4642 DSP or µP

MCKO

BICK

LRCK

SDTO

SDTI

BCLK

LRCK

SDTI

SDTO

MCKI

1fs

≥ 32fs

11.2896MHz, 12MHz, 12.288MHz

13.5MHz, 24MHz, 27MHz

MCLK

256fs/128fs/64fs/32fs

Figure 14. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)

b) PLL reference clock: BICK or LRCK pin

Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6).

K4642

DSP or µP

MCKI

BICK

LRCK

SDTO

SDTI

BCLK

LRCK

SDTI

SDTO

MCKO

1fs

32fs, 64fs

Figure 15. PLL Slave Mode 2 (PLL Reference Clock: LRCK or BICK pin)

The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation

(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4642 may draw

excess current and it is not possible to operat e properly because ut ilizes dynam ic refre shed logic inte rnally. If the external

clocks are not prese nt, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”).

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 EXT Slave M ode (PMPLL bit = “0”, M/S bit = “0”)

When PMPLL bit is “0”, the AK4642 becom es EXT mode. Maste r clock is input from MCKI pin, the internal PLL ci rcuit

is not operate d. Thi s m ode i s c ompa tibl e with I/F of the norm al a udio COD EC. The cl ocks requi red to ope rate are M CKI

(256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.

The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 11).

Mode FS3-2 bits FS1 bit FS0 bit MCKI Input

Frequency Sampling Frequenc y

Range

0 Don’t care 0 0 256fs

7.35kHz ∼ 48kHz Default

1 Don’t care 0 1 1024fs

7.35kHz ∼ 13kHz

2 Don’t care 1 0 256fs

7.35kHz ∼ 48kHz

3 Don’t care 1 1 512fs

7.35kHz ∼ 26kHz

Others Others N/A N/A

Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M /S bit = “0”)

The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.

The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output

through LOUT/ROUT pins at fs=8kHz is shown in Table 12.

MCKI S/N

(fs=8kHz, 20kHzLPF + A-weighted)

256fs 83dB

512fs 93dB

1024fs 93dB

Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins

The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation

(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4642 may draw

excess current and it is not possible to operat e properly because ut ilizes dynam ic refre shed logic inte rnally. If the external

clocks are not prese nt, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bi ts = “0”).

K4642

DSP or µP

MCKI

BICK

LRCK

SDTO

SDTI

BCLK

LRCK

SDTI

SDTO

MCKO

1fs

≥ 32fs

MCLK

256fs, 512fs or 1024fs

Figure 16. EXT Slave Mode

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 System Reset

Upon power-up, the AK4642 should be reset by bringing the PDN pin = “L”. This ensure s that all int ernal regi sters reset

to their in iti al values .

The ADC enters an initi alization cycle that st arts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC

bits is “0”. The initiali zation cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital

data outputs of both channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal aft e r

the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle.

The DAC enters an in i tia liz ation cycle th at starts when the PMDAC b it is change d from “0” to “1 ” a t PMADL and

PMADR bits are “0” . The ini tializat ion cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the

DAC input digita l data of both channels are int ernally forced to a 2's com pliment, “0”. The DAC output reflect s the digital

input data after the initialization cycle is complete. When PMADC or PMADR bit is “1”, the DAC does not require an

initialization cycle.

 Audio Interface Format

Three types of dat a formats are avai lable and are sel ected by setti ng the DIF1-0 bits (seeTable 13). In all modes, the serial

data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LR CK

and BICK are output from the AK4642 in master mode, but must be input to the AK4642 in slave mode. The SDTO is

clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”).

Mode DIF1 bit DIF0 bit SDTO (ADC) SDTI (DAC) BICK Figure

0 0 0 N/A N/A N/A -

1 0 1 MSB justified LSB justified

≥ 32fs Figure 17

2 1 0 MSB justified MSB justified

≥ 32fs Figure 18 Default

3 1 1 I2S compatible I2S co mp atible ≥ 32fs Figure 19

Table 13. Audio Interface Format

If 16-bit data that ADC out puts is converted t o 8-bi t dat a by re m ovi ng LS B 8-bit, “ −1” at 16bit data is converted to “−1”

at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data

and this is a la rge offset. This offset can be rem oved by adding the offset of “128” to 16-bit data before converting to 8-bit

data.

LRCK

BICK(32fs)

SDTO(o)

SDTI(i)

15 14

110

76543210

6543 102

9 1112131415 0 123

15 14 13

1576543210

109 1112131415

BICK(64fs) 01162 3 17 18 31 0 1 2 3 1016 17 18 31

SDTO(o)

SDTI(i)

15 14 13

Don't Care 10

210

15 14

14Don't Care

15:MSB, 0:LSB

Lch Data Rch Data

15 14 13 76543 102

15 14 13 10

Figure 17. Mode 1 Timing

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LRCK

BICK(32fs)

SDTO(o)

SDTI(i)

15 14

110

76543210

6543 102

9 1112131415 0 123

15 14 13

1576543210

109 1112131415

BICK(64fs) 01162 3 17 18 31 0 1 2 3 1016 17 18 31

SDTO(o)

SDTI(i)

15 14 13

Don't Care

15 14

14 Don't Care

15:MSB, 0:LSB

Lch Data Rch Data

13 10 13 10 15

15 14 13 76543 102

15 14 13 10

Figure 18. Mode 2 Timing

LRCK

BICK(32fs)

SDTO(o)

SDTI(i)

15 14

110

76543210

6543 102

9 1112131415 0 123

15 14

76543210

109 1112131415

BICK(64fs) 01162 3 17 18 31 0 1 2 3 1016 17 18 31

SDTO(o)

SDTI(i)

15 14

Don't Care

15 Don't Care

15:MSB, 0:LSB

Lch Data Rch Data

14 21 14 21

0 0

0 15 14 765432108

15 14 210

Figure 19. Mode 3 Timing

 Mono/Stereo Mode

PMADL and PMADR bits set mono/stereo ADC operation.

PMADL bit PMADR bit ADC Lch data ADC Rch data

0 0 All “0” All “0” Default

0 1 Rch Input Signal Rch Input Signal

1 0 Lch Input Signal Lch Input Signal

1 1 Lch Input Signal Rch Input Si gnal

Table 14. Mono/Stereo ADC operation

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 Digital High Pass Filter

The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz

(@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is

enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is

enabled but the HPF of ADC is disabled.

 MIC/LINE Input Selector

The AK4642 has input selector. When MDIF1 and MDIF2 bits are “0”, INL and INR bits select LIN1/LIN2 and

RIN1/RIN2, respectively . When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+,

IN2+ and IN2− pins respecti vely. In this case, full-differential input is available (Figure 21).

MDIF1 bit MDIF2 bit INL bit INR bit Lch Rch

0 LIN1 RIN1 Default

0 1 LIN1 RIN2

0 LIN2 RIN1

0 1 1 LIN2 RIN2

0 x LIN1

IN2+/−

1 1 x N/A N/A

0 N/A N/A

0 x 1 IN1+/− RIN2

1 1 x x

IN1+/− IN2+/−

Table 15. MIC/Line In Path Se lect

LIN1/IN1− pin

DC Lch

RIN1/IN1+ pin

INL bit

MDIF1 bit

RIN2/IN2− pin

DC Rch

LIN2/IN2+ pin

INR bit

MDIF2 bit

AK4642

Figure 20. Mic/Line Input Selector

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IN1− pin

IN1+ pi n

MPWR pin

AK4642

MIC-Amp

Figure 21. Connection Example for Full-differential Mic Input (MDIF1/2 bits = “1”)

 MIC Gain Amplifier

The AK4642 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see

Table 16). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”,

“10” or “11”.

MGAIN1 bit MGAIN0 bit Input Gain

0 0 0dB

0 1 +20dB Default

1 0 +26dB

1 1 +32dB

Table 16. Mic Input Gain

 MIC Power

When PMMP bi t = “1”, the MPWR pi n supplies power for the mi crophone. This output voltage i s typically 0.75 x A VDD

and the load resista nce is minimum 0.5kΩ. In case of usi ng two sets of stereo m ic, the load resistance is minim um 2kΩ for

each channel. No capacitor must not be connected directly to MPWR pin (see Figure 22).

PMMP bit MPWR pin

0 Hi-Z Default

1 Output

Table 17. MIC Power

MPWR pin

≥ 2kΩ

MIC Po we r

Microphone

LIN1 pin

Microphone

RIN1 pi n

Microphone

LIN2 pin

Microphone

RIN2 pin

≥ 2kΩ

Figure 22. MIC Block C ircuit

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 Digital EQ/HPF/LPF

The AK4642 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic

Level Control) by digital doma in for A/D converted data (Figure 23). FIL1, FIL3 and EQ blocks are IIR filters of 1st

order. The fil ter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operat ion”

about ALC.

When only DAC is powered-up, digital EQ/HPF/LPF circuit operates at playback path. When only ADC is powered-up

or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit operates at recording path. Even if the path is

switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3, EQ,

FIL1 and GN1-0 bits should be set to “0” if digital EQ/HPF/LPF is not used for playback path.

PMADL bit, PMADR bit PMDAC bit LOOP bit Status Digital EQ/HPF/LPF

0 x Power-down Power-down Default

“00” 1 x Playback Playback path

0 x Recording Recording path

0 Recording & Playback Recording path

“01”, “10” or “11” 1 1 Recording Monitor Playback Recording path

Note 39. Stereo separation emphasis circuit is effective only at stereo operation.

Table 18. Digital EQ/HPF/LPF Cirtcuit Setting (x: Don’t care)

FIL3 coefficient also sets the attenuation of the stereo separat ion emphasis.

The combination of GN1-0 bit (Table 19) and EQ coefficient set the compensation gain.

FIL1 and FIL3 blocks become HPF when F1AS and F3AS bits are “0” and become LPF when F1AS and F3AS bits are

“1”, respectively.

When EQ and FIL1 bits a re “0”, EQ and FIL1 blocks becom e “through” (0dB). When FIL3 bit is “ 0”, FIL3 block become

“MUTE”. When each filter coefficient is changed, each filter should be set to “through” (“MUTE” in case of FIL3).

FIL3 FIL1 EQ Gain ALC

GN1-0

+24/+12/0dB

A ny coefficient

F1A13-0

F1B13-0

F1AS

Any coef ficien

F3A13-0

F3B13-0

F3AS

Any coeff ic ient

EQA15-0

EQB13-0

EQC15-0

+12dB ∼ 0dB

0dB

∼

-10dB

MUTE

(set by

FIL3 coefficient)

W ind- noise reduction St er eo separation emphasis Gain compensation

Figure 23. Digital EQ/HPF/LPF

GN1 GN0 Gain

0 0 0dB Default

0 1 +12dB

1 x +24dB

Table 19. Gain select of gain block (x: Don’t care)

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[Filter Co e fficient S ett in g]

1) Wh e n FIL1 an d FIL3 are set to “H PF”

fs: Sampling frequency

fc: Cut-off frequency

f: Input signal frequency

K: Filte r gain [dB] (Filte r gain of should be set to 0dB.)

FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B

FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B

(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)

A = 10K/20 x 1 / tan ( πfc/fs)

1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs)

1 + 1 / tan (πfc/fs)

Transfer function Amplitude Phase

H(z) = A 1 − z −1

1 + Bz −1

M(f) = A 2 − 2cos (2πf/fs)

1 + B2 + 2Bcos (2πf/fs)

θ(f) = tan

−

1(B+1)sin (2πf/fs)

1 - B + (B−1)cos (2πf/fs)

2) Whe n FI L1 an d FIL3 are set to “LP F”

fs: Sampling frequency

fc: Cut-off frequency

f: Input signal frequency

K: Filter gain [dB] (Filter gain of FIL1 should be set to 0dB.)

FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B

FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B

(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)

A = 10K/20 x 1

1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs)

1 + 1 / tan (πfc/fs)

Transfer function Amplitude Phase

H(z) = A 1 + z −1

1 + Bz −1

M(f) = A 2 + 2cos (2πf/fs)

1 + B2 + 2Bcos (2πf/fs)

θ(f) = tan

−

1(B−1)sin (2πf/fs)

1 + B + (B+1)cos (2πf/fs)

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3) EQ

fs: Sampling frequency

fc1: Pole frequency

fc2: Zero-point frequency

f: Input signal frequency

K: Filter gain [dB] (Maximum +12dB)

EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C

(MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0)

A = 10K/20 x 1 + 1 / tan (πfc2/fs)

1 + 1 / tan (πfc1/fs) B = 1 − 1 / tan (πfc1/fs)

1 + 1 / tan (πfc1/fs)

, C =10K/20 x 1 − 1 / tan (πfc2/fs)

1 + 1 / tan (πfc1/fs)

Transfer function Amplitude Phase

H(z) = A + Cz −1

1 + Bz −1

M(f) = A2 + C2 + 2ACcos (2πf/fs)

1 + B2 + 2Bcos (2πf/fs)

θ(f) = tan

−

1(AB−C)sin (2πf/fs)

A + BC + (AB+C)cos (2πf/fs)

[Translation the filt er coefficient calculated by the equa tions above from real number to binary code (2’s comp lement)]

X = (Real number of filter coefficient calculated by the equations a bove) x 213

X should be rounded to integer, and then should be translated to binary code (2’s complement).

MSB of each filter coefficient setting register is sine bit.

[Filter Co e fficient Sett ing Example ]

1) FIL1 block

Example: HPF, fs=44.1kHz, fc=100Hz

F1AS bit = “0”

F1A[13:0] bits = 01 1111 1100 0110

F1B[13:0] bits = 10 0000 0111 0100

2) EQ block

Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB

Gain[dB]

+8dB

fc1 fc2 Frequency

EQA[15:0] bits = 0000 1001 0110 1110

EQB[13:0] bits = 10 0001 0101 1001

EQC[15:0] bits = 1111 1001 1110 1111

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 ALC Operation

The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. When only DAC is powered-up, ALC

circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC circuit

operates at recording path.

PMADL bit, PMADR bit PMDAC bit LOOP bit Status ALC

0 x Power-down Power-down Default

“00” 1 x Playback Playback path

0 x Recording Recording path

0 Recording & Playback Recording path

“01”, “10” or “11” 1 1 Recording Monitor Playback Recording path

Table 20. ALC Setting (x: Don’t c are)

1. ALC Limite r Operation

During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 21), the IVL

and IVR values (sam e value) are attenuated a utomatically by the amount defined by the ALC limit er ATT step (Table 22).

The IVL and IVR are then set to the same value for both channels.

When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation

at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing

timeout period of both ALC limiter and recovery operation (Table 23).

When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by

ALC limiter operation. Attenuation step is fixed to 1 step regardl ess as the setting of LMAT1-0 bits.

The attenuati on operation is done continuously until t he input signal level becom es ALC limiter detect ion level (Table 21)

or less. After com pleting the att enuation operation, unless A LC bit is changed to “0”, the operation repeats when the input

signal level exceeds LMTH1-0 bits.

LMTH1 LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level

0 0

ALC Output ≥ −2.5dBFS −2.5dBFS > ALC Output ≥ −4.1dBFS Default

0 1

ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS

1 0

ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS

1 1

ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS

Table 21. ALC Limiter Detection Level / Recovery Counter Reset Level

ZELMN LMAT1 LMAT0 ALC Limiter ATT Step

0 0 1 step 0.375dB Default

0 1 2 step 0.750dB

1 0 4 step 1.500dB

1 1 8 step 3.000dB

1 x x 1step 0.375dB

Table 22. ALC Limiter ATT Step (x: Don’t care)

Zero Crossing Timeout Period

ZTM1 ZTM0 8kHz 16kHz 44.1kHz

0 0 128/fs 16ms 8ms 2.9ms Default

0 1 256/fs 32ms 16ms 5.8ms

1 0 512/fs 64ms 32ms 11.6ms

1 1 1024/fs 128ms 64ms 23.2ms

Table 23. ALC Zero Crossing Timeout Period

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2. ALC Recovery Operation

The ALC recovery operati on wai ts for the WTM1-0 bit s (Tabl e 24) to be set after com plet ing the ALC li m it er operat ion.

If the input signal does not exce ed “ALC recovery wait i ng counter reset le vel ” (Table 21) during the wait time, the ALC

recovery operation is done. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 25) up to

the set reference leve l (Table 26) with zero crossing detec tion which tim eout period is set by ZTM1-0 bits (Table 23).

Then the IVL and IVR a re set to the sam e value for both channels. The ALC recovery operation is done at a period set by

WTM1-0 bits. When zero cross is det ected at both channels during the wait pe riod set by WTM1-0 bits, the ALC recovery

operation waits until WTM1-0 period and the next recovery operation is done.

For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the

auto lim iter operation a nd then the i nput signal level i s gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds

the reference level (REF7-0), the IVOL values are not increased.

When

“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC li miter detection level (L MTH1-0)”

during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When

“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,

the waiting timer of ALC recovery operation starts.

The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation

becomes faster than a norma l recovery operat ion. When large noise i s input to m icrophone instant aneously, the qua lity of

small level in the large noise can be improved by this fast recovery operation.

ALC Recovery Operation Waiting Period

WTM1 WTM0 8kHz 16kHz 44.1kHz

0 0 128/fs 16ms 8ms 2.9ms Default

0 1 256/fs 32ms 16ms 5.8ms

1 0 512/fs 64ms 32ms 11.6ms

1 1 1024/fs 128ms 64ms 23.2ms

Table 24. ALC Recovery Operation Waiting Period

RGAIN1 RGAIN0 GAIN STEP

0 0 1 step 0.375dB Default

0 1 2 step 0.750dB

1 0 3 step 1.125dB

1 1 4 step 1.500dB

Table 25. ALC Recovery GAIN Step

REF7-0 GAIN(dB) Step

F1H +36.0

F0H +35.625

EFH +35.25

: :

E2H +30.375

E1H +30.0 Default

E0H +29.625

: :

03H −53.25

02H −53.625

01H −54.0

0.375dB

00H MUTE

Table 26. Reference Level at ALC Recovery operation

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3. Example of ALC Operation

Table 27 shows the examples of the ALC setting for mic recording.

fs=8kHz fs=44.1kHz

Regis t e r Name Comment Data Operation Data Operation

LMTH Limiter detection Level 01

−4.1dBFS 01 −4.1dBFS

ZELMN Limiter zero crossing detection 0 Enable 0 Enable

ZTM1-0 Zero crossing timeout period 01 32ms 11 23.2 ms

WTM1-0 Recovery waiting period

*WTM1-0 bits should be the sam e dat a

as ZTM1-0 bits 01 32ms 11 23.2ms

REF7-0 Maximum gain at recovery operation E1H +30dB E1H +30dB

IVL7-0,

IVR7-0 Gain of IVOL E1H +30dB E1H +30dB

LMAT1-0 Limiter ATT step 00 1 step 00 1 step

RGAIN1-0 Recovery GAIN ste p 00 1 step 00 1 step

ALC ALC enable 1 Enable 1 Enable

Table 27. Example of the ALC setting

The following registers should not be changed during the ALC operation. These bits should be changed after the ALC

operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.

• LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN

Manual Mode

* The value of IVOL should be

the same or smaller than REF’s

WR (ZTM1-0, WTM1-0)

WR (REF7-0)

WR (IVL/R7- 0)

WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)

Example:

Limiter = Zero crossing Enable

Recovery Cycle = 32ms@8kHz

Limiter and Recovery Step = 1

Maximum Gain = +30.0dB

Limit e r De tection Lev e l = −4.1dBFS

ALC bit = “1”

(1) Addr=06H, Data=14H

(2) Addr=08H, Data=E1H

(5) Addr=07H, Data=01H

(3) Addr=09H&0CH, Data=E1H

ALC Ope r ation

WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H

Note : W R : Write

Figure 24. Registers set-up sequence at ALC operation

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 Input Digital Volume (Manual Mode)

The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.

1. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH and etc)

2. When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.

For example; when t he change of the sampling frequency.

3. When IVOL is used as a manual volume.

IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 28). The IVOL value is changed at zero crossing or

timeout. Zero crossing tim eout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during

PMADL=PMADR bits = “0 ” , IV OL oper a tion starts wi th the written value s at the end o f the ADC ini tia lization cyc le

after PMADL or PMADR bit is changed to “1”.

Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and

IVR7-0 bits should be set to “91H” (0dB).

IVL7-0

IVR7-0 GAIN (dB) Step

F1H +36.0

F0H +35.625

EFH +35.25

: :

E2H +30.375

E1H +30.0 Default

E0H +29.625

: :

03H −53.25

02H −53.625

01H −54

0.375dB

00H MUTE

Table 28. Input Digita l Volume Setting

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When writing t o the IVL7-0 and IVR7-0 bits c ontinuouslly, the control re gister should be written by a n interval more than

zero crossing t imeout. If not, IVL a nd IVR are not changed since ze ro crossing counter is re set at every write operati on. If

the sam e regi ster value as the previ ous write opera tion is writ ten to IVL a nd IVR, thi s write operation is ignored and ze ro

crossing counter is not reset. Therefore, IVL and IVR can be written by an interval less than zero crossing timeout.

LC bit

LC Stat us Disable Enable Disable

IVL7-0 bits E1H(+30dB)

IVR7-0 bits C6H(+20dB)

Internal IVL E1H(+30dB) E1(+30dB) --> F1(+36dB) E1(+30dB)

Internal IVR C6H(+20dB) E1(+30dB) --> F1(+36dB) C6H(+20dB)

(1) (2)

Figure 25. IVOL value during ALC operation

(1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from

ALC bit = “1” t o ALC operation start by IV L7-0 bits is a t most recovery tim e (WTM1-0 bits) plus zerocross tim eout

period (ZTM1-0 bits).

(2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL

changes to the last written dat a by zero crossing or tim eout. When ALC is enabled again, ALC bit should be set to “1”

by an interval more than zero crossing timeout period after ALC bit = “0”.

ASAHI KASEI [AK4642EN]

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 De-emphasis Filter

The AK4642 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the

de-emphasis filter (Table 29).

DEM1 DEM0 Mode

0 0 44.1kHz

0 1 OFF Default

1 0 48kHz

1 1 32kHz

Table 29. De-emphasis Control

 Bass Boost Function

The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 30). If the BST1-0

bits are set to “01” (MIN Level), use a 47µF capaci tor for AC-coupling. If the boosted signal exceeds full scal e, the analog

output clips to the full scale. Figure 26 shows the boost frequency response at –20dB signal input.

Boost F ilt er (fs= 44. 1k Hz)

-5

10 100 1000 10000

Fre quenc y [ Hz]

Level [dB]

MAX

MID

MIN

Figure 26. Bass Boost Frequency Response (fs=44.1kHz)

BST1 BST0 Mode

0 0 OFF Default

0 1 MIN

1 0 MID

1 1 MAX

Table 30. Bass Boost Control

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 Digital Output Volume

The AK4642 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and

DVR7-0 bits. The volum e is i ncluded in front of a DAC block. The i nput data of DAC i s changed from +12 to –115dB or

MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control bot h Lch and Rch attenuation level s. When the DVOLC bit

= “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function.

The DVTM bit se ts the transition t im e between se t values of DVL/R7-0 bits a s ei ther 1061/fs or 256/fs (Tabl e 32). When

DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=24ms@fs=44.1kHz)

from 00H (+12dB) to FFH (MUTE).

DVL/R7-0 Gain

00H +12.0dB

01H +11.5dB

02H +11.0dB

: :

18H 0dB Default

: :

FDH −114.5dB

FEH −115.0dB

FFH MUTE (−∞)

Table 31. Digital Volume Code Table

Transition time between DVL/R7-0 bits = 00H and FFH

DVTM bit Setting fs=8kHz fs=44.1kHz

0 1061/fs 133ms 24ms Default

1 256/fs 32ms 6ms

Table 32. Transit ion Time Set t ing of Digital Output Volume

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 Soft Mute

Soft mute operati on is pe rformed in the digita l doma in. When the SMUTE bit goes to “1”, the output signa l is atte nuated

by −∞ (“0”) during the cycle set by t he DVTM bit. When the SMUTE bit i s returned to “ 0”, the m ute is cancell ed and the

output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the

soft mute i s cancelled within the cy cle set by the DVTM bit aft er starting the operation, the at tenuation is discontinued and

returned to t he value set by the DVL/R7-0 bit s. The soft m ute is effe ctive for changing t he signal source wit hout stopping

the signal transmission (F igure 27).

SM UTE bit

ttenuation

DVTM bit

DVL/R7-0 bits

-∞

DVTM bit

GD GD

(1)

(2)

(3)

nalog O utput

Figure 27. Soft Mute Function

(1) The output signal is attenuated until −∞ (“0”) by the cycl e set by the DVTM bit.

(2) Analog output corresponding to digital input has the group delay (GD).

(3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the

value set by the DVL/R7-0 bits .

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 Analog Mixing: Mono Input

When the PMBP bit is set t o “ 1”, the mono input is powered-up. When the BEEPS bit is set to “1”, the input signal from

the MIN pin i s output t o Spea ker-Am p. When t he BEEPH bi t i s set t o “1”, t he input si gnal from the M IN pin i s output t o

Headphone-Amp. When the B EEP L bit is set t o “1”, the i nput signa l from the MIN pin is output to t he st e reo line output

amplifie r. The external resist er Ri adjusts the signal le vel of MIN input. Table 33, Table 34 and Table 35 show the typical

gain ex a mpl e at Ri = 20kΩ. This gain is in inverse proporti on to Ri .

MIN Ri

LOUT/ROUT pin

BEEPL

HPL/HPR pin

BEEPH

SPP/SPN pin

BEEPS

Figure 7. Block Diagram of MIN pin

LOVL bit MIN Æ LOUT/ROUT

0 0dB Default

1 +2dB

Table 33. MIN Input Æ LOUT/ROUT Output Gain (typ) at Ri = 20kΩ

HPG bit MIN Æ HPL/HPR

0 −20dB Default

1 −16.4dB

Table 34. MIN Input Æ Headphone-Amp Output Gai n (typ) at Ri = 20kΩ

MIN Æ SPP/S PN

SPKG1-0 bits ALC bit = “0” ALC bit = “1”

00 +4.43dB +6.43dB Default

01 +6.43dB +8.43dB

10 +10.65dB +12.65dB

11 +12.65dB +14.65dB

Table 35. MIN Input Æ Speaker-Amp Output Gain (typ) at Ri = 20kΩ

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 Stereo Line Output (LOUT/ROUT pins)

When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When

DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ

(min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is

pulled-down to AVS S by 100kΩ(typ). When the LOPS bit i s “1”, stereo line output enters powe r-save mode. Pop noi se at

power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be

pulled-down to AVS S by 20kΩ after AC coupled as Figure 29. Rise/ Fall tim e is 300m s(max) at C=1µF. When PMLO bit

= LOPS bit = “1”, stereo line output is in normal operation.

LOVL bit set the gain of stereo line output.

DAC

“DACL”

LOUT pin

ROUT pin

“LOVL”

Figure 28. Stereo Line Output

LOPS PMLO Mode LOUT/ROUT pin

0 Power-down Pull-down to AVSS Default

0 1 Normal Operation Normal Operation

0 Power-save Fall down to AVSS

1 1 Power-save Rise up to VCOM

Table 36. Stereo Line Output Mode Select (x: Don’t care )

LOVL Gain Output Voltage (typ)

0 0dB 0.6 x AVDD Default

1 +2dB 0.757 x AVDD

Table 37. Stereo Line Output Volume Setting

LOUT

ROUT 1

F 220

Ω

20k

Ω

Figure 29. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)

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[Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)]

PM LO bit

L OPS bit

LO UT, RO UT pins

(1)

(2)

N orm al O utput

(3) (4)

(5)

(6)

≥ 300 m s ≥ 300 m s

Figure 30. Stereo Line Output Control Sequence (in case of using Pop Re duction Circuit)

(1) Set LOPS bit = “1”. Stereo line output enters the power-save mode.

(2) Set PMLO bit = “1”. Stereo line output exits the power-down mode.

LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF.

(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.

Stereo line output is enabled.

(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.

(5) Set PMLO bit = “1”. Stereo line output enters power-down mode.

LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1µF.

(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.

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 Headphone Output

Power supply volta ge for the Headphone-Amp is suppl ied from the HVDD pin and centered on the HVDD/2 voltage. The

load resistance is 16Ω (min). HPG bit selects the output voltage (see Table 38).

HPG bit 0 1

Output Voltage [Vpp] 0.6 x AVDD 0.91 x AVDD

Table 38. Headphone-Amp Output Voltage

When the HPMTN bit is “0”, the com mon voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to

“L” (HVSS). When the HPMTN bit is “1”, the common voltage rises to HVDD/2. A capacitor between the MUTET pin

and ground reduces pop noise at power-up. R ise/F all ti me constant is i n proporti onal to HVDD volt age and the capaci tor

at MUTET pin.

[Example]: A capacitor between the MUTET pin and ground = 1.0µF , HVDD=3.3V:

Rise/fall time co n s ta nt: τ = 100ms(typ), 250ms(max)

Time until the common goes to HVSS when HPMTN bit = “1” Æ “0”: 500ms(max)

When PMHPL and PMHPR bits are “0”, the He adphone-Amp is powered-dow n, and the outputs (HPL a nd HPR pins) go

to “L” (HVSS).

PMHPL bit,

PMHPR bit

(1) (2) (4)(3)

HPMTN bit

HPL pin,

HPR pin

Figure 31. Power-up/Power-down Timing for Headphone-Amp

(1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still HVSS.

(2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common volta ge of Headphone-Amp is rising.

(3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling.

(4) Headphone-Amp power-down (PMHPL, PMHP R bit = “0”). The outputs are HVSS. If the power supply is switc hed

off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some POP noise occurs.

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When BOOST=OFF, the cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This

fc can be shifted to lower frequency by using bass boost function. Table 39 shows the cut off frequency and the output

power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. Output powers are shown at

HVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp).

When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22µF±20% capacitor and

10Ω±20% resistor) because it has the possibility that Headphone-Amp oscillates.

AK4642

HP-AMP

16Ω

Headphone

10Ω

0.22µ

R C

Figure 32. External Circuit Example of Headphone

Output Power [mW]@0dBFS

HPG bit R [Ω] C [µF] fc [Hz]

BOOST=OFF fc [Hz]

BOOST=MIN

@fs=44.1kHz 2.7V 3.0V 3.3V

100 70 28

6.8 47 149 78 10.1 12.5 15.1

100 50 19

0 16 47 106 47 5.1 6.3 7.7

220 45 17

0 100 100 43 33 41 50

22 62 25

1 100 10 137 69 0.9 1.1 1.3

Table 39. External Circuit Example

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 Speaker Output

Power supply for Speaker-Amp (HVDD ) is 2.6V to 5.25V. In case of dynami c (electrom agnetic) speaker (load re sistance

< 50Ω), HVDD is 2.6V to 3.6V.

Speaker Type Dynamic Speaker Piezo (Ceramic) Speaker

HVDD 2.6 ∼ 3.6V 2.6 ∼ 5.25V

Load Resistance (min) 8Ω 50Ω (Note 23)

Load Capacitance (max) 30pF 3µF (Note 23)

Note 23. Load im pedance is tota l impedanc e of series resist ance and piezo speaker im pedance at 1kHz i n Figure 33. Load

capacita nce is capa cit ance of piezo spea ker. When piez o speaker is used, 10 Ω or more series resi stors should be

connected at both SPP and SPN pins, respectively.

Table 40. Speaker Type and Power Supply Range

The DAC output signal is i nput to the Spe aker-am p as [(L+R)/2] . The S peaker-am p is m ono and BTL out put. The gain is

set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.

Gain

SPKG1-0 bits ALC bit = “0” ALC bit = “1”

00 +4.43dB +6.43dB Default

01 +6.43dB +8.43dB

10 +10.65dB +12.65dB

11 +12.65dB +14.65dB

Table 41. SPK-Amp Gain

SPK-Amp Output (DA C Input = 0dBFS)

AVDD HVDD SPKG1-0 bits ALC bit = “0” A L C b it = “1”

(LMTH1-0 bits = “00”)

00 3.30Vpp 3.11Vpp

01 4.15Vpp (Note 40) 3.92Vpp

10 6.75Vpp (Note 40) 6.37Vpp (Note 40)

3.3V

11 8.50Vpp (Note 40) 8.02Vpp (Note 40)

00 3.30Vpp 3.11Vpp

01 4.15Vpp 3.92Vpp

10 6.75Vpp 6.37Vpp

3.3V

5.0V

11 8.50Vpp 8.02Vpp

Note 40. The output l evel is ca lcula ted by assuming that output signa l is not cl ipped. In actual case, output signal m ay be

clipped when DAC output s 0dBFS signal. DAC output level should be set to lower level by setti ng digital

volume so that Speaker-Amp output level is 4.0Vpp or less and output signal is not clipped.

Table 42. SPK-Amp Output Level

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fs=44.1kHz

LMTH Limiter detection Level 00

−2.5dBFS

ZELMN Limiter zero crossing detection 0 Enable

ZTM1-0 Zero crossing timeout period 10 11.6ms

WTM1-0 Recovery waiting period

*WTM1-0 bits should be the sa me data

as ZTM1-0 bits 11 23.2ms

REF7-0 Maximum gain at recovery operation C1H +18dB

IVL7-0,

IVR7-0 Gain of IVOL 91H 0dB

LMAT1-0 Limiter ATT step 00 1 step

RGAIN1-0 Recovery GAIN step 00 1 step

ALC ALC enable 1 Enable

Table 43. ALC Operati on Example of Speaker Playback

When a piezo speake r (load capacitance > 30pF) is used, resist ances more than 10Ω shoul d be inserted bet ween SPP/SPN

pins and speaker in series, respectively, as shown in Figure 33. Zener diodes should be inserted between speaker and

GND as shown in Figure 33, i n order to protect SPK-Amp of AK4642 f rom the power that the pi ezo speaker outputs when

the speaker is pressured. Zener diodes of the following zener voltage should be used.

0.92 x HVDD ≤ Zener voltage of zener diodo (ZD in Figure 33) ≤ HVDD+0.3V

Ex) In case of HVDD = 5.0V: 4.6V ≤ ZD ≤ 5.3V

For example, zener diode which zener voltage is 5.1V(Min: 4.97V, Max: 5.24V) can be used.

SPP

SPK-Amp

SPN

≥10

Ω

≥10

Ω

Figure 33. Speaker Output Circuit (Load Capacitance > 30pF)

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<Speaker-Amp Control Sequence>

Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pin are in Hi-Z state.

When PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-Am p enters powe r-save mode. In this mode, SPP pi n is placed

in Hi-Z state and SPN pin goes to HVDD/2 voltage. Power-save mode can reduce the pop noise at power-up and

power-down.

PMSPK SPPSN Mode SPP SPN

0 x Power-down Hi-Z Hi-Z Default

0 Power-save Hi-Z HVDD/2

1 1 Normal Operation Normal Operation Normal Operation

Table 44. Speaker-Amp Mode Setting (x: Don’t care)

PMSPK bit

SPPSN bit

SPP pin

SPN pin HVDD/2 HVDD/2

Hi-Z Hi-Z

Figure 34. Power-up/Power-down Timing for Speaker-Amp

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 Serial Control Interface

(1) 3-wire Serial Control Mode (I 2C pin = “L”)

Internal regist ers may be writt en by using the 3-wire µP inte rface pins (CSN, CCLK and CDTI). The data on this interface

consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Regi ster address (M SB first, 5bits) and

Control data (MSB first, 8bi ts). Each bit is cl ocked in on the rising edge (“↑”) of CC LK. Addre ss and data are lat ched on

the 16th CCLK rising edge (“↑”) a fter CSN fall ing edge(“↓”). Clock speed of CCLK is 5MH z (max). The value of

internal registers are initial ized by PDN pin = “L”.

CSN

CCLK 0 1 2 34567891011

12 13 14 15

CDTI C1 C0

4 D7D6D5D4D3D2D1D0

R/W

C1-C0: Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”

R/W: READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”

4-A0: Register Address

D7-D0: Control data

“1” “0” “1”

Figure 35. Serial Control I/F Timing

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(2) I2C-bus Control Mode (I2 C pin = “H”)

The AK4642 supports the fast-mode I2C-bus (max: 400kHz).

(2)-1. WRITE Operations

Figure 36 shows the dat a t ransfer se quence for the I2C-bus mode. All commands are preceded by a START condition. A

HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the

START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit

(R/W). The m ost significant si x bits of the slave address are fixed as “001001”. The next bi t is CAD0 (device address bit).

This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits

(Figure 37). If the slave addre ss ma tches that of t he AK4642, the AK4642 genera tes an acknowledge and the operation is

executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the

acknowledge clock pulse (Figure 43). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”

indicate s that the writ e operatio n is to be ex ec u ted.

The second byte consists of the control register address of the AK4642. The format is MSB first, and those most

significant 3-bits are fixed to zeros (Figure 38). The data after the second byte conta ins control data. The form at is MSB

first, 8bits (Figure 39). The AK4642 generates an acknowledge after each byte has been received. A data transfer is

always te rminate d by a STOP condit ion generate d by the mast er. A LOW to HIGH transition on the SDA line while SCL

is HIGH defines a STOP condition (Figure 42).

The AK4642 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4642

generates an acknowl edge and awaits the next dat a. The master can transm it more than one byte instead of termi nating the

write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is

incremented by one, and the next data is aut omatically taken into the next address.

The data on the SDA line m ust remain sta ble during the HIGH period of the clock. The HIGH or LOW state of the data

line can only change when the clock signal on the SCL line is LOW (Figure 44) except for the START and STOP

conditions.

SDA Slave

Address

R/W="0"

Sub

Address(n) A

Data(n)

Data(n+1)

Data(n+x)

Figure 36. Data Transfer Sequence at the I2C-Bus Mode

0 0 1 0 0 1 CAD0 R/W

(Those CAD1/0 should match with CAD1/0 pins)

Figure 37. The First By te

0 0 0 A4 A3 A2 A1 A0

Figure 38. The Second Byte

D7 D6 D5 D4 D3 D2 D1 D0

Figure 39. Byte Structure after the second byte

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(2)-2. READ Operations

Set the R/W bit = “1” for the READ operat ion of the AK4642. After transmission of data, the master can read the next

address’s data by generating an acknowle dge instead of termi nating the wri te cycl e after the rec eipt of the fi rst data word.

After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is

automatically taken into the next address. If the address exceeds 1FH prior to generating a stop condition, the address

counter will “roll over” to 00H and the previous data will be overwritten.

The AK4642 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.

(2)-2-1. CURRENT ADDRESS READ

The AK4642 contains an inte rnal address counter that maintains the address of the last word accessed, incremented by

one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would

access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4642 generates an

acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal

address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,

the AK4642 ceases transmission.

SDA Slave

Address

R/W="1"

Data(n+1)

Data(n+2)

Data(n+x)

Data(n)

Figure 40. CURRENT ADDRESS READ

(2)-2-2. RANDOM ADDRESS READ

The random read operat ion allows the master to a ccess any m em ory location at random. Pri or to issuing the slave address

with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a

slave address (R/W bit = “0”) and then the register address to read. Afte r the register address is acknow ledged, the m aster

immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4642 then generates an

acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an

acknowledge to the data but instead generates a stop condi tion, the AK4642 ceases transmission.

SDA Slave

Address

R/W="0"

Data(n)

Data(n+x)

Sub

Address(n) SSlave

Address

R/W="1"

Data(n+1)

Figure 41. RANDOM ADDRESS READ

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SCL

SDA

stop co nditionstart condition

Figure 42. START and STOP C onditions

SCL FROM

MASTER

acknowledge

DATA

OUTPUT BY

TRANSMITTER

DATA

OUTPUT BY

RECEIVER

1 98

START

CONDITION

not acknowledge

clock pulse for

acknowledgement

Figure 43. Acknowledge on the I2C-Bus

SCL

SDA

data line

stable;

data valid

change

of data

allowed

Figure 44. Bit Transfer on the I2C-Bus

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 Register Map

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Management 1 0 PMVCM PMBP PMSPK PMLO PMDAC 0 PMADL

01H Power Management 2 0 HPMTN PMHPL PMHPR M/S 0 MCKO PMPLL

02H Signal Select 1 SPPSN BEEPS DACS DACL 0 PMMP 0 MGAIN0

03H Signal Select 2 LOVL LOPS MGAIN1 SPKG1 SPKG0 BEEPL 0 0

04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0

05H Mode Control 2 PS1 PS0 FS3 0 0 FS2 FS1 FS0

06H Timer Select DVTM 0 ZTM1 ZTM0 WTM1 WTM0 0 0

07H ALC Mode Control 1 0 0 ALC ZELMN LMAT1 LMAT0 RGAIN0 LMTH0

08H ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0

09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0

0AH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0

0BH ALC Mode Control 3 RGAIN1 LMTH1 0 0 0 0 0 0

0CH Rch Input Volume Cont rol IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0

0DH Rch Digital Volume C on trol DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0

0EH Mode Control 3 0 LOOP SMUTE DVOLC BST1 BST0 DEM1 DEM0

0FH Mode Control 4 0 0 0 0 IVOLC HPM BEEPH DACH

10H Power Management 3 0 0 HPG MDIF2 MDIF1 INR INL PMADR

11H Digital Filter Select GN1 GN0 0 FIL1 EQ FIL3 0 0

12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0

13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8

14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0

15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8

16H EQ Co-efficient 0 EQA7 EQA6 EQA5 EQA4 EQA3 EQA2 EQA1 EQA0

17H EQ Co - e f f i c ient 1 EQA15 EQA14 EQ A1 3 EQA12 EQA 11 E Q A10 EQA9 EQA8

18H EQ Co-efficient 2 EQB7 EQB6 EQB5 EQB4 EQB3 EQB2 EQB1 EQB0

19H EQ Co-efficient 3 0 0 EQB13 E QB12 EQB11 E QB10 E QB9 EQB8

1AH EQ Co-efficient 4 EQC7 EQC6 EQC5 EQC4 EQC3 EQC2 EQC1 EQC0

1BH E Q Co-efficient 5 EQC15 EQC14 EQC13 E QC12 EQC11 EQC10 E QC9 EQC8

1CH FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0

1DH FIL1 Co-efficient 1 F1AS 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8

1EH FIL 1 Co -e ffi c ie n t 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0

1FH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8

Note 41. PDN pin = “L” resets the registers to their default values.

Note 42. Unused bits must contain a “0” value.

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 Register Definitions

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

00H Power Management 1 0 PMVCM PMBP PMSPK PMLO PMDAC 0 PMADL

Default 0 0 0 0 0 0 0 0

PMADL: MIC-Amp Lch and ADC Lch Power Management

0: Power-down (Default)

1: Power-up

When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms

@44.1kHz) starts. After initializing, digital data of the ADC is output.

PMDAC: DAC Power Management

0: Power-down (Default)

1: Power-up

PMLO: Stereo Line Out Power Management

0: Power-down (Default)

1: Power-up

PMSPK: Speaker-Amp Power M a nagement

0: Power-down (Default)

1: Power-up

PMBP: MIN Input Power Management

0: Power-down (Default)

1: Power-up

Both PMDAC and PMBP bits should be set t o “1” when DAC is powered-up for playback. After that, BEEP L,

BEEPH or BEEPS bit is used to control each path when MIN input is used.

PMVCM: VCOM Power Management

0: Power-down (Default)

1: Power-up

When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only

when all power management bits of 00H, PMPLL and MCKO bits are “0”.

Each block c an be powered-down respec tively by writi ng “0” in e ach bit of this address. When the PDN pi n is “L”, a ll

blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.

When all power managem ent bits are “0” in the 00H, 01H, 02H a nd 10H addresses and MCKO bit i s “0”, all blocks are

powered-down. The register values remain unchanged.

When neither ADC nor DAC are used, external clocks m ay not be present. When ADC or DAC is use d, external clocks

must al ways be present.

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Power Managemen t 2 0 HPMTN PMHPL PM HPR M/S 0 MCKO PMPLL

Default 0 0 0 0 0 0 0 0

PMPLL: PLL Power Management

0: EXT Mode and Power-Down (Default)

1: PLL Mode and Power-up

MCKO: Master Clock Output Enable

0: Disable: MCKO pin = “L” (Default)

1: Enable: Output frequency is selected by PS1-0 bits.

M/S: Master / Slave Mode Select

0: Slave Mode (Default)

1: Master Mode

PMHPR: Headphone-Am p Rc h Power Management

0: Power-down (Default)

1: Power-up

PMHPL: Headphone-Amp Lch Power Management

0: Power-down (Default)

1: Power-up

HPMTN: Headphone-Amp Mute Control

0: Mute (Default)

1: Normal operation

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Signal Sel e c t 1 SPPSN BEEP S DACS DACL 0 PMMP 0 MGAIN0

Default 0 0 0 0 0 0 0 1

MGAIN1-0: MIC-Amp Gain Control (See Table 16)

MGAIN1 bit is D5 bit of 03H.

PMMP: MPWR pin Power Management

0: Power-down: Hi-Z (Default)

1: Power-up

DACL: Switch Control from DAC to Stereo Li ne Output

0: OFF (Default)

1: ON

When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.

DACS: Switch Control from DAC to Speaker-Amp

0: OFF (Default)

1: ON

When DACS bit is “1”, DAC output signal is input to Speaker-Amp.

BEEPS: Switch Control from MIN pin to Speaker-Amp

0: OFF (Default)

1: ON

When BEEPS bit is “1”, mono signal is input to Speaker-Amp.

SPPSN: Speaker-Amp Power-Save Mode

0: Power-Save Mode (Default)

1: Normal Operation

When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, SPP pin goes to Hi-Z and SPN

pin is outputs HVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to

“H”, Speaker-Amp is in power-down mode since PMSPK bit is “0”.

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

03H Signal Sel e c t 2 LOVL LOPS MGAIN1 SPKG1 SPKG0 BEEPL 0 0

Default 0 0 0 0 0 0 0 0

BEEPL: Switch Control from MIN pin to Stereo Line Output

0: OFF (Default)

1: ON

When PMLO bit is “1”, BEEPL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.

SPKG1-0: Speaker-Amp Output Gain Select (See Table 41)

MGAIN1: MIC-Amp Gain Control (Se e Table 16)

LOPS: Stereo Line Output Power-Save Mode

0: Normal O p eration (Defau lt)

1: Power-Save Mode

LOVL: Stereo Line Output Gain Select (Table 37)

0: 0dB (Default)

1: +2dB

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0

Default 0 0 0 0 0 0 1 0

DIF1-0: Audio Interface Format (See Table 13)

Default: “10” (Lef t j utified)

BCKO: BICK Output Frequency Select at Master Mode (See Table 10)

PLL3-0: PLL Reference Clock Select (See Table 4)

Default: “0000”(LRCK pin)

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

05H Mode Control 2 PS1 PS0 FS3 0 0 FS2 FS1 FS0

Default 0 0 0 0 0 0 0 0

FS3-0: Sampling Frequency Select (See Table 5 and Table 6.) and MCKI Frequency Select (See Table 11.)

FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.

PS1-0: MCKO Output Frequency Se lect (Table 9)

Default: “00”(256fs)

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

06H Timer Select DVTM 0 ZTM1 ZTM0 WTM1 WTM0 0 0

Default 0 0 0 0 0 0 0 0

WTM1-0: ALC Recovery Waiting Period (see Table 24.)

Default: “ 00” (128/fs)

ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (see Table 23.)

Default: “ 00” (128/fs)

DVTM: Digital Volume Transition Time Setting (see Table 32.)

0: 1061/fs (Default)

1: 256/fs

This is the transition time between DVL/R7-0 bits = 00H and FFH.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

07H ALC Mode Control 1 0 0 ALC ZELMN LMAT1 LMAT0 RGAIN0 LMTH0

Default 0 0 0 0 0 0 0 0

LMTH1-0: ALC Lim iter Detecti on Level / Recovery Counter Rese t Level (see Table 21.)

Defau lt: “ 00”

LMTH1 bit is D6 bit of 0BH.

RGAIN1-0: ALC Recovery GAIN Step (see Table 25.)

Defau lt: “ 00”

RGAIN1 bit is D7 bit of 03H.

LMAT1-0: ALC Limiter ATT Step (see Table 22.)

Defau lt: “ 00”

ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation

0: Enable (Default)

1: Disable

ALC: ALC Enable

0: ALC Disable (Default)

1: ALC Enable

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

08H ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0

Default 1 1 1 0 0 0 0 1

REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (see Table 26.)

Default: “ E1H” (+3 0 . 0 d B )

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0

0CH R c h Input Vol ume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0

Default 1 1 1 0 0 0 0 1

IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (see Table 28.)

Default: “ E1H” (+3 0 . 0 d B )

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

0AH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0

0DH Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0

Default 0 0 0 1 1 0 0 0

DVL7-0, DVR7-0: Output Digital Volum e (see Table 31.)

Default: “ 1 8H” (0dB )

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

0BH ALC Mode Control 3 RGAIN1 LMTH1 0 0 0 0 0 0

Default 0 0 0 0 0 0 0 0

LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (see Table 21.)

RGAIN1: ALC Recovery GAIN Step (see Table 25.)

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

0EH Mode Control 3 0 LOOP SMUTE DVOLC BST1 BST0 DEM1 DEM0

Default 0 0 0 1 0 0 0 1

DEM1-0: De-emphasi s Frequency Select (Table 29)

Default: “ 01” (OFF)

BST1-0: Bass Boost Function Select (Table 30)

Default: “ 00” (OFF)

DVOLC : Output Di g ita l Volume Control Mode Sel ec t

0: Independent

1: Dependent (Default)

When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of

DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and

DVR7-0 bits control Rch level, respectively.

SMUTE: Soft Mute Control

0 : No rmal Oper a tio n (Def ault)

1: DAC outputs soft-muted

LOOP: Digital Loopback Mode

0: SDTI → DAC (Default)

1: SDTO → DAC

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

0FH Mode Control 4 0 0 0 0 IVOLC HPM BEEPH DACH

Default 0 0 0 0 1 0 0 0

DACH: Switch Control from DAC to Headphone-Amp

0: OFF (Default)

1: ON

BEEPH: Switch Control from MIN pin to Headphone-Amp

0: OFF (Default)

1: ON

HPM: Headphone-Amp Mono Output Select

0: Stereo (Default)

1: Mono

When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-Amp. Both PMHPL

and PMHPR bits should be “1” when HPM bit is “1”.

IVOLC: Input Digital Volume Control Mode Select

0: Independent

1: Dependent (Default)

When IVOLC bit = “1” , IVL7-0 bit s control both Lch and R ch volum e le vel , whil e re gist er val ues of IVL7-0

bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits

control Rch level, respectively.

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

10H Power Management 3 0 0 HPG MDIF2 MDIF1 INR INL PMADR

Default 0 0 0 0 0 0 0 0

PMADR: MIC-Amp Lch and ADC Rch Power Management

0: Power-down (Default)

1: Power-up

INL: ADC Lch Input Source Select

0: LIN1 pin (Default)

1: LIN2 pin

INR: ADC Rch Input Source Select

0: RIN1 pin (Default)

1: RIN2 pin

MDIF1: ADC Lch Input Type Select

0: Single-ended input (LIN1/LIN2 pin: Default)

1: Full-differential input (IN1+/IN1− pin)

MDIF2: ADC Rch Input Type Select

0: Single-ended input (RIN1/RIN2 pin: Default)

1: Full-differential input (IN2+/IN2− pin)

HPG: Headphone-Amp Gain Select (see Table 38.)

0: 0dB (Default)

1: +3.6dB

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

11H Digital Filter Select GN1 GN0 0 FIL1 EQ FIL3 0 0

Default 0 0 0 0 0 0 0 0

GN1-0: Gain Select at GAIN block (see Table 19.)

Defau lt: “ 00”

FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable

0: Disable (Defau l t)

1: Enable

When FIL3 bit is “1”, the set tings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block

is OFF (MUTE).

EQ: EQ (Ga in Compen sation F ilt er) Coef ficient S et tin g Enable

0: Disable (Defau l t)

1: Enable

When EQ bit is “1 ” , th e setting s o f EQA15 -0, EQB1 3 -0 and EQ C 1 5 -0 bits are en a bled. When EQ bi t i s “ 0 ”,

EQ block is through (0dB).

FIL1: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable

0: Disable (Defau l t)

1: Enable

When FIL1 bit is “1”, the set tings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block

is through (0dB).

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0

13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8

14H FIL3 Co-effici e n t 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0

15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8

16H EQ Co-efficient 0 EQA7 EQA6 EQA5 EQA4 EQA3 EQA2 EQA1 EQA0

17H EQ Co-efficient 1 EQA15 EQA14 EQA13 EQA12 EQA11 EQA10 EQA9 EQA8

18H EQ Co-efficient 2 EQB7 EQB6 EQB5 EQB4 EQB3 EQB2 EQB1 EQB0

19H EQ Co-efficient 3 0 0 EQB13 EQB12 EQB11 EQB10 EQB9 EQB8

1AH EQ Co-efficient 4 EQC7 EQC6 EQC5 EQC4 EQC3 EQC2 EQC1 EQC0

1BH EQ Co-efficient 5 EQC15 EQC14 EQC13 EQC12 EQC11 EQC10 EQC9 EQC8

1CH FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0

1DH FIL1 Co-efficient 1 F1AS 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8

1EH FIL1 Co-effici en t 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0

1FH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F 1B1 0 F1B9 F1B8

Default 0 0 0 0 0 0 0 0

F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2)

Default: “0000H”

F3AS: FIL3 (Stereo Se paration Emphasis Filter) Select

0: HPF (Default)

1: LPF

EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1)

Default: “0000H”

F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2)

Default: “0000H”

F1AS: FIL1 (Wind-noise Reduction Filter) Select

0: HPF (Default)

1: LPF

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SYSTEM DESIGN

Figure 45 and Figure 46 shows the system connection diagram for the AK4642. An evaluation board [AKD4642] is

available which demonstrates the optimum layout, power supply arrangements and measurement results.

MUTET

ROUT

LOUT

MIN

RIN2

LIN2

LIN1

RIN1

HPL

HPR

HVSS

HVDD

SPP

SPN

MCKO

MCKI

MPWR

VCOM

VSS

VDD

VCOC

I2C

PDN

CSN

DVSS

DVDD

BICK

LRCK

SDTO

SDTI

CDTI

CCLK

K4642EN

Top View

2.2

External MIC

Internal MIC

0.1u

2.2u

0.1u

6.8 47u

10 0.22u

Power Supply

2.6 ∼ 3.6V

0.1u

DSP

Line Out

Headpho ne Speaker

Mono In

10u

Analog Ground Digital Ground

200

20k

ZD2

ZD1

Dynamic SPK

R1, R2: Short

ZD1, ZD 2: Open

Piezo SPK

R1, R2: ≥10Ω

ZD1, ZD 2: Requir ed

Notes:

- AVSS, DVSS and HVSS of the AK4642 should be distributed separately from the ground of external

controllers.

- All digital input pins should not be left floating.

- When the AK4642 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.

- When the AK4642 is PLL m ode (PMPLL bit = “1”), a resistor a nd capacitor of VCO C pin is shown in Tabl e 4.

- When piezo speaker is used, 2.6 ∼ 5.25V power should be supplie d to HVDD and 10Ω or m ore series resistors

should be connected to both SPP and SPN pins, respectively.

- When the AK4642 is used at m aster mode , LRCK and BICK pins are floating before M/S bit is changed to “1”.

Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4642.

Figure 45. Typical Connection Diagram (MIC Input)

ASAHI KASEI [AK4642EN]

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MUTET

ROUT

LOUT

MIN

RIN2

LIN2

LIN1

RIN1

HPL

HPR

HVSS

HVDD

SPP

SPN

MCKO

MCKI

MPWR

VCOM

VSS

VDD

VCOC

I2C

PDN

CSN

DVSS

DVDD

BICK

LRCK

SDTO

SDTI

CDTI

CCLK

K4642EN

Top View

Line In

0.1u

2.2u

0.1u

6.8 47u

10 0.22u

Power Supply

2.6 ∼ 3.6V

0.1u

DSP

Line Out

Headpho ne Speaker

Mono In

10u

Analog Ground Digital Ground

200

20k

ZD2

ZD1

Dynamic SPK

R1, R2: Short

ZD1, ZD 2: Open

Piezo SPK

R1, R2: ≥10Ω

ZD1, ZD 2: Requir ed

Notes:

- AVSS, DVSS and HVSS of the AK4642 should be distributed separately from the ground of external

controllers.

- All digital input pins should not be left floating.

- When the AK4642 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.

- When the AK4642 is PLL m ode (PMPLL bit = “1”), a resistor a nd capacitor of VCO C pin is shown in Tabl e 4.

- When piezo speaker is used, 2.6 ∼ 5.25V power should be supplie d to HVDD and 10Ω or m ore series resistors

should be connected to both SPP and SPN pins, respectively.

- When the AK4642 is used at m aster mode , LRCK and BICK pins are floating before M/S bit is changed to “1”.

Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4642.

Figure 46. Typical Connection Diagram (Line Input)

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1. Grounding and Power Supply Decoupling

The AK4642 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and HVDD are

usually supplied from the system’s analog supply. If AVDD, DVDD and HVDD are supplie d separately, the power-up

sequence is not cri tical. AVSS, D VSS and HVSS of the AK4642 should be connect ed to the analog ground plane. Syst em

analog ground and digital ground shoul d be c onnected together near to where the supplies are brought onto the printed

circuit boa rd. Decoupli ng capacit ors should be as ne ar to th e AK4642 a s possi ble, wit h the sm al l val ue ceram ic capaci tor

being the nearest.

2. Voltage Reference

VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached

to the VCOM pin eli m ina tes t he effe cts of high frequency noi se. No loa d current m ay be dra wn from the VCOM pin. All

signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the

AK4642.

3. Analog Inputs

The Mic, Li ne and MIN inputs a re single-ended. The input signal range sca les with nominall y at 0.06 x AVDD Vpp (typ)

for the Mic input and 0.6 x AVDD Vpp (typ) for the MIN input, centered around the internal comm on voltage (0.45 x

AVDD). Usually the input signal is AC c oupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4642

can accept input voltages from AVSS to AVDD.

4. Analog Outputs

The input data forma t for t he DAC is 2’s c ompl em ent. The output volt age is a positi ve full scale for 7FFFH(@16bit) and

a negative full scale for 8000H(@16bit). Stereo Line Output is centered at 0.45 x AVDD. The Headphone-Amp and

Speaker-Amp outputs are centered at HVDD/2.

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CONTROL SEQUENCE

 Clock Set up

When ADC or DAC is powered-up, the clocks m ust be suppli ed.

1. PLL Master Mode.

BICK pin

LRCK pin

MCKO bit

(Addr:01H, D1)

PMPLL bi t

(Addr:01H, D0)

40msec(max)

Output

(1)

(6)

Power Supply

PDN pin

PMVCM bit

(Addr:00H, D6)

(2) (3)

MCKI pin (5)

(4)

Input

M/S bit

(Addr:01H, D3)

MCKO pin Output

(8)

(7)

40msec(max)

Example:

Audio I/F Format: MSB justified (ADC & DAC)

BICK frequency at Master Mode: 64fs

Input Master Clock Select at PLL Mode: 11.2896MHz

MCKO: Enable

Sampling Frequency: 8kHz

(1) Power Supply & PDN pin = “L” Æ “H”

(

)

Addr:00H, Data:40H

(2)Addr:01H, Data:08H

Addr:04H, Data:4AH

Addr:05H, Data:00H

(

)

Addr:01H, Data:0BH

MCKO, BICK and LRCK output

Figure 47. Clock Set Up Sequence (1)

(1) After Power Up, PDN pin = “L” Æ “H”

“L” time of 150ns or more is needed to reset the AK4642.

(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.

(3) Power UpVCOM: PMVCM bit = “0” Æ “1”

VCOM should first be powere d-up before the other block operates.

(4) In case of using MCKO output: MC KO bit = “1”

In case of not using MCKO output: MCKO bit = “0”

(5) PLL lock t ime is 40ms(m ax) afte r P M PLL bit c hanges from “0” to “1” and MCKI is suppl ie d from an e xte rnal

source.

(6) The AK4642 start s to output the LRCK and B ICK clocks after the PLL becom es stable. Then normal operation

starts.

(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.

(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.

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2. PLL Slave Mode (LRCK or BICK pin)

PMPLL bit

(Ad dr:01 H , D0 )

Inte rnal Clock

(1)

Power Supply

PDN pin

PMVCM bit

(Ad dr:00 H , D6 )

(2) (3)

LRCK pin

BICK pin (4)

(5)

Input

4fs of

Example:

Audio I/F Format : MSB justified (ADC & DAC)

PLL Reference clock: BICK

BICK frequency: 64fs

Sampling Frequency: 8kHz

(1) Power Supply & PDN pin = “L” Æ “H”

(3) Addr:00H, Data:40H

(2) Addr :04H, Data: 32H

Addr:05H, Data:00H

(4) Addr:01H, Data:01H

Figure 48. Clock Set Up Sequence (2)

(1) After Power Up: PD N pin “ L” Æ “H”

“L” time of 150ns or more is needed to reset the AK4642.

(2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.

(3) Power Up VCOM: PMVCM bit = “0” Æ “1”

VCOM should first be powered up before the other block operat es.

(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is

supplied. PLL lock time is 160ms(max) when LRCK is a PLL reference clock. And PLL lock time is 2ms(max)

when BICK is a PLL reference clock.

(5) Nor mal op e ra tion stats aft er th at the PLL is locked.

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

- 72 -

3. PLL Slave Mode (MCKI pin)

BICK p in

LRCK pin

MCKO bit

(Addr:01H, D1)

PMPLL bit

(Addr:01H, D0)

(1)

Power Supply

PDN pin

PMVCM bit

(Addr:00H, D6)

(2) (3)

MCKI pin (5)

(4)

Input

MCKO pin Output

(6)

(7)

40msec(max)

(8)

Input

Example:

Audio I/F Format: MSB justified (ADC & DAC)

BICK frequency at Master Mode: 64fs

Input Master Clock Select at PLL Mode: 11.2896MHz

MCKO: Enable

Sampling Frequency: 8kHz

(1) Power Supply & PDN pin = “L” Æ “H”

(

)

Addr:00H, Data:40H

(2)Addr:04H, Data:4AH

Addr:05H, Data:00H

(

)

Addr:01H, Data:03H

MCKO output start

BICK and LRCK input start

Figure 49. Clock Set Up Sequence (3)

(1) After Power Up: PDN pin “L” Æ “H”

“L” time of 150ns or more is needed to reset the AK4642.

(2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.

(3) Power Up VCOM: PMVCM bit = “0” Æ “1”

VCOM should first be powere d up before the other block operates.

(4) Enable MCKO output: MCKO bit = “1”

(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.

PLL lock time is 40ms(max) .

(6) The normal clock is output from MCKO after PLL is locked.

(7) The invalid frequency is output from MCKO during this period.

(8) BICK and LRCK clocks should be synchronized with MCKO clock.

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

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4. EXT Slave Mode

(1)

Power Supply

PDN pin

PMVCM bit

(Addr:00H, D6)

(2) (3)

LRCK pin

BICK pin

(4)

Input

(4)

MCKI pin Input

Example:

Audio I/F Format: MSB justified (ADC and DAC)

Input MCKI frequency: 1024fs

Sampling Frequency: 8kHz

MCKO: Disable

(1) Power Supply & PDN pin = “L” Æ “H”

(3) Addr:00H, Data:40H

(2) Addr:04H, Data:02H

Addr:05H, Data:01H

MCKI, BICK and LRCK input

Figure 50. Clock Set Up Sequence (4)

(1) After Power Up: PDN pin “L” Æ “H”

“L” time of 150ns or more is needed to reset the AK4642.

(2) DIF1-0 and FS1-0 bits should be set during this period.

(3) Power Up VCOM: PMVCM bit = “0” Æ “1”

VCOM should first be powered up before the other block operates.

(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

- 74 -

 MIC Input Recording (Stereo)

FS3-0 bits

(Addr:05H, D5&D2-0)

MIC Control

(Add r:0 2H, D2-0 )

PMADL/R bit

(Addr:00H&10H, D0)

ADC Internal

State

1,111X,XXX

001 101

Power Down Initialize Normal State Power Down

1059 / fs

(1)

(2)

(7)

ALC State ALC EnableALC Disable ALC Disable

(5)

ALC Control 1

(Addr:06H) XXH 3CH

(3)

ALC Control 2

(Addr:08H) XXH E1H

(4)

ALC Control 3

(Addr:0BH) XXH 00H

(8)

(6)

ALC Control 4

(Addr:07H) XXH 21H 01H

(9)

Example:

PLL Master Mode

Audio I/F Format:MSB jus tif ie d (ADC & DAC)

Sampling Frequency:44.1kHz

Pre MIC AMP:+20dB

MIC Power On

ALC setting:Refer to Figrure 23

ALC bit=“1”

(2) Addr:02H, Data:05H

(3) Addr:06H, Data:3CH

(1) Addr:05H, Data:27H

(4) Addr:08H, Data:E1H

(5) Addr:0BH, Data:00H

(7) Addr:00H, Data:41H

Addr:10H, Data:01H

Recording

(8) Addr:00H, Data:40H

Addr:10H, Data:00H

(6) Addr:07H, Data:21H

(9) Addr:07H, Data:01H

Figure 51. MIC Input Recording Sequence

This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to

“Figure 24. Registers set-up sequence at ALC operation”

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bit). When the AK4642 is PLL m ode, MIC and ADC should be powered-up

in consideration of PLL lock time after a sampling frequency is changed.

(2) Set up MIC input (Addr: 02H)

(3) Set up Timer Select for ALC (Addr: 06H)

(4) Set up REF value for ALC (Addr: 08H)

(5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)

(6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)

(7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1”

The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz.

After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL

default value (+30dB).

The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog

input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be

shorter by using the following sequence:

At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to

power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling

capacitor at analog input pin and the internal input resistance 60k(typ).

(8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0”

When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is

disabled because the MIC&ADC block is powered-down. If the regi sters for the ALC operation are also changed

when the sam pling frequency i s changed, it should be done after the AK4642 goes to the m anual mode (ALC bit

= “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when

PMADL=PMADR bits = “0”, and then IVO L operation sta rts from the setting value when PMADC or PMADR

bit is changed to “1”.

(9) ALC Disable: ALC bit = “1” → “0”

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

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 Speaker-amp Output

FS3-0 bits

(Addr:05H, D5&D2-0)

DVL/R7 - 0 bit s

(Addr:0AH&0DH, D7-0)

PMDAC bit

(Addr: 00H, D2)

PMSPK bit

(Addr: 00H, D4)

1,111X,XXX

18H XXH

SPP pin Normal Output

SPPSN bit

(Addr: 02H, D7)

Hi-ZHi-Z

SPN pin No rmal Output Hi-ZHi-Z HVDD/2 HVDD/2

(1)

(9)

X0 (7)

ALC bit

(Addr: 07H, D5)

(10)

(11)

(14)

(12)

DACS bit

(Addr:02H, D3)

(13)

0100 (3)

SPKG1-0 bits

(Addr:03H, D4-3)

IVL/R7-0 bits

(Addr:09H&0CH, D7-0) E1H 91H

(8)

(2)

(6)

ALC Control 1

(Addr:06H) XXH 3CH

(4)

ALC Control 2

(Addr:08H) XXH C1H

(5)

ALC Control 3

(Addr:0BH) XXH 00H

PMBP bit

(Addr:00 H , D5)

Example:

PLL Master Mode

Audio I / F F o rmat: MSB justified (ADC & DAC)

Sampling Frequency: 44 .1kH z

Digital Volume: 0dB

ALC: Enable

(2) Addr:02H, Data:20H

(7) Addr:07H, Data:20H

(1) Addr:05H, Data:27H

(9) Addr:0AH & 0DH, Data:28H

(10) Addr:00H, Data:74H

(1 1) Addr:02H, Data:A0H

(12) Addr:02H, Data:20H

Playback

(13) Addr:02H, Data:00H

(14) Addr:00H, Data:40H

(3) Addr:03H, Data:08H

(8) Addr:09H & 0CH, Data:91H

(4) Addr:06H, Data:3CH

(5) Addr:08H, Data:E1H

(6) Addr:0BH, Data:00H

Figure 52. Speaker-Amp Output Sequence

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bits). When the AK4642 is PLL mode, DAC and Speaker-Amp should be

powered-up in consideration of PLL lock time after a sampling frequency is changed.

(2) Set up the path of “DAC Æ SPK-Amp”: DACS bit = “0” Æ “1”

(3) SPK-Amp gain setting: SPKG1-0 bits = “00” Æ “01”

(4) Set up Timer Select for ALC (Addr: 06H)

(5) Set up REF value for ALC (Addr: 08H)

(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)

(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)

When PMADL or PMADR bit is “1”, ALC for DAC path is disabled.

(8) Set up the input digital volume (Addr: 09H and 0CH)

When PMADL = PMADR bit s = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).

(9) Set up the output digital volume (Addr: 0AH and 0DH).

When DVOLC bit is “1” (de fault), DVL7-0 bits set the volum e of both channels. After DAC is powered-up, the

digital volume changes from default value (0dB) to the register setting value by the soft transition.

(10) Power Up of DAC, MIN-Amp and Speaker-A mp: PMDAC = PMBP = PMSPK bits = “0” → “1”

The DAC enters a n i niti al izat i on cyc l e t hat st arts when the PMDAC bit is changed from “0” to “1” at PMADL

and PMADR bi ts are “0”. The initiali zation cycle time is 1059/fs= 24ms@fs=44.1kHz. Duri ng the initiali zation

cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC

outpu t reflects the digital inp ut data afte r the initiali za tion cycle is complete. When PMADC or PMADR bit is

“1”, the DAC does not requi re an initi alization cyc le. When ALC bit is “1”, ALC is disable (ALC gain is set by

IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC

operation starts from the gain set by IVL/R7-0 bits.

(11) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”

(12) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”

(13) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” Æ “0”

(14) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “1” → “0”

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

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 Mono signal output from Speaker-Amp

DACS bit

(Addr:02H, D5)

PMSPK bit

(Addr:00H, D4)

BEEPS bit

(Addr:02H, D6)

SPP pi n Normal Output

SPPSN bi t

(Addr:02H, D7)

Hi-ZHi-Z

SPN pi n Normal Output Hi-ZHi-Z HVDD/2 HVDD/2

(2)

(1) (5)

(4)

PMBP bit

(Addr:00H, D5)

Cl ocks can b e stopp ed.

CLOCK

(3)

(6)

Example:

(2) Addr:02H, Data:60H

(1) Addr:00H, Data:70H

(3) Addr:02H, Data:E0H

Mono Signal Output

(4) Addr:02H, Data:60H

(5) Addr:00H, Data:40H

(6) Addr:02H, Data:00H

Figure 53. “BEPP-Amp Æ Speaker-Amp” Output Sequence

The clocks can be stopped when only M IN-Amp and Speaker-Am p are operating.

(1) Power Up MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “0” → “1”

(2) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “0”

Enable the path of “MIN Æ SPK-Amp”: BEEPS bit = “0” → “1”

(3) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”

(4) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”

(5) Power Down MIN-Amp and Speaker-Amp: PMBP = PM SPK bits = “1” → “0”

(6) Disable the path of “MIN Æ SPK-Amp”: BEEPS bit = “1” → “0”

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

- 77 -

 Headphone-am p Output

FS3-0 bits

(Addr:05H, D5&D2-0)

DVL/R7-0 bits

(Addr:0AH&0DH, D7-0)

PM HPL/R bits

(Addr:01H, D5-4)

HPM TN bit

(Addr:01H, D6)

HPL/R pins

1,111X,XXX

18H XXH

Normal Output

(1)

BST1-0 bits

(Addr:0EH, D3-2) 00 XX 00

(3)

(5)

(12)

PMDAC bit

(Addr:00H, D2) (6) (11)

(7)

(9)(8)

(10)

IVL/R7-0 bits

(Addr:09H&0CH, D7-0 ) E1H 91H

(4)

PMBP b it

(Addr:00H, D5)

DACH bit

(Addr:0FH, D0) (2) (13)

Exam ple :

PLL M aster M ode

Sam pling Frequency: 44.1kHz

D VOL C b it = “1 ”(de fa u lt)

Dig it a l Vo lu m e L ev e l: 0 d B

Bass Boost Level: M iddle

De -e m phases response: OF F

S o ft M u te T ime : 25 6 /fs

(1) Addr:05H , D ata:27H

(5 ) A d dr:0 A H& 0 D H, D a ta 2 8H

(6) Addr:00H , D ata 64H

Playback

(3 ) A d d r:0 EH, Da ta 1 4 H

(9) Addr:01H , D ata 39H

(10) Addr:01H , Data 09H

(7) Addr:01H , D ata 39H

(8) Addr:01H , D ata 79H

(11) Addr:00H , Data 40H

(1 2 ) A d d r:0 EH, Da ta 0 0 H

(4) Addr:09H&0CH, Data 91H

(2 ) A dd r:0F H, D a ta 09 H

(13) Addr:0F H , D ata 08H

Figure 54. Headphone-Amp Output Sequence

At first, clocks should be supplie d according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bits).

(2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1”

(3) Set up the low frequency boost level (BST1-0 bits)

(4) Set up the input digital volume (Addr: 09H and 0CH)

When PMADL = PMADR bit s = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).

(5) Set up the output digital volume (Addr: 0AH and 0DH)

When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,

the digital volume changes from default value (0dB) to the register setting value by the soft transition.

(6) Power up DAC and MIN-Amp: PMDAC = PMBP bits = “0” → “1”

The DAC enters an initializat ion cycle t hat starts when the PMDAC bit is cha nged from “0” to “1” at PMADL

and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the

initiali zation c ycle, t he DAC input di gital da ta of both channels are internall y forced to a 2's complim ent , “0”.

The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or

PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable

(ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the

initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.

(7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1”

Output voltage of headphone-amp is still HVSS.

(8) Rise up the comm on voltage of headphone-amp: HPMTN bit = “0” → “1”

The rise tim e depends on HVDD and the capacit or value connected with the M UTET pin. When HVDD=3.3V

and the capacitor value is 1.0µF, the time consta n t is τr = 100ms(typ), 250ms(max).

(9) Fall down the common voltage of headphone-am p: HPMTN bit = “1” → “0”

The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V

and the capacitor value is 1.0µF, the tim e constant is τ f = 100ms(typ), 250ms(max).

If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to

GND, the pop noise occurs. It takes twice of τf that the common voltage goes to GND.

(10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0”

(11) Power down DAC and MIN-Amp: PMDAC = PMBP bits = “1” → “0”

(12) Off the bass boost: BST1-0 bits = “00”

(13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0”

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

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 Stereo Line Output

FS3-0 bits

(Addr:05H, D5&D2-0)

DVL/R7-0 bits

(Addr:0AH&0DH, D7-0)

PMDAC bit

(Addr:00H, D2)

PMLO bit

(Addr:00H, D3)

1,111

X,XXX

18H XXH

LOUT pin

ROUT pin

(1)

(4)

(5)

(2)

DACL b it

(Addr:02H, D4)

(10)

Normal Outp u t

(7)

LOPS bit

(Addr:03H, D6)

(6)

>300 ms

(8)

(9)

>300 ms

(11)

IVL/R7-0 bits

(Addr:09H&0CH, D7-0) E1H 91H

(3)

PMBP bit

(Addr:00H, D5)

Example:

PLL, Master Mode

Audio I/F Format :MSB justified (ADC & DAC)

Sampling Frequency: 44.1kHz

Digital Volume: 0dB

MGAIN1=SPKG1=SPKG0=BEEPL bits = “0”

(1) Addr:05H, Data:27H

(2) Addr:02H, Data:10H

(4) Addr:0AH&0DH, Data:28H

(5) Addr:03H, Data:40H

(6) Addr :00H, Data:6CH

(7) Addr:03H, Data:00H

Playback

(8) Addr:03H, Data:40H

(9) Addr:00H, Data:40H

(10) Addr:02H, Data:00H

(1 1 ) Addr:03H, Data:00 H

(3) Addr: 09H&0CH, Data:91H

Figure 55. Stereo Lineout Sequence

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up the sampling frequency (FS3-0 bits). When the AK4642 is PLL mode, DAC and Stereo Line-Amp

should be powered-up in consideration of PLL lock time after the sampling frequency is changed.

(2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1”

(3) Set up the input digital volume (Addr: 09H and 0CH)

When PMADL = PMADR bit s = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).

(4) Set up the output digital volume (Addr: 0AH and 0DH)

When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,

the digital volume changes from default value (0dB) to the register setting value by the soft transition.

(5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1”

(6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “0” → “1”

The DAC enters an initiali zation cycle that starts when t he PMDAC bit i s changed from “0” to “1” at PM ADL

and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the

initiali zation c ycle, t he DAC input di gital da ta of both channels are internall y forced to a 2's complim ent , “0”.

The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or

PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable

(ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the

initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.

LOUT and ROUT pi ns rise up t o VC OM volta ge a ft er PMLO bit i s c hanged to “1” . Rise ti m e is 300ms(max)

at C=1µF.

(7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0”

LOPS bit should be se t to “0” aft er LOUT and ROUT pi ns rise up. Stereo Line-Am p goes to norma l operation

by setting LOP S b it to “0”.

(8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1”

(9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “1” → “0”

LOUT and ROUT pins fall down to AVSS. Fall time is 300ms(max) at C=1µF.

(10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0”

(11) Exit power-save mode of Stereo Line -Amp: LOPS bit = “1” Æ “0”

LOPS bit should be set to “0” after LOUT and ROUT pins fa ll down.

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

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 Stop of Clock

Master clock can be stopped when ADC and DAC are not used.

1. PLL Master Mode

Ex ternal MCKI

PMPLL bit

(Addr:01H, D0)

MCKO bit

(Addr:01H, D1)

Input (3)

(1)

(2)

"H" or "L"

Example:

Audio I/F Format: MSB justified (ADC & DAC)

BICK frequency at Master Mode: 64fs

Input Master Clock Select at PLL Mode: 11.2896MHz

Sampling Frequency: 8kHz

(3) S top an external MCKI

(1) (2) Addr:01H, Data:08H

Figure 56. Clock Stopping Sequence (1)

(1) Power down PLL: PMPLL bit = “1” → “0”

(2) Stop MCKO clock: MCKO bit = “1” → “0”

(3) Stop an external master clock.

2. PLL Slave Mode (LRCK or BICK pin)

Extern al BICK

PMPLL bit

(Addr:01H, D0)

Input

(1)

(2)

Extern al LRCK Input (2)

Example

Audio I/F Format : MSB justified (ADC & DAC)

PLL Reference clock: BICK

BICK frequency: 64fs

Sampling Frequency: 8kHz

(

)

Addr:01H, Data:00H

(

)

Stop the external clocks

Figure 57. Clock Stopping Sequence (2)

(1) Power down PLL: PMPLL bit = “1” → “0”

(2) Stop the external BICK and LRCK clocks

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

- 80 -

3. PLL Slave (MCKI pin)

Ex ternal MCKI

PMPLL bit

(Addr:01H, D0)

Input

(1)

(2)

MCKO bit

(Addr:01H, D1)

(1)

Example

Audio I/F Format: MSB justified (ADC & DAC)

PLL Reference clock: MCKI

BICK frequency: 64fs

Sampling Frequency: 8kHz

(

)

Addr:01H, Data:00H

(

)

Stop the external clocks

Figure 58. Clock Stopping Sequence (3)

(1) Power down PLL: PMPLL bit = “1” → “0”

Stop MCKO output: MCKO bit = “1” → “0”

(2) Stop the external master clock.

4. EXT Slave Mode

Ex ternal LRCK Input (1)

Ex ternal BICK Input (1)

Ex ternal MCKI Input (1)

Example

Audio I/F Format :MSB justified(ADC & DAC)

Input MCKI frequency:1024fs

Sampling Frequency:8kHz

(

)

Stop the external clocks

Figure 59. Clock Stopping Sequence (4)

(1) Stop the external MCKI, BICK and LRCK clocks.

 Power down

Power supply current can be shut down (typ. 10µA) by stopping clocks and setting PMVCM bit = “0” afte r all blocks

except for VCOM are powered-down. Power supply current can be also shut down (typ. 10µA) by stopping clocks and

setting PDN pin = “L”. When PDN pin = “L”, the registers are init ialized.

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

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PACKAGE

32pin QFN (Unit: mm)

4.75 ± 0.10

5.00 ± 0. 10

4.75 ± 0.10

0.50

0.23

24 17

0.01

0.08

C0.42

+0.07

-0.05

0.40 ± 0.10

0.20

+ 0.04

- 0.01

Exposed

Pad

3.5

5.00 ± 0.10

0.85 ± 0.05

0.10 MAB

3.5

Note) The exposed pad on the bottom surfa ce of the package must be open or connected to the grournd.

 Material & Lead finish

Package molding compound: Epoxy

Lead frame material: Cu

Lead frame surface treatment: Solder (Pb free) plate

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

- 82 -

MARKING

K4642

XXXX

XXXXX : Date code identifier (5 digits)

Revision History

Date (YY/MM/DD) Revision Reason Page Conte nts

05/09/15 00 First Edition

ASAHI KASEI [AK4642EN]

MS0420-E-00 2005/09

- 83 -

IMPORTANT NOTICE

• These products and their specifications ar e subject to change without notice. Before considering

any use or application, consult the Asahi Kasei Micros ystems Co., Ltd. (AKM) sales office or

authorized distributor conc erning their current status.

• AKM assumes no liability for infringe ment of any patent, intellectual property, or other right in the

application or use of any information contained her ein.

• Any export of these products, or devices or systems containing them, may require an export license

or other official approval under the law and regulations of the country of export pertaining to customs

and tariffs, currency exchange, or strategic ma terials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life

support, or other hazard related device or system, and AKM assumes no responsibility relating to any

such use, except with the express w ritten consent of the Representative Director of AKM. As used

here:

a. A hazard related device or system is one designed or intended for life support or maintenance of

safety or for applications in medicine, aerospace, nuclear energy, or other fields, in whic h its

failure to function or perform may reasonably be expected to result in loss of life or in significant

injury or damage to person or property.

b. A critical component is one whose failure to function or perform may reasonably be expected to

result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or

system containing it, and which must therefore meet very high s tandards of performance and

reliability.

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absence of such notification.