Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Features
■5 V op eration
■Per-ch ann el pr ogram mab le gai ns , equal izati on,
termination impedance, and hybrid balance
■Programmable µ-law, or A-law modes:
— Up to 256 time slots per frame
— Supports PCM data rates of 512 kbits/s to
16.384 Mbits/s
— Double-clock mode timing compatible with
ISDN standard interfaces
■Fully programmable time-slot assignment with bit
offset
■Analog and digital loopback test modes
■Serial microprocessor interface:
— Normal and byte-by-byte control modes
— Fast scan mode
■Six bidirectional control leads per channel, for
SLIC and line card function control
■Differential analog output:
— Mates directly to SLICs, eliminating external
components
■Sigma-delta converters with dither noise reduction
■Quad design to minimize package count on dense
line card applications
■Meets or exceeds ITU-T G.711—G.712 and rele-
vant
Telcordia Technologies
* requirements
*
Telcordia Technologies
is a trademark of Bell Communications
Research, Inc.
Description
The device consists of four independent channels of
codec and digital signal processing functions on one
chip. In addition to the classic A-to-D and D-to-A con-
version, each channel provides termination imped-
ance synthesis and a hybrid balance network.
The device is controlled by a serial microprocessor
interface, and a series of bidirectional I/O leads are
provided so that this control mechanism can be uti-
lized to operate the battery feed device, ringing volt-
age switches, etc. Common data and clock paths can
be shared over any number of devices. All the filter
coefficients, signal processing, SLIC, and test fea-
tures are accessible through this interface. This
serial interface can be operated at speeds up to
4.096 Mbits/s.
The choice of a PCM bus is also programmable, with
any channel capable of being assigned to any time
slot. The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.
The device is available in four packages.
■The T8536 64-pin TQFP features five data latches
per channel and has two PCM ports.
■The T8536 100-pin TQFP features six data latches
per channel and has two PCM ports.
■The T8536 68-pin PLCC features six data latches
per channel and has one PCM port.
■The T8535 44-pin PLCC has no data latches and
one PCM port.
The T8535 and the T8533 Quad Programmable Line
Card Signal Processor with Echo Cancellation are
pin compatible, as are the T8536 68-pin PLCC
device and the T8534 68-pin PLCC Quad Program-
mabl e Li ne C ar d Si gn al P roc e sso r w i th Ec h o Ca nc el -
lation.
2Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Table of Contents
Contents Page
Features ....................................................................................................................................................................1
Description.................................................................................................................................................................1
General Description...................................................................................................................................................5
Pin Information ..........................................................................................................................................................7
Functional Description.............................................................................................................................................15
Clocking Cons id erati ons ..................... ....... ...... ....... ...... ....... ...... ....... ...... ...... .................... ................... ....... ...... ....15
The Control Interface ............................................................................................................................................15
Modes ................................................................................................................................................................15
Protocol..............................................................................................................................................................16
Write Command .................................................................................................................................................18
Read Command.................................................................................................................................................20
Fast Scan Mod e...... ...... ...... ....... ...... .................... ...... ....... ...... ....... ...... ...... ....... ................. .. ....... ...... ....... ...... ....2 4
Write All Channels..............................................................................................................................................27
Reset Functionality ...............................................................................................................................................27
Memory Control Mapping...................................................................................................................................28
Standby Mode.......................................................................................................................................................28
Test Capabilities ...................................................................................................................................................28
SLIC Control Capabilities......................................................................................................................................28
Suggested Initialization Procedures......................................................................................................................29
Signal Processing .................................................................................................................................................29
Absolute Maximum Ratings.....................................................................................................................................30
Operating Ranges . ................... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ............. ....... ............. ...... ....30
Handling Precautions ......... ...... ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... . ..... ....... ...... ....... ...... ....3 0
Electrical Characteristics.........................................................................................................................................31
dc Characteristics .................................................................................................................................................31
Analog Interfa ce.. ....... ...... ...... ....... ...... ....... ...... ....... ................... ....... ...... ...... ....... ...... ............. ....... ...... ....... ...... ....32
Gain and Dynamic Range.....................................................................................................................................33
Noise Characteristics............................................................................................................................................35
Distortion and Group Delay...................................................................................................................................36
Crosstalk...............................................................................................................................................................37
Timing Characteristics.............................................................................................................................................38
Control Interface Timing........................................................................................................................................38
Serial Control Port Timing..................................................................................................................................38
Normal Mode......................................................................................................................................................39
Byte-by-Byte Mode.............................................................................................................................................39
PCM Interface Timing ...........................................................................................................................................40
Single-Clocking Mode ........................................................................................................................................40
Double-Cl oc king Mod e.. ................... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... .. ..... ...... ....... ..........42
Software Interfa ce .................... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ............. ....... ............. ...... ....44
Applications.............................................................................................................................................................48
Outline Diagrams.....................................................................................................................................................49
100-Pin TQFP.......................................................................................................................................................49
68-Pin PLCC.........................................................................................................................................................50
64-Pin TQFP.........................................................................................................................................................51
44-Pin PLCC.........................................................................................................................................................52
Ordering Information................................................................................................................................................53
Lucent Technologies Inc. 3
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Table of Contents (continued)
Figures Page
Figure 1. Functional Block Diagram, Each Section...................................................................................................5
Figure 2. 44-Pin PLCC Pin Diagram .........................................................................................................................7
Figure 3. 68-Pin PLCC Pin Diagram .........................................................................................................................9
Figure 4. 100-Pin TQFP Pin Diagram .....................................................................................................................11
Figure 5. 64-Pin TQFP Pin Diagram .......................................................................................................................13
Figure 6. Command Frame Format, Master to Slave, Read or Write Commands..................................................17
Figure 7. Command Frame Format, Slave to Master, Read Commands................................................................17
Figure 8. Write Operation, Normal Mode (Continuous DCLK)................................................................................18
Figure 9. Write Operation, Normal Mode (Gapped DCLK) .....................................................................................18
Figure 10. Write Operation, Byte-by-Byte Mode (Continuous DCLK).....................................................................19
Figure 11. Write Operation, Byte-by-Byte Mode (Gapped DCLK) ..........................................................................19
Figure 12. Read Operation, Normal Mode (Continuous DCLK)..............................................................................20
Figure 13. Read Operation, Normal Mode (Gapped Clock)....................................................................................21
Figure 14. Read Operation, Byte-by-Byte Mode (Continuous DCLK).....................................................................22
Figure 15. Read Operation, Byte-by-Byte Mode (Gapped DCLK) ..........................................................................23
Figure 16. Fast Scan, Normal Mode (Continuous DCLK).......................................................................................24
Figure 17. Fast Scan, Normal Mode (Gapped DCLK) ............................................................................................25
Figure 18. Fast Scan, Byte-by-Byte Mode (Continuous DCLK)..............................................................................26
Figure 19. Fast Scan, Byte-by-Byte Mode (Gapped DCLK) ...................................................................................26
Figure 20. Hardware Reset Procedure ...................................................................................................................27
Figure 21. Internal Signal Processing .....................................................................................................................29
Figure 22. Serial Interface Timing, Normal Mode (One Byte Transfer Shown).......................................................39
Figure 23. Byte-by-Byte Mode Timing.....................................................................................................................39
Figure 24. Single-Clocking Mode (TXBITOFF = 0, RXBITOFF = 0, PCMCTRL2 = 0x00)......................................41
Figure 25. Single-Clocking Mode (TXBITOFF = 1, RXBITOFF = 2, PCMCTRL2 = 0x01)......................................41
Figure 26. Double-Clocking Mode (Bit Offset = 0, PCMCTRL2 = 0x00).................................................................43
Figure 27. POTS Interface ......................................................................................................................................48
4Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Table of Contents (continued)
Tables Page
Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions...........................................................................7
Table 2. Pin Assignments, 44-Pin PLCC, Common Functions................................................................................. 8
Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions...........................................................................9
Table 4. Pin Assignments, 68-Pin PLCC, Common Functions............................................................................... 10
Table 5. Pin Assignments, 100-Pin TQFP, Per-Channel Functions.......................................................................11
Table 6. Pin Assignments, 100-Pin TQFP, Common Functions.............................................................................12
Table 7. Pin Assignments, 64-Pin TQFP, Per-Channel Functions.........................................................................13
Table 8. Pin Assignments, 64-Pin TQFP, Common Functions............................................................................... 14
Table 9. Bit Assignments for Fast Scan Mode ....................................................................................................... 24
Table 10. dc Characteristics................................................................................................................................... 31
Table 11. Analog Interface .....................................................................................................................................32
Table 12. Power Dissipation................................................................................................................................... 32
Table 13. Gain and Dynamic Range ...................................................................................................................... 33
Table 14. Per-Channel Noise Characteristics ........................................................................................................ 35
Table 15. Distortion and Group Delay....................................................................................................................36
Table 16. Crosstalk.................................................................................................................................................37
Table 17. Serial Control Port Timing ......................................................................................................................38
Table 18. PCM Interface Timing: Single-Clocking Mode........................................................................................ 40
Table 19. PCM Interface Timing: Double-Clocking Mode ...................................................................................... 42
Table 20. Memory Mapping....................................................................................................................................44
Table 21. Control Bit Definition............................................................................................................................... 45
Prelim inary Data Sheet
February 2001
Lucent Technologies Inc. 5
T8535/T8536 Quad Programmable Codec
General Description
Refer to Figure 1 for the following discussion.
5-8125aF
* Second PCM port not available in all package types.
Figure 1. Functional Block Diagram, Each Section
RST
SLIC
TO/FROM
ANALOG
GAIN A/D
CONVERTER
ANALOG
BUFFER
D/A
CONVERTER
DIGITAL
LOOPBACK 3
ANALOG
LOOPBACK 1
DIGITAL
LOOPBACK 2
TERMINATION
IMPEDANCE HYBRID
BALANCE
NETWORK
DIGITAL GAIN
(GAIN TRANSFER)
µ-LAW
PER
CHANNEL COMMON
ANALOG
LOOPBACK 2
DIGITAL
LOOPBACK 1
PCM BUS
INTERFACE
DX0
DR1*
TO/FROM
PCM BUS
POWER AND
GROUND
18
FS
BCLK
SLIC
CONTROL LATCHES MICROPROCESSOR CONTROL
CONTROL AND DATA SIGNALS
4
SERIAL
CONTROL
INTERFACE
PER
CHANNEL COMMON
0 TO 6
FREQUENCY
SYNTHESIZER 0 TO 3 FILTER
OR
CONVERSION
A-LAW
DIGITAL GAIN
(GAIN TRANSFER)
DX1*
TSX0*
TSX1*
DR0
VFROPn
VFRONn
VFXIn
This device perfor ms virtually all the signal proc essing
functions associated with a central office line termina-
tion. Functionality includes line termination impedance
synthesis, fixed hybrid balance impedance synthesis,
and level conversion both in the analog sense to
accommodate various subscriber line interface circuits
(SLICs) and in the digital sense for adjustment of the
levels on the PCM bus. In general, the termination
impedance synthesis generates the equivalent of a cir-
cuit with the parallel combination of a capacitor and a
resistor in series with a resistor, or the parallel combi-
nation of a resistor and the series combination of a
resistor and capacitor. These general forms of imped-
ance characteristic will satisfy most of the requirements
specified throughout the world. Programmable selec-
tion of either µ-law or A-law encoding further aids
worldwide deployment. All coefficients used in the filter-
ing algorithms can be computed off-line in advance and
downloaded to the device at the time of powerup. All
signal processing is contained within the device, and
there are only three interfaces of consequence to the
system designer: the SLIC interface, the PCM inter-
face, and the control interface.
The SLIC interface is designed to be flexible and con-
venient to use with a variety of SLIC circuits. With an
appropriate choice of SLIC, no external components
are required in the interface, with the exception of a dc
blocking capacitor in the transmit direction. In some
cases, dc blocking capacitors in the receive direction
may be necessary as well, since the device operates
from a single low-voltage supply.
66 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
General Description (continued)
The PCM bus interface is flexible in that it allows, inde-
pendently, the transmit and receive data for any chan-
nel to be placed in any time slot. The bus can be
operated at a maximum 16.384 Mbits/s rate to accom-
modate a maximum 256 time slots. Separate pins
are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure for all four channels. The interface will count
8 bits per time slot and insert or read the data for each
channel as programmed. Lower speeds of the PCM
bus are allowed. The PCM clock must be synchronous
with the frame strobe signal.
The microprocessor control interface is a serial inter-
face that uses the classical chip select type of opera-
tion. The interface controls the device by writing or
reading various internal addresses. The command set
consists of simple read and write operations, with the
address determining the effect. All the memory loca-
tions, including the per-chip functions, are organized by
channel.
There are several test modes included to facilitate con-
firmation of correct operation. In the signal path, two
analog and three digital loopback tests are available,
while in the microprocessor interface, there is a write/
read test mode that tests the operation of the memory.
Use of external test access switches allows a complete
test of the signal path through the line card so that cor-
rect operation of various operational modes can be ver-
ified.
Lucent Technologies Inc. 7
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Pin Information
5-7187.b(F)
Figure 2. 44-Pin PLCC Pin Diagram
Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions
Ckt Name Type Name/Description
abcd
15 22 23 30 AGND GND Analog Ground. A common AGND, DGND, SGND plane is
highly recommended.
14 21 24 31 VDD PWR Analog Power Supply.
13 20 25 32 VFXIIVoice Frequency Transmit Input.
12 19 26 33 VFROP O Voice Frequency Receive Output, Positive Polarity. This pin
can drive 2000 Ω (or greater) loads.
11 18 27 34 VFRON O Voice Frequency Receive Output, Negative Polarity. This pin
can drive 2000 Ω (or greater) loads.
54321444342
NC
DCLK
DR
RST
FILTV
DO
64140
VDD
DI
INTS
DGND
2625242322212019 27
VDDb
VFXIc
VFRONb
VFROPb
VFRONc
VDD
AGNDc
2818
VFXIb
VDDc
VFROPc
AGNDb
15
14
13
12
11
10
9
VDDa
PVCOIN
PVCO
SGND
DGND
VDD
VFROPa
16
17
8
7
VFXIa
PLLT
AGNDa
VFRONa
32
34
35
36
38
33
VFXId
DX
DGND
FS
AGNDd
DGND
VFRONd
31
30
29
39
VDD
VFROPd
BCLK
VDDd
37
CS
8Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Pin Information (continued)
Table 2. Pin Assignments, 44-Pin PLCC, Common Functions
Pin Name Type Name/Description
1DOOSerial Data Output. This is a 3-state output.
2DIISerial Data Input.
3DCLKISerial Data Clock Input.
4CSIChip Select Input. This lead determines the interval that the serial interface is
active.
5INTSISerial Interface Select. Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.
6FILTVPWRFrequency Synthesizer Power (5 V). This pin must be tied to VDD.
7PVCOIN—Internal Test Point. Do not connect to this lead.
8PVCO—Internal Test Point. Do not connect to this lead.
9PLLT—Synthesizer Test Point. Do not connect to this lead.
10 SGND GND Synthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.
16, 29,
38, 44 DGND GND Digital Ground. Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is hig hly rec om men ded .
17, 28,
35, 42 VDD PWR Digital Power Supply (5 V).
36 FS I PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source
as BCLK.
37 BCLK I PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock
rates.
39 DX O PCM Transmit Data Output. This is a 3-state output.
40 DR I PCM Receive Data Input.
41 RST I Power-On Reset. A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1 µF capacitor for a power-on reset function, or it may be
driven by external logic. This lead has an internal pull-up.
43 NC — No Connect. This pin may be used as a tie point.
Lucent Technologies Inc. 9
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Pin Information (continued)
5-8126 (F)
Figure 3. 68-Pin PLCC Pin Diagram
Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions
Ckt Name Type Name/Description
abcd
21 34 35 48 AGND GND Analog Ground. A common AGND, DGND, SGND plane is
highly recommended.
20 33 36 49 VDD PWR Analog Power Supply.
19 32 37 50 VFXIIVoice Frequency Transmit Input.
18 31 38 51 VFROP O Voice Frequency Receive Output, Positive Polarity. This pin
can drive 2000 Ω (or greater) loads.
17 30 39 52 VFRON O Voice Frequency Receive Output, Negative Polarity. This pin
can drive 2000 Ω (or greater) loads.
16 29 41 53 SLIC0 I/O SLIC Control 0.
15 27 42 54 SLIC1 I/O SLIC Control 1.
9 264361SLIC2I/OSLIC Control 2.
8 254463SLIC3I/OSLIC Control 3.
7 234664SLIC4I/OSLIC Control 4.
6 224762SLIC5I/OSLIC Control 5.
6 4 3 2 1 68676665645
NC
DCLK
SLIC2d
SLIC3d
RST
INTS
SLIC4a
SLIC2a
DO
789636261
VDD
DI
SLIC5d
SLIC4d
CS
SLIC5a
SLIC3a
DGND
40383736353433323130 39
VDDb
VFXIc
SLIC1b
SLIC0b
VFROPb
VFRONc
SLIC0c
SLIC2c
AGNDc
41 42 43292827
VFXIb
VDDc
VDD
VFRONb
VFROPc
VDD
SLIC1c
AGNDb
23
21
20
19
18
17
16
15
14
13
22
SLIC0a
VDDa
FILTV
PVCO
SGND
SLIC5b
DGND
SLIC2b
VFROPa
24
25
26
12
11
10
SLIC1a
VFXIa
PVCOIN
PLLT
AGNDa
SLIC4b
SLIC3b
VFRONa
47
49
50
51
52
53
54
55
56
57
48
SLIC1d
VFXId
DR
DGND
FS
AGNDd
SLIC4c
SLIC3c
VFRONd
46
45
44
58
59
60
VDD
VFROPd
DX
BCLK
VDDd
SLIC5c
DGND
SLIC0d
10 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Pin Information (continued)
Table 4. Pin Assignments, 68-Pin PLCC, Common Functions
Pin Name Type Name/Description
1DOOSerial Data Output. This is a 3-state output.
2DIISerial Data Input.
3DCLKISerial Data Clock Input.
4CSIChip Select Input. This lead determines the interval that the serial interface is
active.
5INTSISerial Interface Select. Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.
10 FILTV PWR Frequency Synthesizer Power (5 V). This pin must be tied to VDD.
11 PVCOIN —Internal Test Point. Do not connect to this lead.
12 PVCO — Internal Test Point. Do not connect to this lead.
13 PLLT — Synthesizer Test Point. Do not connect to this lead.
14 SGND GND Synthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.
24, 45,
58, 68 DGND GND Digital Ground. Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is hig hly rec om men ded .
28, 40,
55, 66 VDD PWR Digital Power Supply (5 V).
56 FS I PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source
as BCLK.
57 BCLK I PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock
rates.
59 DX O PCM Transmit Data Output. This is a 3-state output.
60 DR I PCM Receive Data Input.
65 RST I Power-On Reset. A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1 µF capacitor for a power-on reset function, or it may be
driven by external logic. This lead has an internal pull-up.
67 NC — No Connect. Pin may be used as a tie point.
Lucent Technologies Inc. 11
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Pin Information (continued)
5-8885 (F)
Figure 4. 100-Pin TQFP Pin Diagram
Table 5. Pin Assignments, 100-Pin TQFP, Per-Channel Functions
Ckt Name Type Name/Description
abcd
17 31 34 54 AGND GND Analog Ground. A common AGND, DGND, SGND plane is
highly recommended.
16 30 36 55 VDD PWR Analog Power Supply.
14 29 41 56 VFXIIVoice Frequency Transmit Input.
13 28 42 57 VFROP O Voice Frequency Receive Output, Positive Polarity. This pin
can drive 2000 Ω (or greater) loads.
11 27 43 58 VFRON O Voice Frequency Receive Output, Negative Polarity. This pin
can drive 2000 Ω (or greater) loads.
6 264665SLIC0I/OSLIC Control 0.
5 244766SLIC1I/OSLIC Control 1.
100 23 48 78 SLIC2 I/O SLIC Control 2.
99 21 49 80 SLIC3 I/O SLIC Control 3.
98 19 52 81 SLIC4 I/O SLIC Control 4.
97 18 53 79 SLIC5 I/O SLIC Control 5.
FILTV DX1
DCLK
CS
INTS
NC
NC
NC
NC
NC
SLIC5a
SLIC4a
SLIC3a
SLIC2a
NC
NC
SGND
SLIC1a
SLIC0a
NC
NC
NC
NC
VFRONa
NC
VFROPa
VFXIa
NC
VDDa
AGNDa
SLIC5b
SLIC4b
DGND
SLIC3b
NC
SLIC2b
SLIC1b
VDD
SLIC0b
VFRONb
VFXIb
VDDb
AGNDb
NC
NC
AGNDc
NC
VDDc
NC
NC
NC
NC
VFXIc
VFROPc
VFRONc
NC
VDD
SLIC0c
SLIC1c
SLIC2c
SLIC3c
TSX0
DR0
DX0
DGND
NC
BCLK
FS
VDD
SLIC1d
SLIC0d
NC
NC
NC
NC
NC
NC
VFRONd
VFROPd
VFXId
VDDd
AGNDd
SLIC5c
DGND
DI
DO
NC
DGND
VDD
RST
SLIC4d
SLIC3d
SLIC5d
SLIC2d
TSX1
DR1
NC
88
89
90
91
92
93
95
96
97
98
99
100
87
86
85
84
83
82
81
80
79
78
77
76
94
38
37
36
35
34
33
31
30
29
28
27
26
39
40
41
42
43
44
45
46
47
48
49
50
32
13
12
11
10
9
8
6
5
4
3
2
1
14
15
16
17
18
19
20
21
22
23
24
25
7
63
64
65
66
67
68
70
71
72
73
74
75
62
61
60
59
58
57
56
55
54
53
52
51
69
SLIC4c
NC
VFROPb
12 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Pin Information (continued)
Table 6. Pin Assignments, 100-Pin TQFP, Common Functions
Pin Name Type Name/Description
1FILTVPWRFrequency Synthesizer Power (5 V). This pin must be tied to VDD.
2, 3, 7—10,
12, 15, 22, 32,
33, 35,
37—40,
44, 50,
59—64, 70,
85, 91—96
NC — No Connect. Pin may be used as a tie point.
4SGNDGNDSynthesizer Ground. Connect to digital ground. A common AGND, DGND,
SGND plane is highly recommended.
20, 51, 71, 84 DGND GND Digital Ground. Logic ground and return for logic power supply. A common
AGND, DGND, SGND plane is highly recommended.
25, 45, 67, 83 VDD PWR Digital Power Supply (5 V).
68 FS I PCM Frame Strobe Input. This 8 kHz clock must be derived from the same
source as BCLK.
69 BCLK I PCM Bit Clock Input. This lead is used to develop internal clocks for certain
clock rates.
72 DX0 O PCM Transmit Data Output 0. This is a 3-state output.
73 DR0 I PCM Rece ive Data Input 0.
74 TSX0 OBackplane Line Driver Enable 0 (Active-Low). Normally, these open-drain
outputs are floating in a high-impedance state. When a time slot is active on
DX0, this output pulls low to enable a backplane line driver.
75 DX1 O PCM Transmit Data Output 1. This is a 3-state output.
76 DR1 I PCM Rece ive Data Input 1.
77 TSX1 OBackplane Line Driver Enable 1 (Active-Low). Normally, these open-drain
outputs are floating in a high-impedance state. When a time slot is active on
DX1, this output pulls low to enable a backplane line driver.
82 RST I Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1 µF capacitor for a power-on reset function, or it
may be driven by external logic. This lead has an internal pull-up.
86 DO O Serial Data Output. This is a 3-state output.
87 DI I Serial Data Input.
88 DCLK I Serial Data Clock Input.
89 CS I Chip Se lect Inp ut. This lead de termi nes t he int erval that the serial inte rface is
active.
90 INTS I Serial Interface Select. Leaving this lead open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte mode.
This lead has an internal pull-up.
Lucent Technologies Inc. 13
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Pin Information (continued)
5-7187dF
Figure 5. 64-Pin TQFP Pin Diagram
Table 7. Pin Assignments, 64-Pin TQFP, Per-Channel Functions
Ckt Name Type Name/Description
abcd
9 212234AGNDGNDAnalog Ground. A common AGND, DGND, SGND plane
is highly recommended.
8 202335 V
DD PWR Analog Power Sup ply.
7 192436 VF
XIIVoice Frequency Transmit Input.
6 182537VF
ROP O Voice Frequency Receive Output, Positive Polarity.
This pin can drive 2000 Ω (or greater) loads.
5 172638VF
RON O Voice Frequency Receive Output, Negative Polarity.
This pin can drive 2000 Ω (or greater) loads.
4 162839 SLIC0I/OSLIC Control 0.
3 142940 SLIC1I/OSLIC Control 1.
64 13 30 51 SLIC2 I/O SLIC Control 2.
63 12 31 52 SLIC3 I/O SLIC Control 3.
62 10 33 53 SLIC4 I/O SLIC Control 4.
60 59 58 57 56 55 54 535261
DCLK
DR1
SLIC3d
RST
INTS
SLIC4a
SLIC2a
DO
626364 51 5049
VDD
DI
SLIC2d
SLIC4d
CS
SLIC3a
DGND
30282726252423222120 29
VDDb
VFXIc
VDD
SLIC0b
VFROPb
VFRONc
SLIC0c
SLIC1c
AGNDc
31 32191817
VFXIb
VDDc
SLIC1b
VFRONb
VFROPc
VDD
AGNDb
13
12
11
10
9
8
7
6
5
4
SLIC0a
VDDa
FILTV
SGND
DGND
SLIC2b
VFROPa
14
15
16
3
2
1
SLIC1a
VFXIa
AGNDa
SLIC4b
SLIC3b
VFRONa
36
38
39
40
41
42
43
44
45
46
37
SLIC1d
VFXId
DX0
DGND
FS
AGNDd
DGND
SLIC2c
VFRONd
35
34
33
47
48
VDD
VFROPd
BCLK
VDDd
SLIC4c
SLIC3c
SLIC0d
DX1
TSX0
DR0
TSX1
14 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Pin Information (continued)
Table 8. Pin Assignments, 64-Pin TQFP, Common Functions
Pin Name Type Name/Description
1FILTVPWRFrequency Synthesizer Power (5 V). This pin must be tied to VDD.
2SGNDGNDSynthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.
11, 32,
44, 56 DGND GND Digital Ground. Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is hig hly rec om men ded .
15, 27,
41, 55 VDD PWR Digital Power Supply (5 V).
42 FS I PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source
as BCLK.
43 BCLK I PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock
rates.
45 DX0 O PCM Transmit Data Output 0. This is a 3-state output.
46 DR0 I PCM Receive Data Input 0.
47 TSX0 OBackplane Line Driver Enable 0 (Active-Low). Normally, these open-drain outputs
are floating in a high-impedance state. When a time slot is active on DX0, this output
pulls low to enable a backplane line driver.
48 DX1 O PCM Transmit Data Output 1. This a 3-state output.
49 DR1 I PCM Receive Data Input 1.
50 TSX1 OBackplane Line Driver Enable 1 (Active-Low). Normally, these open-drain outputs
are floating in a high-impedance state. When a time slot is active on DX1, this output
pulls low to enable a backplane line driver.
54 RST I Power-On Reset. A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1 µF capacitor for a power-on reset function, or it may be
driven by external logic. This lead has an internal pull-up.
57 DO O Serial Data Output. This is a 3-state output.
58 DI I Serial Data Input.
59 DCLK I Serial Data Clock Input.
60 CS I Chip Select Input. This lead determines the interval that the serial interface is
active.
61 INTS I Serial Interface Select. Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.
Lucent Technologies Inc. 15
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description
Clocking Considerations
The PCM bus uses BCLK as the bit clock and the one-
going edge of FS to determine the location of the
beginning of a frame. These two clocks must be
derived from the same source. Internally, the device
develops all the internal clocks with a phase-locked
loop that uses BCLK as the timing source. BCLK and
FS must be continuously present and without gaps in
order for the device to operate correctly.
DCLK is used to clock the internal serial interface and
may be asynchronous to the other clocks. There is no
need to derive this clock from the same source as the
other clocks. The serial bus may be operated at any
speed up to 4.096 Mbits/s. DCLK can be gapped, how-
ever , additional clock cycles are required in and around
the command frame to process data, and during and
after a hardware or a software reset to ensure com-
plete clearing of internal logic. There is no limit on the
number of devices on the same serial bus.
The Control Interface
The device is controlled via a series of memory loca-
tions accessed by a serial data connection to the exter-
nal master controller. This interface operates using the
chip select lead to enable transmission of information.
All chip functions are enabled or disabled by setting or
clearing bits in the control memory. Filter coefficients
and gain adjustments are also stored in this memory.
The codec has both a serial input lead and a serial out-
put lead. These may be used individually for a 4-wire
serial interface, or tied together for a 2-wire interface.
The line driver circuitry is capable of driving relatively
high currents so that in the event that the line is long
enough to show significant transmission line effects, it
can be terminated in the characteristic impedance at
each end with resistors to VCC and ground.
All data transfers on the serial bus are byte oriented
with the least significant bit (shown in this data sheet as
bit 0) transmitted first, followed by the more significant
bits. For data fields, the least significant byte of the first
data byte is transmitted first, followed by the more sig-
nificant bytes, each byte transmitted LSB first. This for-
mat is compatible with the serial port on most
microcontrollers.
Modes
There are two different modes of operation for the
serial interface, the normal mode and the byte-by-byte
mode. These two modes differ in the manner in which
CS is used to control the transfer. Note that the CS
lead is used to control the transfer of serial data from
master controller to slave codec and in the reverse
direction.
In normal mode, (INTS pin open) the CS lead must go
low for the duration of the transfer . The only error check
performed by the codec is to verify that CS is low for an
integral number of bytes. Detection of an active (active-
low) chip select for other than an integral multiple of
8 bits results in the operation being terminated. The
next active excursion of chip select will be interpreted
as a new command; hence, the serial I/O interface can
always be initialized by asserting CS for a number of
clock periods th at is not an integral multiple of 8. CS is
captured using DCLK, so DCLK must be transitioned to
perform this initialization. Undefined command codes
are reserved for future use and may cause unwanted
oper ation of the device.
The byte-by-byte mode (INTS pin tied to ground) uses
CS to control each byte of the transfer. In this mode,
CS goes low for exactly 8 bits at a time, corresponding
to a 1-byte transfer either to or from the codec chip.
Repeated transitions of CS are used to control subse-
quent bytes of data to/from the codec. For a write com-
mand in this mode, CS must go low for each byte of the
transfer until the transfer is complete. For a read com-
mand, CS will go low for each of the 3 bytes of the read
command transferred to the device, then low again for
each byte to be read. Notice that the total number of
bytes transferred (and excursions on CS) is N + 3,
where N is the number of bytes to be read in the com-
mand. This mode of operation is useful in cases where
the master is a microprocessor with a built-in UART
that transfers 1 byte at a time. Error detection is limited
to detection of an active CS for other than an integral
multiple of 8 bits. Recovery is the same as normal
mode. Note that the clock phase is shifted in this mode.
Flow control can be accomplished by suspending the
transitions on DCLK by holding either state. During the
data transfer, CS must remain low while clock transi-
tions are suspended with DCLK in either state.
1616 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Protocol
The format of the command protocol is shown in Fig-
ures 6 and 7.
The control interface operates with one external master
controller and multiple slave codec devices. Each
transfer is initiated by the master, and the slave
responds for either read operations or the fast scan
mode. The slave does not check the bus for activity
prior to transmitting; it only checks for an active CS.
The master should all ow for a wait between the end of
a read command until CS becomes active for the read
data. The master must refrain from sending additional
commands to the slave chip until the response is
received. On a 4-wire bus, commands to other devices
may be initiated before the response is received, but
care in generating the CS function is needed to ensure
that the multiple responses do not interfere. It should
be noted that multiple memory locations can be
accessed in the same command by setting the data
field length field to the desired number of bytes to be
transferred. If flow control is desired, it must be per-
formed by using separate commands, each transfer-
ring smaller blocks of information, or by controlling the
serial clock (gapping the serial clock), or with CS in the
case of byte-by-byte mode.
There is no response from the slave to the master for a
write operation. The response to a read operation sim-
ply includes the data to be read in the data field. This
data is sent least significant bit first, with the bytes sent
in ascending sequence. Commands from the master
controller include data for write operations, but not for
read operations. Since the coefficients and gains are
stored in volatile memory, all the coefficients and gains
must be loaded after powerup. There is, however, no
need to reload them when switching from active to
standby modes, or vice versa. Great care should be
exercised in loading memory when the codec channel
is not in standby mode. Sudden changes in the termi-
nation or balance impedances can result in undesirable
system operation.
All data is transmitted in a byte-oriented fashion with
the least significant bit of each byte transferred first.
Multibyte fields are transferred least significant byte
first in both directions. The data field will contain the
first addressed data location first, with subsequent data
locations transmitted in ascending order.
Lucent Technologies Inc. 17
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Contro l I nterface (continued)
Protocol (continued)
* Location of memory bank selection. All user controls are in memory bank 0; other memory banks contain internal state information for the
device.
Note: Data field length is in bytes for all operations. All data is transmitted in bytes with the LSB for each byte transmitted first. For 16-bit mem-
ory operations, the least significant byte of the first memory location is transmitted first, followed by the most significant byte; each byte is
transmitted LSB first. Additional memory locations are loaded in ascending sequence.
Figure 6. Command Frame Format, Master to Slave, Read or Write Commands
Note: All data is transmitted in bytes with the LSB for each byte transmitted first. For memory operations, the least significant byte of the first
memory location is transmitted first, followed by the most significant byte, each byte transmitted LSB first. Additional memory locations
are loaded in ascending sequence.
Figure 7. Command Frame Format, Slave to Master, Read Commands
LSB MSB LSB MSB LSB MSB LSB
COMMAND (8 bits) START ADDRESS (8 bits) DATA FIELD LENGTH (8 bits) DATA FIELD (VARIABLE LENGTH) WRITE OPERATIONS ONLY
TIME
76543210
MSB LSB
START ADDRESS:
76543210
MSB LSB
DATA FIELD LENGTH:
76543210
MSB LSB
COMMAND: 0* 0* CKT
SELECT 00COMMAND
CKT SELECT: CKT a:
CKT b:
CKT c:
CKT d:
00
01
10
11
COMMA NDS: FAST SCAN MODE:
WRIT E MEMORY:
WRITE ALL CHANNELS:
READ MEM O RY:
10
01
11
00
LSB DATA FIELD (VARIABLE LENGTH) READ OPERATIONS ONLY
18 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Write Command
A write command is used to write to the memory addresses. Figures 8—11 illustrate normal or byte-by-byte opera-
tion with continuous or gapped DCLKs. For gapped DCLK operation, transitions, not frequency, are critical (as long
as transitions occur no faster than 122 ns apart).
0078
* Two or more full DCLK cycles are required before the start of a new command frame.
Note: Data field length of 1 shown.
Figure 8. Write Operation, Normal Mode (Continuous DCLK)
0076
Notes:
Data field length of 1 shown.
CK1 through CK4 are additional DCLK pulses required to properly process the data.
CK3 and CK4 are not necessary if another command frame follows this sequence.
Figure 9. Write Operation, Normal Mode (Gapped DCLK)
COMMAND FRAME
01 7
01 7
CS
DCLK
DI
COMMAND START ADDRESS DATA
01 7 01 7
01 7 01 7
LENGTH
01 7
01 7
*
COMMAND FRAME
01 7
01 7
CS
DCLK
DI
COMMAND START ADDRESS DATA
01 7 01 7
01 7 01 7
CK1
CK2
CK3
CK4
LENGTH
01 7
01 7
Lucent Technologies Inc. 19
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Contro l I nterface (continued)
Write Command (continued)
0074
* Two or more full DCLK cycles are required before the start of a new command frame.
Note: Data field length of 1 shown.
Figure 10. Write Operation, Byte-by-Byte Mode (Continuous DCLK)
0072
Notes:
Data field length of 1 shown.
CK1 through CK4 are additional DCLK pulses required to properly process the data.
CK3 and CK4 are not necessary if another command frame follows this sequence.
Figure 11. Write Operation, Byte-by-Byte Mode (Gapped DCLK)
01 7
01 7
CS
DCLK
DI
COMMAND START ADDRESS LENGTH DATA
01 7 01 7 01 7
01 7 01 7 01 7
COMMAND FRAME
ONE OR MORE FULL DCLK CYCLES REQUIRED HERE
*
CK1
CK2
01 7
01 7
CS
DCLK
DI
COMMAND START ADDRESS LENGTH DATA
COMMAND FRAME
01 7
01 7 01 7 01 7
CK3
CK4
01 7 01 7
20 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Read Command
The normal flow of information to the master controller is always in response to a read command. All control mem-
ory locations are accessed in 8-bit bytes. All read commands from the master controller require a response from
the addressed codec. It is the responsibility of the master controller to ensure that only one device is transmitting
on the serial interface line at any one time. The master controller also must ensure that the CS lead goes high after
transferring the 3-byte sequence used to initiate the read, and then it goes low again for the response. In this case,
it should be noted that the device expects the second time CS goes low that data is to be sent to the master; thus,
it does not interpret the DI lead as containing a valid instruction during that CS excursion and a write during this
time is not recommended. Note also that the CS lead must allow the number of bytes sent in a read command to
be transferred before a subsequent command can be received by the codec. Figures 12—15 illustrate normal or
byte-by-byte operation with continuous or gapped DCLKs. Like a write command, transitions, not frequency, are
critical with regard to gapped DCLK operation.
0079
* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait ≥1.5 µs after the second full DCLK cycle
and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DA TA.
The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK
cycles are required to process the read data.
† Two or more DCLK cyc les are required before the start of a new comm and frame.
Note: Data field length of 1 shown.
Figure 12. Read Operation, Normal Mode (Continuous DCLK)
COMMAND FRAME
01 7
01 7
CS
DCLK
DI
COMMAND START ADDRESS DATA
01 7
01 7 01 7
LENGTH
01 7
01 7
01 7DO
WAIT ≥ 1.5 µs
*
†
Lucent Technologies Inc. 21
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Contro l I nterface (continued)
Read Command (continued)
0077
Notes:
Data field length of 1 shown.
CK1 through CK8 are additional DCLK pulses required to properly process the data.
CK7 and CK8 are not necessary if another command frame follows this sequence.
Figure 13. Read Operation, Normal Mode (Gapped Clock)
COMMAND FRAME
01 7
01 7
CS
DCLK
DI
COMMAND START ADDRESS DATA
01 7
01 7 01 7
CK1
CK2
CK7
CK8
LENGTH
01 7
01 7
01 7
CK5
CK6
CK3
CK4
DO
WAIT ≥ 1.5 µs
22 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Read Command (continued)
0075
* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait ≥1.5 µs after the second full DCLK cycle
and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DA TA.
The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK
cycles are required to process the read data.
† Two or more DCLK cyc les are required before the start of a new comm and frame.
Note: Data field length of 1 shown.
Figure 14. Read Operation, Byte-by-Byte Mode (Continuous DCLK)
01 7
01 7
CS
DCLK
DI
COMMAND START LENGTH DATA
01 7 01 7
01 7 01 7 01 7
*
COMMAND FRAME
ONE OR MORE FULL DCLK
D0 01 7
CYCLES REQUIRED HERE
†
WAIT ≥ 1.5 µs
ADDRESS
Lucent Technologies Inc. 23
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Contro l I nterface (continued)
Read Command (continued)
0073
Notes:
Data field length of 1 shown.
CK1 through CK8 are additional DCLK pulses required to properly process the data.
CK7 and CK8 are not necessary if another command frame follows this sequence.
Figure 15. Read Operation, Byte-by-Byte Mode (Gapped DCLK)
01 7
CK3
CK4
CK5
CK6
DATA
CK1
CK2
01 7 01 7
COMMAND START LENGTH
CS
DCLK
DI
D0
COMMAND FRAME
01 7
CK7
CK8
01 7 01 7 01 7
01 7
WAIT ≥ 1.5 µs
ADDRESS
24 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Fast Scan Mode
The fast scan mode allows a single byte command to read two SLIC control leads for all four channels with a
1-byte reply. This mode significantly speeds up the normal scanning for off-hook, ring trip, and ring ground detec-
tion. This special command sequence allows the controlling microprocessor to fast scan 2 bits in the SLIC control
byte of each of the four channels. The command code is (00000010)2; there are no start address or length fields.
The command returns only a single byte of data, formatted as shown in Table 9.
Table 9. Bit Assignments for Fast Scan Mode
The circuit select in the command structure (Figure 6) is not used for this special single-byte command. The rules
for toggling chip select apply as for the read command. Figures 16—19 illustrate normal or byte-by-byte operation
with continuous or gapped DCLKs.
0125
* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait ≥ 1.5 µs after the second full DCLK cycle
and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between COMMAND and
DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final
DCLK cycles are required to process the read data.
† Two or more DCLK cyc les are required before the start of a new comm and frame.
Figure 16. Fast Scan, Normal Mode (Continuous DCLK)
Bit Reported Status
0 (LSB) Channel 0, bit 0 (ckt a, address 160, bit 0)
1 Channel 0, bit 1 (ckt a, address 160, bit 1)
2 Channel 1, bit 0 (ckt b, address 160, bit 0)
3 Channel 1, bit 1 (ckt b, address 160, bit 1)
4 Channel 2, bit 0 (ckt c, address 160, bit 0)
5 Channel 2, bit 1 (ckt c, address 160, bit 1)
6 Channel 3, bit 0 (ckt d, address 160, bit 0)
7 (MSB) Channel 3, bit 1 (ckt d, address 160, bit 1)
123
CS
DCLK
DI
COMMAND DATA
45
DO
WAIT ≥ 1.5 µs
01234567
67012345670†
*
Lucent Technologies Inc. 25
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Contro l I nterface (continued)
Fast Scan Mode (continued)
0127
Note: CK1 through CK8 are additional DCLK pulses required to properly process the data.
Figure 17. Fast Scan, Normal Mode (Gapped DCLK)
123
CS
DCLK
DI
COMMAND DATA
45
DO
WAIT ≥ 1.5 µs
01234567
67012345670
CK7
CK8
CK0
CK1
CK3
CK4
CK5
CK6
26 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Fast Scan Mode (continued)
0124d
* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait ≥1.5 µs after the second full DCLK cycle
and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between COMMAND and
DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final
DCLK cycles are required to process the read data.
† Two or more DCLK cyc les are required before the start of a new comm and frame.
Figure 18. Fast Scan, Byte-by-Byte Mode (Continuous DCLK)
0126e
Note: CK1 through CK8 are additional DCLK pulses required to properly process the data.
Figure 19. Fast Scan, Byte-by-Byte Mode (Gapped DCLK)
123
CS
DCLK
DI
COMMAND DATA
45
DO
WAIT ≥ 1.5 µs
01234567
67012345670†
*
123
CS
DCLK
DI
COMMAND DATA
45
DO
WAIT ≥ 1.5 µs
01234567
67012345670
CK7
CK8
CK0
CK1
CK3
CK4
CK5
CK6
Lucent Technologies Inc. 27
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description (continued)
The Contro l I nterface (continued)
Write All Channels
The write all channels command causes all four channels to be loaded with the same coefficients with a single data
transfer from the master controller. This allows for a faster initialization of the device after a powerup. This com-
mand should be used with caution since it affects all four channels. The normal memory write and read commands
affect only one channel.
Reset Functionality
0071
Figure 20. Hardware Reset Procedure
The reset function allows the internal logic of the device to be set to a known initial condition, either externally by
activating the reset lead, or on a per-channel basis through the microprocessor interface by setting and then clear-
ing bits, if required, in address RESCTRL (address 128). These two reset functions have different effects, and
each of the software reset functions is a subset of the hardware reset functionality. The primary difference is in the
treatment of the internal memory. The hardware reset is assumed to be a result of a catastrophic hardware event,
such as a loss of power or an initial powerup. Accordingly, the assumption is made that the internal memory does
not contain valid data, and default values for all memory locations are loaded. A software reset, however, can only
be initiated if the device is operational (at least the microprocessor interface), so the contents of the memory may
indeed be valid; thus, the resets may be more specific. Additionally, software resets only affect the selected chan-
nel.
FS
BCLK
RST
DCLK
(GAPPED)
DCLK
(CONTINUOUS)
≥ 8 PULSES REQUIRED
DURING RESET ≥ 12 PULSES REQUIRED
AFTER RESET
NO GAP IS REQUIRED HERE.
≥ 8 PULSES REQUIRED
DURING RESET ≥ 12 PULSES REQUIRED
AFTER RESET
DEVICE CAN NOW BE PROGRAM ME D
WAIT ≥ 5 ms
RUNS CONTINUOUSLY
RUNS CONTINUOUSLY
2828 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Functional Description (continued)
Reset Functionality (continued)
A 0.1 µF capacitor between the RST lead and ground
will effectively hold the lead low long enough to reset
the device on powerup, allowing for a cost-effective
power-on reset function. Notice that the memory must
be reloaded through the serial interface after a hard-
ware reset function. For proper operation, it is neces-
sary for FS and BCLK to be present and stable during
a reset. DCLK transitions (frequency is not critical as
long as the maximum rate is not exceeded) are also
required in order for all internal logic to be properly
cleared as is a wait period for the internal PLL to stabi-
lize. See the timing diagram shown in Figure 20 for the
proper hardware or power-on reset procedure.
For a software reset, the control memory should not be
accessed for a minimum of 256 µs following the reset.
Memory Control Mapping
Several memory locations are used to control the
device. The Software Interface tables (Table 20, Mem-
ory Mapping and Table 21, Control Bit Definition) show
the memory assignments that are useful in call pro-
cessing and system testing. It should be noted that
other memory locations are used by the device to hold
intermediate results and other device state information.
Writing to these other locations can cause serious dis-
ruptions in the operation of the device and should be
avoided.
Stan dby Mode
The device enters a low-power standby mode with
powerup or software reset, or by programming the
CHACTIVE register 129, bit 0. In standby mode, the
control interface is active, capable of writing or reading
registers. SLIC read and write data latches are also
active. Analog signals at VFXI and PCM signals at DR
are ignored in this mode. BCLK must be present for
proper standby mode operation.
Test Capabiliti e s
The device has several built-in test capabilities that can
be used to verify correct operation of the signal pro-
cessing of the line card. These test functions are
accessed in several different control addresses. Five
loopback modes are employed: the first for the digital
signal from the PCM bus to be looped back to the PCM
bus. Thi s loop bac k faci lit y can b e used to ve rify corr ect
operation of the PCM bus interface logic, as well as
operation of the PCM bus. The second digital loopback
function allows complete testing of the digital process-
ing capability of the codec by looping the data back at
the analog/digital conversion interface. The third loop-
back function can be used to check the operation of all
the signal processing performed in the device, includ-
ing the conversions to/from analog. These digital loop-
back functions can be used with tone generation and
reception via the PCM bus.
The first analog loopback facility is at the digital side of
the delta-sigma converters and loops analog transmit
data back to the analog receive path. The second ana-
log loopback is at the PCM bus interface and loops the
transmit data from the line back to the receive path.
By assigning the transmit and receive time slots identi-
cally, a loopback arrangement at the PCM bus can be
effectively programmed for signals generated on the
line side of the codec. This mode is useful for testing
from the line side through the entire device.
SLIC Con trol Capabilities
Memory locations 158, 159, and 160 are used to con-
trol six bidirectional latches that are intended to allow
the serial interface to control other line card devices,
such as ringing/test switches, telecom electromechani-
cal relays, and SLIC devices. When the TTL latches
are configured as outputs, external devices should be
set up to sink current from the latch. Location 158 sets
the operational mode of these latches as either inputs
or outputs. Location 159 specifies what is to be written
on the latch leads driven by the device. Location 160
reports the actual state of these leads. It should be
noted that a channel control reset forces all of these
external leads, except those corresponding to bits 2
and 3, to the high-impedance state, so any inputs con-
nected to bits 0, 1, 4, and 5 should have appropriate
pull-up or pull-down resistors (off-chip, if required) to
force the external device into a known state at power-
up or in the event of a reset. Bits 2 and 3 will reset to
outputs with a value of zero.
Lucent Technologies Inc. 29
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Functional Description (continued)
SLIC Con trol Capabilities (continued)
The fast scan mode allows for a minimal data transfer
on the serial bus to monitor bits 0 and 1 of the SLIC
data memory location (159). If these 2 bits are wired as
inputs to the off-hook and/or ring ground detection cir-
cuits, a convenient method of rapidly scanning for
these two functions is obtained. Bits 2 and 3 default to
outputs; thus, they are convenient to provide control of
the SLIC state. In any event, all six leads are program-
mable for maximum flexibility.
Suggested Initialization Procedures
It is suggested that upon powerup, a hardware reset be
used to set the device into a known state. The serial
interface should then be used to load the memory
addresses that differ from the default values (the write
all channels command is convenient for this function). If
other devices are controlled by the SLIC data memory
location, then it also should be loaded with a known
configuration. After the completion of this sequence,
the device is ready to be activated. Depending on the
application, the next step may either be normal opera-
tion or a set of test sequences. After the initialization of
the memory, the device and associated line card
devices can be controlled by using memory locations
130, 131, 145, 155, 156, 157, 158, 159, and 129; that
is, by supplying the PCM bus time-slot addresses,
switching the SLIC into the proper mode, and activat-
ing the codec. Within memory location 129, the codec
would normally be placed into active mode, with both
directions of the PCM bus enabled at the start of a call.
At the completion of a call, the codec should be placed
into standby mode and the PCM bus disabled. Great
caution should be used when changing the memory
while the codec is in active mode, since termination
impedances, balance impedances, and gains may
change. These changes are likely to yield undesirable
system effects. It is safe to refresh coefficients that are
known to be unchanging in the application. It is always
possible to read the memory to verify its contents with-
out deleterious effects on codec operation. Normal
operation would load the memory and perform all gain
adjustments while the codec is in standby mode.
Under no circumstances should memory above
address 162 be written, since this section of memory is
used for state data and intermediate results. Also, all
reserved addresses should not be written. Changing
this information may have deleterious effects on sys-
tem operation.
Signal Processing
Figure 21 details the signal processing functional
blocks of one channel of the codec.
0497F
* Programmable blocks.
Figure 21. Internal Signal Processing
SPEED
FROM
PCM
BUS
*
GRX1
GAIN
8 kHz
COMP
TO LIN.
TRANSFER
XLPF
GAIN
TWEAKING
GRX2
SINC3
∑-∆
D/A
1-bit
D/A
RCFSMF
TO
0 dB
BAL*
32 kHz4096 kHz
LPF*
DIGITAL
*
*
SLIC
TO
PCM
BUS
*
GAIN
GTX2
LIN.TO
COMP
YLPF
*
GAIN
TWEAKING
GTX1
SINC3
*
FROM
0 dB TO 24 dB
SLIC
TRANSFER
TEQ
∑-∆
A/D
LPF
*
RTZ8 STEPS
IN 5 STEPS
XAG
ANALOG CTZ
*
30 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
1. Sparse copper, one layer test board.
2. Four layer, JEDEC test board.
Operating Ranges
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo-
sure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies employs a human-body
model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation.
ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide stan-
dard has been adopted for the CDM. A standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely
accepted and can be used for comparison.
Parameter Symbol Min Max Unit
Storage Temperature Range Tstg −55 150 °C
Power Supply Voltage (all leads designated power) VDDX —6.5V
Negative Voltage on Any Lead with Respect to Ground VSS −0.25 — V
Thermal Resistance, Junction to Ambient:
68-Pin PLCC1
44-Pin PLCC1
64-Pin TQFP2
100-Pin TQFP2
RΘJA
RΘJA
RΘJA
RΘJA
—
—
—
—
43
49
40
30
°C/W
°C/W
°C/W
°C/W
Package Power Dissipation PD—1W
SLIC Control Interface Latches, Current per Device IL— 160 mA
Parameter Symbol Min Max Unit
Ambient Operating Temperature TA−40 85 °C
Operating Junction Temperature TJ−40 125 °C
Power Supply Voltage (all leads designated power) VDDX 4.75 5.25 V
HBM ESD Threshold Voltage
Device Voltage
T8535/T8536 >2000
Lucent Technologies Inc. 31
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Electrical Characteristics
For all specifications: TA = −40 °C to +85 °C, VDD = 5 V ± 5%, unless otherwise noted. Typical values are for
TA = 25 °C and VDD = 5 V. Input signal frequency is 1004 Hz, BCLK = 16.384 MHz, and DCLK = 4.096 MHz, unless
otherwise noted.
dc Characteristics
Table 10. dc Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
Input V oltage Low VIL All inputs — — 0.8 V
Input V oltage High VIH All inputs 2.0 — — V
Input Current IIL Digital, without pull-up, inputs,
GND < VIN < VDD
With internal pull-up, VIN = GND
(INTS and RST leads)
With internal pull-up, VIN = VDD
(INTS and RST leads)
−10
−240
−10
—
—
—
10
10
10
µA
µA
µA
Output Voltage Low:
All Outputs VOL IL = 3.2 mA — — 0.4 V
SLIC Controls, Configured as Outputs VOL IL = 24 mA — — 1.0 V
Output Voltage Hig h VOH IL = −320 µA3.5——V
Output Current in High-impedance State IOZ —−30 — 30 µA
Line Driver (DX and DO leads) Output
Voltage High VOH IL = −10 mA VDD − 0. 5 — — V
Line Driver (DX and DO leads) Output
Voltage Low VOL IL = 10 mA — — 1.0 V
32 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Electrical Characteristics (continued)
Analog Interface
The following specifications pertain to the analog SLIC interface for each channel.
Table 11. Analog Interface
Table 12. Power Dissipation
Power measurements are made at BCLK = 2.048 MHz, DCLK = 2.048 MHz, no inputs from serial interface, inter-
face latches set as outputs, outputs unloaded.
Parameter Symbol Test Conditions Min Typ Max Unit
Input Resistance RVFXI0.25 < VIN < (VDDX − 0.25) V 100 — 300 kΩ
dc Input Voltage VIX Relative to ground.
Signal should be capacitively
coupled to VFXI.
1.8 2.0 2.2 V
Load Resistance at VFROP and VFRON
(differential) RL
5-8881F
7.5 — — kΩ
Output Resistance RODigital input code correspond-
ing to idle PCM code (µ-law). —210Ω
Output Offset Voltage Between VFROP
and VFRONVOS Digital input code correspond-
ing to idle PCM code (µ-law). −100 0 100 mV
Output Offset Voltage Between VFROP
and VFRON, Standby Mode VOSS RL = 100 kΩ−
20 0 20 mV
Common-mode Output Voltage, Active
Mode VOCM Digital input code correspond-
ing to alternating ± zero µ-law
PCM code.
1.8 2.0 2.2 V
Common-mode Output V oltage, S t andby
Mode VOCMS — 1.7 2.0 2.3 V
Parameter Symbol Test Conditions Min Typ Max Unit
All Channels in Standby, Dissipation for One Channel IDDS — — 21 28 mW
One Channel Active, Dissipation for Active Channel IDD1 — — 200 — mW
Four Channels Active, Dissipation for One Channel IDD1 ——85125mW
RL
RL
RL
RL
Lucent Technologies Inc. 33
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Electrical Characteristics (continued)
Gain and Dynam ic Ra ng e
Table 13. Gain and Dynamic Range
Parameter Symbol Test Conditions Min Typ Max Unit
Absolute Levels GAL Maximum 0 dBm0 levels (1004 Hz):
VFXI (encoder milliwatt), all programma-
ble transmit gains set to 0 dB.
RCV (decoder milliwatt), termination
impedance off, all programmable
receive gains set to 0 dB.
—
—
2.80
5.29
—
—
Vp-p
Vp-p
Absolute Levels GAL Minimum 0 dBm0 levels (1004 Hz):
VFXI (encoder mil liwatt) ,
XAG = 24 dB, GTX1 = 6 dB,
GTX2 = 0 dB.
RCV (decoder milliwatt), termination
impedance off, GRX1 = 0 dB,
GRX2 = −6 dB.
—
—
87.5
2.63
—
—
mVp-p
Vp-p
Absolute Maximum Volt-
age Swings GAL VFXI
VFROP to VFRON (differential) —
——
—3.2
5.28 Vp-p
Vp-p
Transmit Gain Absolute
Accuracy GXA Transmit gain programmed for maxi-
mum 0 dBm0 test level, measured devi-
ation of digital code from ideal
0 dBm0 level at DX digital outputs, with
transmit gain set to 0 dB:
20 °C to 70 °C
0 °C to 85 °C
−40 °C to +85 °C
—
−0.25
−0.35
±0.15
—
—
—
0.25
0.35
dB
dB
dB
Transmit Gain Variation
with Programmed Gain GXAG Measured transmit gain over the range
from maximum to minimum, calculated
deviation from the programmed gain rel-
ative to GXA at 0 dB, VDD = 5 V. −0.1 — 0.1 dB
Transmit Gain Variation
with Frequency, 600 Ω
Resistive Source
Impedance and Syn-
thesized Termination
Impedance
GXAF Relative to 1004 Hz, minimum
gain < GX < maximum gain,
VFXI = 0 dBm0 signal, path gain
set to 0 dB:
f = 16.67 Hz
f = 40 Hz
f = 50 Hz
f = 60 Hz
f = 200 Hz
f = 300 Hz to 3000 Hz
f = 3140 Hz
f = 3380 Hz
f = 3860 Hz
f = 4600 Hz and above
—
—
—
—
—
−0.125
−0.57
−0.735
—
—
−50
−40
−40
−55
−3.5
±0.04
0.01
−0.03
−9.0
—
−30
−26
−30
−30
—
0.135
0.125
0.015
−8.98
−32
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
34 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Electrical Characteristics (continued)
Gain and Dynamic Range (continued)
Table 13. Gain and Dynamic Range (continued)
* Applied to all four channels.
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit Gain Variation
with Signal Level GXAL Sinusoidal test method*,
reference level = 0 dBm0:
VFXI = −40 dBm0 to +3 dBm0
VFXI = −50 dBm0 to −40 dBm0
VFXI = −55 dBm0 to −50 dBm0
−0.25
−0.50
−1.40
—
—
—
0.25
0.50
1.40
dB
dB
dB
Receive Gain Absolute
Accuracy GRA Receive gain programmed to −6 dB,
apply 0 dBm0 signal to IPCM, mea-
sure VRCV, RL = 100 kΩ differentia l:
20 °C to 70 °C
0 °C to 85 °C
−40 °C to +85 °C
—
−0.25
−0.30
±0.15
—
—
—
0.25
0.30
dB
dB
dB
Relative Gain, VFROP to
VFRON — Digital input 0 dBm0 signal,
f = 300 Hz to 3400 Hz. −0.01 — 0.01 dB
Relative Phase, VFROP
to VFRON — Digital input 0 dBm0 signal,
f = 300 Hz to 3400 Hz. −0.25 — 0.25 Degrees
Receive Gain Varia tion
with Programmed Gain GRAG Measure receive gain over the range
from maximum to minimum setting,
calculated deviation from the pro-
grammed gain relative to GRA at
0dB,
VDD = 5 V. −0.1 — −0.1 dB
Receive Gain Varia tion
with Frequency, 600 Ω
Resistive Termination
GRAF Relative to 1004 Hz, digital input =
0 dBm0 code, minimum gain < GR <
maximum gain, 0 dB path gain:
f = below 3000 Hz
f = 3140 Hz
f = 3380 Hz
f = 3860 Hz
f = 4600 Hz and above
−0.125
−0.57
−0.735
—
—
±0.04
±0.04
−0.550
−10.7
—
0.125
0.125
0.015
−8.98
−28
dB
dB
dB
dB
dB
Receive Gain Varia tion
with Signal Level GRAL Sinusoidal test method*,
reference level = 0 dBm0:
IPCM digital level =
−40 dBm0 to +3 dBm0
IPCM digital level =
−50 dBm0 to −40 dBm0
IPCM digital level =
−55 dBm0 to −50 dBm0
−0.25
−0.50
−1.40
—
—
—
0.25
0.50
1.40
dB
dB
dB
Lucent Technologies Inc. 35
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Electrical Characteristics (continued)
Noise Characteristics
Table 14. Per-Channel Noise Characteristics
* RTZ and CTZ paths open. All channels active.
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit Noise,
C-Message Weighted NXC 0 dB transmit gain* —1018dBrnC0
Transmit Noise,
P-Message Weighted NXP 0 dB transmit gain* — — −68 dBm0p
Receiv e Noise,
C-Message Weighted NRC 0 dB receive gain, digital pattern
corresponding to idle PCM code, µ-law*. —1013dBrnC0
Receiv e Noise,
P-Message Weighted NRP 0 dB receive gain, digital pattern
corresponding to idle PCM code, A-law*. ——
−75 dBm0p
Noise, Si ngl e Frequenc y NRS f = 0 kHz to 100 kHz, loop around
measurement, VVFxI = 0 Vrms. ——
−53 dBm0
Power Supply Rejection,
Transmit PSRXVDD = 5.0 VDC + 100 mVrms:
f = 0 kHz to 4 kHz
f = 4 kHz to 50 kHz
C-message weighted
36
30 —
——
—dBC
dBC
Power Supply Rejection,
Receive PSRRMeasured on VFROP,
VDD = 5.0 VDC + 100 mVrm s:
f = 0 kHz to 4 kHz
f = 4 kHz to 25 kHz
f = 25 kHz to 50 kHz
36
40
36
—
—
—
—
—
—
dBC
dBC
dBC
Spurious Out-of-Band
Signals at the Chan-
nel Outputs
SOS 0 dBm0, 300 Hz to 3400 Hz signal applied
to VVFxI, transmit gain set to 0 dB:
4600 Hz to 7600 Hz
7600 Hz to 8400 Hz
8.4 kHz to 50 kHz
—
—
—
—
—
—
−30
−40
−30
dB
dB
dB
36 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Electrical Characteristics (continued)
Dist ortio n and Group D elay
Table 15. Distortion and Group Delay
* Absolute group delay is a function of time-slot assignment and the maximum in this table refers to the optimal (minimum group delay) time-
slot assignment.
Parameter Symbol Test Conditions Min Typ Max Unit
Signal to Total Distortion,
Transmit or Receive STDX
STDRSinusoidal test method level:
µ-law −30 dBm0 to +3 dBm0
A-law −30 dBm0 to +3 dBm0
µ-law −40 dBm0 to −30 dB m0
A-law −40 dBm0 to −30 dBm0
µ-law −45 dBm0 to −40 dB m0
A-law −45 dBm0 to −40 dBm0
36
35
31
30
27
25
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
Single Frequency Distortion,
Transmit SFDX0 dBm0 single frequency input,
200 Hz < fIN < 3400 Hz; measured
at any other single frequency.
——
−46 dB
Single Frequency Distortion,
Receive SFDR0 dBm0 single frequency input,
200 Hz < fIN < 3400 Hz; measured
at any other single frequency.
——
−46 dB
Intermodulation Distortion IMD Transmit or receive, two
frequencies in the range of
300 Hz to 3400 Hz.
—−55 −49 dB
TX Group Delay, Absolute* DXA f = 1600 Hz, 600 Ω
resistive termination. ——475
µs
RX Group Delay, Absolute* DRX f = 1600 Hz, 600 Ω
resistive termination. ——235
µs
Lucent Technologies Inc. 37
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Electrical Characteristics (continued)
Crosstalk
Table 16. Crosstalk
Parameter Symbol Test Conditions Min Typ Max Unit
Transmit to Transmit Crosstalk,
0 dBm0 Level CTX-X f = 300 Hz to 3400 Hz,
any channel to any channel. —−95 −80 dB
Transmit to Receive Crosstalk,
0 dBm0 Level CTX-R f = 300 Hz to 3400 Hz,
any channel to any other channel.
In-channel. —
—−100
−100 −80
−80 dB
dB
Receive to Transmit Crosstalk,
0 dBm0 Level CTR-X f = 300 Hz to 3400 Hz,
any channel to any other channel.
In-channel. —
—−100
−85 −80
−65 dB
dB
Receive to Receive Crosstalk,
0 dBm0 Level CTR-R f = 300 Hz to 3400 Hz,
any channel to any channel. —−100 −80 dB
38 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Timing Characteristics
Control Interface Timing
Serial Control Port Timing
Table 17. Serial Control Port Timing (see Figure 22 and Figure 23)
*The tSXBDLY delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.
Symbol Parameter Test Conditions Min Typ Max Unit
fDCLK Serial Bus Clock Frequency — — — 4096 kHz
— Serial Bus Clock Duty Cycle — 40 50 60 %
tCSSETUP Chip Select Setup Time, Normal Mode DCLK = 4.096 MHz 7 — — ns
tCSHOLD Chip Select Hold Time, Normal Mode DCLK = 4.096 MHz 4 — t DCLK −
tCSSETUP ns
tSXDLY Serial Bus Output Data Delay, Normal Mode DCLK = 4.096 MHz — — 9 ns
tSDHOLD Serial Bus Input Data Hold Time, Normal Mode DCLK = 4.096 MHz 4 — — ns
tSDSETUP Serial Bus Input Data Setup Time, Normal
Mode DCLK = 4.096 MHz 7 — — ns
tRISE Clock Edge Rise Time DCLK = 4.096 MHz — — 12 ns
tFALL Clock Edge Fall Time DCLK = 4.096 MHz — — 12 ns
tRISE,
tFALL Line Driver Rise/Fall Time (DO output) IL = 15 mA,
CLOAD = 100 pF — — 30 ns
tCSBHOLD Chip Select Hold Time, Byte-by-Byte Mode DCLK = 4.096 MHz 4 — — ns
tSXBDLY Serial Bus Output Data Delay, Byte-by-Byte
Mode DCLK = 4.096 MHz* — — 9 ns
tCSBSETUP Chip Select Setup Time, Byte-by-Byte Mode DCLK = 4.096 MHz 7 — — ns
tSDBHOLD Serial Bus Data Hold Time, Byte-by-Byte Mode DCLK = 4.096 MHz 4 — — ns
tSDBSETUP Serial Bus Data Setup Time, Byte-by-Byte
Mode DCLK = 4.096 MHz 7 — — ns
tCSBHOLD Chip Select Hold Time, Byte-by-Byte Mode DCLK = 4.096 MHz 4 — t DCLK −
tCSBSETUP ns
Lucent Technologies Inc. 39
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Timing Characteristics (continued)
Control Interface Timing (continued)
Normal Mode
5-7185.e(F)
Figure 22. Serial Interface T iming, Normal Mode (One Byte Transfer Shown)
Byte-by-Byte Mode
5-7186.b(F)
Figure 23. Byte-by-Byte Mode Timing
123456789
01234567
01234567
CS
DCLK
DO
DI
LSB
tCSSETUP
tSXDLY tSDHOLD
tSDSETUP
tCSHOLD
123456789
01234567
01234567
CS
DCLK
DO
DI
LSB MSB
tCSBSETUP
tSDBSETUP tSXBDLY
tCSBHOLD
tSDBHOLD
tSDBSETUP
4040 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Timing Characteristics (continued)
PCM Interface Timing
Single-Clocking Mode
Frame sync (FS) signifies the start of frame on the
PCM bus for all four channels. FS occurs every
125 µs at an 8 kHz rate. FS must be synchronous
with the PCM bus clock (BCLK) and must be high for a
minimum of one BCLK period. The PCM interface
operates using fixed data rate timing, data timing for
both transmit and receive are controlled by BCLK.
BCLK can be any value from 512 kHz (eight time slots)
to 16.384 MHz (256 time slots) as defined by Table 18.
The PCM bus transfers the most significant bit of the
time slot first, consistent with normal telephony prac-
tice. Figure 24 shows DX beginning on the rising edge
of BCLK and FS and DR being latched on the falling
edge of BCLK. Figure 25 shows DX beginning and FS
being latched on the rising edge of BCLK and DR being
latched on the falling edge of BCLK.
Figure 24 portrays a bit offset of zero, and Figure 25
portrays a transmit bit offset of one and a receive bit
offset of two. Bit offset skews the PCM transmit and/or
receive data independently from the FS reference. Up
to 7 BCLK cycles of bit offset can be employed on a
per-channel basis. This flexibility can accommodate
special timing requirements. If using the same offset for
all channels, simply use the write all channels com-
mand.
TSX0 or TSX1 is active (low) when DX data is transmit-
ting.
Table 18. PCM Interface Timing: Single-Clocking Mode (see Figures 24 and 25)
Symbol Parameter Test Conditions Min Typ Max Unit
fBCLK Allowable BCLK Frequencies —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
512
1024
1536
2048
3072
4096
8192
16384
—
—
—
—
—
—
—
—
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
— Jitte r of BCLK — — — 100 ns in
100 ms =
1 ppm
—
—BCLK Duty Cycle —405060%
tFSSETUP Frame Strobe Setup Time BCLK = 16.384 MHz 7 — — ns
tFSHOLD Frame Strobe Hold Time BCLK = 16.384 MHz 4 — — ns
tFSWIDTH Frame Strobe Width FS synchronous with
BCLK tBCLK —125
µs − tBCLK —
tXDLY PCM Bus Output Data Del ay BCLK = 16.384 MHz — — 9 ns
tIDHOLD PCM Bus Input Data Hold Time BCLK = 16.384 MHz 4 — — ns
tIDSETUP PCM Bus Input Data Setup Time BCLK = 16.384 MHz 7 — — ns
tRISE Clock Edge Rise Time BCLK = 16.384 MHz — — 8 ns
tFALL Clock Edge Fall Time BCLK = 16.384 MHz — — 8 ns
tRISE,
tFALL DX Output Rise/Fall Time IL = 15 mA,
CLOAD = 100 pF — — 30 ns
tDXHIGHZ DX Output Data Float on TS Exit CLOAD = 0 — — 5 ns
tTSXDELAY Line Driver Enable Delay — — — 5 ns
tTSXHIGHZ Line Driver Enable Float on TS Exit — — — 5 ns
Lucent Technologies Inc. 41
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Timing Characteristics (continued)
PCM Interface Timing (continued)
Single-Clocking Mode (continued)
5-7188d F
Figure 24. Single-Clocking Mode (TXBITOFF = 0, RXBITOFF = 0, PCMCTRL2 = 0x00)
5-7185.g F
Figure 25. Single-Clocking Mode (TXBITOFF = 1, RXBITOFF = 2, PCMCTRL2 = 0x01)
123456789
12345678
FS
SCLK
DX0/1
DR0/1
LSB
12345678
TIME SLOT 0
SIGN BIT
tFSHOLD
tFSSETUP
tXDLY tIDHOLD
tIDSETUP
tFSWIDTH
TSX0/1
tTSXDELAY
tDXHIGHZ
tTSXHIGHZ
123456789
12345678
1234567
FS
BCLK
DX0/1
DR0/1 8
TSX0/1
4242 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Timing Characteristics (continued)
PCM Interface Ti ming (continued)
Double-Clocking Mode
As with the single-clocking mode, FS signifies the start
of frame on the PCM bus for all four channels and
occurs every 125 µs at an 8 kHz rate. FS must be
synchronous with BCLK and must be high for a mini-
mum of one BCLK period. And the PCM interface oper-
ates using fixed data rate timing; data timing for both
transmit and receive are controlled by BCLK. In dou-
ble-clocking mode, however, BCLK runs at twice the
PCM data rate. BCLK can be any value from 512 kHz
(data rate of 256 kbits/s, 4 time slots) to 16.384 MHz
(data rate of 8192 kbits/s, 128 time slots) as defined by
Table 19.
The PCM bus transfers the most significant bit of the
time slot first. In Figure 26, the MSB of receive data is
latched on the falling BCLK edge following the first fall-
ing BCLK edge that latches FS. Tr ansmit data starts on
the first rising edge of BCLK prior to the falling BCLK
edge that latches FS.
Figure 26 portrays a bit offset of zero. Like single-clock-
ing mode, bit offset skews the PCM transmit and/or
receive data independently from the FS reference. Up
to 7 BCLK cycles of bit offset can be employed on a
per-channel basis. This flexibility can accommodate
special timing requirements. If using the same offset for
all channels, simply use the write all channels com-
mand.
TSX0 or TSX1 (not shown in Figure 26) is active (low)
when DX data is transmitting.
Table 19. PCM Interface Timing: Double-Clocking Mode (see Figure 26)
Note: DX load = 150 pF.
Symbol Parameter Signal Min Typ Max Unit
fBCLK Allowable BCLK Frequencies BCLK —
—
—
—
—
—
—
—
512
1024
1536
2048
3072
4096
8192
16384
—
—
—
—
—
—
—
—
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
— Jitter of BCLK BCLK — — 100 ns in
100 ms =
1 ppm
—
tBCL Clock Period BCLK 61 — 1953 ns
tR, tF Clock Rise/Fall BCLK — — 8 ns
tWL, tWH Pulse Width BCLK tBCL x 0.4 — tBCL x 0.6 ns
tR, tF Frame Rise/Fall FS — — 15 ns
tWFH Frame Width High FS tBCL — — ns
tWFL Frame Width Low FS tBCL — — ns
tSF Frame Setup FS 7 — tBCL − 50 ns
tHF Frame Hold FS 4 — — ns
tD DC Da ta Delay Clock DX — — 9 ns
tDDF Data Delay Frame DX — — 9 ns
tSD Data Setup DR 7 — — ns
tHD Data Hold DR 4 — — ns
Lucent Technologies Inc. 43
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Timing Characteristics (continued)
PCM Interface Timing (continued)
Double-Clocking Mode (continued)
5-7173F
Figure 26. Double-Clocking Mode (Bit Offset = 0, PCMCTRL2 = 0x00)
BCLK
FS
DX/DR bit 0 bit 1 bit 2
DETAIL A
BCLK
tR tF
tWLtBCL
tWH
tSF tHF
tWFH
tDDF
tDDC
tHD
tSD
FS
DX
DR
DETAIL A
44 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Software Interface
Table 20. Memory Mapping
With the exceptions noted, all of these memory locations may be read to determine the state of the controls con-
tained therein. In the following table, bit 0 is the LSB (transmitted first on the serial interface) and bit 7 is the most
significant bit of the byte. Unused bits in an address or multibyte address should be loaded as zero. All of the mem-
ory locations can be programmed on a per-channel basis.
Note that the entire coefficient set for a channel (or all four channels) may be loaded with one command.
Control
Name Address
(Decimal) # of
Bits
Used
Default
Value Description
HBALTAPS 0—27
64—91 448 — Balanc e impe dan ce tap co efficie nts .
Reserved 28—63
92—127 — — These addresses have no function.
RESCTRL 128 2 0x00 Reset address. Writing a one in the used positions causes a
reset as defined by the bit definition. This reset remains in
force until the bit is written as a zero.
CHACTIVE 129 1 0x00 Standby/active control.
RXBITOFF 130 4 0x00 Bit of fset for receive direction.
RXOFF 131 8 16 * channel # Time-slot assignment for receive direction.
GRX1 132 11 0x0400 Gain transfer for receive direction.
GRX2 134—135 11 0x01ac Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, receive direction.
Reserved 136—139 — — This address has no function.
CTZCTRL 140—143 31 07ed0000 CTZ bleed coefficients.
Reserved 144 — — This address has no function.
PCMCTRL2 145 6 0x00 PCM transmission and sampling edge control.
SDCTRL 146 7 0x19 RTZ, transmit analog gain (XAG), and digital loopback 3
controls.
SDTSI 147 7 17 * channel # Internal time-slot interchanger and loopback controls.
Default sets external pins to state referenced in this data
sheet.
GTX2 148—149 12 0x0400 Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, transmit direction.
ZEQTX 150—152 21 0x000000 Transmit line equalization.
GTX1 153—154 12 0x051a Gain transfer for transmit direction.
TXBITOFF 155 4 or 5 0x00 Bit offset for transmit direction.
TXOFF 156 8 16 * channel # Time-slot assignment for transmit direction.
PCMCTRL1 157 7 0x00 PCM, companding, and loopback controls.
SLICTS 158 6 0x0c SLIC 3-state control. Latch I/O.
SLICWR 159 6 0x00 Data to be written to the SLIC latches if the corresponding
bit is set in the SLICTS control word.
SLICRD 160 6 — Current actual state of the SLIC leads. This will be the same
as SLICWR for those leads configured as outputs. All other
positions will reflect the actual state of the external lead. A
write operation to this word will be ignored, and within one
PCM frame (125 µs), the data will be overwritten.
Reserved 161 — — This address has no function.
VERIFY 162 8 0x00 Test address for serial interface verification.
Lucent Technologies Inc. 45
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Software Interface (continued)
Table 21. Control Bit Definition
The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the
bit being set places the function into the active mode as defined in the function column.
Control Name
(Address) Bit
Assignment(s) Function
HBALTAPS
(0—27, 64—91) 448 Balance impedance coefficients. Default value is 0x00 for all bytes except for
addresses 3 and 5, which are 0x80, and address 69, which is 0x88.
RESCTRL
(128) 2—7 Not used, load as zeros.
1 A one resets all other internal states. Control addresses are not reset.
0 A one resets all control addresses to default values. Note that setting this bit
will result in it and all others of this word becoming cleared on the next PCM
frame as a normal part of the reset functionality. Alternatively, hardware reset
can be used to reset all control and state functions. It is necessary to wait at
leas t 256 µs after asserting this bit before initiating any other serial I/O trans-
actions.
CHACTIVE
(129) 1—7 Load as zeros.
0 Active/standby mode. A zero causes the channel to enter standby (low-
power) mode and disables the PCM interface for this channel. A one acti-
vates the channel and the corresponding PCM bus interface. Default is zero.
RXBITOFF
(130) 5—7 Receive direction bit offset for the FS signal. Defaults to zero. These 3 bits
can be thought of as the least significant bits (RXOFF contains the more sig-
nificant bits) of a bit counter that determines the location of the first bit of the
PCM data from FS.
0—4 Load as zeros.
RXOFF
(131) 0—7 Receive time-slot assignment. Defaults to (16 * channel number). Each time
slot r epresents 8 bits.
GRX1
(132—133) 0—10 Gain adjustment for gain transfer stage in receive direction. Defaults to
0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain of
two (6 dB). 0 dB is the maximum recommended setting.
GRX2
(134—135) 0—10 Gain adjustment for tweak gain stage in receive direction. Defaults to 0x01ac
(−7.58 dB). This is an 11-bit multiply operation with a maximum gain of two
(6 dB). 0 dB is the maximum recommended setting.
CTZCTRL
(140—143) 0—30 Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000.
PCMCTRL2
(145) 6—7 Load as zeros.
5 A one selects DX PCM port 1. A zero selects DX PCM port 0. Defaults to
zero. PCM port 1 is not available in all package types.
4 A one selects DR PCM port 1. A zero selects DR PCM port 0. Defaults to
zero. PCM port 1 is not available in all package types.
3 A one selects double-clocking mode. Defaults to zero (single-clocking mode).
A write to any channel affects all four channels.
2 A one starts transmit data on a falling BCLK edge. A zero starts transmit data
on a rising BCLK edge. Defaults to zero. A write to any channel affects all
four channels.
1 A one latches receive data on a rising BCLK edge. A zero latches receive
data on a falling BCLK edge. Defaults to zero. A write to any channel affects
all four channels.
0 A one latches FS on a rising BCLK edge. A zero latches FS on a falling BCLK
edge. Defaults to zero. A write to any channel affects all four channels.
46 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Software Interface (continued)
Table 21. Control Bit Definition (continued)
Control Name
(Address) Bit
Assignment(s) Function
SDCTRL
(146) 7 Load as zero.
6 Enable digital loopback 3. Defaults to zero (loopback disabled).
3—5 RTZ gain. Defaults to 3 (equal level point value of 3 * 0.075 = 0.225). Turn off
by writing to zero.
0—2 Transmit analog gain (XAG). Defaults to 1 (6 dB)
gain. Bit Number Function
(dB)
210
0 0 0 0.0
001 6.02
0 1 0 12.04
0 1 1 18.06
1 0 0 24.08
SDTSI
(147) 7 Load as zero.
6 Digital loopback, receive to transmit at the sigma-delta converters (digital
loopback 2). Defaults to zero (no loopback).
4—5 Digital channel feeding this analog receive channel. Defaults to channel num-
ber.
3 Send idle-channel code (alternating bits) to this analog receive path. Defaults
to zero (off).
2 Loopback from transmit to receive at the sigma-delta converters (analog loop-
back 1). Defaults to zero (no loopback).
0—1 Analog channel feeding this digital channel in the transmit direction. Defaults
to channel number.
GTX2
(148—149) 0—11 Gain control for gain transfer stage in transmit direction. Defaults to 0x0400
(0 dB). This is a 12-bit multiply operation with a maximum gain of four (12 dB).
ZEQTX
(150—152) 0—20 Coefficients for the transmit equalization stage. Varies frequency response
and accommodates current sensing SLICs. Defaults to 0x000000.
GTX1
(153—154) 0—11 Gain control for tweak gain stage in transmit direction. Defaults to 0x051a
(2.11 dB). This is a 12-bit multiply operation with a maximum gain of four
(12 dB).
TXBITOFF
(155) 5—7 Transmit direction bit offset for the FS signal. Defaults to zero. These 3 bits
can be thought of as the least significant bits (TXOFF contains the more signif-
icant bits) of a bit counter that determines the location of the first bit of the
PCM data from FS.
0—4 Load as zeros.
TXOFF
(156) 0—7 Transmit time-slot assignment. Defaults to (16 * channel number). Each time
slot repres ents 8 bits.
Lucent Technologies Inc. 47
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Software Interface (continued)
Table 21. Control Bit Definition (continued)
Control
Name
(Address)
Bit
Assignment(s) Function
PCMCTRL1
(157) 7 3-state transmit PCM interface. Defaults to zero. A one forces the PCM interface
into a high-impedance state during its assigned time-slot on the PCM bus. Plac-
ing the channel in standby mode also forces a high-impedance condition on the
transmit interface.
6 Transmit zeros instead of data. Defaults to zero (off).
5 Load as zero.
4 Place idle-channel code on receive path. Defaults to zero (off).
3 Loopback receive to transmit at PCM conversion interface (digital loopback 1).
Resets to zero.
2 Loopback transmit to receive at PCM conversion interface (analog loopback 2).
Resets to zero.
1 Reserved. Must be programmed to zero. Defaults to zero.
0µ-law or A-law. A one sets A-law mode, and a zero sets µ-law mode. Defaults to
zero (µ-law).
SLICTS
(158) 6—7 Load as zeros.
0—5 Controls the drivers for the corresponding SLIC latches. A one enables the lead
as an output. Defaults to 0x0C (bits 2 and 3 set, the rest cleared).
SLICWR
(159) 6—7 Load as zeros.
0—5 SLIC data latches. If the corresponding bit in the SLICTS address is set for an
output, the device will drive the corresponding bit according to the contents of this
address. Writes are performed within 125 µs. Wait 125 µs before a subsequent
write to the same channel or between write all channel commands. Default is
zero.
SLICRD
(160) 6—7 Not used, ignore on read.
0—5 Reports the actual state of the SLIC leads. Anything written to this address is
ignored. The state updates within 125 µs.
VERIFY
(162) 0—7 Test location for serial interface. This location has no internal use, but merely
latches write data for the purpose of testing the serial interface.
48 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Applications
The following reference circuit shows a complete schematic for interfacing to the Lucent L9215G SLIC. All ac
parameters are programmed by the T8536. Note that this implementation differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit.
12-3534.f (F)
Figure 27. POTS Interface
VBAT1 BGND VBAT2 VCC AGND ICM TRGDET
ground key
not used
CBAT1
0.1 µF
CBAT2
0.1 µF
CCC
0.1 µF
RTFLT
DCOUT
PR
PT
OVH
VPROG
VREF
CRT
0.1 µF
RRT
383 kΩ
LUCENT
L7591
VBAT1
FUSIBLE OR PTC
50 Ω
50 Ω
CF1 CF2
rate of battery
reversal not
ramped
FB1 FB2 NSTAT BR B2 B1 B0
CF1
0.47 µFCF2
0.1 µF
PPM
0.5 Vrms
CPPM
10 nF
RINGIN PPMIN
VITR
RCVP
RCVN
ITR
VTX
TXI
RGX
4640 Ω
VBAT1
DBAT1
VBAT2 VCC
CTX
0.1 µF
CRING
0.47 µF
FROM
PROGRAMMABLE
D/A VOLTAGE
SOURCE
CC1
PCM
HIGHWAY
DX0
DR0
DX1
DR1
FS
BCLK
DGND
VDD
SYNC
AND
VDD
VFXI
VFROP
VFRON
SLIC4a
SLIC3a
SLIC2a
SLIC1a
SLIC0a
CLOCK
L9215G
FROM/TO
CONTROL
B2
B1
BR
NSTAT
B0
0.1 µF
FUSIBLE OR PTC
T8536
RPD1 10 kΩ
Lucent Technologies Inc. 49
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Outline Diagrams
100-Pin TQFP
Dimensions shown are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only.
For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Repre-
sentative.
5-2146F
0.50 TYP
1.60 MAX
SEATING PLANE
0.08
1.40 ± 0.05
0.05/0.15
DETAIL A DETAIL B
14.00 ± 0.20
16.00 ± 0.20
76100
1
25
26 50
51
75
14.00
± 0.20
16.00
± 0.20
PIN #1 IDENTIFIER ZONE
DETAIL B
0.19/0.27
0.08 M
0.106/0.200
DETAIL A 0.45/0.75
GAGE PLANE
SEATING PLANE
1.00 REF
0.25
50 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Outline Diagrams (continued)
68-Pin PLCC
Dimensions shown are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only.
For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Repre-
sentative.
5-2139
19
10
26
27 43
44
60
61
PIN #1 IDENTIFIER ZONE
25.146 ± 0.127
24.231 ± 0.102
25.146
± 0.127
24.231
± 0.102
1.27 TYP 0.330/0.533
5.080
MAX
0.51 MIN,
TYP
SEATING PLANE
0.10
Lucent Technologies Inc. 51
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Outline Diagrams (continued)
64-Pin TQFP
Dimensions shown are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only.
For detailed schematics to assist your design efforts, please contact your Lucent Technologies Sales Repre-
sentative.
5-3080
DETAIL A
0.50 TYP
1.60 MAX
SEATING PLAN E
0.08
DETAIL B
0.05/0.15
1.40 ± 0.05
10.00 ± 0.20
12.00 ± 0.20
1
64 49
16
17 32
48
33
10.00
± 0.20
12.00
± 0.20
PIN #1
IDENTIFIER ZONE
DETAIL A
0.45/0.75
GAGE PLANE
SEATING PLANE
1.00 REF
0.25
DETAIL B
0.19/0.27
0.08 M
0.106/0.200
52 Lucent Technologies Inc.
Preliminary Data Sheet
February 2001
T8535/T8536 Quad Programmable Codec
Outline Diagrams (continued)
44-Pin PLCC
Dimensions are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only.
For detailed footprint drawings to assist your design efforts, please contact your Lucent Technologies Sales
Representative.
5-2506(F)
4.57
MAX
1.27 TYP 0.53
MAX
0.10
SEATING PLANE
0.51 MIN
TYP
1640
7
17 29
39
18 28
PIN #1 IDENTIFIER
ZONE
16.66 MAX
17.65 MAX
16.66
MAX
17.65
MAX
Lucent Technologies Inc. 53
Prelim inary Data Sheet
February 2001 T8535/T8536 Quad Programmable Codec
Ordering Information
Device Code Package Temperature Comcode
T-8535 - - - ML-D 44-Pin PLCC
Dry-bagged −40 °C to +85 °C 108420472
T-8536 - - - ML-D 68-Pin PLCC
Dry-bagged −40 °C to +85 °C 108420506
T-8536 - - - ML-DT 68-Pin PLCC
Tape & Reel
Dry-bagged
−40 °C to +85 °C 108420514
T-8536 - - 1TL-DB 100-Pin TQFP
Dry Pack Tray −40 °C to +85 °C 108558511
T-8536 - - 1TL-DT 100-Pin TQFP
Tape & Reel
Dry-bagged
−40 °C to +85 °C 108760091
T-8536 - - - TL-DB 64-Pin TQFP
Dry Pack Tray −40 °C to +85 °C 108420498
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result o f their use o r application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 2001 Lucent Technologies Inc.
All Rights Reserved
February 2001
DS01-047ALC (Replaces DS00-377ALC )
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
E-MAIL: docmaster@micro.lucent.com
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1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC:Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652
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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
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