TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 Eight-Channel LED Driver with Intelligent Headroom Voltage Monitor (iHVMTM) Check for Samples: TLC5960 FEATURES * 1 * * 23 * * * * * * 250kHz PWM Dimming Four Intelligent Headroom Voltage Monitor (iHVM) Outputs Eight-Channel, High-Voltage LED Driver: - 0.3% (typ) Accuracy Between Channels Control Interface with Four PWM Inputs Easy-To-Use Analog Dimming Interface 10% to 100% Analog Brightness Dimming Integrated 5V Internal Regulator Integrated Power-On Reset (POR) Circuitry * * Full Protection/Diagnostic Functions: - LOD: LED Open Detection - LSD: LED Short Detection - FOD: FET Open Detection - FSD: FET Short Detection Built-In Phase Shift Function 38-Pin TSSOP Package APPLICATIONS * * LED Backlights for LCD-TV High-Current LED Lighting DESCRIPTION The TLC5960 is an eight-channel PWM LED driver with four intelligent headroom voltage monitor (iHVM) outputs. The LED drivers have scalable, high-voltage capability and provide 1% maximum current matching accuracy between LED strings. To achieve optimal efficiency, the iHVM automatically optimizes the external dc/dc converter output voltage to compensate for the forward-voltage variations of the LED Compared to a conventional HVM solution that requires several MOSFETs, capacitors, and resistors, the iHVM is designed to use only a single external resistor. The LED driver design is capable of up to 250kHz PWM dimming, and also provides an analog brightness dimming interface. This device easily adapts to various LED and power configurations with a single voltage input rail. Full protection and diagnostic functions are provided to protect the entire system, such as LED open/short detection (LOD/LSD), FET open/short detection (FOD/FSD) and thermal shutdown (TSD). In case of failure, the TLC5960 automatically disconnects the failed channel(s) from the operating channels and pulls down the open drain fault buffer (XFLT) to signal an error status. iHVMTM VLED4 DC/DC4 DC/DC3 DC/DC2 DC/DC1 VLED1 Ch1 VIN D1 G1 S1 Ch2 D2 G2 S2 Ch8 D8 G8 S8 HVM[1:4] CTRL[1:4] TLC5960 EN XFLT VREG5 VADJ Typical Application Circuit 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. iHVM is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010, Texas Instruments Incorporated TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR ORDERING NUMBER TLC5960 TSSOP-38 DA TLC5960DA For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE Voltage (2) Temperature MIN MAX VIN, CTRL2, CTRL4 -0.3 30 V S1 to S8, D1 to D8 -0.3 38 V EN, CTRL1, CTRL3, VADJ, VREG5, G1 to G8, XFLT, HVM1 to HVM4 -0.3 6.0 V Operating virtual junction, TJ -40 +150 C Storage, Tstg -55 +150 C 2 kV 1000 V 200 V Human Body Model (HBM, JESD22-A114) Electrostatic Discharge Rating (3) Charged Device Model (CDM. JESD22-C101) Machine Model (MM) (1) (2) (3) UNIT Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TLC5960 THERMAL METRIC (1) DA UNITS 38 PINS qJA Junction-to-ambient thermal resistance 71.2 qJCtop Junction-to-case (top) thermal resistance 21.8 qJB Junction-to-board thermal resistance 43.6 yJT Junction-to-top characterization parameter 0.5 yJB Junction-to-board characterization parameter 38.7 qJCbot Junction-to-case (bottom) thermal resistance N/A (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. DISSIPATION RATINGS 2 PACKAGE OPERATING FACTOR ABOVE TA = +25C TA < +25C POWER RATING TA = +70C POWER RATING TA = +85C POWER RATING TSSOP-38 (DA) 14mW/C 1404mW 770mW 560mW Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 RECOMMENDED OPERATING CONDITIONS TLC5960 PARAMETER MIN NOM MAX UNIT 10 24 28 V DC Characteristics VIN Supply voltage VD Voltage applied to sense input (D1 to D8, S1 to S8) GND 34 V VIH High-level input voltage (CTRL1 to CTRL4) 1.2 5.5 V VIL Low-level input voltage (CTRL1 to CTRL4) GND 0.4 V ISINK Low-level output current (XFLT) CLOAD Capacitive load of Gn outputs (G1 to G8) VG MOSFET threshold voltage (G1 to G8) CVREG5 Regulator output capacitor (VREG5) 1.0 TA Operating free-air temperature range -40 +85 C TJ Operating junction temperature range -40 +125 C 100 1 mA 500 pF 2.8 V 2.2 F AC Characteristics: At VIN = 10V to 28V and TA = -40C to +85C tWH0/tWL0 CTRLn pulse duration (CTRL1, 2, 3, 4 = high or low) 4 s tWH1/tWL1 EN pulse duration (EN = high or low) 50 s tSU0 Setup time (EN to CTRL1, 2, 3, 4) 50 s tH0 Hold time (EN to CTRL1, 2, 3, 4) 2 s Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 3 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS At VIN = 10.0V to 28.0V and TA = -40C to +85C. Typical values at VIN = 24V and TA = +25C, unless otherwise noted. TLC5960 PARAMETER VOL TEST CONDITIONS Open-drain low-level output voltage RPD Internal pull-down resistance MIN TYP IOL = 1mA at XFLT MAX 0.8 UNIT V EN 100 CTRL1 to CTRL4 500 k 2 M HVM4, CTRL2 > 7.0V k VIN < VPOR (1) 20 40 A IIN VIN supply current VIN > VPOR, EN = high or low, CTRL1 to CTRL4 = high or low 10 16 mA IOH High-level output current (G1 to G8) EN = CTRL1 to CTRL4 = high VOFFSET Input offset voltage of output amplifier (S1 to S8) VADJ = 1.2V -10 VDREF+ HVM upper threshold (D1 to D8) EN = CTRL1 to CTRL4 = high 2.5 VDREF- HVM lower threshold (D1 to D8) EN = CTRL1 to CTRL4 = high VHVM HVM output voltage range (HVM1 to HVM4) EN = high or low, CTRL1 to CTRL4 = high or low HVM output source current HVM1 to HVM4 = 1.25V HVM output sink current HVM1 to HVM4 = 0.14V 1.5 VLOD LED open detection threshold (D1 to D8 undervoltage detection) EN = CTRL1 to CTRL4 = high 0.7 0.8 0.9 V VLSD LED short detection threshold (D1 to D8 overvoltage detection) EN = CTRL1 to CTRL4 = high, CTRL2,4 < 6V, HVM 2CH mode 18.0 19.2 20.4 V VFOD FET open detection threshold (S1 to S8 undervoltage detection) EN = high, CTRL1 to CTRL4 = high, VADJ = 5.0V 300 VFSD FET short detection threshold (S1 to S8 overvoltage detection) EN = high 0.8 0.9 1.0 V VFSDHYS FET short detection hysteresis (S1 to S8 overvoltage detection) 150 200 250 mV TSTD Thermal shutdown junction temperature (2) IHVM ILIM mA 10 mV 2.6 2.7 V 1.55 1.6 1.65 V 0.1 0.7 1.3 V -1.5 mA mA mV +160 5V LDO VREG 2 C CVREG5 = 2.2F Regulator output voltage 10V < VIN < 28V, IVREG5 < 25mA Current limit 4.75 5.00 5.25 VIN = 24V, VREG5 = 4.5V 20 40 80 mA V VIN = 24V, VREG5 = 0V 10 20 40 mA Negative going threshold on VIN 6.5 7.0 7.5 POWER-ON RESET (POR) VPOR Undervoltage lockout on VIN VPORHYS Undervoltage lockout hysteresis AC CHARACTERISTICS 500 V mV TA = +25C tDET Protection time after channel enabled tDET1 Detection time after channel enable 13 s tDET2 Protection/XFLT indication wait time after detection (3) 13 s tD Built-in phase shift unit delay time 13 s (1) (2) (3) 21 26 31 s VPOR is the power-on reset voltage. Specified by design. XFLT is the fault indicator; protection means that the failed channel shuts off. tDET = tDET1 + tDET2. SWITCHING CHARACTERISTICS At VIN = 10.0V to 28.0V and TA = -40C to +85C, with typical values at VIN = 24V and TA = +25C, unless otherwise noted. TLC5960 PARAMETER tSW 4 Switching time of output current TEST CONDITIONS MIN S1 to S8, from 10% to 90% or 90% to 10%, CLOAD < 100pF Submit Documentation Feedback TYP MAX 1.5 2 UNIT s Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 PIN CONFIGURATIONS DA PACKAGE TSSOP-38 (TOP VIEW) VIN 1 38 GND VADJ 2 37 HVM2 VREG5 3 36 HVM3 HVM1 4 35 HVM4 CTRL1 5 34 CTRL3 CTRL2 6 33 CTRL4 EN 7 32 XFLT D1 8 31 D5 G1 9 30 G5 S1 10 29 S5 D2 11 28 D6 G2 12 27 G6 S2 13 26 S6 D3 14 25 D7 G3 15 24 G7 S3 16 23 S7 D4 17 22 D8 G4 18 21 G8 S4 19 20 S8 PIN DESCRIPTIONS PIN NAME NO. I/O VIN 1 I Supply voltage input VADJ 2 I Analog dimming input VREG5 3 O Internal linear regulator 5V output HVM1, 2, 3, 4 4, 35, 36, 37 IO DC/DC feedback interface for thermal control. HVM4 is also used to set LED short detection threshold during 4CH and 8CH HVM modes (see the Flexible Configurations of the iHVM section). CTRL1, 2, 3, 4 5, 6, 33, 34 I Parallel PWM input control interface. High turns on corresponding channels. Configuration depends on the HVM mode. 7 I High enables driver control from CTRL1 to CTRL4. Low disables driver control from CTRL inputs D1 to D8 8, 11, 14, 17, 22, 25, 28, 31 I External FET drain node sense voltage input G1 to G8 9, 12, 15, 18, 21, 24, 27, 30 IO S1 to S8 10, 13, 16, 19, 20, 23, 26, 29 I External FET source node sense voltage input EN DESCRIPTION External FET gate driver output XFLT 32 O Fault detection notifying buffer output (open drain) GND 38 -- Common ground Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 5 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN DC/DC 1 DC/DC 2 DC/DC 3 DC/DC 4 HVM Configuration TLC5960 HVM1 HVM1 (Ch1, Ch2) HVM Fault Detection HVM2 HVM2 (Ch3, Ch4) Driver Control HVM3 HVM3 (Ch5, Ch6) Phase Delay HVM4 HVM4 (Ch7, Ch8) HVM Fault Detection Driver Control EN PWM Control Logic Channel 1 CTRL1 PWM1 CTRL1 (Ch1, Ch2) HVM Fault Detection CTRL2 PWM2 CTRL2 (Ch3, Ch4) Driver Control CTRL3 PWM3 CTRL3 (Ch5, Ch6) Phase Delay CTRL4 PWM4 CTRL4 (Ch7, Ch8) HVM Fault Detection Driver Control VREF Channel 2 XFLT Buffer HVM Fault Detection Driver Control VREF Channel 3 VIN VREG5 LDO Regulator HVM Fault Detection Driver Control VREF Channel 4 Thermal Shutdown VREF VADJ 0V to 1.4V Analog Input Buffer HVM Fault Detection Driver Control VREF Channel 5 HVM Fault Detection Driver Control GND Phase Delay D3 S3 D4 S4 D5 G5 Driver VREF Channel 6 S5 D6 G6 Driver VREF Channel 7 S6 D7 G7 Driver VREF Phase Delay S2 G4 Driver Phase Delay D2 G3 Driver Phase Delay S1 G2 Driver Phase Delay XFLT G1 Driver Phase Delay D1 Channel 8 S7 D8 G8 Driver VREF S8 Figure 1. Configuration with Four PWM Inputs and Four DC/DC Converters 6 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com VIN SBVS147 - SEPTEMBER 2010 DC/DC 1 DC/DC 2 HVM Configuration HVM1 HVM2 HVM1 (Ch1, Ch2, Ch5, Ch6) HVM Fault Detection Driver Control 4CH Mode VREG5 TLC5960 HVM3 HVM4 HVM2 (Ch3, Ch4, Ch7, Ch8) HVM Fault Detection PWM Control Logic CTRL1 PWM1 VIN CTRL2 CTRL1 (Ch1, Ch2, Ch5, Ch6) CTRL3 PWM2 CTRL4 VREF Channel 2 HVM Fault Detection Driver Control VREF Channel 3 HVM Fault Detection Driver Control VREF Channel 4 XFLT XFLT Buffer HVM Fault Detection Driver Control VREF Channel 5 VIN VREG5 LDO Regulator HVM Fault Detection Driver Control VREF Channel 6 Thermal Shutdown VREF VADJ 0V to 1.4V Analog Input Buffer HVM Fault Detection Driver Control VREF HVM Fault Detection Driver Control GND Channel 7 Phase Delay D4 S4 D5 S5 D6 S6 D7 G7 Driver VREF Phase Delay S3 G6 Driver Phase Delay D3 G5 Driver Phase Delay S2 G4 Driver Phase Delay D2 G3 Driver Phase Delay CTRL2 (Ch3, Ch4, Ch7, Ch8) S1 G2 Driver Phase Delay D1 G1 Driver Phase Delay Driver Control EN Channel 1 Channel 8 S7 D8 G8 Driver VREF S8 Figure 2. Configuration with Two PWM Inputs and Two DC/DC Converters Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 7 TLC5960 SBVS147 - SEPTEMBER 2010 VIN www.ti.com DC/DC HVM Configuration HVM1 HVM2 8CH Mode VREG5 HVM3 TLC5960 HVM Fault Detection HVM1 (Ch1, Ch2, Ch3, Ch4, Ch5, Ch6, Ch7, Ch8) Driver Control Driver Control EN PWM Control Logic CTRL1 PWM1 VIN CTRL2 CTRL3 VIN HVM Fault Detection CTRL1 (Ch1, Ch2, Ch3, Ch4, Ch5, Ch6, Ch7, Ch8) Driver Control Channel 2 Driver Control VREF Channel 3 XFLT XFLT Buffer HVM Fault Detection Driver Control VREF Channel 4 VIN VREG5 LDO Regulator HVM Fault Detection Driver Control VREF Channel 5 Thermal Shutdown VREF VADJ 0V to 1.4V Analog Input Buffer HVM Fault Detection Driver Control VREF Channel 6 HVM Fault Detection Driver Control GND Phase Delay S3 D4 S4 D5 S5 D6 G6 Driver VREF Channel 7 S6 D7 G7 Driver VREF Phase Delay D3 G5 Driver Phase Delay S2 G4 Driver Phase Delay D2 G3 Driver Phase Delay S1 G2 Driver Phase Delay HVM Fault Detection CTRL4 VREF Phase Delay D1 G1 Driver Phase Delay HVM Fault Detection HVM4 Channel 1 Channel 8 S7 D8 G8 Driver VREF S8 Figure 3. Configuration with One PWM Input and One DC/DC Converter 8 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 MEASUREMENT CIRCUIT VLED 5V (1) Gn FET Test Point Sn RS 12W (1) Suggested FET: Sanyo MCH6440. Figure 4. Constant Current Switching Speed (tSW) Measurement Circuit Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 9 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS ANALOG DIMMING LINEARITY (ILED vs VADJ) PWM DIMMING LINEARITY (ILED vs CTRL PULSE DURATION) 1000 160 TA = +25C VIN = 24V 140 100 100 ILED (mA) ILED (mA) 120 80 60 TA = +25C VIN = 24V RS = 5W PWM = 100% duty 40 20 10 1 0.1 VADJ = 1.2V (100%) VADJ = 0.6V (50%) VADJ = 0.12V (10%) 0.01 0 0 0.2 0.4 0.6 0.8 VADJ (V) 1.0 1.2 0.1 1.4 1 10 PWM Dimming Duty at 320Hz (%) Figure 5. Figure 6. TYPICAL TURN-ON WAVEFORM TYPICAL TURN-OFF WAVEFORM TA = +25C VIN = 24V ILED1 (50mA) 2ms TA = +25C VIN = 24V ILED1 (50mA) ILED1 (0mA) ILED1 (0mA) 2ms CTRL1 CTRL1 Time (2ms/div) Time (2ms/div) Figure 7. Figure 8. LDO LOAD REGULATION LDO LINE REGULATION 5.25 5.25 TA = +25C VIN = 24V 5.15 5.15 5.10 5.10 5.05 5.00 VREG5 4.95 5.05 5.00 4.95 4.90 4.90 4.85 4.85 4.80 4.80 4.75 TA = +25C Load = 25mA 5.20 VREG5 (V) VREG5 (V) 5.20 VREG5 4.75 0 5 10 15 20 Load Current (mA) 25 30 10 Figure 9. 10 100 12 14 16 18 20 VIN (V) 22 24 26 28 Figure 10. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) VIN SUPPLY CURRENT DURING SHUTDOWN MODE (VIN < VPOR) GATE OUTPUT VOLTAGE LINE REGULATION 40 5.0 35 VGn 4.0 30 3.5 25 3.0 IIN (mA) Gn Output Voltage (V) TA = +25C EN = Low TA = +25C 4.5 2.5 2.0 20 15 IIN 1.5 10 1.0 5 0.5 0 0 10 12 14 16 18 20 VIN (V) 22 24 26 0 28 1.0 2.0 Figure 11. 3.0 4.0 VIN (V) 5.0 6.0 7.0 Figure 12. VIN SUPPLY CURRENT WHEN CHANNELS ARE ENABLED 16 TA = +25C VIN = 24V 14 12 IIN (mA) 10 8 6 4 2 CTRL1-4 = High (EN = High) CTRL1-3 = High (EN = High) CTRL1,2 = High (EN = High) CTRL1 = High (EN = High) EN = High EN = Low 0 Figure 13. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 11 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com FUNCTIONAL DESCRIPTION CONTROLLING THE EXTERNAL-FET GATE DRIVERS The eight-channel TLC5960 is equipped with eight external-FET gate drivers (one per channel) to drive FETs in series with the LED strings. In normal mode, a CTRL input enables/disables the corresponding two-channel drivers. That is, CTRL1 turns on the channel 1 (ch1) and ch2 gate drive outputs (G1 and G2) sequentially. A total of four parallel inputs (CTRL1 to CTRL4) are used to provide eight channels of PWM control. EN high enables this CTRLn PWM interface, and EN low shuts down all channels simultaneously. The control interface logic truth table is shown in Table 1. Table 1. Output Channel Control Truth Table (Normal Mode) EN CTRL1 Low High CTRL2 CTRL3 CTRL4 OUTPUT STATUS All channels disabled X X X X Low Low Low Low All channels disabled High Low Low Low Ch1 (G1)/Ch2 (G2) enabled Low High Low Low Ch3 (G3)/Ch4 (G4) enabled Low Low High Low Ch5 (G5)/Ch6 (G6) enabled Low Low Low High Ch7 (G7)/Ch8 (G8) enabled High High High High All channels enabled Figure 14 shows the on and off timing of the control input CTRL1 and the related gate driver outputs of ch1 and ch2. The TLC5960 integrates an internal phase shift function between the channels; therefore, the G1 and G2 outputs on-off timing have an internal unit delay time (tD). Refer to the Built-In Phase Shift and PWM Input Minimum On-Time Requirement section for more details. The EN signal polarity change, on the other hand, immediately applies to all channel outputs. tWL1 tSU0 EN tH0 tWL0 tWH1 tWH0 CTRL1 tSW G1 tSW OFF ON OFF tSW G2 OFF ON OFF ON OFF ON tSW OFF ON tD OFF tD ON OFF ON tD Figure 14. Gate Driver On and Off Timing Sequence 12 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 CONSTANT CURRENT CONTROL: PWM AND ANALOG DIMMING D1 VREG5 ILED The dedicated FET gate drivers help regulate the constant currents on the LED strings, as shown in Figure 15. A sense resistor (RS) sets the constant current value on the corresponding LED channel. The gate driver regulates this source node (Sn) voltage to be the same as the internal reference voltage (VREF). The default setting of VREF is 0.6V. This internal reference voltage can be configured through the external input, VADJ. This function can be used as a linear or analog dimming function for all LED strings simultaneously. As shown in Figure 16, the TLC5960 uses halved VADJ input as the internal VREF. If VADJ is greater than 1.4V, the internal VREF falls back to the typical 0.6V (100% analog dimming). Here, 1.4V is a positive-going threshold and is designed to have 100mV negative-going hysteresis as a noise margin. The VREF fallback mechanism is also applied in case VADJ = open. The analog dimming linearity range is specified from 10% to 100%. G1 On/Off Control S1 RS VREF 0.6V TYP VADJ Channel 1 Figure 15. Constant Current Drive Amplifier 0.7 Internal VREF (V) 0.6 10% to 100% Dimming Area 0.06 0 0.12 1.2 1.4 VADJ (V) Figure 16. VADJ vs Internal Reference Voltage The constant current value in the LED strings is set using the following equations: VADJ/2 If VADJ < 1.4V, then ILED = RS If VADJ > 1.4V, then ILED = (1) 0.6V RS (2) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 13 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com CHANNEL-TO-CHANNEL CONSTANT CURRENT MISMATCH RATING The current mismatch rate between channels is primarily induced by the external sense resistor mismatch rating. Additionally, the TLC5960 driver input offset contributes to the current mismatch rating between the channels. The gate drive amplifier offset (VOFFSET) is specified in the Electrical Characteristics. VREG5 ILED D1 G1 VREF 0.6V S1 VS + DVS RS + DRS Channel 1 Figure 17. Channel-to-Channel Mismatch Factors Figure 17 shows the mismatch contributing factors on this system. RS represents the resistor mismatch. VS denotes the contribution of the gate amplifier input equivalent offset, VOFFSET. Using these two external and internal error factors, the total mismatch rate is estimated in Equation 3. In this case, with a 1% accurate RS used, the total current mismatch value is estimated within 1.9%. ILED = VS + DVS RS + DRS DILED = 14 VS DVS RS VS VS RS - 1+ DVS VS - DRS RS DRS RS (3) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 BUILT-IN PHASE SHIFT AND PWM INPUT MINIMUM ON-TIME REQUIREMENT The TLC5960 is equipped with a built-in phase shift function to prevent noise from affecting all eight channels. The gate drive timing has a sequential delay time between each combination of channels. This built-in delay time (tD) is typically 13s, and consists of four internal clock cycles. Figure 18 describes the phase shift sequence. G1 turns on immediately after the CTRL1 input goes high. After the unit delay of tD, the G2 output powers on. On the other hand, G3, which is driven by control input CTRL2, already has twice the unit delay from the turn-on timing of CTRL2. G4 turns on after G3 with a sequential unit delay. CTRL3 turns on G5 and G6; these outputs have a built-in (tD x 4) and (tD x 5) phase shift, respectively. Finally, CTRL4 turns on G7 and G8; these outputs have built-in (tD x 6) and (tD x 7) phase shift, respectively, from CTRL4 on-timing. This description is for the HVM 2CH mode; however, the phase shift function is available in all of the HVM modes. In 4CH HVM mode, CTRL1 drives G1, G2, G6, and G7. These output delays are fixed at 0, tD, (tD x 5), and (tD x 6), respectively. CTRL3 turns on the other four channels, G3, G4, G7, and G8. These phase shifts are also fixed at (tD x 2), (tD x 3), (tD x 6), and (tD x 7), respectively. The phase shift function works in the same manner in the 8CH HVM mode. The internal clock cycle is equal to the minimum on-time of the TLC5960 gate driver. The gate drivers are designed to drive the external FET turn-on and turn-off within 1s for both rise and fall times, typically. Therefore, the internal clock cycle of 3.2s defines the minimum on-time pulse width on the LED strings in the TLC5960-based system. 3.2ms Minimum On time Internal CLK CTRL1 CTRL2 CTRL3 CTRL4 G1 tD = 3.2ms 4 13ms G2 G3 tD 2 26ms G4 tD G5 tD 4 52ms tD G6 tD 6 81ms G7 tD G8 Figure 18. Built-In Phase Shift Output Sequence Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 15 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com PROTECTION FEATURES The TLC5960 provides protection features to keep the entire system safe. The TLC5960 internal error recognition routine is triggered when the detection comparator detects an abnormal system status. After the error recognition, the TLC5960 first shuts off the corresponding error channel and separates the channel from the other normal operating channels; then, the TLC5960 indicates the error status through the XFLT buffer drive. In cases of LED failure, the TLC5960 provides protection for both the LED open detection (LOD) and LED short detection (LSD). Also, if the external FET fails, the FET open detection (FOD) and FET short detection (FSD) features are provided, as shown in Figure 19. The error status can be easily identified by monitoring the XFLT output. The XFLT output drive is designed to toggle with a different duty ratio, each with a fixed frequency corresponding to the failure mode. The XFLT toggle frequency is approximately 80kHz. The duty ratio is 25%, 50%, 75% ,and 100% for each of the respective failure modes: LOD, LSD, FOD, and FSD. Table 2 summarizes the indications and the protective actions to take for all protection modes. The appropriate LED short detection (LSD) threshold can be selected in 4/8CH HVM mode through the HVM4 input voltage. Other detection thresholds are automatically determined internally by the TLC5960. VLED TLC5960 LED Short (LSD) Drain Node Failure Detectors XFLT LED Open (LOD) Dn Failure Recognition Logic Routine Sn FET Short (FSD) FET Open (FOD) Source Node Failure Detectors VADJ Figure 19. Protection Features on the TLC5960 Driver System Table 2. Protection Feature Summary (1) (2) 16 PROTECTION FUNCTION DETECTION THRESHOLD MONITOR LATCH INDICATION PROTECTIVE ACTION RECOVERY CONDITION LED open detection (LOD) Dn < 0.8V During on Yes XFLT = low 25% duty Channel off LED short detection (LSD) See Note (1) During on Yes XFLT = low 50% duty Channel off FET open detection (FOD) Sn < VADJ/4 (VADJ < 1.4V) During on Yes XFLT = low 75% duty Channel off FET short detection (FSD) (2) Sn > 0.9V Continuous No XFLT = low 100% duty N/A Sn < 0.7V Thermal shutdown (TSD) Temp > +160C Continuous Yes XFLT = low 100% duty VREG5 off, all channels off VIN < VPOR or toggle EN high, low, high VIN < VPOR or toggle EN high, low, high Detection threshold is Dn > 19.2V for HVM 2CH mode, and Dn > 8 x HVM4(V) for 4/8CH mode. In the case of FSD, the TLC5960 has already driven Gn to a lower level so that the failed channel is shut off and no additional protection is needed. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 FAILURE MODE DETECTION AND RELEASE TIMING When the FET is on, the TLC5960 protects the system by monitoring the triggers of the LOD, LSD, and FOD detectors. After the LED channel is on (EN = CTRLn = high), the TLC5960 waits for a detection time of tDET1 before capturing the drain and source node information on the external FETs. In case the error comparator(s) detect an abnormal status, the TLC5960 starts to determine whether this state is a true error condition or not. If the status is determined as an error in system with a processing time of tDET2, the TLC5960 shuts off the corresponding channel(s), separates it from the operating channels, and the XFLT notification sequence is started. After the abnormal situation is recovered, toggling of the EN pin (high-to-low-to-high) reverts the TLC5960 to the default operating status. Otherwise, the device remains in the error status until VIN is less than VPOR. The detection time (tDET1) and error processing time (tDET2) are both set to 13s. Figure 20 shows the case of CTRL1, D1, and D2. EN CTRL1 tDET = tDET1 + tDET2 Internal CLK Error Status Release tDET1 D1 LOD, LSD, FOD Check LED On with No Error Outputs tD D2 tDET1 LOD, LSD, FOD Check LED On with No Error Outputs tD tDET1 LED Open Detected LOD, LSD, FOD Check tDET1 LED Remains Off when Protected tDET2 XFLT LED Open Recovery XFLT Error Notification Figure 20. LOD, LSD, and FOD Detection and Error Status Release Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 17 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com LED OPEN DETECTION (LOD) AND LED SHORT DETECTION (LSD) The TLC5960 senses the drain node of the external FET when the FET is on, as shown in Figure 21. When the LED is open, the drain voltage falls below the default detection level (0.8V). The LED short detection (LSD) triggers at an abnormal overvoltage detection threshold of 19.2V, typically. This LSD detection threshold can be redefined in the 4CH and 8CH HVM modes according to the various system configurations. The threshold is defined by Equation 4 and Equation 5. For example, when detecting two shorted LEDs on an 15-LED string, this voltage range can be set to ~10V (HVM4 input = 1.25V) in 4CH and 8CH HVM modes. This ~10V voltage setting can be calculated by multiplying VF by the two failed LEDs (~3.5V x 2 = 7V) and adding the result to the normal regulating Dn voltage range (1.6V to 2.6V). In the case of LDO and LSD, the TLC5960 shuts off the failed LED string(s) and automatically separates the failed string(s) from the operating strings. For 2CH HVM mode: VLSD = 19.2V (4) For 4/8CH HVM modes: VLSD = 8 HVM4 (V) (5) VLED LED Short (LSD) Error Detection Comparator Failure Recognition Logic Routine LED Open (LOD) Dn EN HVM4 (4CH, 8CH HVM Modes) Comparison Voltage: LED Short = 19.2V typ LED Open = 0.8V typ Figure 21. TLC5960 Drain Terminals Sensing to Protect LED Failure 18 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 FET OPEN DETECTION (FOD) AND FET SHORT DETECTION (FSD) The TLC5960 monitors the source terminal of the FETs to detect any abnormal status of the external FETs, as shown in Figure 22. In case a FET is open (FOD), the source node stays at a lower level, even if the TLC5960 drives the gate voltage higher and higher. To detect this error status, the default threshold is set to 0.3V. The TLC5960 automatically adjusts the detection threshold internally, as described in Equation 6 and Equation 7, depending on the analog dimming setting. VADJ If VADJ < 1.4V, then VFOD = (V) 4 (6) If VADJ > 1.4V, then VFOD = 0.3V (7) The FET short detection (FSD) detects overvoltage sensed at the source node. This failure mode usually implies that the overcurrent is in the entire system and it may induce a critical situation because of potential thermal-related issues. The TLC5960 always monitors the FSD threshold to keep the entire system safe. The detection threshold is typically set at 0.9V. In the case of FOD, the TLC5960 shuts off the failed LED string(s) and automatically separates the failed string(s) from the operating strings. In the case of FSD, the TLC5960 normal function already shut off the failed LED string(s), and then the TLC5960 delivers the failure notification signal through the XFLT output buffer. If the failure phenomenon is removed, the FSD is automatically recovered, unlike LOD, LSD, and FOD, as shown in Table 2. VLED Error Detection Comparator Failure Recognition Logic Routine Sn FET Open (FOD) FET Short (FSD) EN VADJ Comparison Voltage: FET Short = 0.9V typ FET Open = 0.3V typ Figure 22. TLC5960 Source Terminal Sensing to Protect FET Failure Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 19 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com THERMAL SHUTDOWN The TLC5960 includes integrated internal temperature sensors for providing thermal shutdown protection. If an over-temperature state is detected, the TLC5960 automatically shuts down all the functions, including the internal low-dropout regulator (LDO). This status is latched until VIN < VPOR, or the EN input signal toggles from high to low to high. POWER-ON RESET (POR) The TLC5960 is equipped with internal power-on reset circuitry. When VIN < 7.0V, the remaining circuit blocks are all locked to stay in standby mode. This function is also called undervoltage lockout (UVLO). The specifications for VPOR and VPORHYS are listed in the Electrical Characteristics. HEADROOM VOLTAGE MONITOR FEEDBACKS (iHVM) The TLC5960 provides an intelligent feedback mechanism of the headroom voltage information to automatically adjust the dc/dc converter output voltage. Up to four dc/dc converter outputs can be optimized using the TLC5960 iHVM buffers; the output levels are automatically adjusted through the internal iHVM mechanism. Figure 23 shows a basic configuration of one dc/dc converter for a two-channel output (HVM 2CH mode). Only one additional external resistor is required to modify the dc/dc converter output voltage. VLED DC/DC Converter R1 VIN ILED R2 VREF R3 MN1 VHVM HVM1 D1 G1 S1 MN2 D2 G2 S2 HVM Detection Channel 1 Buffer HVM Logic Calculation Routine HVM Detection Channel 2 Q D C Sampling Clock TLC5960 Figure 23. Headroom Voltage Monitor Feedback Mechanism 20 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 SETTING THE DC/DC CONVERTER OUTPUT RANGE The given VLED voltage setting by the iHVM system is shown in Equation 8. VREF is the internal reference voltage of the dc/dc converter. VHVM is the regulated voltage output from the HVM buffer, which outputs 0.7V initially and is automatically adjusted by the internal iHVM mechanism. R1 + R2 R1 VLED = VREF + (VREF - VHVM) R2 R3 (8) The voltage range for VHVM is 0.14V (min) to 1.25V (max) with a typical value of 0.7V. Given these values, the available VLED range with iHVM is calculated as shown in Equation 9 through Equation 11: R1 + R2 R1 VLEDMIN = VREF + (VREF - 1.25) R2 R3 (9) R1 + R2 R1 VLEDTYP = VREF + (VREF - 0.7) R2 R3 (10) R1 + R2 R1 VLEDMAX = VREF + (VREF - 0.14) R2 R3 (11) In this case, if VREF = 0.7V, R1 = 200k, R2 = 1k, and R3 = 20k, then the variable range on the dc/dc output, VLED, is 140V 6V. The appropriate VLED voltage range can easily be set by selecting the values of R1, R2, and R3. BASIC POWER DISSIPATION CONSIDERATIONS The most critical components for power consumption are the external FETs in the system. These components are critical because the forward voltage variance of all the LED strings are concentrated in these components. For optimal system performance with the appropriate thermal dissipation, the LED selection and iHVM VLED range must be set accordingly. The iHVM VLED range should be determined from the VLED worst-case variance without turning off the LED strings. Here, the FET power dissipation rating (PFET) is defined as shown in Equation 12: PFET = (VD - 0.6) ILED (12) If the FET is supposed to tolerate 1W, then the VD should be 10.6V under worst-case conditions with a 100mA ILED setting. FLEXIBLE CONFIGURATIONS OF THE iHVM The TLC5960 provides flexible configurations for the dc/dc converter and LED driver channel count. By default, the TLC5960 has four PWM inputs, eight LED strings, and four dc/dc converter control outputs (2CH mode). In this case, the best thermal capability is provided with dc/dc peripherals overhead; see Figure 24. The TLC5960 provides drain node voltage control within the range of 1.6V to 2.6V on at least four out of eight channels. The upper-right side of Figure 24 illustrates this four-channel control capability that automatically minimizes the FET power dissipation. The TLC5960 integrates two other configuration modes: 4CH HVM mode and 8CH HVM mode. In these modes, the TLC5960 is capable of controlling the headroom voltage range in two out of the eight channels, or one out of eight channels. Also in these modes, the total VD variance that is coming from the LED VF variance is much larger than in 2CH mode, as shown in the upper-right side of Figure 25. If the LED components are not appropriately selected, only one LED string is well-controlled within the HVM range of 1.6V to 2.6V. It is more important to have a better selection criteria on LEDs instead of than less peripheral overhead in order to better handle the thermal rating. Application of voltage greater than 7.0V on CTRL2 drives the TLC5960 HVM mode into 4CH mode. CTRL1 and CTRL3 PWM inputs are used to control Ch1, Ch2, Ch5, Ch6 and Ch3, Ch4, Ch7, Ch8, respectively. Two HVM outputs are used to control two dc/dc converter output voltages. If voltage greater than 7.0V is placed on both CTRL2 and CTRL4, the TLC5960 HVM logic goes into 8CH mode. CTRL1 controls all of the LED string outputs and the HVM output is consolidated into one HVM1 output. Table 3 summarizes the HVM mode configurations. The applicable voltage on CTRL2 and CTRL4 is defined up to the VIN level. It is recommended to tie CTRL2 and/or CTRL4 to VIN through a 10k resistor. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 21 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com Ch5 DC/DC4 VD (V) VLED4 DC/DC3 VLED3 DC/DC2 Ch2 VDREF - 1.6 VLED1 Ch7 Ch4 Ch8 Ch3 VDREF + 2.6 VLED2 DC/DC1 Ch1 Ch6 RHVM [1:4] VHVM [1:4] HVM[1:4] D1 G1 TLC5960 S1 2CH Mode D2 G2 CTRL1 S2 8 LED CTRL2 CTRL3 CTRL4 D1 G1 D7 G2 S1 Strings D8 G8 S8 EN D2 G7 G8 S2 RS D8 S7 RS S8 RS RS Figure 24. HVM 2CH Mode Typical Configuration Ch4 VD (V) Ch3 Ch1 Ch7 Ch6 Ch8 VDREF + 2.6 VLED DC/DC Ch5 VDREF - 1.6 Ch2 RHVM1 VHVM1 HVM1 D1 G1 TLC5960 S1 8CH Mode D2 G2 CTRL1 S2 8 LED CTRL2 CTRL3 CTRL4 D1 G1 Strings EN D2 D7 G2 S1 D8 G8 S8 G7 S2 RS D8 G8 S7 RS S8 RS RS Figure 25. HVM 8CH Mode Typical Configuration On the 4CH mode and 8CH mode, the TLC5960 LED-Short-Detection threshold voltage can be adjusted by setting the external input voltage to the HVM4 pin. The threshold calculation is shown in Equation 5. Table 3. HVM Configuration Modes IN OUT HVM LOGIC MODE CTRL1 CTRL2 CTRL3 CTRL4 HVM1 HVM2 HVM3 HVM4 2CH Ch1, 2 Ch3, 4 Ch5, 6 Ch7, 8 Ch1, 2 Ch3, 4 Ch5, 6 Ch7, 8 4CH Ch1, 2, 5, 6 > 7.0V Ch3, 4, 7, 8 GND Ch1, 2, 5, 6 Ch3, 4, 7, 8 N/A REFLSD (Input) 8CH Ch1 to Ch8 > 7.0V GND > 7.0V Ch1 to Ch8 N/A N/A REFLSD (Input) 22 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 APPLICATION INFORMATION CASCADING SYSTEM USING iHVM iHVM provides flexibility to the application configuration with a minimum of external components. Figure 26 shows an example for using a diode-OR to configure multiple iHVM controllers. This configuration can be applicable to as many controllers as a daisy-chain configuration allows. Care must be taken regarding the available HVM voltage range affected by the dc/dc converter reference voltage shown in Equation 13 through Equation 16. For example, the TPS40210 internal reference voltage is 700mV. In case of this combination, the diode-OR operation achieves the minimum voltage of the HVM buffer outputs, and the VLED adjustable range is limited to the upper-half region compared to the normal configuration. VLED DC/DC R1 DH2 HVM2 R3 VFB HVM1 DH1 R2 VREF iHVM Process Core D2 D1 G2 G1 S2 S1 RS RS Figure 26. iHVM System Cascade Configuration through a Diode-OR VLED = R1 + R2 R2 VREF + R1 R3 (VREF - VF - VH) Where: VH = Min(VH1,VH2) VREF - VF - VH 0 VF = forward voltage of DH1 and DH2 VLEDMIN = VLEDTYP = VLEDMAX = R1 + R2 R2 R1 + R2 R2 R1 + R2 R2 VREF + VREF + VREF + R1 R3 R1 R3 R1 R3 (13) (VREF - VF - 1.25) (14) (VREF - VF - 0.7) (15) (VREF - VF - 0.14) (16) In this case, if VREF = 0.7V, R1 = 200k, R2 = 1k, and R3 = 20k, then the diode forward voltage of VF = 0.3V and the available VLED output range would be 138V to 143V. Refer to Equation 9 to compare with normal conditions. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 23 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com UNUSED DRIVER OUTPUT CONNECTION Figure 27 shows the recommended connection when not all eight channels are needed. Basically, Dn should be connected to the adjacent pin of the corresponding D terminal in order to prevent the TLC5960 protection routine from activating these unneeded output pins. The Gn and Sn pins should be tied together. VLED TLC5960 D1 G1 S1 D2 RS G2 S2 Figure 27. Unused Driver Output Recommended Connection BIPOLAR DRIVE CAPABILITY The TLC5960 integrated driver is designed to work with not only FETs, but also with bipolar devices, as shown in Figure 28. In this case, the amount of the base current must be considered when you define the LED current. The amount of base current is deducted from the LED current, based on Equation 17. The output current capability of Gn is specified as IOH in the Electrical Characteristics. V ILED = REF - IB RS (17) D1 G1 ILED VREG5 IB VREF 0.6V TYP RS Channel 1 IE S1 Figure 28. Bipolar Output Capability 24 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 iHVM: STABILITY ANALYSIS ON CONVENTIONAL SYSTEM Figure 29 shows a dual loop, a conventional dc/dc output topology adjustment enabled by the information of the drain node feedback mechanism. This system basically consists of two feedback loops. The primary feedback loop is a voltage feedback loop for the dc/dc converter. The additional secondary feedback loop is established to integrate the cathode node information of the LED string to optimize thermal dissipation regarding LED string voltage change as a result of variance of LED component forward voltage. DC/DC + LED Driver VLED DC/DC R1 Primary Loop COUT R2 Secondary Loop Error Amp VREF2 ILED = VREF2 VREF RS VREF RS Figure 29. Conventional Drain Information Feedback Loop Structure In order to keep this total system stable, the circuit constants are appropriately set so that they do not conflict with these feedback loops. The primary loop frequency response must be set faster than the secondary loop; typically, a 10x faster setting is known to generate a stable system. The conventional approach restricts total system performance on the following: 1. The LED drive dimming speed must be as slow as the secondary loop response; or, 2. If faster dimming LED switching is needed, then the dc/dc output capacitance must be larger (sometimes over 1000F) in order to keep the VLED line stable enough, with tight LED forward voltage selection criteria to maintain required thermal performance. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 25 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com Figure 30(a) shows a typical switching of the on-off sequence in this conventional system. Here, VLED (the output voltage of the dc/dc converter) starts from a higher point (VINIT). As the drain node information feedback loops, the VLED is driven lower to the appropriate voltage level (VOPT) for lower power consumption while maintaining the constant current regulation. After the signal feedback, the VLED transient speed is limited by the primary loop response speed and the slowest timing in this sequence is normally the falling edge of VLED. The maximum speed of the falling time (tF) is calculated in Equation 18, and only the constant current of ILED is available to lower the VLED in an LED backlight system. C tF = OUT (VINIT - VHVM) ILED (18) VLED (V) tF tR VINIT VOPT Time (s) (a) Typical Setting with Appropriate LED Switching VLED (V) VINIT VOPT Time (s) (b) Faster LED Switching: Not Enough Settling Time VLED (V) VINIT VOPT Time (s) (c) Faster LED Switching with Large COUT: Tight LED Selection Needed Figure 30. VLED Voltage Regulation Sequence on Conventional System In this case, with COUT = 100F, ILED = 100mA, VINIT = 180V and VOPT = 155V, the maximum speed of tF is calculated as 25ms. This slower transient speed absolutely limits the LED switching speed. If maximum tF is 25ms, the fastest dimming cycle with a full dual-loop system advantage is limited to only 40Hz. If the LED switching speed is faster than that value, the VLED regulation voltage would appear as shown in Figure 30(b). HVM power saving is only achievable with one-fourth of the typical case (a). To solve this situation on a conventional system, COUT can sometimes be increased to keep the voltage stable. Figure 30(c) shows that switching waveform. These possible power-savings are achieved by lowering VINIT using tightly selected LEDs in relation to its forward voltage specification. 26 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 TLC5960 www.ti.com SBVS147 - SEPTEMBER 2010 STABILITY ANALYSIS OF PROPOSED iHVM SYSTEM Figure 31 shows the feedback system with the proposed iHVM control mechanism. The biggest difference (and advantage) compared to a conventional system is that the iHVM processing core controls the secondary loop. With this system, there are no limitations on the primary loop and secondary loop settings. The FETs drain node voltage information is processed easily and can be automatically adjusted to fit the primary loop feedback response, as long as the primary loop unity gain frequency is approximately 1kHz. See Equation 8 for the iHVM output voltage setting calculation. The second term is the variable portion of VLED output voltage and is well-regulated by the iHVM mechanism. VLED DC/DC Primary Loop R1 COUT Secondary Loop ISINK HVM1 VFB VREF iHVM Process Core R3 ISOURCE D1 G1 R2 S1 TLC5960 RS Figure 31. iHVM Loop Structure Here, focusing on the appropriate minimal time range, the only condition required to maintain the total iHVM feedback system stability is shown in Equation 19. R1 I dv(iHVM) < LED dt(iHVM) COUT R3 (19) The left-hand term describes the value of the output voltage range by iHVM during the minimal time of dt(iHVM). Therefore, in an iHVM system, the slowest response in the entire system can be designated by the values of ILED and COUT, as long as the primary system unity gain frequency is set at a minimum of 1kHz. Here, the derivation of the iHVM circuit response is already known as 10V/s. The resulting equation to keep the entire iHVM system stable is shown in Equation 20. I R3 COUT < LED 10V/s R1 Where the unity gain frequency of the primary loop > 1kHz. (20) In this case, ILED = 100mA, R1 = 400k, and R3 = 40k, COUT should be less than 1000F to retain the transient response to achieve 100% power saving by iHVM caused by LED VF variance. In a typical application, this value is large enough. Therefore, we can conclude that the only condition required to keep iHVM stable is to set the primary feedback loop unity-gain frequency greater than 1kHz with a minimum amount of COUT (typically 100F to 300F, depending on the required LED current value) to keep the VLED line stable when the LED is switching. Refer to the dc/dc controller manual for setting the appropriate minimum output capacitance value. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 27 TLC5960 SBVS147 - SEPTEMBER 2010 www.ti.com Figure 32 shows the iHVM transient response. Only the first cycle of the HVM cycle is needed to set the appropriate voltage for the VLED corresponding to the LED strings total VF. Therefore, the first tF should be a similar transient with conventional system; however, from the next cycle, the intelligent iHVM mechanism reuses the once-settled value. As shown in the results, the second falling edge can be much faster than the first cycle, and almost zero transient power consumption is achievable in Figure 32(a). VLED (V) tF tR tF VINIT VOPT Time (s) (a) VLED Typical Transient Response on iHVM system VLED (V) VINIT VOPT Time (s) (b) Very Low Transient Loss on iHVM system with Fast Switching Figure 32. Transient Response of the iHVM-Based System In addition to this power saving, faster LED switching speeds can be set up to 250kHz. The transient response in this case is shown in Figure 32(b). The power-saving iHVM mechanism is designed to work perfectly with that faster switching speed, as well. Figure 33 shows the application evaluation results of an iHVM system. As the dc/dc portion, the TPS40210 SEPIC configuration (supply voltage = 170V, VLED ~150V) is employed. 48 LEDs are series connected and RS is set to 12 in order to achieve a 50mA constant current. The iHVM system works well to keep the once-settled VLED voltage well-regulated with a constant current value. VLED (150V 200mV)) ILED (50mA) 2ms ILED (0mA) Time (2ms/div) Figure 33. Switching Characteristics for 1% PWM Dimming on 240Hz 28 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): TLC5960 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLC5960DA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples TLC5960DAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC5960DAR Package Package Pins Type Drawing TSSOP DA 38 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5960DAR TSSOP DA 38 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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