AD737
Rev. H | Page 13 of 24
AVERAGE EO = EO
DC ERROR, OUTPUT RIPPLE, AND
AVERAGING ERROR
Figure 25 shows the typical output waveform of the AD737 with
a sine wave input voltage applied. As with all real-world devices,
the ideal output of VOUT = VIN is never exactly achieved; instead,
the output contains both a dc and an ac error component.
DC ERROR = EO – EO (IDEAL)
EO
IDEAL
EO
DOUBLE-FREQUENCY
RIPPLE
TIME
00828-026
Figure 25. Output Waveform for Sine Wave Input Voltage
As shown, the dc error is the difference between the average of
the output signal (when all the ripple in the output has been
removed by external filtering) and the ideal dc output. The dc
error component is, therefore, set solely by the value of the
averaging capacitor used—no amount of post filtering (using a
very large postfiltering capacitor, CF) allows the output voltage
to equal its ideal value. The ac error component, an output
ripple, can be easily removed using a large enough CF.
In most cases, the combined magnitudes of the dc and ac error
components must be considered when selecting appropriate
values for CAV and CF capacitors. This combined error, repre-
senting the maximum uncertainty of the measurement, is
termed the averaging error and is equal to the peak value of the
output ripple plus the dc error. As the input frequency increases,
both error components decrease rapidly. If the input frequency
doubles, the dc error and ripple reduce to one-quarter and
one-half of their original values, respectively, and rapidly
become insignificant.
AC MEASUREMENT ACCURACY AND
CREST FACTOR
The crest factor of the input waveform is often overlooked when
determining the accuracy of an ac measurement. Crest factor is
defined as the ratio of the peak signal amplitude to the rms
amplitude (crest factor = VPEAK/V rms). Many common
waveforms, such as sine and triangle waves, have relatively low
crest factors (≥2). Other waveforms, such as low duty cycle
pulse trains and SCR waveforms, have high crest factors. These
types of waveforms require a long averaging time constant to
average out the long time periods between pulses. Figure 10
shows the additional error vs. the crest factor of the AD737 for
various values of CAV.
CALCULATING SETTLING TIME
Figure 18 can be used to closely approximate the time required
for the AD737 to settle when its input level is reduced in
amplitude. The net time required for the rms converter to settle
is the difference between two times extracted from the graph:
the initial time minus the final settling time. As an example,
consider the following conditions: a 33 µF averaging capacitor,
an initial rms input level of 100 mV, and a final (reduced) input
level of 1 mV. From Figure 18, the initial settling time (where
the 100 mV line intersects the 33 µF line) is approximately
80 ms. The settling time corresponding to the new or final input
level of 1 mV is approximately 8 seconds. Therefore, the net
time for the circuit to settle to its new value is 8 seconds minus
80 ms, which is 7.92 seconds.
Note that, because of the inherent smoothness of the decay
characteristic of a capacitor/diode combination, this is the total
settling time to the final value (not the settling time to 1%,
0.1%, and so on, of the final value). Also, this graph provides
the worst-case settling time because the AD737 settles very
quickly with increasing input levels.
Table 5. Error Introduced by an Average Responding Circuit When Measuring Common Waveforms
Type of Waveform
1 V Peak Amplitude
Crest Factor
(VPEAK/V rms)
True RMS
Value (V)
Reading of an Average Responding Circuit Calibrated to
an RMS Sine Wave Value (V) Error (%)
Undistorted Sine Wave 1.414 0.707 0.707 0
Symmetrical Square Wave 1.00 1.00 1.11 11.0
Undistorted Triangle Wave 1.73 0.577 0.555 −3.8
Gaussian Noise (98% of
Peaks <1 V) 3 0.333 0.295 −11.4
Rectangular 2 0.5 0.278 −44
Pulse Train 10 0.1 0.011 −89
SCR Waveforms
50% Duty Cycle 2 0.495 0.354 −28
25% Duty Cycle 4.7 0.212 0.150 −30