®
1. General description
The DAC1617D1G0 is a high-speed 16-bit dual channel Digital-to-Analog Converter
(DAC) with selectable ×2, ×4 and ×8 interpolation filters. The device is optimized for
multi-carrier and broadband wireless transmitters at sample rates of up to 1 Gsps.
Supplied from a 3.3 V and a 1.8 V source, the DAC1617D1G0 integrates a differential
scalable output current up to 34 mA.
The Serial Peripheral Interface (SPI) provides full control of the DAC1617D1G0.
The DAC1617D1G0 integrates a Low Voltage Differential Signaling (LVDS) Double Data
Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR
interface accepts a multiplex input data stream such as interleaved or folded. An internal
LVDS input auto-calibration ensures the robustness and stability of the interface.
Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. A
40-bit Numerically Controlled Oscillator (NCO) sets the mixer frequency. High resolution
internal gain, phase and offset control provide outstanding image and Local Oscillator
(LO) signal rejection at the system analog modulator output.
An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at
the DAC output.
Multiple device synchronization allows synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
The DAC1617D1G0 includes a very low noise capacitor-free integrated Phase-Locked
Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.
The DAC1617D1G0 is available in an HVQFN72 package (10 mm ×10 mm).
DAC1617D1G0
Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8
interpolating
Rev. 4 — 12 December 2012 Product data sheet
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 2 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
2. Features and benefits
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communications: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Dual-channel 16-bit resolution Synchronization of multiple DAC
devices
1 Gsps maximum update rate 3-wire or 4-wire mode SPI interface
Selectable ×2, ×4 and ×8 interpolation
filters
Differential scalable output current from
8.1 mA to 34 mA
Very low noise capacitor-free integrated
Phase-Locked Loop (PLL)
External analog offset control
(10-bit auxiliary DACs)
Embedded Numerically Controlled
Oscillator (NCO) with 40-bit
programmable frequency
High resolution internal digital gain and
offset control to support high
performance IQ-modulator image
rejection
Embedded complex(I/Q) digital IF
modulator
Internal phase correction
1.8 V and 3.3 V power supplies Inverse (sin x) / x function
LVDS DDR compatible input interface
with on-chip 100 Ω terminations
Power-down mode and Sleep mode;
5-bit NCO low-power mode
LVDS DDR input clock up to 370 MHz On-chip 1.25 V reference
LVDS or LVPECL compatible DAC clock Industrial temperature range −40 °C to
+85 °C
Interleaved or folded I and Q data input
mode
72 pins small form factor HVQFN
package
Table 1. Ordering information
Type number Package
Name Description Version
DAC1617D1G0HN HVQFN72 plastic thermal enhanced very thin quad flat package; no leads;
72 terminals; body 10 ×10 ×0.85 mm
SOT813-3
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 3 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
5. Block diagram
Fig 1. DAC1617D1G0 block diagram
IOUTBP
IOUTBN
IOUTAP
IOUTAN
AUXAP
AUXAN
sincos
+
OFFSET
CONTROL
DAC B
X
sin X
GAPOUT
VIRES
+
X
sin X
10-BIT
ANALOG GAIN
CONTROL
10-BIT
ANALOG GAIN
CONTROL
CLIPPING
CLIPPING
10-BIT
OFFSET
CONTROL
NCO
40-bit frequency setting
16-bit phase adjustment
10-BIT
OFFSET
CONTROL
REF.
BANDGAP
AND
BIASING
DAC A
AUX.
DAC
AUXBP
AUXBN
AUX.
DAC
x2
FIR 2
x2
FIR 1
MULTI-DAC
SYNCHRONIZATION
x2
FIR 2
x2
FIR 3
x2
FIR 3
x2
FIR 1
CLOCK GENERATOR/PLL
DCMSU
CDI
SPI
SDO SDIO SCS_N SCLK
MDS
COARSE
PHASE COMPENSATION
DIGITAL GAIN/OFFSET
LVDS
DDR/
DIF
CLKP
LDCLKN
LDCLKP
LD(15)N to
LD(0)N
LD(15)P to
LD(0)P
ALIGNN
ALIGNP
CLKN
MDSP
MDSN
INTERRUPT
INTERNAL MONITORING
IO1
IO0
RESET_N
DAC
COMPLEX MODULATOR
+
+
+
-
16
16
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 4 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. DAC1617D1G0 pin configuration
DAC
Transparent top view
LD[4]N
LD[12]N
LD[11]P
LD[3]P
LD[12]P LD[3]N
LD[13]N LD[2]P
LD[13]P LD[2]N
VDDD VDDD
LD[14]N LD[1]P
LD[14]P LD[1]N
LD[15]N LD[0]P
LD[15]P LD[0]N
ALIGNN IO1
ALIGNP IO0
TM SDO
MDSN SDIO
MDSP SCLK
CLKN SCS_N
LD[10]P
LD[10]N
LD[9]P
LD[9]N
LD[8]P
LD[8]N
VDDD
LCKP
LCKN
n.c.
LD[7]P
LD[7]N
LD[6]P
LD[6]N
LD[5]P
LD[5]N
IOUTAN
IOUTAP
VDDA(1V8)_D
VDDA(3V3)
AUXAP
AUXAN
VDDA(1V8)_P2
GAPOUT
VIRES
VDDA(1V8)_P1
AUXBN
AUXBP
VDDA(3V3)
VDDA(1V8)_D
IOUTBP
IOUTBN
LD[11]N LD[4]P
CLKP RESET_N
VDDD
VDDD
VDDA(1V8)_D
VDDA(1V8)_D
17
18
38
37
16 39
15 40
14 41
13 42
12 43
11 44
10 45
946
847
748
649
550
451
352
2
1
53
54
71
72
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
20
19
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
terminal 1
index area
Table 2. Pin description
Symbol Pin Type
[1]
Description
CLKP 1 I DAC clock positive input
CLKN 2 I DAC clock negative input
MDSP 3 IO multi-device synchronization positive signal
MDSN 4 IO multi-device synchronization negative signal
TM 5 I Test mode selection (connect to GND)
ALIGNP 6 I positive input for data alignment
ALIGNN 7 I negative input for data alignment
LD[15]P 8 I LVDS positive input bit 15
[2]
LD[15]N 9 I LVDS negative input bit 15
[2]
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 5 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
LD[14]P 10 I LVDS positive input bit 14
[2]
LD[14]N 11 I LVDS negative input bit 14
[2]
V
DDD
12 P digital power supply
LD[13]P 13 I LVDS positive input bit 13
[2]
LD[13]N 14 I LVDS negative input bit 13
[2]
LD[12]P 15 I LVDS positive input bit 12
[2]
LD[12]N 16 I LVDS negative input bit 12
[2]
LD[11]P 17 I LVDS positive input bit 11
[2]
LD[11]N 18 I LVDS negative input bit 11
[2]
V
DDD
19 P digital power supply
LD[10]P 20 I LVDS positive input bit 10
[2]
LD[10]N 21 I LVDS negative input bit 10
[2]
LD[9]P 22 I LVDS positive input bit 9
[2]
LD[9]N 23 I LVDS negative input bit 9
[2]
LD[8]P 24 I LVDS positive input bit 8
[2]
LD[8]N 25 I LVDS negative input bit 8
[2]
V
DDD
26 P digital power supply
LCKP 27 I LVDS positive data clock input
LCKN 28 I LVDS negative data clock input
n.c. 29 G not connected
LD[7]P 30 I LVDS positive input bit 7
[2]
LD[7]N 31 I LVDS negative input bit 7
[2]
LD[6]P 32 I LVDS positive input bit 6
[2]
LD[6]N 33 I LVDS negative input bit 6
[2]
LD[5]P 34 I LVDS positive input bit 5
[2]
LD[5]N 35 I LVDS negative input bit 5
[2]
V
DDD
36 P digital power supply
LD[4]P 37 I LVDS positive input bit 4
[2]
LD[4]N 38 I LVDS negative input bit 4
[2]
LD[3]P 39 I LVDS positive input bit 3
[2]
LD[3]N 40 I LVDS negative input bit 3
[2]
LD[2]P 41 I LVDS positive input bit 2
[2]
LD[2]N 42 I LVDS negative input bit 2
[2]
V
DDD
43 P digital power supply
LD[1]P 44 I LVDS positive input bit 1
[2]
LD[1]N 45 I LVDS negative input bit 1
[2]
LD[0]P 46 I LVDS positive input bit 0
[2]
LD[0]N 47 I LVDS negative input bit 0
[2]
IO1 48 IO IO port bit 1
IO0 49 IO IO port bit 0
SDO 50 O SPI data output
Table 2. Pin description
…continued
Symbol Pin Type
[1]
Description
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 6 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
[1] P: power supply; G: ground; I: input; O: output.
[2] The LVDS input data bus order can be reversed and each element can be swapped between P and N using
dedicated registers (see Table 60).
SDIO 51 IO SPI data input/output
SCLK 52 I SPI clock
SCS_N 53 I SPI chip select (active LOW)
RESET_N 54 I general reset (active LOW)
V
DDA(1V8)_D
55 P 1.8 V analog power supply (DAC core)
IOUTBN 56 O complementary DAC B output current
IOUTBP 57 O DAC B output current
V
DDA(1V8)_D
58 P 1.8 V analog power supply (DAC core)
V
DDA(3V3)
59 P 3.3 V analog power supply
AUXBP 60 O auxiliary DAC B output current
AUXBN 61 O complementary auxiliary DAC B output current
V
DDA(1V8)_P1
62 P 1.8 V analog power supply (PLL)
VIRES 63 IO DAC biasing resistor
GAPOUT 64 IO band gap input/output voltage
V
DDA(1V8)_P2
65 P 1.8 V analog power supply (PLL)
AUXAN 66 O complementary auxiliary DAC A output current
AUXAP 67 O auxiliary DAC A output current
V
DDA(3V3)
68 P 3.3 V analog power supply
V
DDA1V8_D
69 P 1.8 V analog power supply (DAC core)
IOUTAP 70 O DAC A output current
IOUTAN 71 O complementary DAC A output current
V
DDA(1V8)_D
72 P 1.8 V analog power supply (DAC core)
GND H G ground (exposed die pad)
Table 2. Pin description
…continued
Symbol Pin Type
[1]
Description
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 7 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
7. Limiting values
[1] Connect the analog 1.8 V power supply to pins VDDA1V8_D, VDDA1V8_P1, and VDDA1V8_P2.
8. Thermal characteristics
[1] Value for six-layer board in still air with a minimum of 49 thermal vias.
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DDA(3V3)
analog supply voltage
(3.3 V)
−0.5 +4.6 V
V
DDD
digital supply voltage −0.5 +2.5 V
V
DDA(1V8)
analog supply voltage
(1.8 V)
[1]
−0.5 +2.5 V
V
I
input voltage input pins referenced to GND −0.5 +2.5 V
V
O
output voltage pins IOUTAP, IOUTAN,
IOUTBP, IOUTBN, AUXAP,
AUXAN, AUXBP and AUXBN
referenced to GND
−0.5 +4.6 V
T
stg
storage temperature −55 +150 °C
T
amb
ambient temperature −40 +85 °C
T
j
junction temperature −40 +125 °C
Table 4. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction
to ambient
[1]
16.2 K/W
R
th(j-c)
thermal resistance from junction
to case
[1]
6.7 K/W
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 8 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
9. Characteristics
Table 5. Characteristics
V
DDA(1V8)
= 1.8 V; V
DDD
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
V
DDA(3V3)
analog supply
voltage (3.3 V)
C 3.15 3.3 3.45 V
V
DDD
digital supply
voltage
C 1.7 1.8 1.9 V
V
DDA(1V8)
analog supply
voltage (1.8 V)
C
[2]
1.7 1.8 1.9 V
I
DDA(3V3)
analog supply
current (3.3 V)
Auxiliary DAC on C 51 55 59 mA
I
DDD
digital supply
current (1.8 V)
f
s
= 983.04 67;
×4 interpolation; no NCO;
MDS off
C 475 525 585 mA
f
s
= 620 Msps;
×2 interpolation; NCO on;
no MDS
C 400 450 500 mA
I
DDA(1V8)
analog supply
current (1.8 V)
f
s
= 983.04 Msps; 1 V (p-p) C
[2]
207 218 230 mA
f
s
= 620 Msps; 1 V (p-p) C 207 218 230 mA
P
tot
total power
dissipation
f
s
= 983.04 Msps;
×4 interpolation; NCO off;
MDS off
C - 1580 - mW
f
s
= 983.04 Msps;
×4 interpolation;
5-bit NCO; MDS off
C - 1500 - mW
f
s
= 620 Msps;
×2 interpolation; 5-bit
NCO; MDS off
- 1370 - mW
power-down using SPI
register
C - 63 - mW
Clock inputs (pins CLKP, CLKN)
V
i(clk)dif
differential clock
input voltage
peak-to-peak C 150 - 1000 mV
R
i
input resistance D - 200 - kΩ
C
i
input
capacitance
D - 1 - pF
Digital inputs (pins LD[15]P to LD[0]P, LD[15]N to LD[0]N, LCKP and LCKN, ALIGNP and ALIGNN)
V
i
input voltage |V
gpd
| < 50 mV
[3]
C 825 - 1575 mV
V
idth
input differential
threshold
voltage
|V
gpd
| < 50 mV
[3]
C−100 - +100 mV
R
i
input resistance D - 100 - Ω
C
i
input
capacitance
D - 0.8 - pF
pins LCKP and LCKN D - 0.9 - pF
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 9 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Digital inputs/outputs (pins MDSN, MDSP)
V
o(dif)(p-p)
peak-to-peak
differential
output voltage
C - 500 - mV
C
i
input
capacitance
between GND and pin
MDSN or MDSP
D - 0.6 - pF
R
i
input resistance D - 100 - Ω
V
i
input voltage |V
gpd
| < 50 mV
[3]
C 825 - 1575 mV
V
idth
input differential
threshold
voltage
|V
gpd
| < 50 mV
[3]
C−100 - +100 mV
Digital inputs/outputs (pins SDO, SDIO, SCLK, SCS_N, RESET_N, IO0, IO1)
V
IL
LOW-level input
voltage
C GND - 0.3V
DDD(1V8)
V
V
IH
HIGH-level
input voltage
C 0.7V
DDD(1V8)
- V
DDD(1V8)
V
V
OL
LOW-level
output voltage
pins IO0, IO1, SDO and
SDIO
C GND - 0.1V
DDD(1V8)
V
V
OH
HIGH-level
output voltage
pins IO0, IO1, SDO and
SDIO
C 0.9V
DDD(1V8)
- V
DDD(1V8)
V
I
IL
LOW-level input
current
maximum VIL I −10 - +10 µA
I
IH
HIGH-level
input current
maximum VIL I −10 - +10 µA
C
i
input
capacitance
D - 2.2 - pF
Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN)
I
bias
bias current DC current D - 2.5 - mA
I
O(fs)
full-scale output
current
controlled by the analog
GAIN registers
(see Table 32)
D 8.1 - 34 mA
default value D - 20 - mA
V
O
output voltage compliance range D 2.3 - V
DDA(3V3)
V
V
O(cm)
common-mode
output voltage
1 V (p-p) DAC output D - 3 - V
2 V (p-p) DAC output - 2.8 - V
R
o
output
resistance
D - 250 - kΩ
C
o
output
capacitance
between pins OUTAN and
OUTBN and pins OUTBN
and OUTBP
D - 5 - pF
Reference voltage output (pin GAPOUT)
V
O(ref)
reference output
voltage
T
amb
= +25 °C I - 1.22 - V
Table 5. Characteristics
…continued
V
DDA(1V8)
= 1.8 V; V
DDD
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 10 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
I
O(ref)
reference output
current
1.25 V external voltage D - 40 - µA
Analog auxiliary outputs (pins AUXAP, AUXAN, AUXBP and AUXBN)
I
O(fs)
full-scale output
current
auxiliary DAC A;
differential outputs
I - 3.1 - mA
auxiliary DAC B;
differential outputs
I - 3.1 - mA
V
O(aux)
auxiliary output
voltage
compliance range D 0 - 2.3 V
LVDS input timing
f
data
data rate f
s(max)
specification must
be respected
(f
s
= f
data
×interpolation
factor)
C - - 370 MHz
t
sk(clk-D)
skew time from
clock to data
input
f
DATA
= 184.32 Mhz C 800 - 830 ps
f
DATA
= 245.76 MHz C 500 - 675 ps
f
DATA
= 307.2 MHz C 300 - 520 ps
f
DATA
= 368.64 MHz C 150 - 500 ps
t
su
set-up time manual tuning mode
(see Figure 16); depends
on LDCLK_DEL[3:0]
0000 C −300 - - ps
0001 C −365 - - ps
0010 C −440 - - ps
0011 C −520 - - ps
0100 C −590 - - ps
0101 C −675 - - ps
0110 C −750 - - ps
0111 C −830 - - ps
1000 C −845 - - ps
1001 C −845 - - ps
1010 C −1000 - - ps
1011 C −1100 - - ps
1100 C −1220 - - ps
1101 C −1290 - - ps
1110 C −1360 - - ps
1111 C −1450 - - ps
Table 5. Characteristics
…continued
V
DDA(1V8)
= 1.8 V; V
DDD
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 11 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
t
hold
hold time manual tuning mode
(see Figure 15); depends
on LDCLK_DEL[3:0]:
0000 C 790 - - ps
0001 C 870 - - ps
0010 C 950 - - ps
0011 C 1055 - - ps
0100 C 1140 - - ps
0101 C 1230 - - ps
0110 C 1360 - - ps
0111 C 1460 - - ps
1000 C 1900 - - ps
1001 C 2075 - - ps
1010 C 2250 - - ps
1011 C 2400 - - ps
1100 C 2560 - - ps
1101 C 2740 - - ps
1110 C 2900 - - ps
1111 C 3000 - - ps
DAC output timing
f
s(max)
sampling rate C 1000 - - Msps
t
s
settling time to ± 0.5 LSB D - 20 - ns
Internal PLL timing
f
s
sampling rate D 50 - 1000 Msps
40-bit NCO frequency range; f
s
= 1000 Msps
f
NCO
NCO frequency two’s complement coding
register value =
8000000000h
D - −500 - MHz
register value =
FFFFFFFFFFh
D - −0.9095 - mHz
register value =
0000000000h
D - 0 - Hz
register value =
0000000001h
D - +0.9095 - mHz
register value =
7FFFFFFFFFh
D - +499.99909 - MHz
f
step
step frequency D - 0.9095 - mHz
Table 5. Characteristics
…continued
V
DDA(1V8)
= 1.8 V; V
DDD
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 12 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Low-power NCO frequency range; f
s
= 1000 MHz
f
NCO
NCO frequency two’s complement coding
register value =
F8000000000h
D - −500 - MHz
register value =
F8000000000h
D - −31.25 - MHz
register value =
00000000000h
D - 0 - Hz
register value =
08000000000h
D - +31.25 - MHz
register value =
7FFFFFFFFFh
D - +468.75 - MHz
f
step
step frequency D - 31.25 - MHz
Dynamic performance
SFDR spurious-free
dynamic range
f
data
= 245.76 MHz;
f
s
= 983.04 Msps;
BW = f
s
/ 2
f
o
= 20 MHz at −1 dBFS I - 78 - dBc
f
data
= 184.32 MHz;
f
s
= 737.28 Msps;
BW = f
s
/ 2
f
o
= 20 MHz at −1 dBFS - 78 - dBc
SFDR
RBW
restricted
bandwidth
spurious-free
dynamic range
f
data
= 245.76 MHz;
f
s
= 983.04 Msps;
f
o
= 150 MHz
- - dBc
BW = 100 MHz - 78 - dBc
BW = 180 MHz - 78 - dBc
IMD3 third-order
intermodulation
distortion
f
data
= 245.76 MHz;
f
s
= 983.04 Msps;
f
o1
= 20 MHz;
f
o2
= 21 MHz;
×4 interpolation;
output level = −1 dBFS
C - 75 - dBc
f
data
= 245.76 MHz;
f
s
= 983.04 Msps;
f
o1
= 152 MHz;
f
o2
= 155.1 MHz;
×4 interpolation;
output level = −1 dBFS
I - 75 - dBc
Table 5. Characteristics
…continued
V
DDA(1V8)
= 1.8 V; V
DDD
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 13 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] Connect V
DDA(1V8)_D
, V
DDA(1V8)_P1
and V
DDA(1V8)_P2
to the same 1.8 V analog power supply. Use dedicated filters for the three power
pins.
[3] |V
gpd
| represents the ground potential difference voltage. This voltage is the result of current flowing through the finite resistance and the
inductance between the receiver and the driver circuit ground voltages.
ACPR adjacent
channel power
ratio
WCDMA pattern;
f
s
= 983.04 Msps;
×4 interpolation;
f
NCO
= 153.6 MHz
1 carrier; BW = 5 MHz C - 73 - dBc
2 carriers; BW = 10 MHz C - 70 - dBc
4 carriers; BW = 20 MHz C - 68 - dBc
α
isol(ch-ch)
isolation
between
channels
f
s
= 1228.8 Msps;
×4 interpolation;
f
out
= 10 MHz; NCO = off;
level = 0.1 dBFS; both
DAC channels enabled
C - 110 - dBc
f
s
= 1228.8 Msps;
×4 interpolation;
f
out
= 83 MHz; NCO = off;
level = 0.1 dBFS; both
DAC channels enabled
C - 95 - dBc
f
s
= 1228.8 Msps;
×4 interpolation;
f
out
= 210 MHz; NCO = on;
level = 0.1 dBFS; one DAC
channel enabled; one DAC
channel disabled
C - 81 - dBc
NSD noise spectral
density
f
s
= 983.04 Msps;
×4 interpolation;
f
o
= 20 MHz at −1 dBFS
D - −158 - dBm/Hz
f
s
= 983.04 Msps;
×4 interpolation;
f
o
= 153.6 MHz at −1 dBFS
D - −155 - dBm/Hz
Table 5. Characteristics
…continued
V
DDA(1V8)
= 1.8 V; V
DDD
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
°
C; R
L
= 50
Ω
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in Figure 29; output level = 1 V (p-p).
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 14 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10. Application information
10.1 General description
The DAC1617D1G0 is a dual 16-bit DAC operating up to 1000 Msps. Each DAC consists
of a segmented architecture, comprising a 6-bit thermometer subDAC and a 10-bit binary
weighted subDAC.
A maximum input LVDS DDR data rate of up to 370 MHz and a maximum output sampling
rate of 1000 Msps ensure more flexibility for wide bandwidth and multi-carrier systems.
The internal 40-bit NCO of the DAC1617D1G0 simplifies the frequency selection of the
system. The DAC1617D1G0 provides ×2, ×4 or ×8 interpolation filters that are useful for
removing the undesired images.
Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN
and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (I
O(fs)
) of
up to 34 mA. An internal reference is available for the reference current which is externally
adjustable using pin VIRES.
High resolution internal gain, phase and offset control provide outstanding image and
Local Oscillator (LO) signal rejection at the system analog modulator output.
Multiple device synchronization enables synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
All functions can be set using an SPI interface.
10.2 Serial Peripheral Interface (SPI)
10.2.1 Protocol description
The DAC1617D1G0 serial interface is a synchronous serial communication port ensures
easy interface with many industry microprocessors. It provides access to the registers that
define the operating modes of the chip in both write and read mode.
This interface can be configured as a 3-wire type (pin SDIO as bidirectional pin) or 4-wire
type (pins SDIO and SDO as unidirectional pins, input and output port, respectively). In
both configurations, SCLK acts as the serial clock and SCS_N as the serial chip select.
Figure 3 shows the SPI protocol. An SCS_N signal follows each read/write operation. A
LOW assertion enables it to drive the chip with 2 bytes to 5 bytes, depending on the
content of the instruction byte (see Table 7).
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 15 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
R/W indicates the mode access (see Table 6)
Table 7 shows the number of bytes to be transferred. N1 and N0 indicate the number of
bytes transferred after the instruction byte.
A[4:0] indicates which register is being addressed. If a multiple transfer occurs, this
address concerns the first register. The other registers follow directly in a decreasing
order (see Table 21, Table 35 and Table 53).
The DAC1617D1G0 incorporates more than the 32 SPI registers allowed by the address
value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each
containing 32 registers. The 32
nd
register of each page indicates which page is currently
addressed (00h, 01h or 0Ah).
Fig 3. SPI protocol
RESET_N
(optional)
SCS_N
SCLK
SDIO
SDO
(optional)
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Table 6. Read or Write mode access description
R/W Description
0 Write mode operation
1 Read mode operation
Table 7. Number of bytes transferred
N1 N0 Number of bytes transferred
0 0 1 byte
0 1 2 bytes
1 0 3 bytes
1 1 4 bytes
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 16 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.2.2 SPI timing description
The SPI interface can operate at a frequency up to 25 MHz. The SPI timings are shown in
Figure 4.
The SPI timing characteristics are given in Table 8.
10.3 Power-on sequence
There are three steps for the power-on sequence (see Figure 5):
1. The board is power-on. At the turn-on time, all DAC1617D1G0 supplies have reached
their specification ranges.
2. At least 1 µs after the turn-on time pin RESET_N must be released.
3. When the DAC clock and LVDS clock are stable, the SPI configuration is sent to the
DAC1617D1G0. Writing 0 in bits RST_DCLK and RST_LCLK of the register
MAIN_CNTRL (see Table 54) starts the automatic calibration. 30 µs after this
calibration, the DAC1617D1G0 is operational.
Fig 4. SPI timing diagram
Table 8. SPI timing characteristics
Symbol Parameter Min Typ Max Unit
f
SCLK
SCLK frequency - - 25 MHz
t
w(SCLK)
SCLK pulse
width
30 - - ns
t
su(SCS_N)
SCS_N set-up
time
20 - - ns
t
h(SCS_N)
SCS_N hold
time
20 - - ns
t
su(SDIO)
SDIO set-up
time
10 - - ns
t
h(SDIO)
SDIO hold time 5 - - ns
t
w(RESET_N)
RESET_N pulse
width
30 - - ns
50 %
tw(RESET_N)
tsu(SCS_N)
tsu(SDIO)
th(SDIO)
th(SCS_N)
tw(SCLK)
50 %
RESET_N
SCS_N
SCLK
SDIO
50 %
50 %
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 17 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.4 LVDS Data Input Format (DIF) block
The Data Input Formatting (DIF) block captures and resynchronizes data on the LVDS bus
with its own LCLKP/LCLKN clock. Each LVDS input buffer has an internal resistance of
100 Ω, so an external resistor is not required. The DIF block includes two subblocks:
•
LVDS receiver:
Provides high flexibility for the LVDS interface, especially for the PCB layout and the
control of the input port polarity and the input port mapping.
•
Data format block:
Enables the adaptation, which ensures the support of several data encoding modes.
10.4.1 Input port polarity
The polarity of each individual LVDS input (LD[15]P to LD[0]P and LD[15]N to LD[0]N) can
be changed. This ensures a much easier PCB layout design. The input polarity is
controlled with bits LD_POL[15:0] (see Table 59).
10.4.2 Input port mapping
Inverting the order of the LSB and the MSB of the LVDS bus using bit WORD_SWAP in
register LD_CNTRL (see Table 60) also simplifies the design of the PCB (see Table 9).
Fig 5. Power-on sequence
SPI bus
WRITE DAC CONFIGURATION
START CLOCK CALIBRATION
time
RESET_N
ton
power in
specification
range
tspi_start
trst
power supplies
Fig 6. LVDS Data Input Format (DIF) block diagram
16
16
LVDS
RECEIVER
to DAC A
to DAC B
PA[15..0]
PB[15..0]
16
16
I[15..0]
Q[15..0]
LCLK
LD[15]P
LD[15]N
LD[0]P
LD[0]N
LCLKP
LCLKN
DATA
FORMAT
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 18 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.4.3 Input port swapping
The LVDS DDR receiver block internally maps the incoming LVDS data bus into two
buses with a single data rate (Figure 7).
These two buses can be swapped internally using bit LDAB_SWAP of register
LD_CNTRL (see Table 60 and Figure 8).
Table 9. Input LVDS bus swapping
Internal LVDS bus External LVDS bus
(WORD_SWAP = 0)
External LVDS bus
(WORD_SWAP = 1)
LDI[15]P,N LD[15]P,N LD[0]P,N
LDI[14]P,N LD[14]P,N LD[1]P,N
LDI[13]P,N LD[13]P,N LD[2]P,N
LDI[12]P,N LD[12]P,N LD[3]P,N
LDI[11]P,N LD[11]P,N LD[4]P,N
LDI[10]P,N LD[10]P,N LD[5]P,N
LDI[9]P,N LD[9]P,N LD[6]P,N
LDI[8]P,N LD[8]P,N LD[7]P,N
LDI[7]P,N LD[7]P,N LD[8]P,N
LDI[6]P,N LD[6]P,N LD[9]P,N
LDI[5]P,N LD[5]P,N LD[10]P,N
LDI[4]P,N LD[4]P,N LD[11]P,N
LDI[3]P,N LD[3]P,N LD[12]P,N
LDI[2]P,N LD[2]P,N LD[13]P,N
LDI[1]P,N LD[1]P,N LD[14]P,N
LDI[0]P,N LD[0]P,N LD[15]P,N
Fig 7. LVDS DDR receiver mapping LDAB SWAP = 0
A0 B0 A1 B1 A2 B2 A3 B3
LVDS
RECEIVER
LD[15..0]P/N
LCLKP/N
PA[15..0]
PB[15..0]
LCLK
A0 A1
to DAC A
to DAC B
A2 A3
B0 B1 B2 B3
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 19 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.4.4 Input port formatting
The LVDS DDR input bus multiplexes two 16-bit streams. The LVDS receiver block
demultiplexes these two streams.
The two streams can carry two data formats:
•
Folded
•
Interleaved
The data format block is in charge of the data format adaptation (see Figure 9).
The DAC1617D1G0 can correctly decode the input stream using bit IQ_FORMAT of
register LD_CNTRL (see Table 60), because it can determine which format is used on the
LVDS DDR bus.
Table 10 shows the format mapping between the LVDS input data and the data sent to the
two DAC channels depending on the data format selected.
Fig 8. LVDS DDR receiver mapping LDAB SWAP = 1
A0 B0 A1 B1 A2 B2 A3 B3
LVDS
RECEIVER
LD[15..0]P/N
LCLKP/N
PA[15..0]
PB[15..0]
LCLK
B0 B1
to DAC A
to DAC B
B2 B3
A0 A1 A2 A3
Fig 9. LVDS DDR data formats
A0 B0 A1 B1 A2 B2 A3 B3
LVDS
RECEIVER
LD[15..0]P/N
LCLKP/N
PA[15..0]
PB[15..0]
LCLK
DATA
FORMAT
A0 A1 A2 A3
B0 B1 B2 B3
I0 I1
to DAC A
to DAC B
I2 I3
Q0 Q1 Q2 Q3
Table 10. Folded and interleaved format mapping
Data format Data bit mapping
interleaved format (IQ_FORMAT = 1) In[15..0] = An[15..0]; Qn[15..0] = Bn[15..0]
folded format (IQ_FORMAT = 0) In[15..8] = An[15..8]; In[7..0] = Bn[15..8]
Qn[15..8] = An[7..0]; Qn[7..0] = Bn[7..0]
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 20 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.4.5 Data parity/data enable
The ALIGN pins can be used in several ways:
•
As datastream start flag for Multiple Devices Synchronization (see Section 10.13).
•
As LVDS data enable which can be used to insert a DC level into the datastream. The
SEL_EN bits in register LD_CNTRL (see Table 60) enable the programming of this
mode. The DC level for both channels is selected using registers I_DC_LVL and
Q_DC_LVL (see Table 62)
•
As parity bit for the LD[15:0] to detect disruptions at the LVDS-input port bit PARITYC
in register LD_CNTRL (see Table 60) enabling the control of this mode. A Parity error
can generate an interrupt (INTR) reported on either IO0 or IO1 pin
10.5 Interrupt controller
The DAC1617D1G0 incorporates an interrupt controller that makes notifying a
host-controller in case of an internal event. The INTR-signal can be made available on
one of the IO pins. The polarity on the IO pins is programmable.
The internal event that must be tracked and generates an interrupt can be selected using
the INTR_EN register (see Table 45). Two types of interrupt sources are considered:
•
The ready-indicators (MAQ_RDY_B, MAQ_RDY_A, AUTO_CAL_RDY, and
AUTO_DL_RDY; register INTR_FLAGS; see Table Table 47) notify the host-interface
that the corresponding process (invoked by the host interface) has been finalized
•
The error flags indicate that a failure has been detected. For example, on the
LVDS-interface it is possible to check for parity errors and/or to monitor if the internal
timing of the LVDS clock delay has changed since the calibration. Errors like these
can result in critical timings within the Clock Domain Interface (CDI) which transfers
the data from the LCLK to the DCLK domain
The selected event that has invoked the interrupt can be determined using the
INTR_FLAGS register (see Table 47). The flags and the INTR signal are reinitialized by
setting the INTR_CLEAR control bit in register INTR_CTRL (see Table 45).
10.6 General-purpose IO pins
The DAC1617D1G0 provides two general-purpose pins, IO0 and IO1. These pins can be
used to observe the interrupt signal (INTR) or other internal signals (internal clocks, LVDS
data, etc.). These pins can also be used as generic outputs to control external devices.
The internal signals that must be observed on these pins are selected using registers
IO_MUX0, IO_MUX1, and IO_MUX2 (see Table 63 and Table 64).
10.7 Input clock
The DAC1617D1G0 operates with two clocks, one for the LVDS DDR interface and one
for the DAC core.
10.7.1 LVDS DDR clock
The LVDS DDR clock can be interfaced as shown in Figure 10 because the clock buffer
contains a 100 Ω internal resistor.
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 21 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.7.2 DAC core clock
The DAC core clock can achieve a frequency of up to 1 Gsps. It includes internal biasing
to support both AC-coupling and DC-coupling. The clock can be easily connected to any
LVDS, CML or PECL clock sources.
Depending on the interface selected, the hardware configuration varies
(see Figure 11 to Figure 13).
Fig 10. LVDS DDR clock configuration
Z = 100 Ω
100 Ω
DAC
LVDS
LCLKP
LCLKN
LVDS
a. DC-coupling
b. AC-coupling
Fig 11. DAC core clock: LVDS configuration
Fig 12. DAC core clock: CML configuration with AC-coupling
Z = 100 Ω
100 Ω
LVDS
CLKP
CLKN
DAC
Z = 100 Ω
100 Ω
LVDS
CLKP
CLKN
DAC
100 nF
100 nF
Z = 50 Ω
50 Ω
DAC
Z = 50 Ω
CML
3.3 V
50 Ω
3.3 V
CLKP
CLKN
100 nF
100 nF
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 22 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.8 Timing
The DAC1617D1G0 can operate at an update rate (f
s
) of up to 1 Gsps and with an input
data rate (f
data
) of up to 370 MHz.
The sampling position of the LVDS data can be tuned using a 16-step compensation delay
clock. An internal clock is generated to define the exact sampling position of the LVDS
data (see Figure 14, signals LDCLKPcp and LDCLKNcp) which depends on the
compensation delay.
Figure 14 shows how the compensation delay helps to recover the LVDS DDR data on
both the A and B paths.
The compensation delay time (t
cmp
in Figure 14) can be tuned automatically or manually.
Bit CAL_CNTRL of the MAIN_CNTRL register (see Table 54) enables the switching
between automatic tuning and manual tuning.
In Automatic tuning mode, the external LVDS data and clock signals are generated using
the same reference clock (inside the FPGA). The LDCLK clock is similar to a data bit that
toggles each time (the rising edge and falling edge of the LDCLK and LVDS data occur at
the same time). In automatic tuning, the internal compensation delay time (t
cmp
) is defined
automatically to compensate the internal DAC1617D1G0 delay time optimally.
The timing requirement in automatic tuning mode is defined in Figure 15 and in Table 5.
Fig 13. DAC core clock: PECL configuration with AC-coupling
Z = 50 Ω
100 Ω
200 Ω
200 Ω
DAC
Z = 50 Ω
PECL
CLKP
CLKN
100 nF
100 nF
Fig 14. LVDS DDR demux timing (LVDS A and B paths not swapped; LDAB_SWAP = 0)
Dn[i]
Dn[i]
Dn + 1[i]
Dn + 1[i] Dn + 3[i]
Dn − 1[i]
tcmp
Dn − 1[i]
Dn + 2[i]
Dn + 2[i]
LDCLKN
LDCLKP
LD[i]N
LD[i]P
LDCLKNcp
LDCLKPcp
LDA[i]
LDB[i]
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 23 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Use manual tuning mode if the LVDS data and the LDCLK clock signals provided to the
DAC1617D1G0 device have a systematic delay. The compensation delay time can be
adjusted to compensate for the systematic delay. The compensation delay time (t
cmp
in
Figure 14), can be defined using bits LDCLK_DEL[3:0] of register MAN_LDCLKDEL
(see Table 55).
The timing requirement in manual tuning mode is defined in Figure 16 and in Table 5.
10.9 Operating modes
The DAC1617D1G0 requires two differential clocks:
•
The LVDS clock (LDCLKP, LDCLKN) for the LVDS DDR interface
•
The data clock (CLKP, CLKN) for the internal PLL and the dual DAC core
In Normal mode, provide both the DAC clock and the LVDS clock to the DAC1617D1G0.
Align the ratio frequency between these two clocks needs with selected ×2, ×4 or ×8
interpolation filters. The clocks provided to the DAC1617D1G0 must respect the LVDS
input timing and the DAC output timing specifications as defined in Table 5.
t
sk(min)
= minimum skew time
t
sk(max)
= maximum skew time
Fig 15. Timing requirement automatic tuning
Fig 16. Timing requirement in manual tuning mode
LVDS data
LVDS clock
VIH
VIL
VIH
VIL
tsk(min)
tsk(max)
LVDS
data
tsu (negative)
LDCLK
sampling
window
sampling
window
thold
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 24 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
In PLL mode, provide the LVDS clock to pins LDCLKP/LDCLKN and pins CLKP/CLKN.
Depending on selected interpolation filter, the internal PLL can be set to generate the right
DAC core clock frequency internally. The clocks provided to the DAC1617D1G0 pins must
respect the LVDS input timing and the DAC output timing specifications as defined in
Table 5. The PLL settings must also respect the maximum sampling rate of the PLL (see
the sampling rate (f
s
) in subsection Internal PLL timing of Table 5).
The main function of the Clock Domain Interface (CDI) is to resynchronize the input data
streams to the internal clock the digital processing uses. The CDI also performs the
required reformatting of the input datastreams. Set PLL, CDI, and the interpolation filters,
which depend on the targeted application accordingly. Section 10.9.1 (×2), Section 10.9.2
(×4), and Section 10.9.3 (×8) explain how to set the DAC1617D1G0 to support the
different upsampling modes.
10.9.1 CDI mode 0 (x2 interpolation)
CDI mode 0 (×2 interpolation) is required when the value of the LVDS DDR clock is twice
the internal maximum CDI frequency. Table 11 shows examples of applications using an
internal PLL or an external clock for the DAC core.
[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61).
[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 23).
[3] If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23).
[4] Pins CLKP and CLKN (see Figure 2).
[5] Bit PLL_PD of register PLLCFG (see Table 24).
[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 24).
Table 11. CDI mode 0: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
DAC input
clock
[4]
(MHz)
PLL
status
[5]
PLL
divider
[6]
320 320 0 ×2 640 640 320 enabled 2
320 320 0 ×2 640 640 640 disabled n.a.
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 25 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.9.2 CDI mode 1 (x4 interpolation)
CDI mode 1 (×4 interpolation) is required when the values of the LVDS DDR clock and the
internal CDI frequency are equal. Table 12 shows examples of applications using an
internal PLL or an external clock for the DAC core.
[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61).
[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 23).
[3] If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23).
[4] Pins CLKP and CLKN (see Figure 2).
[5] Bit PLL_PD of register PLLCFG (see Table 24).
[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 24).
10.9.3 CDI mode 2 (x8 interpolation)
CDI mode 2 (×8 interpolation) is required when the LVDS DDR clock is half the maximum
CDI frequency or less. Table 13 shows examples of applications using an internal PLL or
an external clock for the DAC core.
[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61).
[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 23).
[3] If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23).
[4] Pins CLKP and CLKN (see Figure 2).
[5] Bit PLL_PD of register PLLCFG (see Table 24).
[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 24).
Table 12. CDI mode 1: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
DAC input
clock
[4]
(MHz)
PLL
status
[5]
PLL
divider
[6]
250 250 1 ×4 1000 1000 250 enabled 4
250 250 1 ×4 1000 1000 1000 disabled n.a.
Table 13. CDI mode 2: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
mode
[1]
FIR mode
[2]
SSBM
rate
[3]
(Msps)
DAC rate
(Msps)
PLL configuration
DAC input
clock
[4]
(MHz)
PLL
status
[5]
PLL
divider
[6]
125 125 2 ×8 1000 1000 125 enabled 4
125 125 2 ×8 1000 1000 1000 disabled n.a.
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 26 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.10 FIR filters
The DAC1617D1G0 integrates three selectable Finite Impulse Response (FIR) filters
which enable the use of the device with ×2, ×4 or ×8 interpolation rates. All three
interpolation FIR filters have a stop-band attenuation of at least 80 dBc and a pass-band
ripple of less than 0.0005 dB. Table 14 shows the coefficients of the interpolation filters.
Fig 17. First stage half-band filter response
Fig 18. Second stage half-band filter response
NF (fs)
0 0.50.40.2 0.30.1
magnitude
(dB)
0
-100
-20
-40
-80
-60
NF (fs)
0 0.50.40.2 0.30.1
magnitude
(dB)
0
-100
-20
-40
-80
-60
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 27 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Fig 19. Third stage half-band filter response
Table 14: Interpolation filter coefficients
First interpolation filter Second interpolation filter Third interpolation filter
Lower Upper Value Lower Upper Value Lower Upper Value
- H(27) +65536 H(11) - +32768 H(7) - +1024
H(26) H(28) +41501 H(10) H(12) +20272 H(6) H(8) +615
H(25) H(29) 0 H(9) H(13) 0 H(5) H(9) 0
H(24) H(30) −13258 H(8) H(14) −5358 H(4) H(10) −127
H(23) H(31) 0 H(7) H(15) 0 H(3) H(11) 0
H(22) H(32) +7302 H(6) H(16) +1986 H(2) H(12) +27
H(21) H(33) 0 H(5) H(17) 0 H(1) H(13) 0
H(20) H(34) −4580 H(4) H(18) −654 H(0) H(14) −3
H(19) H(35) 0 H(3) H(19) 0 - - -
H(18) H(36) +2987 H(2) H(20) +159 - - -
H(17) H(37) 0 H(1) H(21) 0 - - -
H(16) H(38) −1951 H(0) H(22) −21 - - -
H(15) H(39) 0 - - - - - -
H(14) H(40) +1250 - - - - - -
H(13) H(41) 0 - - - - - -
H(12) H(42) -773 - - - - - -
H(11) H(43) 0 - - - - - -
H(10) H(44) +456 - - - - - -
H(9) H(45) 0 - - - - - -
H(8) H(46) −252 - - - - - -
H(7) H(47) 0 - - - - - -
H(6) H(48) +128 - - - - - -
H(5) H(49) 0 - - - - - -
H(4) H(50) −58 - - - - - -
NF (fs)
0 0.50.40.2 0.30.1
magnitude
(dB)
0
-100
-20
-40
-80
-60
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 28 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Equation 1 defines the dependency of the FIR1 output Y(m) on its inputs X(m):
(1)
Equation 2 defines the dependency of the FIR2 output Y(m) on its inputs X(m):
(2)
Equation 3 defines the dependency of the FIR3 output Y(m) on its inputs X(m):
(3)
10.11 Single SideBand Modulator (SSBM)
The SSBM is a quadrature modulator that enables mixing the I data and Q data with the
sine and cosine signals generated by the NCO to generate path A and path B
(see Figure 20).
H(3) H(51) 0 - - - - - -
H(2) H(52) +22 - - - - - -
H(1) H(53) 0 - - - - - -
H(0) H(54) −6 - - - - - -
Table 14: Interpolation filter coefficients
…continued
First interpolation filter Second interpolation filter Third interpolation filter
Lower Upper Value Lower Upper Value Lower Upper Value
Y m( ) 1
H 27( )
--------------- H n( ):X m n–( )[ ]
n 0=
n 54=
∑
×=
Y m( ) 1
H 11( )
--------------- H n( ):X m n–( )[ ]
n 0=
n 22=
∑
×=
Y m( ) 1
H 7( )
------------ H n( ):X m n–( )[ ]
n 0=
n 14=
∑
×=
Fig 20. SSBM principle
+/−
cos
A
B
I
sin
+/−
sin
Q
cos
+/−
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 29 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
The frequency of the NCO is programmed over 40 bits. NCO enables inverting the sine
component to operate a positive or negative, lower or upper SSB upconversion
(see register TXCFG in Table 23).
10.11.1 NCO in 40 bits
When using NCO, the frequency can be set over 40 bits by five registers, FREQNCO_B0
to FREQNCO_B4 (see Table 25).
The frequency is calculated with Equation 4.
(4)
Where:
•
M is the two’s complement coding representation of FREQ_NCO[39:0]
•
f
s
is the DAC clock sampling frequency
The default settings are:
•
f
NCO
= 96 MHz
•
f
s
= 640 Msps
Registers PHINCO_LSB and PHINCO_MSB over 16 bits from 0° to 360° (see Table 31)
can set the phase of the NCO.
10.11.2 NCO low power
The five MSB-bits of register FREQNCO_B4 (bits FREQ_NCO[39:35]; see Table 25) can
set the frequency, when using NCO low power (bit NCO_LP_SEL; see Table 23).
The frequency is calculated with Equation 5.
(5)
Where:
•
M is the two’s complement coding representation of FREQ_NCO[39:35]
•
f
s
is the DAC clock sampling frequency
The five MSB-bits of register PHINCO_MSB (see Table 31) can set the phase of the NCO
low power.
10.11.3 Complex modulator
The complex modulator upconverts the single side band by mixing NCO signals and I and
Q input signals. Table 15 shows the various possibilities set by bits MODULATION[2:0] of
register TXCFG (see Table 23).
The effect of the MODULATION parameter is better viewed after mixing the A and B
signal with a LO frequency through an IQ modulator:
f
NCO
M f
s
×
2
40
--------------
=
f
NCO
M f
s
×
2
5
--------------
=
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 30 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.11.4 Minus 3dB
In normal use, a full-scale pattern is also full-scale at the DAC output. Nevertheless, when
the I data and Q data come close to full-scale simultaneously, some clipping can occur.
The Minus 3dB function (bit MINUS_3DB of register DAC_OUT_CTRL; see Table 28) can
be used to reduce the 3 dB gain in the modulator. It retains a full-scale range at the DAC
output without added interferers.
10.12 Inverse (sin x) / x
A selectable FIR filter is incorporated to compensate the (sin x) / x effect caused by the
roll-off effect of the DAC. This filter has no effect at DC. It introduces a gain for high
frequency. The coefficients are represented in Table 16. The filter response is presented
in Figure 22.
Fig 21. Complex modulation after LO mixing
0LO-NCO
negative positive
lowerupper lower upper
LO+NCOLO frequency
Table 15. Complex modulator operation mode
MODULATION[2:0] Mode Path A Path B
000 bypass
001 positive
upper sob
010 positive
lower ssb
011 negative
upper ssb
100 negative
lower ssb
others not defined - -
I t( )
Q t( )
I t( ) ω
NCO
t×( )cos Q t( ) ω
NC O
t×( )sin×–×
I t( ) ω
NC O
t×( )sin Q t( ) ω
NC O
t×( )cos×+×
I t( ) ω
NCO
t×( )cos Q t( ) ω
NC O
t×( )sin×+×
I t( ) ω
NC O
t×( )sin Q t( ) ω
NC O
t×( )cos×–×
I t( ) ω
NCO
t×( )cos Q t( ) ω
NC O
t×( )sin×–×
I t( )–ω
NCO
t×( )sin Q t( ) ω
NCO
t×( )cos×–×
I t( ) ω
NCO
t×( )cos Q t( ) ω
NC O
t×( )sin×+×
I t( )–ω
NCO
t×( )sin Q t( ) ω
NC O
t×( )cos×+×
Table 16. Inversion filter coefficients
First interpolation filter
Lower Upper Value
H(1) H(9) +1
H(2) H(8) −4
H(3) H(7) +13
H(4) H(6) −51
H(5) - +610
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 31 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.13 Multiple Devices Synchronization (MDS)
Several DAC channels can be sampled synchronously and phase coherently using the
MDS feature.
When all DAC slave devices of one system receive the same MDS signal (or at least a
synchronous version of this reference) all devices are time-aligned at ±1 DAC clock
accuracy at the end of the synchronization process.
10.13.1 MDS concept
The FPGA(s) has(have) to activate the ALIGN pins to identify the LVDS data flow start
(see Figure 23).
The ALIGN signal is used to generate a local reference inside the DAC1617D1G0 which
is 'aligned' with the IQ-data.
The DAC1617D1G0 devices use the MDS signals to do the output synchronization
(see Figure 24).
Fig 22. Inverse (sin x) / x response
Normalized Frequency = 2 x fout / fs
0 1.00.80.4 0.60.2
-2
2
6
Magnitude
(dB)
-6
Fig 23. Align LVDS data
ln-2 Qn-2
align
LVDS data ln-1 Qn-1 lnQnln+1 Qmlm+1 Qm+1 lm+2 Qm+2 lm+3 Qm+3 lm+4 Qm+4 lm+5
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 32 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
The signal detector of the DAC1617D1G0 detects the presence of the MDS signals. Once
detected, an internal copy process of this reference starts. The MDS early/late detector
block then compares the phase difference of these two signals to align the copy to its
reference accurately. The alignment is done inside an "enabling window" that avoids the
misinterpretation of the signal edges. This alignment process is done by moving the
internal pointer of register MDS_ADJDELAY (see Table 43) (so inserting/removing a delay
in data flow). This pointer can have a preset offset. This is specified by register
MDS_OFFSET_DLY (see Table 42). Using the MDS_MAN and MDS_MAN_ADJDELAY
bits in register MDS_MAN_ADJUSTLY register (see Table 39), the alignment can also be
set manually.
Fig 24. MDS synchronization
DATA FLOW
DELAY
MDS CONTROL
AND
GENERATION
MDS internal ref
EARLY/LATE
DETECTOR
early
late
window
DAC A
DAC A
DATA FLOW
DELAY
MDS CONTROL
AND
GENERATION
MDS internal ref
EARLY/LATE
DETECTOR
early
late
window
DAC A
DAC SLAVE
DAC MASTER
DAC A
DAC CLK
MDS
LVDS align
LVDS data
DAC CLK
MDS
LVDS align
LVDS data
align MDS
adj delay
align MDS
adj delay
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 33 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
During the whole alignment process, the MDS controller tries to adjust the delay to get the
internal copy signal aligned to the external MDS signal. Once aligned, the MDS signal is
not required anymore. it can be switched off at system level. The alignment is done just in
front of the analog DACs cores ensuring the ±1 DAC clock sample accuracy.
At the end of the MDS process, the MDS circuitry is disabled to avoid any analog
disturbances.
The MDS feature can be used in two modes:
•
All slaves mode
•
Master/slaves mode
The mode can be set using the MD_MASTER bit of register MDS_MAIN (see Table 36).
10.13.1.1 MDS in All slaves mode
In this mode, each device uses its ALIGN pins signal to identify the LVDS data flow start
(see Figure 23). The FPGA(s) has(have) to generate these ALIGN signals.
The FPGA is also used to generate the different MDS reference signals to enable the
DAC1617D1G0 devices to do the synchronization of the output. Use this mode when two
or more DAC1617D1G0 devices must be synchronized.
Figure 25 shows the MDS All slave mode schematic.
Fig 25. MDS in All slaves mode
DAC A
align
LD[15:0]
LCLK
MDS
to DEVn
MDS
align
LD[15:0]
LCLK
DAC
DEVICE 2
FPGA1
MDS
REFERENCE
GENERATOR
system
start
reference
FPGA2
DAC B
DAC A
DAC
DEVICE 1
CLOCK
DISTRIBUTION
DAC B
all output
are aligned
DAC CLK1
ref
to FPGAn
DAC CLK2
to device n
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 34 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.13.1.2 MDS in Master/slaves mode
In this mode, one DAC1617D1G0 device is used as master, the other one is used as
slave. The FPGA(s) still has(have) to provide the ALIGN signal to the DAC devices to
identify the LVDS data flow start (see Figure 23). The master generates the reference
MDS signal. The slave uses this signal to do the synchronization of the output. This mode
is recommended when only two DAC1617D1G0 devices must be synchronized.
Figure 25 shows the MDS Master/slaves mode schematic.
10.13.2 MDS flexibility and constraints
Getting a ±1 clock period alignment can become very difficult without the MDS feature.
There are many sources of misalignment:
•
At 1 GHz, two signals with only 15 cm PCB length difference have a 1 clock period
skew. So the PCB traces off the FPGA reference clock, the LVDS data/clock, or the
DAC clock introduce delay.
•
The clock generation circuit can cause delay between the different clocks.
•
The most important delay comes from the internal FPGA design that can cause 1 or 2
LVDS clock delays between the different LVDS data patterns.
The DAC1617D1G0 MDS feature compensates these delays when:
•
The overall delay compensated by the DAC1617D1G0 remains below ±64 DAC clock.
•
Each FPGA has to activate its ALIGN signal with the beginning of the LVDS data flow
start (even if the different ALIGN signals are mis-aligned)
Fig 26. MDS Master/slaves mode
DAC A
align
LD[15:0]
LCLK
MDS (input)
MDS (output)
align
LD[15:0]
LCLK
DAC
SLAVE DEVICE
FPGA1
system
start
reference
FPGA2
DAC B
DAC A
DAC
MASTER DEVICE
CLOCK
DISTRIBUTION
DAC B
all output
are aligned
DAC CLK1
ref DAC CLK2
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 35 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
•
All slave devices use the MDS signals for the fine alignment. Any misalignment
between these signals causes misalignment on the output. Minimize the delay
between the different MDS signals to avoid misalignments:
–In All slave mode: Use a low skew buffer on the FPGA to generate this signal. Use
the same PCB length for all MDS signal trace distributions.
–In Master/slave mode: Minimize the MDS PCB length between the master and the
slave (or compensate the introduced MDS PCB delay manually).
10.14 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
•
•
The output current of DAC A depends on the digital input data. Bits DAC_A_DGAIN[11:0]
of register DAC_A_DGAIN_LSB (see Table 27) define the gain factor.
(6)
(7)
The output current of DAC B depends on the digital input data. Bits DAC_B_DGAIN[11:0]
of register DAC_B_DGAIN_LSB (see Table 27) define the gain factor.
(8)
(9)
It is possible to define if the DAC1617D1G0 operates with a binary input or a
two's complement input (bit CODING; see Table 22).
Table 17 shows the output current as a function of the input data, when
I
OA(fs)
= I
OB(fs)
= 20 mA.
Table 17. DAC transfer function
Data I15 to I0/Q15 to Q0
(binary coding)
I15 to I0/Q15 to Q0
(two’s complement
coding
IOUTAP/IOUTBP IOUTAN/IOUTBN
0 0000 0000 0000 0000 1000 0000 0000 0000 0 mA 20 mA
... ... ... ... ....
32768 1000 0000 0000 0000 0000 0000 0000 0000 10 mA 10 mA
... ... ... ... ...
65535 1111 1111 1111 1111 0111 1111 1111 1111 20 mA 0 mA
I
OA fs( )
I
IO U T A P
I
IOUTA N
+=
I
OB fs )( )
I
IO U TBP
I
IOUT B N
+=
I
IOU T A P
I
OA fs( )
DACADGAIN( )
1024
----------------------------------------- DATA
65535
----------------
××=
I
IOU T A N
I
OA fs( )
1DACADGAIN( )
1024
----------------------------------------- DATA
65535
----------------
×–
×=
I
IOU T B P
I
OB fs( )
DACBDGAIN( )
1024
----------------------------------------- DATA
65535
----------------
××=
I
IOU T B N
I
OB fs( )
1DACBDGAIN( )
1024
----------------------------------------- DATA
65535
----------------
×–
×=
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 36 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.15 Full-scale current
10.15.1 Regulation
The DAC1617D1G0 reference circuitry integrates an internal band gap reference voltage
which delivers a 1.25 V reference on the GAPOUT pin. Decouple pin GAPOUT using a
100 nF capacitor.
The reference current is generated via an external resistor of 910 Ω (1 %) connected to
VIRES. A control amplifier sets the appropriate full-scale current (I
OA(fs)
and I
OB(fs)
) for
both DACs (see Figure 27).
Figure 27 shows the optimal configuration for temperature drift compensation because the
band gap reference voltage can be matched to the voltage across the feedback resistor.
Applying an external reference voltage to the non-inverting input pin GAPOUT and
disabling the internal band gap reference voltage (bit GAP_PON of the COMMON
register; see Table 22) also adjust the DAC current.
10.15.2 Full-scale current adjustment
The default full-scale current (I
O(fs)
) is 20 mA. However, further adjustments, ranging from
8.1 mA to 34 mA, can be made to both DACs independently using the serial interface.
The settings applied to DAC_A_GAIN[9:0] (registers 17h and 18h; see Table 32) define
the full-scale current of DAC A:
(10)
The DAC_B_GAIN[9:0] (registers 19h and 1Ah; see Table 32;) define the full-scale current
of DAC B:
(11)
Fig 27. Internal reference configuration
910 Ω (1 %)
100 nF
DAC
CURRENT
SOURCES
ARRAY
BAND GAP
REFERENCE
GAPOUT
AGND
AGND VIRES
DAC
I
O fs( )
µA( ) 8100 DAC_A_GAIN[9:0] 25.3×+=
I
O fs( )
µA( ) 8100 DAC_B_GAIN[9:0] 25.3×+=
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 37 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.16 Limiter/clip control
A limiter at the end of the data path saturates the output signal in case the signal does not
fit the output range. This feature is activated using the CLIPPING_ENA bit in register
DAC_OUT_CTRL (see Table 28).
The clipping level can be programmed using the CLIPPING_LEVEL register
(see Table 29.). The output range is limited (or clipped) to between
−128x CLIPPING_LEVEL and +128x CLIPPING_LEVEL.
At the DAC analog output, the AC current range is limited to:
(12)
10.17 Digital offset adjustment
The DAC1617D1G0 provides digital offset correction (bits DAC_A_OFFSET[15:0] in
Table 30). This correction can be used to adjust the common-mode level at the output of
each DAC. It adds an offset at the end of the digital part, just before the DACs. Table 18
shows the range of variation of the digital offset.
This offset can be used to remove the LO image at the IQ modulator output.
10.18 Analog output
The device has two output channels, producing two complementary current outputs,
which enable the reduction of even-order harmonics and noise. The pins are
IOUTAP/IOUTAN and IOUTBP/IOUTBN. Connect these pins via a load resistor R
L
to the
3.3 V analog power supply (V
DDA(3V3)
).
Figure 28 shows the equivalent analog output circuit of one DAC. This circuit includes a
parallel combination of NMOS current sources and associated switches for each
segment.
I
O FS( )
2
--------------
–CLIPPING_LEVEL
256
----------------------------------------------------
×I
IO U T
+I
O FS( )
2
--------------
CLIPPING_LEVEL
256
----------------------------------------------------
×≤ ≤
Table 18. Digital offset adjustment
DAC_A_OFFSET[15:0]
DAC_B_OFFSET[15:0]
(two’s complement)
Offset applied
1000 0000 0000 0000 −32768
1000 0000 0000 0001 −32767
... ...
1111 1111 1111 1111 −1
0000 0000 0000 0000 0
0000 0000 0000 0001 +1
... ...
0111 1111 1111 1110 +32766
0111 1111 1111 1111 +32767
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 38 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
The cascode source configuration increases the output impedance of the source, which
improves the dynamic performance of the DAC because there is less distortion.
Depending on the application, the various stages and the targeted performances, the
device can be used for an output level of up to 2 V (p-p).
10.19 Auxiliary DACs
The DAC1617D1G0 integrates two auxiliary DACs, which are used to compensate any
offset between the DACs and the next stage in the transmission path. Both auxiliary DACs
have a 10-bit resolution and are current sources (referenced to ground).
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
•
•
The output current depends on the digital input data set by SPI registers
DAC_A_Aux_MSB (bits AUX_A[9:0]) and DAC_B_Aux_MSB (bits AUX_B[9:0]; see
Table 33).
(13)
(14)
(15)
(16)
Fig 28. Equivalent analog output circuit
RL
IOUTAP/IOUTBP IOUTAN/IOUTBN
3.3 V
GND GND
RL
3.3 V
I
OAUXA fs( )
I
AUXAP
I
AUXAN
+=
I
OAUXB fs( )
I
AUXBP
I
AUXBN
+=
I
AUXAP
I
OAUXA fs( )
DATAA
1023
--------------------
×=
I
AUXAN
I
OAUXA f s( )
1023 DATAA–
1023
--------------------------------------
×=
I
AUXBP
I
OAUXB fs( )
DATAB
1023
--------------------
×=
I
AUXBN
I
OAUXB f s( )
1023 DATAB–
1023
--------------------------------------
×=
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 39 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 19 shows the output current as a function of the auxiliary DACs data DATAA and
DATAB in Equation 13 to Equation 16.
10.20 Output configuration
The DAC1617D1G0 supports various output configurations.
The system application must check that for IOUTA/IOUTB output, the output compliance
range (V
o
) and the common-mode output voltage (V
o(cm)
) specification points are
respected to define other configurations.
Similarly, the system application must check that the output compliance range (V
o
)
specification point is respected for AUXA/AUXB DAC (if used).
The common-mode voltage (V
o(cm)
) value for each IOUTA/IOUTB pin depends on the DC
resistor(s) connected to these pins and the IOUT DC sink currents on these pins.
Equation 17 defines the DC sink output current is:
(17)
Where:
•
I
O(fs)
= full-scale output current
•
I
bias
(DC) = DC bias current
The common-mode voltage (V
o(cm)
) value for each AUXA/AUXB pins depend on the DC
resistor(s) connected to these pins and the AUX DC source currents.
Equation 18 defines these AUX DC source currents:
(18)
Where:
•
I
O(fs)
= full-scale output current
The output compliance range (V
o
) of all DAC outputs depends on the AC resistor load
connected to the DAC:
Table 19. Auxiliary DAC transfer function
DATAA; DATAB AUX_A[9:2]/AUX_A[1:0];
AUX_B[9:0]/AUX_B[1:0]
(binary coding)
I
AUXAP
; I
AUXBP
(mA) I
AUXAN
; I
AUXBN
(mA)
0 00 0000 0000 0 3.1
... ... ... ...
512 10 0000 0000 1.55 1.55
... ... ... ...
1023 11 1111 1111 3.1 0
I
O ksin( )
DC( ) I
bia s
DC( ) I
O fs( )
2
------------
+=
I
O sou rce( )
DC( ) I
O fs( )
2
------------
=
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 40 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
(19)
(20)
Where:
•
V
O(cm)
= common-mode output voltage
•
I
O(fs)
= full-scale output current
•
R
AC
= DAC outputs AC resistor load
10.20.1 Basic output configuration
The use of a differentially coupled transformer output (see Figure 29) provides optimum
distortion performance. In addition, it helps to match the impedance and provides
electrical isolation.
The DAC1617D1G0 can operate a differential output of up to 2 V (p-p). In this
configuration, connect the center tap of the transformer to a 33 Ω resistor, which is
connected to the 3.3 V analog power supply. This adjusts the DC common-mode to
around 2.8 V (see Figure 30).
V
O max( )
V
O cm( )
I
O fs( )
2
------------ R
AC
×+=
V
O min( )
V
O cm( )
I
O fs( )
2
------------ R
AC
×–=
Fig 29. 1 V (p-p) differential output with transformer
50 Ω
50 Ω
2:1
1:1
50 Ω
IOUTAP/IOUTBP
DAC
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 3 V
VO(dif) = 1 V
IOUTAN/IOUTBN
3.3 V
22 Ω
3.3 V
3.3 V
0 mA to 20 mA
0 mA to 20 mA
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 41 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.20.2 Low input impedance IQ-modulator interface
The DAC1617D1G0 can be easily connected to low input impedance IQ-modulators. The
image of the local oscillator can be canceled using the digital offset control in the device.
Figure 31 shows an example of a connection between the DAC1617D1G0 and a low input
impedance modulator.
10.20.3 IQ-modulator - DC interface
When the system operation requires to keep the DC component of the spectrum, the
DAC1617D1G0 can use a DC interface to connect an IQ-modulator. In this case, the
image of the local oscillator can be canceled using the digital offset control in the device.
Fig 30. 2 V (p-p) differential output with transformer
100 Ω
4:1
100 Ω
DAC
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.8 V
VO(dif) = 2 V
3.3 V
33 Ω
50 Ω
3.3 V
3.3 V
0 mA to 20 mA
0 mA to 20 mA
1:1
(1) If R
int
= 100 Ω, then R
ext
= not connected
(2) If R
int
= 200 Ω , then R
ext
= 200 Ω
Fig 31. DAC1617D1G0 with low input impedance IQ-modulator interface
IOUTAP/IOUTBP
3.3 V
DAC IQ modulator
Rint = 100 Ω/200 Ω
50 Ω
Rext Rint
50 Ω
IOUTAN/IOUTBN
AUXAP/AUXBP
AUXAN/AUXBN
BBAP/BBBP
BBAN/BBBN
0 mA to 20 mA
low pass
filter
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.7 V
VO(dif) = 1 V
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 42 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Figure 32 shows an example of a connection to an IQ modulator with a 1.7 V common
input level.
Figure 33 shows an example of a connection to an IQ-modulator with a 3.3 V common
input level.
Fig 32. IQ-modulator: DC interface with a 1.7 V common input level
Fig 33. IQ-modulator: DC interface with a 3.3 V common input level
IOUTAP/IOUTBP
5 V
DAC
68 Ω
54.9 Ω
54.9 Ω
68 Ω
84.5 Ω 84.5 Ω
IOUTAN/IOUTBN
BBAP/BBBP
BBAP/BBAN
BBBP/BBBN
VI(cm) = 1.7 V
VI(dif) = 0.92 V
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.78 V
VO(dif) = 1.52 V
IQ modulator
(VI(cm) = 1.7 V)
BBAN/BBBN
0 mA to 20 mA
100 Ω
low pass
filter
IOUTAP/IOUTBP
5 V
DAC
64.9 Ω
15 Ω
15 Ω
64.9 Ω
205 Ω 205 Ω
IOUTAN/IOUTBN
AUXAP/AUXBP
AUXAN/AUXBN
BBAP/BBBP
BBAP/BBAN
BBBP/BBBN
VI(cm) = 3.3 V
VI(dif) = 0.93 V
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.9 V
VO(dif) = 1.43 V
IQ modulator
(VI(cm) = 3.3 V)
BBAN/BBBN
0 mA to
20 mA
100
Ω
low pass
filter
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 43 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
The auxiliary DACs can be used to control the offset within an accurate range or with
accurate steps.
Figure 34 shows an example of a connection to an IQ-modulator with a 1.7 V common
input level and auxiliary DACs.
The constraints to adjust the interface are:
•
The output compliance range of the DAC
•
The output compliance range of the auxiliary DACs
•
The input common-mode level of the IQ-modulator
•
The range of offset correction
Fig 34. IQ-modulator: DC interface with a 1.7 V common input level and auxiliary DACs
5 V
DAC
69.8 Ω
57.6 Ω
57.6 Ω
69.8 Ω
3.9 Ω 3.9 Ω
78.7 Ω 78.7 Ω
BBAP/BBBP
BBAP/BBAN
BBBP/BBBN
VI(cm) = 1.7 V
VI(dif) = 0.92 V
offset correction = up to 147 mV
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.8 V
VO(dif) = 1.56 V
IQ modulator
(VI(cm) = 1.7 V)
BBAN/BBBN
0 mA to 20 mA
1.59 mA (typical)
100 Ω
low pass
filter
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 44 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.20.4 IQ-modulator - AC interface
Use the DAC1617D1G0 AC-coupled when the IQ-modulator common-mode voltage is
close to ground. The auxiliary DACs are required for local oscillator cancelation.
Figure 35 shows an example of a connection to an IQ-modulator with a 0.5 V common
input level and auxiliary DACs.
10.21 Design recommendations
10.21.1 Power and grounding
Use a separate power supply regulator for the generation of the 1.8 V analog power
(pins 65, 62, 55, 69, 72 and 58) and the 1.8 V digital power (pins 12, 19, 36, 26 and 43) to
ensure optimal performance.
Also, include individual LC decoupling for the following six sets of power pins:
•
V
DDA(1V8)_P1
(pin 62)
•
V
DDA(1V8)_P2
(pin 65)
•
V
DDA(1V8)
(pins 55, 69, 72 and 58)
•
V
DDD
(pins 12, 19, 26, 36, and 43)
•
V
DDA(3V3)
(pins 59 and 68)
Use at least two capacitors for each power pin decoupling. Locate these capacitors as
close as possible to the DAC1617D1G0 power pins.
The die pad is used for both the power dissipation and electrical grounding. Insert several
vias (7 ×7 typical) to connect the internal ground plane to the top layer die area.
Fig 35. IQ-modulator: AC interface with a 0.5 V common input level and auxiliary DACs
IOUTAP/IOUTBP
IOUTAN/IOUTBN
AUXAP/AUXBP
AUXAN/AUXBN
5 V
DAC
91 Ω
10 nF
10 nF
91 Ω
5 V
2.4 kΩ2.4 kΩ
147 Ω 147 Ω
68 Ω 68 Ω
270 Ω 270 Ω
BBAP/BBBP
BBAP/BBAN
BBBP/BBBN
VI(cm) = 0.5 V
VI(dif) = 1 V
offset correction = up to 190 mV
IOUTAP/IOUTAN
IOUTBP/IOUTBN
VO(cm) = 2.9 V
VO(dif) = 1 V
IQ modulator
(VI(cm) = 0.5 V)
BBAN/BBBN
0 mA to
20 mA
105 Ω
low pass
filter
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 45 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22 Configuration interface
10.22.1 Register description
The DAC1617D1G0 incorporates more than the 32 SPI registers allowed by the address
value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each
containing 32 registers. The 32nd register of each page indicates which page is currently
addressed (00h, 01h or 0Ah).
Page 00h (see Table 21) is dedicated to the main control of the DAC1617D1G0:
•
Mode selection
•
NCO control
•
Auxiliary DAC control
•
Gain/phase/offset control
•
Power-down control
Page 01h (see Table 35) is dedicated to:
•
Multi-Device Synchronization (MDS)
•
DAC analog core control (biasing current, Sleep mode)
Page 0Ah (see Table 53) is dedicated to the LVDS input interface configuration.
10.22.2 SPI start-up sequence
The following SPI sequence shows the list of commands to be used to start the
DAC1617D1G25 in interpolation ×4 mode, with NCO frequency = 153.6 MHz
(f
DAC
= 983.04 MHz), PLL bypass mode, and without inverse (sin x) / x. Other start-up
sequences can be easily derived from this sequence:
Table 20. SPI start-up sequence
Step SPI (address, data) Comment
1 Write(0x1F, 0x00) select SPI (page 0)
2 Write(0x00, 0x47) reset SPI
3 Write(0x01, 0x86) set NCO on with positive upper sideband conversion,
interpolation ×4, No inverse (sin x) / x
4 Write(0x02, 0xA0) PLL in bypass mode
5 Write(0x04, 0xFF) select NCO frequency (FREQ_NCO[7:0])
6 Write(0x05, 0xFC) select NCO frequency (FREQ_NCO[15:8])
7 Write(0x06, 0xFF) select NCO frequency (FREQ_NCO[23:16])
8 Write(0x07, 0xFF) select NCO frequency (FREQ_NCO[31:24])
9 Write(0x08, 0x27) select NCO frequency (FREQ_NCO[39:32])
10 Write(0x1F, 0x01) select SPI (page 1)
11 Write(0x15,0x0A) set DAC_current_6 to 0X0A in order to guaranty good
performance over process/temperature/voltage
12 Write(0x1F, 0x0A) select SPI (page A)
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 46 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
13 Write(0x0A, 0x33) specify LVDS interface setting (no DAC A/B swapping, no
parity check, no data enable, …)
14 Write(0x0B, 0x01) set CDI block setting (interpolation ×4, CDI mode)
15 Write(0x00, 0x00) release LVDS reset (start of the DAC1617)
Table 20. SPI start-up sequence
…continued
Step SPI (address, data) Comment
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DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 47 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22.3 Page 0 register allocation map
Table 21 shows an overview of all registers on page 0 (00h in hexadecimal).
Table 21. Page_00 register allocation map
Address Register name R/W Bit definition Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex
0 00h COMMON R/W 3W_SPI SPI_RST - - - CODING IC_PON GAP_PON 1000
0111
87h
1 01h TXCFG R/W NCO_ON NCO_LP
_SEL
INV_SIN
_SEL
MODULATION[2:0] INTERPOLATION[1:0] 0000
0001
01h
2 02h PLLCFG R/W PLL_BP PLL_BUF
_PD
PLL_PLL
_PD
PLL_DIV[1:0] PLL_PHASE[1:0] PLL_
OSC_PD
1010
0001
A1h
4 04h FREQNCO_B0 R/W FREQ_NCO[7:0] 0110
0110
66h
5 05h FREQNCO_B1 R/W FREQ_NCO[15:8] 0110
0110
66h
6 06h FREQNCO_B2 R/W FREQ_NCO[23:16] 0110
0110
66h
7 07h FREQNCO_B3 R/W FREQ_NCO[31:24] 0010
0110
66h
8 08h FREQNCO_B4 R/W FREQ_NCO[39:32] 0010
0110
26h
9 09h PH_CORR_CTL0 R/W PHASE_COR[7:0] 0000
0000
00h
10 0Ah PH_CORR_CTL1 R/W PH_COR
_ENA
- - PHASE_COR[12:8] 0000
0000
00h
11 0Bh DAC_A_DGAIN_LSB R/W DAC_A_DGAIN[7:0] 1101
0100
50h
12 0Ch DAC_A_DGAIN_MSB R/W - - - - DAC_A_DGAIN[11:8] 0000
1011
0Bh
13 0Dh DAC_B_DGAIN_LSB R/W DAC_B_DGAIN[7:0] 1101
0100
50h
14 0Eh DAC_B_DGAIN_MSB R/W - - - - DAC_B_DGAIN[11:8] 0000
0010
0Bh
15 0Fh DAC_OUT_CTRL R/W - - - - A_DGAIN_E B_DGAIN_E MINUS
_3DB
CLIPPING
_ENA
0000
0000
00h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 48 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
16 10h DAC_CLIPPING R/W CLIPPING_LEVEL[7:0] 1111
1111
FFh
17 11h DAC_A_OFFSET_LSB R/W DAC_A_OFFSET[7:0] 0000
0000
00h
18 12h DAC_A_OFFSET_MSB R/W DAC_A_OFFSET[15:8] 0000
0000
00h
19 13h DAC_B_OFFSET_LSB R/W DAC_B_OFFSET[7:0] 0000
0000
00h
20 14h DAC_B_OFFSET_MSB R/W DAC_B_OFFSET[15:8] 0000
0000
00h
21 15h PHINCO_LSB R/W PH_NCO[7:0] 0000
0000
00h
22 16h PHINCO_MSB R/W PH_NCO[15:8] 0000
0000
00h
23 17h DAC_A_GAIN1 R/W DAC_A_GAIN[7:0] 1101
1000
D8h
24 18h DAC_A_GAIN2 R/W DAC_A_GAIN[9:8] - - - - - - 0100
0000
40h
25 19h DAC_B_GAIN1 R/W DAC_B_GAIN[7:0] 1101
1000
D8h
26 1Ah DAC_B_GAIN2 R/W DAC_B_GAIN[9:8] - - - - - - 0100
0000
40h
27 1Bh DAC_A_AUX_MSB R/W AUX_A[9:2] 1000
0000
80h
28 1Ch DAC_A_AUX_LSB R/W AUX_A
_PON
- - - - - AUX_A[1:0] 1000
0000
80h
29 1Dh DAC_B_AUX_MSB R/W AUX_B[9:2] 1000
0000
80h
30 1Eh DAC_B_AUX_LSB R/W AUX_B
_PON
- - - - - AUX_B[1:0] 1000
0000
80h
31 1Fh PAGE_ADDRESS R/W - - - - - PAGE[2:0] 0000
0000
00h
Table 21. Page_00 register allocation map
…continued
Address Register name R/W Bit definition Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 49 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22.4 Page 0 bit definition detailed description
The tables in this section contain detailed descriptions of the page 0 registers.
Table 22. Register COMMON (address 00h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 3W_SPI R/W serial interface bus type
0 4-wire SPI
1 3-wire SPI
6 SPI_RST R/W serial interface reset
0 no reset
1 performs a reset on all registers except address 00h
2 CODING R/W coding of input word
0 two’s complement coding
1 unsigned format
1 IC_PON R/W IC power control
0 all circuits (digital and analog, except SPI) are in
power-down
1 all circuits (digital and analog, except SPI) are
switched on
0 GAP_PON R/W internal band gap power control
0 band gap is power-down
1 internal band gap references are switched on
Table 23. Register TXCFG (address 01h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 NCO_ON R/W NCO
0 NCO disabled, the NCO phase is reset to 0
1 NCO enabled
6 NCO_LP_SEL R/W NCO low-power selection
0 low-power NCO disabled
1 low-power NCO enabled (frequency and phase
given by the five MSB of the registers 06h and 08h,
respectively)
5 INV_SIN_SEL R/W inverse (sin x) / x function selection
0 disable
1 enable
4 to 2 MODULATION[2:0] R/W modulation
000 dual DAC: no modulation
001 positive upper single sideband upconversion
010 positive lower single sideband upconversion
011 negative upper single sideband upconversion
100 negative lower single sideband upconversion
others not defined
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 50 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
1 to 0 INTERPOLATION[1:0] R/W interpolation
00 no interpolation
01 ×
××
×2 interpolation
10 ×4 interpolation
11 ×8 interpolation
Table 23. Register TXCFG (address 01h) bit description
…continued
Default values are shown highlighted.
Bit Symbol Access Value Description
Table 24. Register PLLCFG (address 02h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 PLL_BP R/W PLL bypass
0 DAC clock generated by PLL
1 DAC clock provided via external pins CLKN and
CLKP (PLL bypass mode)
6 PLL_BUF_PD R/W PLL test buffer control
0 Power-down mode
1 enabled
5 PLL_PLL_PD R/W PLL and CKGEN control
0 Power-down mode
1 enable
4 to 3 PLL_DIV[1:0] R/W PLL divider factor
00 f
s
= 2 ×
××
×f
data
01 f
s
= 4 ×f
data
10 f
s
= 8 ×f
11 undefined
2 to 1 PLL_PHASE[1:0] R/W PLL phase shift
00 0 degrees phase shift of f
s
01 120 degrees phase shift of f
s
10 240 degrees phase shift of f
s
11 240 degrees phase shift of f
s
0 PLL_OSC_PD R/W PLL oscillator output power-down
0 Power-down mode
1 enabled
Table 25. NCO frequency registers (address 04h to 08h) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
04h FREQNCO_B0 7 to 0 FREQ_NCO[7:0] R/W NCO frequency (two’s complement
coding)
- least significant 8 bits for the NCO
frequency setting
05h FREQNCO_B1 7 to 0 FREQ_NCO[15:8] R/W - intermediate 8 bits for the NCO
frequency setting
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 51 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
06h FREQNCO_B2 7 to 0 FREQ_NCO[23:16] R/W - intermediate 8 bits for the NCO
frequency setting
07h FREQNCO_B3 7 to 0 FREQ_NCO[31:24] R/W - intermediate 8 bits for the NCO
frequency setting
08h FREQNCO_B4 7 to 0 FREQ_NCO[39:32] R/W - most significant 8 bits for the NCO
frequency setting
Table 25. NCO frequency registers (address 04h to 08h) bit description
…continued
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
Table 26. DAC output phase correction registers (address 09h to 0Ah) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
09h PH_CORR_CTL0 7 to 0 PHASE_COR[7:0] R/W DAC output phase correction factor
(LSB)
- least significant 8 bits for the DAC
output phase correction factor
0Ah PH_CORR_CTL1 7 PH_COR_ENA R/W DAC output phase correction control
0 DAC output phase correction
disabled
1 DAC output phase correction enabled
4 to 0 PHASE_COR[12:8] R/W DAC output phase correction factor MSB
00000 most significant 5 bits for the DAC
output phase correction factor
Table 27. Digital gain control registers (address 0Bh to 0Eh) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
0Bh DAC_A_DGAIN_LSB 7 to 0 DAC_A_DGAIN[7:0] R/W DAC A digital gain control
- least significant 8 bits for the DAC
A digital gain
0Ch DAC_A_DGAIN_MSB 3 to 0 DAC_A_DGAIN[11:8] - most significant 4 bits for the DAC
A digital gain
0Dh DAC_B_DGAIN_LSB 7 to 0 DAC_B_DGAIN[7:0] R/W DAC B digital gain control
- least significant 8 bits for the DAC
B digital gain
0Eh DAC_B_DGAIN_MSB 3 to 0 DAC_B_DGAIN[11:8] - most significant 4 bits for the DAC
B digital gain
Table 28. Register DAC_OUT_CTRL (address 0Fh)
Default values are shown highlighted.
Bit Symbol Access Value Description
3 A_DGAIN_E R/W DAC A digital gain control
0 disable
1 enable
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 52 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
2 B_DGAIN_E R/W DAC B digital gain control
0 disable
1 enable
1 MINUS_3DB R/W DAC attenuation control
0 unity gain
1−3 dB gain
0 CLIPPING_ENA R/W Digital DAC output clipping control
0 disable
1 enable
Table 28. Register DAC_OUT_CTRL (address 0Fh)
…continued
Default values are shown highlighted.
Bit Symbol Access Value Description
Table 29. Register DAC_CLIPPING (address 10h)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 to 0 CLIPPING_LEVEL[7:0] R/W - Digital DAC output clipping level value
Table 30. Digital offset value registers (address 11h to 14h) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
11h DAC_A_OFFSET_LSB 7 to 0 DAC_A_OFFSET[7:0] R/W DAC A digital offset value
- least significant 8 bits for the
DAC A digital offset
12h DAC_A_OFFSET_MSB 7 to 0 DAC_A_OFFSET[15:8] - most significant 8 bits for the
DAC A digital offset
13h DAC_B_OFFSET_LSB 7 to 0 DAC_B_OFFSET[7:0] R/W DAC B digital offset value
- least significant 8 bits for the
DAC B digital offset
14h DAC_B_OFFSET_MSB 7 to 0 DAC_B_OFFSET[15:8] - most significant 8 bits for the
DAC B digital offset
Table 31. NCO phase offset registers (address 15h to 16h) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
15h PHINCO_LSB 7 to 0 PH_NCO[7:0] R/W NCO phase offset LSB
- least significant 8 bits for the NCO phase
setting
16h PHINCO_MSB 7 to 0 PH_NCO[15:8] R/W NCO phase offset MSB
- most significant 8 bits for the NCO phase
setting
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 53 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 32. Analog gain control registers (address 17h to 1Ah) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
17h DAC_A_GAIN1 7 to 0 DAC_A_GAIN[7:0] R/W - DAC A analog gain control (LSB)
18h DAC_A_GAIN2 7 to 6 DAC_A_GAIN[9:8] R/W - DAC A analog gain control (MSB)
19h DAC_B_GAIN1 7 to 0 DAC_B_GAIN[7:0] R/W - DAC B analog gain control (LSB)
1Ah DAC_B_GAIN2 7 to 6 DAC_B_GAIN[9:8] R/W - DAC B analog gain control (MSB)
Table 33. Auxiliary DAC registers (address 1Bh to 1Eh) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
1Bh DAC_A_AUX_MSB 7 to 0 AUX_A[9:2] R/W - most significant 8 bits for auxiliary
DAC A
1Ch DAC_AUX_LSB 7 AUX_A_PON R/W auxiliary DAC A power
0 off
1 on
1 to 0 AUX_A[1:0] R/W - least significant 2 bits for auxiliary
DAC A
1Dh DAC_B_AUX_MSB 7 to 0 AUX_B[9:2] R/W - most significant 8 bits for auxiliary
DAC B
1Eh DAC_B_AUX_LSB 7 AUX_B_PON R/W auxiliary DAC B power
0 off
1 on
1 to 0 AUX_B[1:0] R/W - least significant 2 bits for auxiliary
DAC B
Table 34. SPI_PAGE register (address 1Fh) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
2 to 0 PAGE[2:0] R/W - SPI page address
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 54 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22.5 Page 1 allocation map
Table 35 shows an overview of all registers on page 1 (01h in hexadecimal).
Table 35. Page 1 register allocation map
Address Register name R/W Bit definition Default
[1]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex
0 00h MDS_MAIN R/W MDS_EQCHECK[1:0] MDS_
RUN
MDS_
NCO
MDS_
NCO_
PULSE
MDS_
SREF_
DIS
MDS_
MASTER
MDS_
ENA
0000
0100
04h
1 01h MDS_WIN_
PERIOD_A
R/W MDS_WIN_PERIOD_A[7:0] 1000
0000
80h
2 02h MDS_WIN_
PERIOD_B
R/W MDS_WIN_PERIOD_B[7:0] 0100
0000
40h
3 03h MDS_
MISCCNTRL0
R/W - - - MDS_
EVAL_
ENA
MDS_
PRERUN_E
MDS_PULSEWIDTH[2:0] 0001
0000
10h
4 04h MDS_MAN_
ADJUSTDLY
R/W MDS_
MAN
MDS_MAN_ADJUSTDLY[6:0] 0100
0000
40h
5 05h MDS_AUTO_
CYCLES
R/W MDS_AUTO_CYCLES[7:0] 1000
0000
80h
6 06h MDS_
MISCCNTRL1
R/W MDS_SR_
CKEN
MDS_SR_
LOCKOUT
MDS_
SR_LOCK
MDS_
RELOCK
MDS_LOCK_DELAY[3:0] 0000
1111
0Fh
7 07h MDS_
OFFSET_DLY
RW - - - MDS_OFFSET_DLY[4:0] 0000
0000
00h
8 08h MDS_
ADJDELAY
RW - MDS_ADJDELAY[6:0] 0000
0000
00h
9 09h MDS_
STATUS0
R EARLY LATE EQUAL MDS_EQ EARLY_
ERROR
LATE_
ERROR
EQUAL_
FOUND
MDS_
ACTIVE
uuuu
uuuu
uuh
10 0Ah MDS_
STATUS1
R - - ADD_ERR MDS_EN_PHASE[1:0] MDS_
PRERUN
MDS_
LOCKOUT
MDS_
LOCK
uuuu
uuuu
uuh
11 0Bh INTR_CTRL R/W - - - - - INTR_
CLEAR
INTR_MON_DCLK_
RANGE
0000
0100
04h
12 0Ch INTR_EN R/W MAQB_EN MAQA_EN AUTO_DL_
EN
AUTO_CAL
_EN
FLAG_DL_E
N
LCLKSAMP_
EN
PARBER_
EN
MON_DCLK
_EN
0000
0000
00h
13 0Dh INTR_FLAGS R MAQB_
RDY
MAQA_
RDY
AUTO_
DL_RDY
AUTO_
CAL_RDY
FLAG_
DL_ERR
LCLKSAMP_
ERR
PARBER_
ERR
MON_DCLK
_ERR
uuuu
uuuu
uuh
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 55 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
[1] u = undefined at power-up or after reset.
14 0Eh DAC_
CURRENT_
AUX
R/W - - - - DAC_AUX_BIAS[3:0] 0000
0111
07h
15 0Fh DAC_
CURRENT_0
R/W - - - - DAC_DIG_BIAS[3:0] 0000
0111
07h
16 10h DAC_
CURRENT_1
R/W - - - - DAC_MST_BIAS[3:0] 0000
0111
07h
17 11h DAC_
CURRENT_2
R/W - - - - DAC_DRV_BIAS[3:0] 0000
0111
07h
18 12h DAC_
CURRENT_3
R/W - - - - DAC_SLV_BIAS[3:0] 0000
0111
07h
19 13h DAC_
CURRENT_4
R/W - - - - DAC_CK_BIAS[3:0] 0000
0111
07h
20 14h DAC_
CURRENT_5
R/W - - - - DAC_CAS_BIAS[3:0] 0000
0111
07h
21 15h DAC_
CURRENT_6
R/W - - - - DAC_COM_BIAS[3:0] 0000
0111
07h
22 16h DAC_PON_
SLEEP
R/W DAC_B_
PON
DAC_B_
SLEEP
DAC_B_
COM_PD
DAC_B_
BLEED_
PD
DAC_A_
PD
DAC_A_
SLEEP
DAC_A_
COM_PD
DAC_A_
BLEED_
PD
10111
011
BBh
23 17h DAC_CLKDIG_
DELAY
R/W - - - - - PLL_DIG_DELAY[2:0] 0000
0010
02h
31 1Fh PAGE_
ADDRESS
R/W - - - - - PAGE[2:0] 0000
0000
00h
Table 35. Page 1 register allocation map
…continued
Address Register name R/W Bit definition Default
[1]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 56 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22.6 Page 1 bit definition detailed description
The tables in this section contain detailed descriptions of the page 1 registers.
Table 36. MDS_MAIN register (address 00h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 to 6 MDS_EQCHECK[1:0] R/W lock mode
00 lock when (early = 1 and late = 1)
01 lock when (early = 1, late = 1 and equal = 1)
10 lock when equal = 1
11 force lock (equal-check = 1)
5 MDS_RUN R/W evaluation process restart control
0 no action
1 (0 ≥1) transition restarts evaluation_counter
4 MDS_NCO R/W NCO synchronization
0 no action
1 enable
3 MDS_NCO_PULSE R/W NCO pulse
0 no action
1 manual control NCO tuning
2 MDS_SREF_DIS R/W internal pulse generation
0 normal mode
1 disable
1 MDS_MASTER R/W MDS mode selection
0 slave mode
1 master mode
0 MDS_ENA R/W MDS function control
0 disable
1 enable
Table 37. MDS window time registers (address 01h to 02h) bit description
Legend: * reset value; <= mandatory value
Address Register Bit Symbol Access Value Description
01h MDS_WIN_PERIOD_A 7 to 0 MDS_WIN_
PERIOD_A[7:0]
R/W - determines MDS window LOW time
02h MDS_WIN_PERIOD_B 7 to 0 MDS_WIN_
PERIOD_B[7:0]
R/W - determines MDS window HIGH time
Table 38. MDS_MISCCNTRL0 register (address 03h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
4 MDS_EVAL_ENA R/W MDS evaluation
0 disable
1 enable
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 57 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
3 MDS_PRERUN_ENA R/W automatic MDS start-up
0 no mds_win/mds_ref generation in advance
1 mds_win/mds_ref run-in before mds_evaluation
2 to 0 MDS_PULSEWIDTH[2:0] R/W width of MDS (in output clock -periods)
000 1 DAC clock period
001 2 DAC clock periods
010 to 111 (mds_pulsewidth −1) ×4 DAC clock periods
Table 38. MDS_MISCCNTRL0 register (address 03h) bit description
…continued
Default values are shown highlighted.
Bit Symbol Access Value Description
Table 39. MDS_MAN_ADJUSTDLY register (address 04h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 MDS_MAN R/W adjustment delays mode
0 auto-control adjustment delays
1 manual control adjustment delays
6 to 0 MDS_MAN_ADJUSTDLY[6:0] R/W adjustment delay value
- if MDS_MAN = 0 then initial value adjustment delay
- if MDS_MAN = 1 then controls adjustment delay
Table 40. MDS_AUTO_CYCLES register (address 05h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 to 0 MDS_AUTO_CYCLES[7:0] R/W - number of evaluation cycles applied for MDS. If set to
255, the IC continuously generates/monitors the MDS
pulse
Table 41. MDS_MISCCNTRL1 register (address 06h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 MDS_SR_CKEN R/W - lock mode
0 free-running MDS_SR_CKEN
1 MDS_SR_CKEN forced low
6 MDS_SR_LOCKOUT R/W lockout detector soft reset
0 MDS_SR_LOCKOUT in use
1 MDS_SR_LOCKOUT forced low
5 MDS_SR_LOCK R/W lock detector soft reset
0 MDS_SR_LOCK in use
1 MDS_SR_LOCK forced low
4 MDS_RELOCK R/W relock mode
0 no action
1 relock when lockout occurs
3 to 0 MDS_LOCK_DELAY[3:0] R/W - number of succeeding 'equal' detections until lock
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 58 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 42. MDS_OFFSET_DLY register (address 07h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
4 to 0 MDS_OFFSET_DLY[6:0] R/W - delay offset for dataflow (two’s complement [−16 to 15]
Table 43. MDS_ADJDELAY register (address 08h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
6 to 0 MDS_ADJDELAY[6:0] R - actual value adjustment delay
Table 44. MDS status registers (address 09h to 0Ah) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
09h MDS_STATUS0 7 EARLY R early signal (sampled) from
early-to-late detector
0 false
1 true
6 LATE R late signal (sampled) from
early-to-late detector
0 false
1 true
5 EQUAL R equal signal (sampled) from
early-to-late detector
0 false
1 true
4 MDS_LOCK R result equal-check
0 false
1 true
3 EARLY_ERROR R adjustment delay maximum value
stops the search
0 false
1 true
2 LATE_ERROR R adjustment delay minimum value
stops the search
0 false
1 true
1 EQUAL_FOUND R evaluation logic has detected equal
condition
0 false
1 true
0 MDS_ACTIVE R evaluation logic active
0 false
1 true
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 59 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
0Ah MDS_STATUS1 5 ADD_ERR R adjustment delay error detection
0 OK
1 delay offset cannot be applied in
available range
4 to 3 MDS_EN_PHASE[1:0] R MDS enable phase
00 enable phase = 0
01 enable phase = 1 (only for ×2)
10 enable phase = 2
(only for ×2 and ×4)
11 enable phase = 3 (only for ×2)
2 MDS_PRERUN R MDS-PRERUN phase active flag
0 false
1 true
1 MDS_LOCKOUT R MDS_LOCKOUT detected flag
0 false
1 true
0 MDS_LOCK R MDS_LOCK flag
0 false
1 true
Table 44. MDS status registers (address 09h to 0Ah) bit description
…continued
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
Table 45. Interrupt control register (address 0Bh) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
3 INTR_CTRL R/W internal interrupt and flags clearance
0 disabled
1 enabled
2 to 0 INTR_MON_DCLK_RANGE R/W Interrupt condition as related to the DCLK monitoring
00 mon_dclk_flag when mon_dclk drifts to (1 or 5)
(detect small drift)
01 mon_dclk_flag when mon_dclk drifts to (2 or 4)
(detect large drift)
10 mon_dclk_flag when mon_dclk drifts to (3)
(detect maximum drift)
11 mon_dclk_flag disabled
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 60 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 46. Interrupt enable register (address 0Ch) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 MAQB_EN R/W acquisition module B interrupt
0 disabled
1 enabled
6 MAQA_EN R/W acquisition module A interrupt
0 disabled
1 enabled
5 AUTO_DL_EN R/W automatic download MTP interrupt
0 disabled
1 enabled
4 AUTO_CAL_EN R/W LVDS automatic calibration interrupt
0 disabled
1 enabled
3 FLAG_DL_EN R/W MTP download error interrupt
0 disabled
1 enabled
2 LCLKSAMP_EN R/W lclk sampling monitor error interrupt
0 disabled
1 enabled
1 PARBER_EN R/W LVDS parity or ber error interrupt
0 disabled
1 enabled
0 MON_DCLK_EN R/W dclk monitor error interrupt
0 disabled
1 enabled
Table 47. INTR_FLAGS register (address 0Dh) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 MAQB_RDY R acquisition module B status
0 not ready
1 ready
6 MAQA_RDY R acquisition module A status
0 not ready
1 ready
5 AUTO_DL_RDY R automatic download MTP status
0 not ready
1 ready
4 AUTO_CAL_RDY R LVDS automatic calibration status
0 not ready
1 ready
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 61 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
[1] All default values (except for register DAC_current_6) are OK for good performance over Process Voltage and Temperature.
[2] The register DAC_current_6 (address 0X15) must be set to 0X0A.
3 FLAG_DL_ERR R error during MTP download
0 no error
1 error detected
2 LCLKSAMP_ERR R error on lclk sampling monitor
0 no error
1 error detected
1 PARBER_ERR R error on LVDS parity or ber error
0 no error
1 error detected
0 MON_DCLK_ERR R error on dclk monitor
0 no error
1 error detected
Table 47. INTR_FLAGS register (address 0Dh) bit description
…continued
Default values are shown highlighted.
Bit Symbol Access Value Description
Table 48. Bias current control registers (address 0Eh to 15h) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
0Eh DAC_CURRENT_AUX 3 to 0 DAC_AUX_BIAS[3:0] R/W - bias current control
(see Table 49)
0Fh DAC_CURRENT_0 3 to 0 DAC_DIG_BIAS[3:0] R/W -
10h DAC_CURRENT_1 3 to 0 DAC_MST_BIAS[3:0] R/W -
11h DAC_CURRENT_2 3 to 0 DAC_DRV_BIAS[3:0] R/W -
12h DAC_CURRENT_3 3 to 0 DAC_SLV_BIAS[3:0] R/W -
13h DAC_CURRENT_4 3 to 0 DAC_CK_BIAS[3:0] R/W -
14h DAC_CURRENT_5 3 to 0 DAC_CAS_BIAS[3:0] R/W -
15h DAC_CURRENT_6 3 to 0 DAC_COM_BIAS[3:0] R/W -
Table 49. Bias current control table
BIAS[3:0] Deviation from nominal current
0 0 0 0 −35 %
0 0 0 1 −30 %
0 0 1 0 −25 %
0 0 1 1 −20 %
0 1 0 0 −15 %
0 1 0 1 −10 %
0 1 1 0 −5 %
0 1 1 1 +0 % (default)
1 0 0 0 +5 %
1 0 0 1 +10 %
1 0 1 0 +15 %
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 62 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
1 0 1 1 +20 %
1 1 0 0 +25 %
1 1 0 1 +30 %
1 1 1 0 +35 %
1 1 1 1 +40 %
Table 49. Bias current control table
…continued
BIAS[3:0] Deviation from nominal current
Table 50. DAC_PON_SLEEP register (address 16h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
7 DAC_B_PON R/W - DAC B power control
0 power-down
1 power on
6 DAC_B_SLEEP R DAC B mode selection
0 normal operation
1 Sleep mode
5 DAC_B_COM_PD R commutator B control
0 disable (power-down)
1 enable
4 DAC_B_BLEED_PD R DAC B bleed current control
0 disable (power-down)
1 enable
3 DAC_A_PON R DAC A power control
0 power-down
1 power on
2 DAC_A_SLEEP R DAC B mode selection
0 normal operation
1 Sleep mode
1 DAC_A_COM_PD R commutator A control
0 disable (power-down)
1 enable
0 DAC_A_BLEED_PD R DAC A bleed current control
0 disable (power-down)
1 enable
Table 51. DAC_TEST_8 register (address 17h) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
2 to 0 PLL_DIG_DELAY[2:0] R/W - digital clock delay offset of PLL/CKGEN_DIV8
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 63 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 52. SPI_PAGE register (address 1Fh) bit description
Default values are shown highlighted.
Bit Symbol Access Value Description
2 to 0 PAGE[2:0] R/W - SPI page address
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 64 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22.7 Page A register allocation map
Table 53 shows an overview of all registers on page A (0Ah in hexadecimal).
Table 53. Page_0A register allocation map
Address Register name R/W Bit definition Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex
0 00h MAIN_CNTRL R/W - - - LD_PD PD_CNTRL CAL_
CNTRL
RST_
DCKL
RST_
LCKL
0000
0011
03h
1 01h MAN_LDCLKDEL R/W - - - - LDCLK_DEL[3:0] 0000
0000
00h
2 02h DBG_LVDS R/W - - - - SBER RESERVED 0000
0000
00h
4 04h RST_EXT_LDCLK R/W RST_EXT_LCLK_TIME[7:0] 0011
1111
3Fh
5 05h RST_EXT_DCLK R/W RST_EXT_DCLK_TIME[7:0] 0010
0000
20h
6 06h DCMSU_PREDIV R/W DCMSU_PREDIVIDER[7:0] 0001
1101
1Dh
8 08h LD_POL_LSB R/W LD_POL[7:0] 0000
0000
00h
9 09h LD_POL_MSB R/W LD_POL[15:8] 0000
0000
00h
10 0Ah LD_CNTRL R/W PARITYC DESCRAMBLE SEL_EN[1:0] WORD_SWAP LDAB_
SWAP
IQ_
FORMAT
EDGE_
LDCLK
0000
0011
03h
11 0Bh MISC_CNTRL R/W SR_CDI RESERVED I_LEV_
CNTRL[1:0]
Q_LEV_CNTRL[1:0] CDI_MODE[1:0] 0000
0000
00h
12 0Ch I_DC_LVL_LSB R/W I_DC_LEVEL[7:0] 0000
0000
00h
13 0Dh I_DC_LVL_MSB R/W I_DC_LEVEL[15:8] 1000
0000
80h
14 0Eh Q_DC_LVL_LSB R/W Q_DC_LEVEL[7:0] 0000
0000
00h
15 0Fh Q_DC_LVL_MSB R/W Q_DC_LEVEL[15:8] 1000
0000
80h
16 10h IO_MUX0 R/W IO_SELECT0[7:0] 1111
1111
FFh
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 65 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
17 11h IO_MUX1 R/W IO_SELECT1[7:0] 1111
1111
FFh
18 12h IO_MUX2 R/W IO_SELECT1[9:8] - IO_SELECT0[9:8] - 1111
1111
FFh
27 1Bh TYPE_ID R DAC FRONTEND[1:0] DUAL DSP[1:0] BIT_RES[1:0] 0011
1010
3Ch
28 1Ch DAC_VERSION R DAC_VERSION_ID[7:0] 0010
1001
29h
29 1Dh DIG_VERSION R DIG_VERSION_ID[7:0] 0000
0100
04h
30 1Eh LD_VERSION R LVDS_VERSION_ID[7:0] 0000
1001
09h
31 1Fh PAGE_ADDRESS R/W - - - - - PAGE[2:0] 0000
0000
00h
Table 53. Page_0A register allocation map
…continued
Address Register name R/W Bit definition Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 66 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.22.8 Page A bit definition detailed description
The tables in this section contain detailed descriptions of the page A registers.
Table 54. Register MAIN_CNTRL (address 00h)
Default values are shown highlighted.
Bit Symbol Access Value Description
4 LD_PD R/W LVDS interface power-down (control possible only
when PD_CNTRL = 1)
0 switched on
1 switched off
3 PD_CNTRL R/W power-down modes controlled by
0 DCMSU block
1 SPI registers
2 CAL_CNTRL R/W compensation delay controlled by
0 DCMSU block (automatic calibration)
1 SPI registers (manual control)
1 RST_DCLK R/W reset DCLK
0 disable
1 enable
0 RST_LCLK R/W reset LVDS clock
0 disable
1 enable
Table 55. Register MAN_LDCLKDEL (address 01h)
Default values are shown highlighted.
Bit Symbol Access Value Description
3 to 0 LDCLK_DEL[3:0] R/W LVDS clock compensation delay (control only if
CAL_CNTRL = 1)
- 4-bit compensation delay for LVDS clock
Table 56. Register DBG_LVDS (address 02h)
Default values are shown highlighted.
Bit Symbol Access Value Description
3 SBER R/W simple BER control
0 no action
1 simple BER active
2 to 0 RESERVED R/W 000 reserved
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 67 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 57. Extension time reset registers (address 04h to 05h) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
04h RST_EXT_LCLK 7 to 0 RST_EXT_LCLK_
TIME[7:0]
R/W specifies extension time reset,
expressed in LVDS clock periods
- 8 bits for the extension time reset
05h RST_EXT_DCLK 7 to 0 RST_EXT_DCLK_
TIME[7:0]
R/W specify extension time reset,
expressed in DCLK periods
- 8 bits for the extension time reset
Table 58. Register DCSMU_PREDIV (address 06h)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 to 0 DCMSU_PREDIVIDER[7:0] R/W predivider value for the DCMSU, expressed in LVDS
clock period
- 8 bits for the predivider value
Table 59. LSB/MSB of polarity registers (address 08h to 09h) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
08h LD_POL_LSB 7 to 0 LD_POL[7:0] R/W toggles polarity of corresponding bit
pair within LD[7:0]
- most significant 6 bits for the
polarity toggle
09h LD_POL_MSB 7 to 0 LD_POL[15:8] - most significant 6 bits for the
polarity toggle
Table 60. Register LD_CNTRL (address 0Ah)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 PARITYC R/W parity check
0 disable
1 enable
6 DESCRAMBLE R/W Descramble control
0 disable descrambling
1 enable descrambling
5 to 4 SEL_EN[1:0] R/W LDVS data enable
00 LVDS data enable = align signal from channel A
01 LVDS data enable = align signal from channel B
10 LVDS data enable = 0
11 LVDS data enable = 1
3 WORD_SWAP R/W reverse order for LVDS path
0 normal operation
1 MSB to LSB order reversed
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 68 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
2 LDAB_SWAP R/W swaps LVDS A and LVDS B paths
0 normal operation
1 LVDS A and LVDS B paths are swapped
1 IQ_FORMAT R/W specify IQ supplied format
0 folded
1 interleaved
0 EDGE_LDCLK R/W specify sampling edge for LVDS data path
0 falling edge of LDCLK
1 rising edge of LDCLK
Table 60. Register LD_CNTRL (address 0Ah)
…continued
Default values are shown highlighted.
Bit Symbol Access Value Description
Table 61. Register MISC_CNTRL (address 0Bh)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 SR_CDI R/W CDI block software reset control
0 no action
1 perform a software reset on CDI
6 RESERVED R/W 0 reserved
5 to 4 I_LEV_CNTRL[1:0] R/W specifies output from CDI for I path
00 normal operation (CDI data output sent to digital
signal processing input)
01 if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = I_DC_LEVEL register value
10 digital signal processing input = I_DC_LEVEL
11 digital signal processing input = I_DC_LEVEL
3 to 2 Q_LEV_CNTRL[1:0] R/W specifies output from CDI for Q path
00 normal operation (CDI data output sent to digital
signal processing input)
01 if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = Q_DC_LEVEL register value
10 digital signal processing input = Q_DC_LEVEL
11 digital signal processing input = Q_DC_LEVEL
1 to 0 CDI_MODE[1:0] R/W specifies CDI mode
00 cdi_mode 0 (×
××
×2 mode)
01 cdi_mode 1 (×4 mode)
10 cdi_mode 2 (×8 mode)
11 not used
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 69 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 62. LDS/MDS of I/Q DC levels registers (address 0Ch to 0Fh) bit description
Default values are shown highlighted.
Address Register Bit Symbol Access Value Description
0Ch I_DC_LVL_LSB 7 to 0 I_DC_LEVEL[7:0] R/W I_DC_LEVEL
- least significant 8 bits for
I_DC_LEVEL
0Dh I_DC_LVL_MSB 7 to 0 I_DC_LEVEL[15:8] - most significant 8 bits for
I_DC_LEVEL
0Eh Q_DC_LVL_LSB 7 to 0 Q_DC_LEVEL[7:0] R/W Q_DC_LEVEL
- least significant 8 bits for
Q_DC_LEVEL
0Fh Q_DC_LVL_MSB 7 to 0 Q_DC_LEVEL[15:8] - most significant 8 bits for
Q_DC_LEVEL
Table 63. Register IO_MUX0 and IO_MUX2 (address 10h and 12h)
Default values are shown highlighted.
IO_SELECT0[9:0] Signal on pin IO0 Description
00 0000 0000 lclk internal LVDS lclk clock
00 0000 0001 ringo internal low frequency oscillator
(approximately 1 MHz)
01 0000 nnnn Ldout_A<nnnn> internal LVDS data bit of
channel A (<nnnn> = 15 to 0;
enabling the selection of the bit
number to be observed)
10 0000 1111 AND (Ldout_B bits) AND result of the 16 LVDS data
bits of channel B
10 0001 1111 OR (Ldout_B bits) OR result of the 16 LVDS data
bits of channel B
10 0010 1111 AND (Ldout_A bits) AND result of the 16 LVDS data
bits of channel A
10 0011 1111 OR (Ldout_A bits) OR result of the 16 LVDS data
bits of channel A
11 1100 0000 INTR active low interrupt signal
11 1100 0001 INTR active high interrupt signal
11 1111 1110 1 set the general-purpose IO to
high level
11 1111 1111 0 set the general-purpose IO to
low level
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 70 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 64. Register IO_MUX1 and IO_MUX2 (address 11h and 12h)
Default values are shown highlighted.
IO_SELECT1[9:0] Signal on pin IO1 Description
00 0000 0000 dclk internal dclk clock (f
s
/ 8
frequency)
01 0000 nnnn Ldout_B<nnnn> internal LVDS data bit of
channel B (<nnnn> = 15 to 0;
enabling the selection bit
number to be observed)
10 0000 1111 AND (Ldout_B bits) AND result of the 16 LVDS data
bits of channel B
10 0001 1111 OR (Ldout_B bits) OR result of the 16 LVDS data
bits of channel B
10 0010 1111 AND (Ldout_A bits) AND result of the 16 LVDS data
bits of channel A
10 0011 1111 OR (Ldout_A bits) OR result of the 16 LVDS data
bits of channel A
11 1100 0000 INTR active low interrupt signal
11 1100 0001 INTR active high interrupt signal
11 1111 1110 0 set the general-purpose IO to
low level
11 1111 1111 1 set the general-purpose IO to
high level
Table 65. Register TYPE_ID (address 1Bh)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 DAC R calibration
0 uncalibrated device
1 calibrated device
6 to 5 FRONTEND R 01 LVDS input interface
4 DUAL R 0 dual DAC
3 to 2 DSP R internal digital signal processing
11 interpolation filter + SSBM
10 SSBM
01 interpolation filter
00 none
1 to 0 BIT_RES R DAC bit resolution
00 16 bits
01 14 bits
10 12 bits
11 10 bits
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 71 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 66. Register DAC_VERSION (address 1Ch)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 to 0 DAC_VERSION_ID[7:0] R DAC version number
- 8 bits for the DAC version number
Table 67. Register DIG_VERSION (address 1Dh)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 to 0 DIG_VERSION_ID[7:0] R digital version number
- 8 bits for the digital version number
Table 68. Register LVDS_VERSION (address 1Eh)
Default values are shown highlighted.
Bit Symbol Access Value Description
7 to 0 LVDS_VERSION_ID[7:0] R LVDS receiver version number
- 8 bits for the LVDS receiver version number
Table 69. Register PAGE_ADD (address 1Fh)
Default values are shown highlighted.
Bit Symbol Access Value Description
2 to 0 PAGE[2:0] R/W Page address
- current page address
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 72 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
11. Package outline
Fig 36. Package outline SOT813-3 (HVQFN72)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT813-3 - - -
- - -
- - -
sot813-3_po
10-04-02
11-06-20
Unit
mm
max
nom
min
1.00
0.85
0.80
0.05
0.02
0.00
0.2
10.1
10.0
9.9
7.2
7.1
7.0
10.1
10.0
9.9
0.5 8.5
0.5
0.4
0.3
0.1
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN72: plastic thermal enhanced very thin quad flat package; no leads;
72 terminals; body 10 x 10 x 0.85 mm SOT813-3
A1b
0.30
0.21
0.18
c D(1) DhE(1) Eh
7.2
7.1
7.0
e e1e2
8.5
L v
0.1
w
0.05
y
0.05
y1
0 5 10 mm
scale
terminal 1
index area
B A
D
E
C
y
C
y1
X
detail X
A
c
A1
b
e2
e1
e
e
1/2 e
1/2 e AC B
v
Cw
terminal 1
index area Dh
Eh
1
18
L
19 36
37
54
5572
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 73 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
12. Abbreviations
Table 70. Abbreviations
Acronym Description
BW BandWidth
BWA Broadband Wireless Access
CDI Clock Domain Interface
CDMA Code Division Multiple Access
CML Current Mode Logic
CMOS Complementary Metal Oxide Semiconductor
DAC Digital-to-Analog Converter
EDGE Enhanced Data rates for GSM Evolution
FIR Finite Impulse Response
GSM Global System for Mobile communications
IF Intermediate Frequency
IMD3 Third Order InterModulation
LMDS Local Multipoint Distribution Service
LO Local Oscillator
LVDS Low-Voltage Differential Signaling
NCO Numerically Controlled Oscillator
NMOS Negative Metal-Oxide Semiconductor
PLL Phase-Locked Loop
SFDR Spurious-Free Dynamic Range
SPI Serial Peripheral Interface
WCDMA Wide band Code Division Multiple Access
WLL Wireless Local Loop
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 74 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
13. Glossary
13.1 Static parameters
INL — The deviation of the transfer function from a best fit straight line (linear regression
computation).
DNL — The difference between the ideal and the measured output value between
successive DAC codes.
13.2 Dynamic parameters
Spurious-Free Dynamic Range (SFDR) — The ratio between the RMS value of the
reconstructed output sine wave and the RMS value of the largest spurious observed
(harmonic and non-harmonic, excluding DC component) in the frequency domain.
Decibels relative to full scale (dBFS) — Unit used in a digital system to measure the
amplitude level in decibel relative to the maximum peak value.
InterModulation Distortion (IMD) — From a dual-tone digital input sine wave (these two
frequencies being close together), the intermodulation distortion products IMD2 and IMD3
(second order and third order components) are defined below.
IMD2 — The ratio between the RMS value of either tone and the RMS value of the worst
second order Intermodulation product.
IMD3 — The ratio between the RMS value of either tone and the RMS value of the worst
third order Intermodulation product.
Total Harmonic Distortion (THD) — The ratio between the RMS value of the harmonics
of the output frequency and the RMS value of the output sine wave. Usually, the
calculation of THD is done on the first 5 harmonics.
Signal-to-Noise Ratio (SNR) — The ratio between the RMS value of the reconstructed
output sine wave and the RMS value of the noise excluding the harmonics and the DC
component.
Restricted BandWidth Spurious-Free Dynamic Range (SFDR
RBW
) — The ratio
between the RMS value of the reconstructed output sine wave and the RMS value of the
noise, including the harmonics, in a given bandwidth centered around f
offset
.
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 75 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Contact information
6024 Silver Creek Valley Road
San Jose, California 95138
14. Revision history
Table 71. Revision history
Document ID Release date Data sheet status Change notice Supersedes
DAC1617D1G0 v.4 20120720 Product data sheet - DAC1716D1G0 v.3
DAC1617D1G0 v.3 20120702 Rebranded/updated - DAC1617D1G0 v.2
DAC1617D1G0 v.2 20120630 Preliminary data sheet - DAC1617D1G0 v.1.1
DAC1617D1G0 v.1.1 20110930 Objective data sheet - DAC1617D1G0 v.1
DAC1617D1G0 v.1 20110906 Objective data sheet - -
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 76 of 78
continued >>
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
15. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 4. Thermal characteristics . . . . . . . . . . . . . . . . . . .7
Table 5. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 6. Read or Write mode access description . . . . .15
Table 7. Number of bytes transferred . . . . . . . . . . . . . .15
Table 8. SPI timing characteristics . . . . . . . . . . . . . . . .16
Table 9. Input LVDS bus swapping . . . . . . . . . . . . . . . .18
Table 10. Folded and interleaved format mapping . . . . . .19
Table 11. CDI mode 0: operating modes examples . . . .24
Table 12. CDI mode 1: operating modes examples . . . .25
Table 13. CDI mode 2: operating modes examples . . . .25
Table 14: Interpolation filter coefficients . . . . . . . . . . . . .27
Table 15. Complex modulator operation mode . . . . . . . .30
Table 16. Inversion filter coefficients . . . . . . . . . . . . . . . .30
Table 17. DAC transfer function . . . . . . . . . . . . . . . . . . .35
Table 18. Digital offset adjustment . . . . . . . . . . . . . . . . .37
Table 19. Auxiliary DAC transfer function . . . . . . . . . . . .39
Table 20. SPI start-up sequence . . . . . . . . . . . . . . . . . . .45
Table 21. Page_00 register allocation map . . . . . . . . . . .47
Table 22. Register COMMON (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 23. Register TXCFG (address 01h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 24. Register PLLCFG (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 25. NCO frequency registers (address 04h to 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 26. DAC output phase correction registers
(address 09h to 0Ah) bit description . . . . . . . .51
Table 27. Digital gain control registers (address 0Bh to 0Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 28. Register DAC_OUT_CTRL (address 0Fh) . . .51
Table 29. Register DAC_CLIPPING (address 10h) . . . . .52
Table 30. Digital offset value registers (address 11h to 14h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 31. NCO phase offset registers (address 15h to 16h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 32. Analog gain control registers (address 17h to 1Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 33. Auxiliary DAC registers (address 1Bh to 1Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 34. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 35. Page 1 register allocation map . . . . . . . . . . . .54
Table 36. MDS_MAIN register (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 37. MDS window time registers (address 01h to 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 38. MDS_MISCCNTRL0 register (address 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 39. MDS_MAN_ADJUSTDLY register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 40. MDS_AUTO_CYCLES register (address 05h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 41. MDS_MISCCNTRL1 register (address 06h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 42. MDS_OFFSET_DLY register (address 07h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 43. MDS_ADJDELAY register (address 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 44. MDS status registers (address 09h to 0Ah)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 45. Interrupt control register (address 0Bh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 46. Interrupt enable register (address 0Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 47. INTR_FLAGS register (address 0Dh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 48. Bias current control registers (address 0Eh to 15h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 49. Bias current control table . . . . . . . . . . . . . . . . 61
Table 50. DAC_PON_SLEEP register (address 16h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 51. DAC_TEST_8 register (address 17h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 52. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 53. Page_0A register allocation map . . . . . . . . . . 64
Table 54. Register MAIN_CNTRL (address 00h) . . . . . . 66
Table 55. Register MAN_LDCLKDEL (address 01h) . . . 66
Table 56. Register DBG_LVDS (address 02h) . . . . . . . . 66
Table 57. Extension time reset registers
(address 04h to 05h) bit description . . . . . . . . 67
Table 58. Register DCSMU_PREDIV (address 06h) . . . 67
Table 59. LSB/MSB of polarity registers
(address 08h to 09h) bit description . . . . . . . . 67
Table 60. Register LD_CNTRL (address 0Ah) . . . . . . . . 67
Table 61. Register MISC_CNTRL (address 0Bh) . . . . . . 68
Table 62. LDS/MDS of I/Q DC levels registers
(address 0Ch to 0Fh) bit description . . . . . . . . 69
Table 63. Register IO_MUX0 and IO_MUX2
(address 10h and 12h) . . . . . . . . . . . . . . . . . . 69
Table 64. Register IO_MUX1 and IO_MUX2
(address 11h and 12h) . . . . . . . . . . . . . . . . . . 70
DAC1617D1G0 © IDT 2012. All rights reserved.
Product data sheet Rev. 4 — 12 December 2012 77 of 78
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 65. Register TYPE_ID (address 1Bh) . . . . . . . . . .70
Table 66. Register DAC_VERSION (address 1Ch) . . . . .71
Table 67. Register DIG_VERSION (address 1Dh) . . . . .71
Table 68. Register LVDS_VERSION (address 1Eh) . . . .71
Table 69. Register PAGE_ADD (address 1Fh) . . . . . . . .71
Table 70. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 71. Revision history . . . . . . . . . . . . . . . . . . . . . . . .75
Integrated Device Technology
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Disclaimer
Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion.
All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters
of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual
property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the
health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are
the property of IDT or their respective third party owners.
Copyright, 2012. All rights reserved.
16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Thermal characteristics . . . . . . . . . . . . . . . . . . 7
9 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Application information. . . . . . . . . . . . . . . . . . 14
10.1 General description . . . . . . . . . . . . . . . . . . . . 14
10.2 Serial Peripheral Interface (SPI). . . . . . . . . . . 14
10.2.1 Protocol description . . . . . . . . . . . . . . . . . . . . 14
10.2.2 SPI timing description . . . . . . . . . . . . . . . . . . . 16
10.3 Power-on sequence . . . . . . . . . . . . . . . . . . . . 16
10.4 LVDS Data Input Format (DIF) block . . . . . . . 17
10.4.1 Input port polarity . . . . . . . . . . . . . . . . . . . . . . 17
10.4.2 Input port mapping . . . . . . . . . . . . . . . . . . . . . 17
10.4.3 Input port swapping . . . . . . . . . . . . . . . . . . . . 18
10.4.4 Input port formatting . . . . . . . . . . . . . . . . . . . . 19
10.4.5 Data parity/data enable. . . . . . . . . . . . . . . . . . 20
10.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20
10.6 General-purpose IO pins . . . . . . . . . . . . . . . . 20
10.7 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.7.1 LVDS DDR clock. . . . . . . . . . . . . . . . . . . . . . . 20
10.7.2 DAC core clock . . . . . . . . . . . . . . . . . . . . . . . . 21
10.8 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.9 Operating modes . . . . . . . . . . . . . . . . . . . . . . 23
10.9.1 CDI mode 0 (x2 interpolation). . . . . . . . . . . . . 24
10.9.2 CDI mode 1 (x4 interpolation). . . . . . . . . . . . . 25
10.9.3 CDI mode 2 (x8 interpolation). . . . . . . . . . . . . 25
10.10 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.11 Single SideBand Modulator (SSBM). . . . . . . . 28
10.11.1 NCO in 40 bits . . . . . . . . . . . . . . . . . . . . . . . . 29
10.11.2 NCO low power . . . . . . . . . . . . . . . . . . . . . . . 29
10.11.3 Complex modulator . . . . . . . . . . . . . . . . . . . . 29
10.11.4 Minus 3dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.12 Inverse (sin x) / x . . . . . . . . . . . . . . . . . . . . . . 30
10.13 Multiple Devices Synchronization (MDS). . . . 31
10.13.1 MDS concept . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.13.1.1 MDS in All slaves mode . . . . . . . . . . . . . . . . . 33
10.13.1.2 MDS in Master/slaves mode . . . . . . . . . . . . . 34
10.13.2 MDS flexibility and constraints . . . . . . . . . . . . 34
10.14 DAC transfer function. . . . . . . . . . . . . . . . . . . 35
10.15 Full-scale current . . . . . . . . . . . . . . . . . . . . . . 36
10.15.1 Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.15.2 Full-scale current adjustment. . . . . . . . . . . . . 36
10.16 Limiter/clip control . . . . . . . . . . . . . . . . . . . . . 37
10.17 Digital offset adjustment. . . . . . . . . . . . . . . . . 37
10.18 Analog output. . . . . . . . . . . . . . . . . . . . . . . . . 37
10.19 Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 38
10.20 Output configuration. . . . . . . . . . . . . . . . . . . . 39
10.20.1 Basic output configuration . . . . . . . . . . . . . . . 40
10.20.2 Low input impedance IQ-modulator
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.20.3 IQ-modulator - DC interface. . . . . . . . . . . . . . 41
10.20.4 IQ-modulator - AC interface . . . . . . . . . . . . . . 44
10.21 Design recommendations . . . . . . . . . . . . . . . 44
10.21.1 Power and grounding. . . . . . . . . . . . . . . . . . . 44
10.22 Configuration interface. . . . . . . . . . . . . . . . . . 45
10.22.1 Register description . . . . . . . . . . . . . . . . . . . . 45
10.22.2 SPI start-up sequence . . . . . . . . . . . . . . . . . . 45
10.22.3 Page 0 register allocation map . . . . . . . . . . . 47
10.22.4 Page 0 bit definition detailed description . . . . 49
10.22.5 Page 1 allocation map . . . . . . . . . . . . . . . . . . 54
10.22.6 Page 1 bit definition detailed description . . . . 56
10.22.7 Page A register allocation map . . . . . . . . . . . 64
10.22.8 Page A bit definition detailed description . . . . 66
11 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 72
12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 73
13 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . 74
13.2 Dynamic parameters . . . . . . . . . . . . . . . . . . . 74
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 75
15 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
