DEMO MANUAL DC1954A LTC6954 Low Phase Noise, Triple Output Clock Distribution Divider/Driver Description Demonstration Circuit 1954A features the LTC(R)6954, a Low Phase Noise, Triple Output Clock Distribution Divider/ Driver. 0.5" spaced SMA connectors. The LTC6954's EZSyncTM function is made available via a turret and an SMA connector. There are four options of the DC1954A, one for each version of the LTC6954. Table 1 summarizes the available DC1954A options. A DC590 USB serial controller board is used for SPI communication with the LTC6954, controlled by the supplied LTC6954_GUI software. The DC1954A LVPECL outputs are AC-coupled 50 transmission lines making them suitable for driving 50 impedance instruments. The LVDS/CMOS outputs of the DC1954A are terminated with a 100 differential resistor and are DC-coupled. All differential input and outputs have Design files for this circuit board are available at http://www.linear.com/demo/DC1954A 3.3V DC Supply, banana jack & turret L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. GND, banana jack & turret Ribbon cable connection to DC590 OUT0 Outputs, SMA LTC69541/2/3 LVPECL, AC coupled LTC69544 LVDS/CMOS, DC coupled OUT1 Outputs, SMA LTC69541/2 LVPECL, AC coupled IN Inputs, SMA AC coupled LTC69543/4 LVDS/CMOS, DC coupled OUT2 Outputs, SMA LTC69541 LVPECL, AC coupled EZSyncTM SYNC Input, SMA & turret Temperature monitoring diode, turret OUTxSEL Inputs, Headers For LVPECL OUTPUTS: H=IBIAS ON; L=IBIAS OFF LTC69542/3/4 LVDS/CMOS, DC coupled For LVDS/CMOS OUTPUTS: H=LVDS; L=CMOS Figure 1. DC1954A Connections dc1954af 1 DEMO MANUAL DC1954A Quick Start Procedure The DC1954A is easy to set up to evaluate the performance of the LTC6954. Follow the procedure below. Connect the DC590 to one of your computer's USB ports with the included USB cable. The DC590 and LTC6954_GUI application are required to control the DC1954A through a personal computer (PC). LTC6954_GUI Installation DC590 Configuration Place the DC590 jumpers in the following positions (refer to Figure 2): JP4: EE Must be in the EN position. JP5: ISO ON must be selected. JP5: SW ON must be selected. The LTC6954_GUI software is used to communicate with the LTC6954. It uses the DC590 to translate between USB and SPI-compatible serial communications formats. The following are the LTC6954_GUI system requirements: * Windows Operating System: Windows XP, Windows 2003 Server, Windows Vista, Windows 7 * Microsoft .NET 3.5 SP1 or later JP6: VCCIO 3.3V or 5V must be selected. This sets the SPI port to 3.3V or 5V operation, 3.3V operation is recommended. * Windows Installer 3.1 or later * Linear Technology's DC590 hardware Figure 2. DC590 Jumper and Connector Locations 2 dc1954af DEMO MANUAL DC1954A Quick Start Procedure Download the LTC6954_GUI setup file at: www.linear.com/LTC6954_GUI. Run the LTC6954_GUI setup file and follow the instructions given on the screen. The setup file will verify and/or install Microsoft .NET and install the LTC6954_GUI. DC1954A Configuration 1. Connect the GND and V+ 3.15V-3.45V, turrets to a power supply and apply power (see Figure 1 and the Typical DC1954A Requirements and Characteristics table). 2. Connect the DC590 to the DC1954A with the provided ribbon cable. 3. Run the LTC6954_GUI application. 4. From the LTC6954_GUI, click File -> Load Settings and point to the LTC6954.6954set file. 5. From the LTC6954_GUI, select the Read All button. This will update the GUI to display the correct part number and associated output types. 6. Connect a low phase-noise (or jitter) single-ended or differential signal to IN+ (J8) and/or IN- (J9). Refer to the LTC6954 data sheet for acceptable input frequencies and amplitudes. 7. From the LTC6954_GUI, update Fin to the frequency of the input signal in step 6. This will update the LTC6954_GUI with the correct output frequencies. 8. Refer to the Typical DC1954A Requirements and Characteristics table for desired OUTxSEL level. Set JP1, JP2 and JP3 accordingly. 9. Connect desired output (OUT0, OUT1, OUT2) to a test instrument or other demo board to evaluate performance. [The LVDS/CMOS outputs are DC-coupled, please make sure the levels do not exceed the test equipment input levels]. 10. To synchronize outputs provide a 1ms or greater high pulse to the SYNC SMA to take advantage of the EZSync function. Be sure to power down or terminate any unused RF output with 50, or poor spurious performance may result. Figure 3. LTC6954_GUI Screenshot dc1954af 3 DEMO MANUAL DC1954A Quick Start Procedure Troubleshooting If the board is not functioning as expected, follow the instructions below: 1. Verify that you are able to communicate with the DC1954A. The bottom status line in LTC6954_GUI should read LTC6954 and Comm Enabled. 2. Verify that V+ 3.15V-3.45V turret has the correct voltage. (see the Typical DC1954A Requirements and Characteristics table). 3. Ensure JP1, JP2, and JP3 are set to desired position. 4. If the output type is LVPECL and the output is AC-coupled, OUTxSEL must be high for proper signal swing. 5. If the output type is LVDS, the outputs must be AC-coupled into single-ended, 50 input test equipment. Additionally, the unconnected output must be AC-coupled into a 50 load to ground to provide a balanced output load. If the LVCSx bit is low, the signal amplitude at the instrument will be approximately half of the data sheet value due to the existing 100 termination on the demo board. 6. If the output is CMOS, a 200 series resistor must be included to limit the output current when connecting to the 50 input on test equipment. The signal swing at the instrument is then approximately 20 percent of the data sheet value. Contact the factory for further troubleshooting. DC1954A Reconfiguration The DC1954A allows for a variety of input and output configurations. The following covers the hardware reconfiguration of the DC1954A. LVPECL Output Options The DC1954A LVPECL outputs are AC-coupled and require internal biasing (OUTxSEL=H) with the default termination network. The DC1954A provides pull-down, series and a differential termination resistor options to accommodate the other LVPECL termination networks described in the data sheet. LVDS/CMOS Output Options The LVDS/CMOS outputs are DC-coupled and have an on board differential 100 resistor termination by default. The DC1954A provides pull-down, series and a differential termination resistor options to accommodate the other LVDS/ CMOS termination networks described in the data sheet. Input Options The inputs have a 50 termination resistor to GND and are AC-coupled by default. The DC1954A provides pull-down, pull-up and a differential termination resistor options to accommodate the other input termination networks described in the data sheet. Clock Follower Input Network When using the DC1954A as a clock follower, EZSync requires the LTC6954 inputs to be taken to a low state while the SYNC pin is high. To meet this requirement, the DC1954A must be modified to support DC-coupling. Refer to the EZSync Function section and to the data sheet for more details on using the LTC6954 as a clock follower. EZSync Function Apply a 1ms or greater high pulse to the SYNC SMA connector to take advantage of the EZSync function. Refer to the LTC6954 data sheet for SYNC timing and level requirements. Assembly Options Table 1. DC1954A Assembly Options ASSEMBLY VERSION U1 PART NUMBER OUT0+/- OUT1+/- OUT2+/- DC1954A-A LTC6954IUFF-1 LVPECL LVPECL LVPECL DC1954A-B LTC6954IUFF-2 LVPECL LVPECL LVDS/CMOS DC1954A-C LTC6954IUFF-3 LVPECL LVDS/CMOS LVDS/CMOS DC1954A-D LTC6954IUFF-4 LVDS/CMOS LVDS/CMOS LVDS/CMOS 4 dc1954af DEMO MANUAL DC1954A Typical DC1954A Requirements and Characteristics PARAMETER INPUT OR OUTPUT PHYSICAL LOCATION DETAILS 3.3V Power Supply Input J11 and J10 Banana Jacks, or 3.15V-3.45V and GND Turrets Low-Noise and Spur-Free 3.3V, 400mA Capable Power Supply; Typically DC1954 Consumes ~300mA; Powers LTC6954, U2, U3, and U4 OUT0+, OUT0- Two Outputs J1 and J2 SMA Connectors* Refer to Figure 1 or Table 1 for Output Type OUT1+, OUT1- Two Outputs J3 and J4 SMA Connectors* If LVPECL: AC-Coupled OUT2+, OUT2- Two Outputs J5 and J6 SMA Connectors* If LVDS/CMOS: DC-Coupled Refer to LTC6954 Data Sheet for Output Levels for LVPECL, or LVDS/CMOS Option OUT0SEL Input JP1 3-Pin Headers If LVPECL: OUT1SEL Input JP2 3-Pin Headers OUTxSEL=H: IBIAS=ON, for Default LVPECL BOM OUT2SEL Input JP3 3-Pin Headers OUTxSEL=L: IBIAS=OFF, Must Install External Pull-Down Resistor, Refer to schematic If LVDS/CMOS: OUTxSEL=H: LVDS, Default LVDS/CMOS BOM OUTxSEL=L: CMOS, Remove 100 Differential Termination, Refer to Schematic TEMP Input/Output Turret TEMP GND Input Turret Temperature Monitoring Diode; Force Current Measure Voltage, Refer to Data Sheet SYNC Input J7 SMA Connector and Turret EZSync, 0V to 3.3V Control Signal, Refer to the Data Sheet IN+, IN- Input J8 and J9 SMA Connectors Input Signal Pins *Any unused RF output must be powered down or terminated with 50, or poor spurious performance may result. PCB Layout Top Layer dc1954af 5 DEMO MANUAL DC1954A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER CAP., X7R, 0.1F, 10V, 10%, 0402 AVX, 0402ZC104KAT2A Required Circuit Components 2 17 C1-C10, C12, C13, C22-C24, C28, C29 3 1 C14 CAP., X7R, 1.0F, 16V, 10%, 0603 AVX, 0603YC105KAT2A 4 9 C15, C17-C21, C25-C27 CAP., X7R, 0.01F, 6.3V, 10%, 0201 MURATA, GRM033R70J103KA01D 5 1 C16 CAP., TANT, 22F 10V, 3528 AVX, TPSB226K010R0400 6 3 E9, E12, E13 TURRET, 0.064" MILL-MAX, 2308-2-00-80-00-00-07-0 7 2 E10, E11 TURRET, 0.094" MILL-MAX, 2501-2-00-80-00-00-07-0 8 3 JP1, JP2, JP3 JMP, 3 PINS 2mm CTRS. SAMTEC, TMM-103-02-L-S 9 8 J1-J6, J8, J9 CONN., SMA 50 EDGE-LAUNCH EMERSON, 142-0701-851 10 1 J7 CONN, SMA STRAIGHT CONNEX, 132134 11 2 J10, J11 JACK, BANANA KEYSTONE, 575-4 12 1 J12 CONN., HEADER 14POS 2mm VERT GOLD MOLEX, 87831-1420 13 6 R2, R4, R7, R9, R12, R14 RES., CHIP, 0, 5% 0402 NIC, NRC04Z0TRF 14 0 R3, R5, R8, R10, R13, R15-R17, R19 RES., CHIP, 0402 OPT 15 2 R18, R20 RES., CHIP, 49.9, 1/16W, 1%, 0402 NIC, NRC04F49R9TRF 16 5 R22, R35, R37-R39 RES., CHIP, 200k, 1/16W, 1%, 0402 NIC, NRC04F2003TRF 17 3 R23, R24, R25 RES., CHIP, 4.99k, 1/16W, 1%, 0402 NIC, NRC04F4991TRF 18 1 R26 RES., CHIP, 0, 0603 NIC, NRC06Z0TRF 19 0 R27-R29, R30-R32 RES., CHIP, 0603 OPT 20 4 R33, R34, R36, R40 RES., CHIP, 100, 1/16W, 5%, 0402 NIC, NRC04J101TRF 21 2 U2, U3 I.C., DUAL BUFFER, SC70-6 FAIRCHILD SEMI., NC7WZ17P6X 22 1 U4 I.C., DUAL TRANSCEIVER, SOT363 NXP, 74LVC1T45GW 23 1 U5 I.C., EEPROM 2KBIT 400KHZ 8TSSOP MICROCHIP, 24LC025-I /ST 24 3 SHUNTS SHOWN ON ASSY DWG SHUNT, 2mm CTRS. SAMTEC, 2SN-BK-G DC1954A-A Required Circuit Components 1 1 GENERAL BOM 2 0 R1, R6, R11 RES., CHIP, 0402 OPT 3 6 Z1, Z2, Z3, Z4, Z5, Z6 CAP., X7R, 0.1F 16V, 10%, 0402 AVX, 0402YC104KAT2A 4 1 U1 I.C., QFN36UFF-4X7 LINEAR TECH., LTC6954IUFF-1#PBF 6 dc1954af DEMO MANUAL DC1954A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER DC1954A-B Required Circuit Components 1 1 2 0 GENERAL BOM R1, R6 RES., CHIP, 0402 OPT 3 1 R11 RES., CHIP, 100 1/16W, 5%, 0402 NIC, NRC04J101TRF 4 4 Z1-Z4 CAP., X7R, 0.1F 16V, 10%, 0402 AVX, 0402YC104KAT2A 5 2 Z5, Z6 RES., CHIP, 0, 0402 NIC, NRC04Z0TRF 6 1 U1 I.C., QFN36UFF-4X7 LINEAR TECH., LTC6954IUFF-2#PBF DC1954A-C Required Circuit Components 1 1 2 0 R1 RES., CHIP, 0402 GENERAL BOM OPT 3 2 R6, R11 RES., CHIP, 100 1/16W, 5%, 0402 NIC, NRC04J101TRF 4 2 Z1-Z2 CAP., X7R, 0.1F 16V, 10%, 0402 AVX, 0402YC104KAT2A 5 4 Z3, Z4, Z5, Z6 RES., CHIP, 0, 0402 NIC, NRC04Z0TRF 6 1 U1 I.C., QFN36UFF-4X7 LINEAR TECH., LTC6954IUFF-3#PBF DC1954A-D Required Circuit Components 1 1 GENERAL BOM 2 3 R1, R6, R11 RES., CHIP, 100 1/16W, 5%, 0402 NIC, NRC04J101TRF 3 6 Z1, Z2, Z3, Z4, Z5, Z6 RES., CHIP, 0, 0402 NIC, NRC04Z0TRF 4 1 U1 I.C., QFN36UFF-4X7 LINEAR TECH., LTC6954IUFF-4#PBF dc1954af 7 A B C D J8 J7 E9 J10 SMA GND * E13 E12 SMA-R J9 SMA-R TEMP IN- IN+ SYNC SYNC GND GND E11 E10 R16 OPT C14 1uF 0603 V+ V+ R19 OPT R17 OPT R20 49.9 R18 49.9 C2 0.1uF CS SDI SCLK SDO C17 0.01uF 0201 C1 0.1uF C15 0.01uF 0201 C18 0.01uF 0201 R35 200K C19 0.01uF 0201 5 ASSY -A -B -C -D LTC6954IUFF-1 LTC6954IUFF-2 LTC6954IUFF-3 LTC6954IUFF-4 U1 0.1uF 0 OHM 100 OHM 100 OHM 100 OHM 0 OHM 4 0 OHM 0.1uF 0.1uF Z1-Z2 Z3-Z4 100 OHM 0.1uF OPEN R11 30 29 28 27 26 25 24 23 22 21 20 19 C20 0.01uF 0201 100 OHM 100 OHM 0.1uF OPEN OPEN OPEN OPEN R6 OPEN R1 1. ALL RESISTORS ARE IN OHMS, 0402 ALL CAPACITORS ARE IN MICROFARADS, 0402 NOTE: UNLESS OTHERWISE SPECIFIED 22uF 10V 3528 + C16 0 OHM 0 OHM 0 OHM 0.1uF Z5-Z6 V+IN GND IN- IN+ GND V+IN V+A V+A SYNC V+D SDI SCLK C21 0.01uF 0201 C25 0.01uF 0201 16 3.15V - 3.45V V+ C26 0.01uF 0201 * V+ QFN36UFF-4X7 U1 14 J11 4 18 V+D 17 SDO GND 32 OUT1SEL 33 TEMP 31 CS 15 V+A V+A V+ 34 V+OUT2 OUT2- OUT2+ V+OUT2 V+OUT1 OUT1- OUT1+ V+OUT1 V+OUT0 OUT0- OUT0+ V+ OUT2SEL R28 OPT 0603 R27 OPT 0603 C12 0.1uF H L JP1 1 2 3 OUT0SEL C10 0.1uF CUSTOMER NOTICE OUT1SEL 1 2 3 4 5 6 7 8 9 10 11 C9 0.1uF OUT0SEL C8 0.1uF 12 R32 OPT 0603 R31 OPT 0603 V+OUT0 V+ V+ OUT0SEL 1 2 3 C23 0.1uF H L SIZE JP2 R15 OPT R13 OPT R10 OPT R8 OPT R5 OPT V+ 2 REV * * * * C29 0.1uF H L 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 SCALE = NONE DATE: N/A 1 JP3 1 2 3 OUT2SEL SMA-R J6 SMA-R J5 SMA-R J4 SMA-R J3 SMA-R J2 OUT2- OUT2+ OUT1- OUT1+ OUT0- OUT0+ MICHEL A. APPROVED GND GND GND 10/03/2013, 10:30 AM 1 DEMO CIRCUIT 1954A LTC6954IUFF-1/-2/-3/-4 SHEET 1 LOW PHASE NOISE, TRIPLE OUTPUT CLOCK DISTRIBUTION DIVIDER/ DRIVER IC NO. DATE 10-03-13 OF 2 2 REV. 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only V+ J1 SMA-R PRODUCTION DESCRIPTION REVISION HISTORY OUT2SEL C28 0.1uF OUT1SEL Z6 Z5 Z4 Z3 Z2 * Z1 * C24 0.1uF R3 OPT __ ECO OUT1SEL R14 0 R12 0 R9 0 R7 0 R4 0 R2 0 C22 0.1uF APPROVALS V+ * * R6 * R1 R11 C13 0.1uF 2 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; TECHNOLOGY HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. MICHEL A. TITLE: SCHEMATIC APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. R30 OPT 0603 R29 OPT 0603 3 C27 0.01uF 0201 OUT0SEL 13 GND GND 35 OUT2SEL 36 GND 8 37 V+ 3.15V - 3.45V 5 A B C D DEMO MANUAL DC1954A Schematic Diagram dc1954af Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C 5 1 V+ 2 5V 6 CS 4 SCK/SCL 7 MOSI/SDA 5 MISO 10 EEVCC 9 EESDA 11 EESCL 12 EEGND 14 AUX J12 HD2X7-079-MOLEX GND GND GND 13 8 3 D WP R25 4.99K 6 5 7 3 2 1 R23 4.99K U5 24LC025-I /ST SCL SDA WP A2 A1 A0 3 R26 0 0603 C3 0.1uF APPROVALS R40 100 R39 200K R22 200K SIZE C7 0.1uF R38 200K 3 2 1 4 3 4 6 GND DIR VCC(A) VCC(B) U4 74LVC1T45GW 2 GND VCC 5 3 1 U3 NC7WZ17P6X 2 GND VCC 5 6 U2 NC7WZ17P6X 1 2 4 5 6 4 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONE DATE: N/A R37 200K C6 0.1uF C5 0.1uF C4 0.1uF R36 100 R34 100 R33 100 1 SDO SDI SCLK CS IC NO. 2 10/03/2013, 10:30 AM DEMO CIRCUIT 1954A LTC6954IUFF-1/-2/-3/-4 1 SHEET 2 LOW PHASE NOISE, TRIPLE OUTPUT CLOCK DISTRIBUTION DIVIDER/ DRIVER OF 2 2 REV. 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only V+ V+ V+ LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; TECHNOLOGY HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. MICHEL A. TITLE: SCHEMATIC APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. CUSTOMER NOTICE V+ DC590 SPI INTERFACE NOTE: EEPROM FOR BOARD IDENTIFICATION EEGND R24 4.99K V+DIG CS SCLK SDI SDO ARRAY 4 EEPROM 8 VCC GND 4 5 A B C D DEMO MANUAL DC1954A Schematic Diagram Note: The buffers shown on sheet 2 of 2 of the schematic are used to protect the LTC6954 when connected to the DC590 before the LTC6954 is powered up. There is no need for such circuitry if the SPI bus is not active before powering up the LTC6954. The EEPROM is for identification and is not needed to program the LTC6954. dc1954af 9 DEMO MANUAL DC1954A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright (c) 2004, Linear Technology Corporation 10 Linear Technology Corporation dc1954af LT 1014 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2014