Evaluation Board User Guide
UG-600
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADAU1977/ADAU1978/ADAU1979
FEATURES
For the evaluation of the ADAU1977/ADAU1978/ADAU1979
quad ADCs
Total harmonic distortion (THD) plus noise (N): −95 dB at
−1 dBFS
Signal to noise ratio (SNR): 109 dB, A weighting filter
Built-in diagnostics for microphone inputs
APPLICATIONS
Automotive
GENERAL DESCRIPTION
The E VA L -ADAU1977Z/E VA L-ADAU1978Z/E VA L -
ADAU1979Z is used for quick evaluation of the
ADAU1977/ADAU1978/ADAU1979 quad ADCs. The
evaluation board can output up to four channels of digital
output. The evaluation board requires a power supply of +5 V
for the ADAU1978 and the ADAU1979 and a power supply of
+5 V and ±20 V (optional) for testing the diagnostic features of
the ADAU1977.
EVALUATION BOARD CONNECTION DIAGRAM
Figure 1.
11751-001
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 27
UG-600 Evaluation Board User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Evaluation Board Connection Diagram ........................................ 1
Revision History ............................................................................... 2
Evaluation Board Hardware ............................................................ 3
Power Supply Connectors ........................................................... 3
Input Connectors .......................................................................... 3
Output Connectors ...................................................................... 3
I2C/SPI Control Connector ......................................................... 3
Jumpers .......................................................................................... 3
Setup of the Evaluation Board Connections ................................. 5
Evaluation Board Setup Instructions ..........................................6
Jumper Settings ..............................................................................6
USBi and Standalone GUI Setup .................................................7
ADAU1977 Power-On ..................................................................7
Standalone GUI I2C Control ........................................................7
Microphone Diagnostics ..............................................................8
Standalone GUI SPI Control .......................................................9
Standalone Mode ...........................................................................9
Evaluation Board Schematics and Artwork ................................ 10
Board Layout ............................................................................... 16
Ordering Information .................................................................... 23
Bill of Materials ........................................................................... 23
REVISION HISTORY
8/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 27
Evaluation Board User Guide UG-600
EVALUATION BOARD HARDWARE
The E VA L -ADAU1977Z board is common for the ADAU1977,
ADAU1978, and ADAU1979. The evaluation board is designed
as a 4-layer printed circuit board (PCB). The top and bottom
layers are for signals, whereas Layer 2 and Layer 3 are used as
ground and a power plane, respectively. The PCB layout is
important to achieve good audio performance. The following
sections offer useful guidelines for operation of the board.
POWER SUPPLY CONNECTORS
The E VA L -ADAU1977Z board requires +5 V for the
ADAU1978 and ADAU1979 and may need an additional ±20 V
for testing the 10 V rms inputs of the ADAU1977. Connect the
5 V power supply at J5 and J4. Connect the ±20 V power supply
at either TP3 (+20 V) or TP1 (−20 V). The +5 V power supply
must be capable of providing a 1 A current rating, and the
±20 V power supply must be capable of providing at least a
100 mA current rating. When the diagnostics feature is not
used, the ±20 V supply is not required.
INPUT CONNECTORS
The E VA L -ADAU1977Z has five 3.5 mm audio jack connectors
for analog inputs: J9, J17, J28, J38, and J47. The J9 connector is
used for generating line level inputs capable of 10 V rms, with a
common-mode level of 7 V for the ADAU1977. The J17, J28,
J38, and J47 connectors are used as Channel 1, Channel 2,
Channel 3, and Channel 4 line level inputs to the ADC,
respectively. All five inputs are differential.
OUTPUT CONNECTORS
The ADC digital output is available at J25 (unbuffered) and J26
(buffered). In addition, ADC digital output is available as a
2-channel Sony Philips digital interface format (SPDIF). J25 and
J26 are used for I2S or time division multiplex (TDM), serial
digital output. The U16 provides the SPDIF optical output, and
J35 provides the SPDIF coaxial output.
I2C/SPI CONTROL CONNECTOR
The J8 (10-way header) can be used for I2C/SPI serial port
communication for controlling the board. The supplied USB
interface board can be used for setting the device. The graphic
user interface (GUI) software is used along with the USB
interface board.
JUMPERS
The E VA L-ADAU1977Z board provides jumpers for setting this
board into various operating modes.
Table 1. Jumper Descriptions
Component No. Mnemonic Description
J1 MICBIAS SELECT AUX IN This jumper allows selecting either internal or external micbias for auxiliary input.
J2 CM SELECT AUX IN Used for setting the common mode level for auxiliary input.
J4 GND Ground or 0 V connection for the power supply.
J5 +5V +5 V connection for the power supply.
J8
USBi
Connector for USBi board.
J9 AUX IN Connector for auxiliary input.
J10 IOVDD Selects the IOVDD 1.8 V or 3.3 V.
J11 IOVDD Ext/Int Selects the internal or external supply for IOVDD.
J12 VBAT Ext/Int Selects the internal or external supply for VBAT.
J13 3.3 V Ext/Int Selects the internal or external 3.3 V supply.
J14 AVDD Ext/Int Selects the internal or external AVDD supply for the ADAU1977.
J15/J20 Input 1 Select Selects the input source for Channel 1.
J16 AVDD Current This jumper is used to measure the AVDD current.
J17 CH1 Input Connector for Channel 1 input.
J19 Input Short This jumper is used to short the ± Channel 1 input.
J21 Boost Current This jumper is used to measure the boost converter current.
J22 MICBIAS-CH1 Selects the internal or external micbias for Channel 1.
J24 Boost Switch This jumper is used to measure the boost switch current.
J25 ADC Output Header for connection to ADC digital pins.
J26 ADC Output Buffered Header for ADC digital output.
J27/J30 Input 2 Select Selects the input source for Channel 2.
J28
CH2 Input
Connector for Channel 2 input.
J29 Input Short This jumper is used to short the ± Channel 2 input.
Rev. 0 | Page 3 of 27
UG-600 Evaluation Board User Guide
Component No. Mnemonic Description
J31 MICBIAS-CH1 Selects the internal or external micbias for Channel 2.
J33 IOVDD Current Connector for measuring IOVDD current.
J34 128fs Mode Selects the 96 k sample rate for the SPDIF transmitter.
J35 Coaxial Output Connector for SPDIF coaxial output.
J36/J40
Input 3 Select
Selects the input source for Channel 3
J28 CH3 Input Connector for Channel 3 input.
J39 Input Short This jumper is used to short the ± Channel 3 input.
J41 MICBIAS-CH1 Selects the internal or external micbias Channel 3.
J42 DVDD External DVDD current measurement.
J43 MCLKIN Selects the external master clock input to the ADAU1977.
J44 PLL Filter Selects the PLL filter for LRCLK mode.
J45 PLL Filter Selects the PLL filter for MCLK mode.
J46/J49 Input 4 Select Selects the input source for Channel 4.
J48 Input Short This jumper is used to short the ± Channel 4 Input.
J50 MCLKIN Selects the source for MCLKIN between oscillator, header, and Subminiature Version A,
SMA.
J51 MICBIAS-CH1 Selects the internal or external micbias Channel 4.
J52 MCLK Input SMA connector for external master clock input.
J53 FREQ Select Selects the switching frequency for the 3.3 V regulator.
JP1 AUX IN Header for external auxiliary input
JP2 CH1 IN Header for external Channel 1 input.
JP3 CH2 IN Header for external Channel 2 input.
JP4 Reset SPDIF Tx SPDIF Tx reset.
JP5 CH3 IN Header for external Channel 3 input.
JP6 SA Mode This jumper is used for standalone mode.
JP7 CH4 IN Header for external Channel 4 input.
JP8 RESET Header for the ADAU1977 reset.
JP9 MCLKIN Header for master clock input.
JP10 Reserved Reserved for internal use.
JP11 Oscillator Enable Enables the oscillator.
Rev. 0 | Page 4 of 27
Evaluation Board User Guide UG-600
SETUP OF THE EVALUATION BOARD CONNECTIONS
Figure 2. Evaluation Board Jumper Settings
AARDVARK/USBi
SLIDE SW ITCH SETTI NG S
CHIP ADDRESS 0 x 1 1 ON ON
OFF
ON
ADDR1
ADDR0
256*fs
48K
I2S
MASTER
TDM4
SLOTS 1 – 4
384*fs
96K
TDM
SLAVE
TDM8
SLOTS 5 – 8
LRCLK
BCLK
SDATA2
SDATA1
SERI AL DAT A OUTPUT
MASTERSLAVE
SDATA TO I2 S HDR
BCLK
LRCLK
SDATA TO SPDI F OUT
BCLK
LRCLK
SDATA2
SDATA1
SDATA2
SDATA1
SDATA2
SDATA1
MCLK
+5V0V
EXT DVDD EXT IOVDDEXT AVDD
–17V TO –22V
0V
+17V TO + 22V
REQ UIRED O NLY
FO R GENERATING
VBAT AND 10 V RMS
SI GNAL AT 7V CM
BUFFER TO BE USED FOR G E NERATING
10V RM S SI GNAL AT VARIO US CM L EVEL
GND
1/3 MICBIAS
VBAT/2
GND
2/3 MIC BIAS
VBAT/2
CM OPTIONS
AUX ANALO G INPUT
10V RMS
FAULT INPUT + INPUTS
FAULT INPUT –INPUTS
0V
CONNE CT VOLTAGE SOURCE
TO INTRO DUCE T HE F AULT
ON INPUT 0V TO 18 V MAX
NORMAL
CONT ROL FO R AV DD SW ITCHER
PWDN
–BUFF
–INx
+INx
ADC INP UT
SELECT
ONOFF
DIRE CT COUPLE
INPUTS
NORMAL
MICBIAS
NORMAL
FAULTx
GND
GENERATE
FAULT
ON INPUTS
ON
OFF
MICBIAS
RESISTOR
SELECT
300Ω
500Ω
INT
EXT
MICBIAS
SELECT
PLL FILTER
SELECT
LRCK
MCLK
POWER
DOWN
OSCILLATOR
PSIA
OSC
SMA
MCLK
SELECT
PSI A MCLKI N
EXT MCLK
IN
DIRECT
LEVEL SHIF T
INSTALL
FO R SA MODE
DO NOT CONNECT POWER SUP PLY
INT ERNAL USE ONLY
DO NOT CONNECT
POW ER SUPPLY
INT ERNAL USE ONLY
7 BI T DEVICE ADDRESS
ADDRESS
SETTING
FOR 0x71
ANALO G INP UT1
MAX 10V RMS
ANALO G INP UT2
MAX 10V RMS
ANALO G INP UT3
MAX 10V RMS
ANALO G INP UT4
MAX 10V RMS
+BUFF
MCLKADAU197x
SELECT
CHIP ADDRESS 0 x 3 1 ON OFF
CHIP ADDRESS 0 x 5 1 OFFON
CHIP ADDRESS 0 x 7 1 OFFOFF
STAND ALONE MODE
SPI MODE
I2CMODE
1.2MHz
600kHz
CONNECT
5V SUPPLY
11751-002
Rev. 0 | Page 5 of 27
UG-600 Evaluation Board User Guide
EVALUATION BOARD SETUP INSTRUCTIONS
To setup the E VA L -ADAU1977Z, the user needs a 5 V power
supply, differential analog input source, and a PC with a USB
port. Use a single 5 V, 1 A current rating for the power supply.
For full evaluation of the ADAU1977, a ±20 V supply is
required. This power supply facilitates the generation of a
10 V rms signal as well as a VBAT supply for microphone
diagnostics.
JUMPER SETTINGS
See Figure 2 for the setup of the evaluation board connections.
Connect the positive power supply lead to J5 and the 0 V lead to
J4 of the evaluation board. Do not turn the power supply on at
this time.
In the power supply section, take the following steps:
1. Set Jumpers J13 and J14 to the INT position.
2. Set Switch S1 to the ON position.
3. Set Jumper J10 to the desired IOVDD supply, 3.3 V, or
1.8 V.
4. Set Jumper J11 to the INT position for the internal
IOVDD.
5. Set Switch S2 to the ON position to turn on the 1.8 V
regulator.
In the daughter board section, take the following steps:
1. Install Jumpers J16, J21, J24, and J33. The J16 jumper
provides the AVDD. Jumpers J21 and J24 provide the 3.3 V
power supply to the boost converter. The J33 jumper
provides the IOVDD to the
ADAU1977/ADAU1978/ADAU1979.
In the PLL and MCLK section, take the following steps:
1. Select the master clock source. The evaluation board
provides three options for providing the master clock to
the ADC. The three options include the following: the on-
board 12.288 MHz oscillator, the external source at JP9,
and the SMA Connector J52.
2. To use the on-board oscillator, install Jumper JP11. To shut
down the oscillator, remove Jumper JP11.
3. Set Jumper J50 in the OSC center position.
4. Alternatively, if the external master clock is available, it can
either be connected at J52 as a coaxial 50 Ω SMA
connector, or at JP9 as a 2-way header (0.1” pitch). If using
JP9 as the source, install J50 in the PSIA position. If using
J52 as the source, install J50 in the SMA position.
5. The MCLK is level shifted to the required IOVDD. By default,
the level shifted master clock is used. Set Jumper J43 to the
IOVDD position. Alternatively, if direct MCLK pin access
is needed, set J43 to the 3V3 position. In this case, ensure
that the master clock supplied to the ADAU1977 is at the
correct IOVDD level.
6. Two options are provided for the PLL filter, MCLK mode
or LRCLK mode. By default, the MCLK mode is selected
by installing Jumper J44 in the MCLK position. If the
LRCLK mode is required, set J44 in the LRCLK position.
In the I2S output section, take the following steps:
1. Determine the serial data format used for the ADC output.
Either I2S/left justified (LJ)/right justified (RJ)/TDM
format or SPDIF format are available.
For I2S/LJ/RJ/TDM format, take the following steps:
1. Set LK3 and LK5 to the I2S position.
2. Set LK1 and LK2 to the I2S position.
3. Set Switch S13 to the MASTER position if the
ADAU1977/ADAU1978/ADAU1979 is used as a master for
the serial audio port. Alternatively, it can be set to the
SL AVE position; however, in this case, both the LRCLK
(frame clock) and the BCLK (bit clock) must be provided
from an external source.
4. The buffered serial output is available on the J26 (4-way
dual row, 0.1” pitch) header. Alternatively, the direct
(unbuffered) ADAU1977 serial outputs are available on the
J25 (8-way dual row, 0.1” pitch) header.
For SPDIF format, take the following steps:
1. Ensure LK3 and LK5 are set to the SPDIF position.
2. Ensure LK1 and LK2 are set to the SPDIF position.
3. Ensure LK4 is set to the desired serial data pair. Either
Pair 1 (Ch1 and Ch2) or Pair 2 (Ch3 and Ch4) can be
selected because only 2-channel SPDIF output is available
on the evaluation board.
4. Ensure LK6 is set to the SPDIF position which provides
the MCLK to the SPDIF transmitter.
5. The SPDIF output is available on U16 as an optical form or
on J35 as a coaxial form.
For the I2C/SPI control section, take the following steps:
1. Slide Switches S3, S4, and S5 are used to set the control
communication protocol for the ADAU1977.
For I2C protocol, take the following steps:
1. Set Switches S3, S4, and S5 to the I2C position.
2. Ensure JP6 is not installed.
3. The device address for the ADAU1977 is set using
Switch S9. The possible 7-bit device addresses are 0x11,
0x31, 0x51, or 0x71. The E VA L -ADAU1977Z evaluation
board is set for the 0x71 address.
4. The 20-way (10-pin, dual row, 0.1” pitch), Shrouded
Connector J8 is used to connect the supplied USBi.
Alternatively, any other I2C master controller can be
connected at J8 to control the ADAU1977.
5. The Analog Devices, Inc., USBi is the quickest way to set
the E VA L -ADAU1977Z board using the supplied
standalone GUI or SigmaStudio™ software.
Rev. 0 | Page 6 of 27
Evaluation Board User Guide UG-600
For the ADAU1977 line input application, take the following
steps:
1. J9 is used to level shift the input source to the VBAT/2
level.
2. For the ADAU1977, connect the analog audio source to the
J9 auxiliary input connector.
3. J2 has two jumpers that must be set to the VBAT and
VBAT2 positions.
4. Check the dc voltage at J2 (Pin 2). This voltage should be
approximately 7 V. If n o t, set J2 using the preset R5.
5. Set the S10, S16, S21, and S26 switches to the ON position
for dc-coupled inputs.
6. Set Jumpers J15, J20, J27, J30, J36, J40, J46, and J49 to the
BUFF position.
7. Alternatively, the signal source can be connected directly to
J17, J28, J38, and J47 by setting Jumpers J15, J20, J27, J30,
J36, J40, J46, and J49 to the –IN or +IN position. Note that
in this setting, the input source must be level shifted
appropriately.
For the ADAU1978/ADAU1979 line input applications, take the
following steps:
1. Ensure Jumper J15 and Jumper J20 are set to the –IN and
+IN position for Ch1.
2. Ensure Jumper J27 and Jumper J30 are set to the –IN and
+IN position for Ch2.
3. Ensure Jumper J36 and Jumper J40 are set to the –IN and
+IN position for Ch3.
4. Ensure Jumper J46 and Jumper J49 are set to the –IN and
+IN position for Ch4.
5. Ensure Switches S10, S16, S21, and S26 are set to the OFF
position for the ADAU1978 and the ADAU1979, which
sets the inputs as ac-coupled mode.
For the ADAU1977 microphone input application, take the
following steps:
1. Ensure Switches S7, S12, S15, S18, S20, S23, S25, and S29
are set to the ON position for using the ADAU1977 inputs
as microphone.
2. These switches are used to set the microphone bias
resistors for the microphone inputs. Either 300 Ω or 500 Ω
can be selected when switches are set to the ON position
for the respective inputs.
3. Ensure Jumpers J22, J31, J41, and J51 are set to the INT
position (the internal micbias is used). These jumpers
allow the microphone bias to be selected either from the
ADAU1977, or externally, if desired.
4. Jumpers J17, J28, J38, and J47 are used for the microphone
input connection.
5. Ensure Jumpers J15, J20, J27, J30, J36, J40, J46, and J49 are
set to the IN position.
6. Ensure Switches S10, S16, S21, and S26 are set to the ON
position for direct-coupled mode.
USBi AND STANDALONE GUI SETUP
To set up the USBi and standalone GUI, take the following steps:
1. If using the standalone GUI, click the appropriate x86 or
x64 folder setup.exe to install the GUI.
2. The software is installed on your desktop with the
ADAU1977 Rev C icon.
ADAU1977 POWER-ON
To power-on the EVA L -ADAU1977Z, take the following steps:
1. Turn on the 5 V supply. Typical 40 mA current is drawn
from the 5 V supply in standby condition.
STANDALONE GUI I2C CONTROL
The E VA L -ADAU1977Z board can be controlled via the I2C
using the standalone GUI and USBi. Take the following steps:
1. Connect the provided USBi board to J8 and to the USB
port on the PC.
2. Double-click the ADAU1977 Rev C icon on your desktop
to invoke the GUI.
3. A new window, as is shown in Figure 3, will appear.
4. The USBi - Connected message will appear at the top of
the window (see Figure 3).
5. Click Power Up. The Communication Established
message will appear at the top of the window (see Figure 3).
6. Click Read all to read the PLL status. The PLL status
should be green and locked.
7. When using the ADAU1977, and the boost converter is
turned on, the Boost Good indicator should be green. For
the ADAU1978 and the ADAU1979, this function is not
applicable and will stay red.
8. Go to the ADC Control tab (see Figure 4) and click
Master/Slave for the ADC master mode. When green, the
ADC is in master mode and it will output the bit clock and
frame clock, together with the serial data at the J25.
9. Connect the input source at the desired input to AIN1,
AIN2, AIN3, and AIN4 or AUXIN using 3.5 mm audio
jacks. Alternatively, the 2-pin (0.1” pitch) header can be
used to feed the inputs to the E VA L -ADAU1977Z
evaluation board. Note that the input level requirements
for the ADAU1977, the ADAU1978, and the ADAU1979
are different, and the appropriate level input signal must be
applied. The full-scale inputs for the ADAU1977 is
10 V rms, for the ADAU1978 is 2 V rms, and for the
ADAU1979 is 4.5 V rms.
10. The ADC output is available at the J26 header or the SPDIF
output depending on the selected option.
Rev. 0 | Page 7 of 27
UG-600 Evaluation Board User Guide
Figure 3. Register Control for the ADAU1977 GUI Page 1
Figure 4. Register Control for the ADAU1977 GUI Page 2
Figure 5. Register Control for the ADAU1977 GUI Page 3
MICROPHONE DIAGNOSTICS
Microphone diagnostics are applicable for the ADAU1977 only,
used with the microphone input application circuit, as
described in the ADAU1977 data sheet.
1. Connect the microphone to the desired input connector:
J17, J28, J38, or J47.
2. Ensure that the inputs are dc-coupled by setting Switches
S10, S16, S21, and S26 to On.
3. Select the appropriate bias resistors using Switches S7 and
S12 for Channel 1, Switches S15 and S18 for Channel 2,
Switches S20 and S23 for Channel 3, Switches S25 and S29
for Channel 4. The resistor options are 300 Ω or 500 Ω.
4. Select the internal microphone bias by setting Jumpers J22,
J31, J41, J51 to the INT position.
5. Ensure that the Boost Good indicator is green on the GUI
Power Up tab.
6. Ensure Boost is On.
7. By default, the 48 k sample rate is selected, and the boost
switching frequency is 1.5 MHz.
8. In the MIC BIAS CONTROL section, select the desired
microphone bias output voltage (see Figure 3). By default,
it is 8.5 V.
9. Ensure Mic Bias is Enabled (see Figure 3).
10. Check the microphone bias voltage output on the EVA L -
ADAU1977Z board at the test point (TP).
11. Go to the Diagnostics tab on the GUI (see Figure 5).
12. With the microphone connected, the typical voltage at the
positive (+) input is 2/3 of microphone bias, and at the
negative (−) input is 1/3 of microphone bias.
13. Click Read in the Diagnostics tab on the GUI (see Figure 5).
14. With proper connections and normal working conditions,
all of the channel status indicators will be blue for each
respective channel connected with the microphone.
15. To check the diagnostics functionality, create a fault situation
at the microphone input. This fault situation is done by
11751-003
11751-004
11751-005
Rev. 0 | Page 8 of 27
Evaluation Board User Guide UG-600
either using the microphone itself or by using the dummy
300 Ω or 500 Ω resistor connected across the positive and
negative input terminals of the evaluation board.
16. The faults are reported in the channel status indicators for
each channel for which Diag Control is Enabled (see
Figure 5).
17. The GUI shown in Figure 5 provides access to all the
diagnostics registers.
18. The DIAG TRIP POINT ADJUST1 section provides
control for adjusting the trip thresholds (see Figure 5).
19. The DIAG_ADJUST2 section provides the fault timeout
adjustment controls (see Figure 5).
20. The DIAG IRQ1 section is used to generate the IRQ using
the FAULT pin. The Fault Pin Drive section is used to
report the fault in the system (see Figure 5).
21. Use the previous controls, as well as the ADAU1977
diagnostics registers in this data sheet, to suit the needs of
the system using the intended microphone.
STANDALONE GUI SPI CONTROL
The E VA L -ADAU1977Z can also be configured for SPI control
instead of for I2C control. To use in SPI control mode, take the
following steps:
1. Change Slide Switches S3, S4, and S5 to SPI mode.
2. Ensure JP6 is not installed.
3. In the GUI, go to Options/Comm Protocol and select SPI
mode. (The default is I2C mode).
4. The evaluation board is now configured for the SPI
protocol, and the GUI functions similarly to the GUI
functions in I2C mode.
STANDALONE MODE
The evaluation board (E VA L -ADAU1977Z) also has a
standalone mode that does not require any I2C or SPI control.
In standalone mode, the ADAU1977/ADAU1978/ADAU1979
are set internally for a specific operation; no register access is
provided because the I2C and SPI ports are disabled. To invoke
the standalone mode (SA mode), insert Jumper JP6 and set
Slide Switches S3, S4, and S5 to the standalone position. In SA
mode, limited options are available that can be set using the
dual inline package (DIP) Switch S8. See Table 2 for the S8
switch settings.
Table 2. Settings in SA Mode
ADAU1977 Pin No.,
Mnemonic Switch S8 Function OFF ON
Pin 17, SDA/COUT S8-6 MCLK 256 fs to 384 fs select IOVDD 384 fs GND 256 fs
Pin 18, SCL/CCLK S8-5 Full-scale (FS) 48 k/96 k select IOVDD 96 k GND 48 k
Pin 19, ADDR0/CLATCH S8-4 I2S/TDM select IOVDD TDM GND I2S
Pin 20, ADDR1/CIN S8-3 Master/slave select IOVDD Slave GND Master
Pin 14, SDATAOUT2 S8-2 TDM 4 to TDM 8 select IOVDD TDM 8 GND TDM 4
Pin 8, FAULT S8-1 TDM 8 slot assignments, Slot 1 to Slot 4 or
Slot 5 to Slot 8
IOVDD Slot 5 to Slot 8 GND Slot 1 to Slot 4
Rev. 0 | Page 9 of 27
UG-600 Evaluation Board User Guide
EVALUATION BOARD SCHEMATICS AND ARTWORK
Figure 6. EVAL-ADAU1977Z Schematic, Page 1 of 6
PLL FILTER SELECTION
IDVDD
DAUGHTER BOARD HE ADE RS
AVDD_1977
AVDD
MICBIAS
SCAN T E S T HEADER
RESE T ADAU1977
SEL E CT J44 OR J45
NORM ALLY OPEN INSTALL IF US ING EX T DVDD
NOTES ON JUMPER SELECTION
J21: Use for Measuring Current into DC-DC pre inductor
J24: Use for Measuring Current into DC-DC at SW node
J33: Use fo r measuring DUT IOV DD current
J16: Use for Measuring DUT AV DD Cu rre nt
J44: PLL filter selection is using LRCLK as PLL input
J45: PLL filter selection is using MCLK as PLL input
J50: Use fo r selecti ng the level shi f t ed MCL K f or the DUT
J43: Use fo r selecti ng the direct extern al MCL K f or the DUT
1
3
5
7
9
2
4
6
8
10
11
13
15
17
19
12
14
16
18
20
J23
2x10
1
3
5
7
9
2
4
6
8
10
11
13
15
17
19
12
14
16
18
20
J37
2x10
1
3
5
7
9
2
4
6
8
10 11
13
15
17
19
12
14
16
18
20
J32
2x10
C53
0.10µF
C65
0.10µF
C66
0.10µF
C67
0.10µF
C68
0.10µF
C61
0.10µF
C50
10µF
25V
R80
4K87
C97
39nF
C94
2.2nF NP0
1 2
L3
C39
10µF
25V
C42
0.10µF
1
3
5
7
9
2
4
6
8
10 11
13
15
17
19
12
14
16
18
20
J18
2x10
12
J21
DC-DC CURRENT MEASURE M E NT
12
J16
2-JUMPER
R81
1k00
C98
5.6nF
C95
390pF
12
J44
PLL-LRCK
12
J45
PLL-MCLK
R111
OPEN
12
J24
CURRENT
MEASUREMENT
TP34
12
J33
C71
10µF
12
J42
C70
10µF
C49
1.0nF
+C45
10µF
R41
OPEN
TP65
TP66
TP67
TP68
TP35
TP36
TP38
TP41
1AGND1
2VREF
3PLL_FILT
4AVDD2
5AGND2
6/PD/RST
7MCLKIN
8FAULT/TBD_SEL
9SA_MODE
10 DVDD
11
DGND 12
IOVDD 13
SDATAOUT1 14
SDATAOUT2/TDM_SEL 15
LRCLK 16
BCLK 17
SDA/COUT/MCLK_SEL 18
SCL/CCLK/FS_SEL 19
ADDR0/CLATCH/FMT_SEL 20
ADDR1/CIN/MS_SEL
21
PGND
22
PGND
23
SW
24
SW
25
VBOOST_OUT
26
VBOOST_IN
27
MICBIAS
28
MB_GND
29
AGND3
30
VBAT
31 AVDD3
32 AIN1N
33 AIN1P
34 AIN2N
35 AIN2P
36 AIN3N
37 AIN3P
38 AIN4N
39 AIN4P
40 AVDD1
41 EPAD
U12
ADAU1977 TP43
TP44
TP46
TP47
TP74
TP71
TP55
TP54
TP42
TP40
TP29
TP28
TP23
TP50
TP24
TP25
TP63
TP61
TP27
TP69
TP45
TP57
TP72
R47
49.9Ω R50
49.9Ω R53
49.9Ω R56
49.9Ω
TP73
R86
49.9Ω
L5
C106
0.10µF
JP11
R92
10.0kΩ10.0kΩ
R85
49.9Ω
C104
10pF
R83
0Ω
J52
R87
49.9Ω
C105
10pF
R90
0Ω
2
A1
3
A2
7B1
6B2
1
VCCA
8
VCCB
4GND
5
DIR
U20
SN74LVC2T45DCTR
C46
0.10µF
C108
0.10µF
R78
49.9Ω
R82
10.0kΩ
1
2
JP9
R91
OPEN
R89
OPEN
1 2
3 4
5 6
J50
AB 1
2
3
J43
1
3
5
7
9
2
4
6
8
10
11
13
15
12
14
16
J25
2x8
R84
10.0kΩ
JP8
C101
0.10µF
S27
TP62
1OE
2
GND
3
OUTPUT
4
VDD
Y1
OSC_AP3S-12.288MHZ_SMD
R130 0Ω
R131
OPEN
R132
OPEN
C111 C112
R134
10.0kΩ
1
2
J54
FAULT-PULLUP
AVDD
AVDD_ADC
IOVDD_1977
ADDR1/CIN/MS _S E L [1, 5]
ADDR0/CLATCH/ FMT _S E L [1,5]
SCL/CCLK/FS_SEL [5]
SDA/ COUT/ M CLK_SEL [5]
IOVDD
VBAT [2,4]
AIN1N
[2,6] AIN1P
[2,6] AIN2N
[2,6] AIN2P
[2,6] AIN3N
[2,6]
AIN4P
[2,6] AIN4N
[2,6] AIN3P
[2,6]
AVDD_ADC
[1] PD/RST _1977
[1,3] M CLKIN_1977
[5] SA_MODE
AVDD_ADC
AVDD_DC_DC
VREF
VBOOST_IN
AVDD
ADDR1/CIN/MS_SEL
ADDR0/CLATCH/FMT_SEL
SDA/COUT/MCLK_SEL
SCL/CCLK/FS_SEL
FAULT/TBD_SEL
MICBIAS_1977
SA_MODE
MCLKIN_1977
PD/RST_1977
AIN4P
AIN4N
AIN3P
AIN3N
AIN2P
AIN2N
AIN1P
AIN1N
VBAT
MICBIAS_1977 [2]
VREF
DVDD_IN
DVDD
GND
GND
GND
VREF
BCLK
LRCLK
SDATAOUT2/TDM_SEL
SDATAOUT1
BCLK_X [ 3]
LRCLK_X [3]
SDATAOUT2/TDM_SEL_X [3]
SDAT AOUT1_X [ 3]
IOVDD+3.3V
MCLKIN_1977 [1, 3]
+3.3V
MCLK_3.3V
+3.3V
OSC
SMA
AP
[1,3] M CLKIN_1977
[5] SDATAOUT2/TDM_SEL
[1] PD/RST _1977
SDATAOUT1
[1, 5] ADDR0/CLAT CH/FM T_SEL
[1,5] ADDR1/CIN/MS_SEL
LRCLK
BCLK
PD/RST_1977
[1]
IOVDD
AVDD_ADC
AVDD_ADC
AVDD_ADC
11751-006
Rev. 0 | Page 10 of 27
Evaluation Board User Guide UG-600
Figure 7. EVAL-ADAU1977Z Schematic, Page 2 of 6
INP UT CH1
MIC BIAS SELECT P
MIC BIAS SELECT N
FAULT GEN SELECT P
FAULT GEN SELECT N
AC COUP LING CAP BY P AS S
SHO RT P&N
INP UT CH2
MIC BIAS SELECT P
MIC BIAS SELECT N
FAULT GEN SELECT P
FAULT GEN SELECT N
AC COUP LING CAP BY P AS S
SHO RT P&N
INP UT CH3
MIC BIAS SELECT P
MIC BIAS SELECT N
FAULT GEN SELECT P
FAULT GEN SELECT N
AC COUP LING CAP BY P AS S
SHO RT P&N
INP UT CH4
MIC BIAS SELECT P
MIC BIAS SELECT N
FAULT GEN SELECT P
FAULT GEN SELECT N
AC COUP LING CAP BY P AS S
SHO RT P&N
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
INP UT BUFF E R FOR LEVEL SHIFTING INPUT
ANALOG I NP UTS
CM INPUT SELECT
ADJUST FOR DESIRED CM LEVEL
R106 499Ω
R108 499Ω
R105 301Ω
R107 301Ω
1
23
4
S12
1
2 3
4
S7
A B
1
2
3
J22
TP30
AB 1
2
3J20
HDR-3WAY
AB 1
2
3J15
HDR-3WAY
RING
SLEEVE
TIP
J17
C43
1.0nF
C37
1.0nF
1
2
JP2
1
2 3
4
S10
C40
OPEN
C36
OPEN
+
C41
10µF
+
C38
10µF
TP33
R110 499Ω
R113 499Ω
R109 301Ω
R112 301Ω
1
23
4
S18
1
2 3
4
S15
A B
1
2
3
J31
TP49
AB 1
2
3J30
HDR-3WAY
AB 1
2
3J27
HDR-3WAY
RING
SLEEVE
TIP
J28
C78
1.0nF
C60
1.0nF
1
2
JP3
1
2 3
4
S16
C77
OPEN
C56
OPEN
+
C74
10µF
+
C57
10µF
R115 499Ω
R117
499Ω
R114 301Ω
R116 301Ω
1
23
4
S23
1
2 3
4
S20
A B
1
2
3
J41
TP56
AB 1
2
3J40
HDR-3WAY
AB 1
2
3J36
HDR-3WAY
RING
SLEEVE
TIP
J38
C89
1.0nF
C85
1.0nF
1
2
JP5
1
2 3
4
S21
C88
OPEN
C84
OPEN
+
C90
10µF
+
C86
10µF
R119 499Ω
R121
499Ω
R118 301Ω
R120 301Ω
1
23
4
S29
1
2 3
4
S25
A B
1
2
3
J51
TP76
AB 1
2
3J49
HDR-3WAY
AB 1
2
3J46
HDR-3WAY
RING
SLEEVE
TIP
J47
C103
1.0nF
C92
1.0nF
1
2
JP7
1
2 3
4
S26
C102
OPEN
C91
OPEN
+
C100
10µF
+
C93
10µF
12
J19
12
J29
12
J39
12
J48
2–
3+
1
O
8
V+
4
V–
U1-A
R16
10.0kΩ
R17 10.0kΩ
+C18
10µF
R13
100kΩ
C19
10µF
RING
SLEEVE
TIP
J9
1
2
JP1
C16 22pF
R12
10.0Ω
6–
5+7
O
U1-B
R7
10.0kΩ
R9 10.0kΩ
+
C5
10µF
R8
100kΩ
C10
10µF
C6 22pF
R6
10.0Ω
R4
10.0kΩ
R3
10.0kΩ
R2
10.0kΩ
R1
10.0kΩ
CW
2
1
3
R5
1 2
3
5
7
9
11
4
6
8
10
12
J2
HEADER_12WAY_UNSHROUD
C1
C2
5
4
3
2
1
S11
C1
C2
5
4
3
2
1
S6
C1
C2
5
4
3
2
1
S17
C1
C2
5
4
3
2
1
S14
C1
C2
5
4
3
2
1
S22
C1
C2
5
4
3
2
1
S19
C1
C2
5
4
3
2
1
S28
C1
C2
5
4
3
2
1
S24
C12
0.10µF
C13
0.10µF
A B
1
2
3
J1
TP4
TP16
TP5 TP52
TP32
TP26
TP58
TP51
TP39
TP60
TP59
TP53
TP64
TP77
TP70
TP75
R122
0Ω
R123
0Ω
R124 0Ω
R125 0Ω
R126
0Ω
R127
0Ω
R128
0Ω
R129
0Ω
AIN1N
[1,6]
AIN1P
[1,6]
VBAT [2,6]
[1,2,4]
MI CBIAS_CH1 [2]
MICBIAS_1977MICBIAS_EXT
MICBIAS_CH1
+O UT_BUFF E R [ 2]
[2] –OUT_BUFFER
AIN_CH1–
AIN_CH1+
FAULT_IN+
FAULT_IN–
[2,6]
VBAT [2,6]
[1,2,4]
MI CBIAS_CH1 [2]
FAULT_IN+
FAULT_IN–
[2,6]
VBAT [2,6]
[1,2,4]
MI CBIAS_CH1 [2]
FAULT_IN+
FAULT_IN–
[2,6]
AIN2N
[1,6]
AIN2P
[1,6]
MICBIAS_1977MICBIAS_EXT
MICBIAS_CH2
+O UT_BUFF E R [ 2]
–OUT_BUFF E R [ 2]
AIN_CH2–
AIN_CH2+
AIN3N
[1,6]
AIN3P
[1,6]
MICBIAS_1977MICBIAS_EXT
MICBIAS_CH3
+O UT_BUFF E R [ 2]
–OUT_BUFF E R [ 2]
AIN_CH3–
AIN_CH3+
AIN4N
[1,6]
AIN4P
[1,6]
MICBIAS_1977MICBIAS_EXT
MICBIAS_CH4
+O UT_BUFF E R [ 2]
–OUT_BUFF E R [ 2]
AIN_CH4–
AIN_CH4+
[2]
[2]
HVDD
HVSS
[2] CM_IN+
+O UT_BUFF E R [ 2]
+IN_BUFFER
-IN_BUFFER
[2] CM_IN–
–OUT_BUFF E R [ 2]
MICBIAS
VBAT
[1,2,4]
CM_IN+ [2]
CM_IN– [ 2]
2/3MICBIAS
1/3MICBIAS
1/2VBAT
HVSS
HVDD
MICBIAS_1977MICBIAS_EXT
NOTES ON JUMPER SELECTION
J2: USE FOR SELECTING THE CM LEVEL FO R THE EXTERNAL INPUT
J1, J22, J31, J41, J51 : US E FOR SE LECT ING I NTERNAL OR EXTERNAL M ICBIAS FOR INPUTS
S12, S18, S23, S29: USE FOR SELECTING THE MICBIAS RESISTOR +INPUTS
S5, S15, S20, S25: USE FOR SELECTING THE MICBIAS RESISTOR -INPUTS
J20, J15, J30, J27, J40, J36, J49, J46: USE FOR S E LECTING THE DIRE CT OR BUF FERED INPUT
J19, J29, J39, J48: USE FOR SHORTING THE +/- INPUT PINS FOR DIAGNOSTICS TEST
S11, S6, S17, S14, S22, S19, S28, S24: USE FOR GENERATING FAULT ON INPUT PINS FOR DIAGNOSTICS TESTING
11751-007
Rev. 0 | Page 11 of 27
UG-600 Evaluation Board User Guide
Figure 8. EVAL-ADAU1977Z Schematic, Page 3 of 6
I2S TO SPDIF
SPDIF CO AX OUTP UT
SPDIF O P TICAL OUT P UT
INSTALL FOR 96KHz Fs
I2S OUTPUT
MASTER / SLAVE SELECT
SDATA1
SDATA2
LRCLK
BCLK
NC
RESET_SPDIF
NOTES ON JUMPER SELECTION
LK3, LK5: US E FOR ROUTI NG THE S DATA TO SPDI F OR I2S HEADER
LK2: US E FOR RO UTING THE LRCLK TO S P DIF O R I2S HEADE R
LK2: US E FOR RO UTING THE BCLK TO SPDIF O R I2S HEADE R
LK2: US E FOR RO UTING THE M CLK TO SPDIF
S13: USE FOR SELECTING THE I2S BUFFER AS MASTER OR SLAVE
I2S/TDM OUTPUT
14 SDIN
12 ILRCLK
13 ISCLK
21 OMCK
3EMPH
16 CEN
1COPY/C
28 ORIG
4SFMT0
9RST
6
VD
23
VL
26
TXP
25
TXN
24
H/S
19
AUDIO
10
APMS
20
HWCK0
11
TCBLD
27
HWCK1
22 GND
5SFMT1 2
NC1
7
NC2
8
NC3
17
V
15 TCBL
18 U
U17
CS8406_HARDWARE
C107
0.10µF
C81
0.10µF
R67 47.5kΩ
R66 47.5kΩ
R61 47.5kΩ
R74
47.5kΩ
R76 47.5kΩ
R64 47.5kΩ
R73 47.5kΩ
R63 47.5kΩ
R75 47.5kΩ
R71 47.5kΩ
R60 47.5kΩ
R77 47.5kΩ
R59 47.5kΩ
R62 47.5kΩ
R72
47.5kΩ
B A
LK2
B A
LK1
BA
LK6
BA
LK5
B A
LK4
BA
LK3
1
4
5
8
2
6
U19
SC937-02_AES_TRANSFORMER
1
GND
2
DVDD
3INPUT
U16
TOTX147L(FT)
R69
243Ω
R68
110Ω
R65
10.0kΩ
L4
600Ω @ 100MHz
C73
0.10µF
J35
CTP-021A-S-YEL
C79
10nF
C87
22pF
1
2
J34
128*Fs
2A
3
GND
1
VCCA
5
VCCY
GND VCCA
VCCY
GND VCCA
VCCY
GND VCCA
VCCY
4
YU15
FXLP34P5X
2A
3
154
Y
U14
FXLP34P5X
2A
3
154
Y
U9
FXLP34P5X
2A
3
154
Y
U18
FXLP34P5X
12 34 5
67
8
J26
R51 49.9Ω
C58 10pF
R37 49.9Ω
C44 10pF
R54 49.9Ω
C54 10pF
R70 49.9Ω
C82 10pF
R42 1k00
C47 100pF
R45 1k00
C52 100pF
R38
10.0kΩ
24
U8
NC7SZ04M5
R55 49.9Ω
R48 49.9Ω
R43 24.9Ω
R40 24.9Ω
R52 1k00
R57 1k00
C59 100pF
C64 100pF
R44 24.9Ω
R39 24.9Ω
R49 24.9Ω
R46 24.9Ω
5A2
4
OE2
6
Y2
U11-B
9A3
10
OE3
8
Y3
U11-C
12 A4
13
OE4
11
Y4
U11-D
2A1
1
OE1
3
Y1
U11-A
SN74LVC125ADR
2
A
3
GND
1
OE
5
VCCY
4Y
U13
NC7SZ125
2
A
3
GND
15
VCCY
4Y
U10
NC7SZ125
7
GND 14
VCC
U11-E
SN74LVC125ADR
C80
0.10µF
C72
0.10µF
C96
0.10µF
12
S13
SPST_1SEC_SMD
R58 10.0kΩ
JP4
C63
0.10µF
C99
0.10µF
C17
0.10µF
C48
0.10µF
C24
0.10µF
C69
0.10µF
C26
0.10µF
C75
0.10µF
+3.3V +3.3V
+3.3V
[1] LRCLK_X
[1] SDATAOUT2/TDM_SEL_X
[1] MCLKIN_1977
+3.3V
[1] BCLK_X
[1] S DATAOUT 1_X
LO
HI
+3.3V
+3.3V
IOVDD +3.3V
IOVDD
+3.3V
IOVDD
+3.3V
+3.3V
IOVDD
SDATA1_OUT
SDATA2_OUT
BCLK_IO
LRCLK_IO
IOVDD
MASTER_SEL[3]
SLAVE_SEL[3]
IOVDD
IOVDD
SLAVE_SEL
[3]
IOVDD
MASTER_SEL
[3]
SDATA1_OUT
SDATA2_OUT
LRCLK_IO
BCLK_IO
11751-008
OE
Rev. 0 | Page 12 of 27
Evaluation Board User Guide UG-600
Figure 9. EVAL-ADAU1977Z Schematic, Page 4 of 6
HV I NPUT 3. 3V REG SELECT
1. 8V REG SELECT IOVDD SELECT
+2 2 VDC MAX
GND
+5VDC
+5V INPUT
–22VDC MAX
TP13TP15TP21
B
A
123
J13
TP18
TP17
C30
1.0µF
C31
1.0µF
+C32
10µF
+C29
15µF
3EN
2
GND
1IN 5
OUT 4
BYP
U4
ADP1711AUJZ-1.8-R7
C33
10nF
D3
Red Diffused
R26
475R
TP2
B A 1
2
3J10
HDR-3WAY
TP31 TP37
1SYNC/MODE
2FREQ
3TRK
4FB
5GND
6PGND
7PGND
8PGND
9
SW
10
SW
11
SW
12
PVIN
13
PVIN
14
VIN
15
EN
16
PGOOD
17
EPAD
U3
ADP2118
R10
10Ω
R11
10.0kΩ
R18
10.0kΩ
R14
2.21kΩ
1 2
L2
C28
100µF
C14
100µF
TP9
TP3
C4
0.10µF +C2
47µF
1
2
J4
BINDING_POST_571_BLK
D2
TP48
TP6
C11
0.10µF+C15
47µF
1
2
J5
BINDING_POST_571_RED
L1
100Ω @ 100MHz TP8
TP22
R23
243Ω
C35
0.10µF
C22
0.10µF
D1
DL4001_50V_1A_DL41
R24
2.67kΩ
C34
0.10µF
D4
3IN
1
ADJ
4
OUT1
U2
LM317BD2T
B A 1
2
3J12
TP20
TP1 C3
0.10µF +C1
47µF
R25
10k0
12
S1
12 S2
SPST_1SEC_SMD
TP19
1
2
J7
BINDING_POST_571_RED BA
123
J11
C9
OPEN
1
2
J3
BINDING_POST_571_RED BA
123
J14
C7
NF 25V
TP7
1
2
J6
BINDING_POST_571_RED C8
OPEN
C109
1µF
C110
0.10µF
BA
123
J53
+3.3V +3.3V_EXT
+5V 1.8V
1.8V
+3.3V IOVDD_INT
+3.3V_REG
+5V
HVDD
+5V_EXT
+15V_REG EXT_VBAT
VBAT
HVSS
IOVDD_INTIOVDD
IOVDD_EXT
+3.3V
AVDD
AVDD_EXT
DVDD_IN
+5V
DVDD_IN
11751-009
Rev. 0 | Page 13 of 27
UG-600 Evaluation Board User Guide
Figure 10. EVAL-ADAU1977Z Schematic, Page 5 of 6
USBi OR AARDVARK I 2C INTERFACE
USBI_CLK
USBI_5V00
I2 C L EVEL SHIFT & DUT ADDRESS
MR L INE CO M E S FROM USBi BOARD RESET
LEVEL SHIF T
I2 C COMMUNICATI ON
SPI LEVEL SHI FT
I2 C, SPI or STAND- ALONE MODE SELECT
I2 C- SPI OR SA M ODE SELECT
ADDR1
ADDR0
STAND ALONE MODE
ADDRESS
NOT ES F OR JUM PE RS AND SW ITCHES
S3, S 4, S5 ARE 3 WAY SWIT CHES T O BE USED I N T ANDEM FO R I2C, SPI OR SA MO DE
SET ALL T HREE S W ITCHES TO EITHER LEF T, CENTER OR RI GHT
S8 I S USED F OR SETTING THE P IN FUNCTI ONS IN SA M ODE
J8: USE FO R CONNECTING T HE AARDVARK I2C/SPI CONT ROL ADAPTER OR USBI
1
3
5
7
9
2
4
6
8
10
J8
R21
2.43kΩ
R22
2.43kΩ R15
10.0kΩ
TP11TP10
2
SCLA 3
SDAA
7SCLB
6SDAB
1
VCCA
8VCCB
4
GND
5EN U6
PCA9517DP-T_I2CBUSRPT_LVLTRANS_TSSOP8
C55
C25
0.10µF
C51
0.10µF
C27
0.10µF
2
A1 3
A2
7B1
6B2
1
VCCA
8
VCCB
4GND
5
DIR
U5
SN74LVC2T45DCTR
C62
0.10µF
C83
0.10µF
1
2 3
4
S9
R34
10.0kΩ
R33
10.0kΩ
R20
2k00 R19
2k00
3
1
2
4
S4-A
7
5
6
8S4-B
3
1
2
4
S5-A
7
5
6
8S5-B
3
1
2
4
S3-A
7
5
6
8S3-B
JP6
R79
10.0kΩ
R32 10.0kΩ
R31 10.0kΩ
R30 10.0kΩ
R29 10.0kΩ
1
2
3
4
5
67
8
9
10
11
12 S8
R28 10.0kΩ
R27 10.0kΩ
R36 1k00
R35 1k00
2A
3
GND
1
VCCA
5
VCCY
GND VCCA
VCCY
4
Y
U23
FXLP34P5X
2A
3
154
Y
U24
FXLP34P5X
C113
0.10µF
C114
0.10µF
R133
10.0kΩ
USBI_SCL [5,6]
USBI _CCL K [5]
USBI _CL ATCH [5]
USBI_CIN_MOSI [5]
+3.3V
ADDR1/ CIN/MS_ SEL [1]
ADDR0/ CL ATCH/FMT_SEL [ 1 ]
SDA/ COUT/ MCLK_SEL [ 1 ]
SCL/CCLK/FS_SEL [1]
+3.3V IOVDD
USBI_SCL[5,6]
USBI_SDA[5,6]
IOVDD
+3.3V
USBI _CL ATCH [5]
IOVDD+3.3V
USBI_CIN_MOSI [5]
USBI _CCL K [5]
USBI_COUT_MISO [5]
IOVDD
IOVDD
USBI_COUT_MISO [5]
USBI _S DA [ 5 ,6]
SDATAO UT 2/TDM_SEL [1]
FAULT/TBD_SEL [1]
SA_MODE SA_MODE [1]
IOVDD
FMT_SEL
MCLK_SEL
TDM_SEL
TBD_SEL
FS_SEL
MS_SEL
CIN_IOVDD
CLATCH_IOVDD
SCL_IOVDD
CCLK_IOVDD
SDA_IOVDD
COUT_IOVDD
+3.3V IOVDD
IOVDD
+3.3V
0.10µF
11751-010
Rev. 0 | Page 14 of 27
Evaluation Board User Guide UG-600
Figure 11. EVAL-ADAU1977Z Schematic, Page 6 of 6
FAULT GENERATION L OGIC CONTRO L 1 FAULT GENERATION L OGIC CONTRO L 2
INP UT CH1
INP UT CH2
INP UT CH3
INP UT CH4
SHO RT AIN2P TO AIN2N FAULT_ IN– TO AIN2 N FAULT_ IN+ T O AIN2 P
FAULT_ IN– TO AIN1 N FAULT_ IN+ T O AIN1 P SHO RT AIN3P TO AIN3N FAULT_ IN– TO AIN3 N FAULT_IN+ T O AI N3P
SHO RT AIN4P TO AIN4N FAULT_ IN– TO AIN4 N FAULT_IN+ T O AI N4P
SHO RT AIN1P TO AIN1N
DISABLE FAULT LOGI C
I2C ADDRESS 0x19Hex
I2C ADDRESS 0x18Hex
FAULT GENERATION F OR AUTO MATED TEST ING
1SCL
2SDA
3AD0
4AD1
5AD2
6IO0
7IO1
8GND 9
IO2 10
IO3 11
IO4 12
IO5 13
IO6 14
IO7 15
RESET 16
VDD
U22
MAX7310-QSOP16
R100 10.0kΩ R96 OPEN
R104 10.0kΩ R103 OPEN
R101 10.0kΩ R97 OPEN
C23
0.10µF
1SCL
2SDA
3AD0
4AD1
5AD2
6IO0
7IO1
8GND 9
IO2 10
IO3 11
IO4 12
IO5 13
IO6 14
IO7 15
RESET 16
VDD
U21
MAX7310-QSOP16
R93 OPEN R94 10.0KΩ
R98 10.0kΩ R102 OPEN
R95 10.0kΩ R99 OPEN
C76
0.10µF
+
5
8
2
4
K1
+
5
8
2
4
K6
+
5
8
2
4
K5
1
IN
2
GND
3
OUT
Q1
1
IN
2
GND
3
OUT
Q6
1
IN
2
GND
3
OUT
Q5
KA
D9
KA
D10
KA
D5
+
5
8
2
4
K2
+
5
8
2
4
K8
+
5
8
2
4
K7
1
IN
2
GND
3
OUT
Q2
1
IN
2
GND
3
OUT
Q8
1
IN
2
GND
3
OUT
Q7
KA
D11
KA
D12
KA
D6
+
5
8
2
4
K3
+
5
8
2
4
K10
+
5
8
2
4
K9
1
IN
2
GND
3
OUT
Q3
1
IN
2
GND
3
OUT
Q10
1
IN
2
GND
3
OUT
Q9
KA
D13
KA
D14
K
A
D7
+
5
8
2
4
K4
+
5
8
2
4
K12
+
5
8
2
4
K11
1
IN
2
GND
3
OUT
Q4
1
IN
2
GND
3
OUT
Q12
1
IN
2
GND
3
OUT
Q11
KA
D15
KA
D16
KA
D8
TP12
TP14
C20
0.10µF
C21
0.10µF
R88 10.0kΩ
JP10
+3.3V
USBI_SCL [5,6]
USBI _S DA [ 5 ,6]
+3.3V
FAULT_ AIN4P [ 6 ]
FAULT_ AIN2P [ 6 ]
FAULT_ AIN1P [ 6 ]
FAULT_ AIN3P [ 6 ]
FAULT_ AIN4N [ 6 ]
FAULT_ AIN2N [ 6 ]
FAULT_ AIN1N [ 6 ]
FAULT_ AIN3N [ 6 ]
+3.3V
USBI_SCL [1,2]
USBI _S DA [ 1 ,2]
+3.3V
FAULT_ AIN3P_AIN3N [6]
FAULT_ AIN1P_AIN1N [6]
FAULT_ AIN4P_AIN4N [6]
FAULT_ AIN2P_AIN2N [6]
FAULT_ AIN1P [ 6 ]
FAULT_ AIN1N [ 6 ]
FAULT_ AIN1P_AIN1N [6]
AIN1P [1,2]
AIN1N [1,2]
+3.3V +3.3V +3.3V
FAULT_IN–
[2,6] [2,6]
FAULT_IN+
FAULT_ AIN2P [ 6 ]
FAULT_ AIN2N [ 6 ]
FAULT_ AIN2P_AIN2N [6]
AIN2P [1,2]
AIN2N [1,2]
+3.3V +3.3V +3.3V
FAULT_IN–
[2,6] FAULT_IN+
[2,6]
FAULT_ AIN3P [ 6 ]
FAULT_ AIN3N [ 6 ]
FAULT_ AIN3P_AIN3N [6]
AIN3P
[1,2]
AIN3N
[1,2]
+3.3V +3.3V +3.3V
FAULT_IN–
[2,6] FAULT_IN+
[2,6]
FAULT_ AIN4P [ 6 ]
FAULT_ AIN4N [ 6 ]
FAULT_ AIN4P_AIN4N [6]
AIN4P
[1,2]
AIN4N
[1,2]
+3.3V +3.3V +3.3V
FAULT_IN–
[2,6] FAULT_IN+
[2,6]
FAULT_IN+
[2,6]
FAULT_IN–
[2,6]
+3.3V
DISABLE_FAULT_LOGIC
11751-011
Rev. 0 | Page 15 of 27
Evaluation Board User Guide UG-600
ORDERING INFORMATION
BILL OF MATERIALS
Table 3.
Qty1 Component Number Description Manufacturer Part Number
2 C10, C19 Ceramic capacitor, 10 µF,
50 V, X7R, 20%, 2220
Digi-Key 445-1454-1-ND
NF C107, C108 Multilayer ceramic, 16 V, X7R
(0402)
Digi-Key PCC13490CT-ND
1 C109 Multilayer ceramic capacitors
(MLCC), 50 V, X7R (1206)
Digi-Key 490-4795-6-ND
34 C11, C17, C23 to C27, C42, C46,
C48, C51, C53, C55, C61 to C63,
C65 to C69, C72, C75, C76, C80,
C81, C83, C96, C99, C101, C106,
C110, C113, C114
Ceramic capacitor, 0.1 µF,
16 V, 10%, X7R, 0402
Digi-Key 490-3261-1-ND
NF C111, C112 Ceramic capacitor, 1000 pF,
50 V, 10%, X7R, 0603
Digi-Key 490-1494-1-ND
3 C1, C2, C15 Aluminium electrolytic
capacitor frequency
converter (FC), 105°, surface-
mount device E (SMD_E)
Digi-Key PCE4008CT-ND
2 C14, C28 Multilayer ceramic, 6.3 V, X5R
(1210 )
Digi-Key 490-3390-1-ND
NF C20, C21 Multilayer ceramic, 50 V, X7R
(0603)
Digi-Key PCC2398CT-ND
1 C29 Surface-mount device (SMD),
tantalum capacitor, 0805, 6.3
V
Digi-Key 511-1448-1-ND
2 C30, C31 Ceramic capacitor, 1 µF, 16 V,
10%, X7R, 0603
Digi-Key 490-3900-1-ND
1 C32 SMD, tantalum capacitor,
0805, 6.3 V
Digi-Key 511-1447-1-ND
2 C33, C79 Multilayer ceramic, 25 V, NP0
(0603)
Digi-Key 445-2664-1-ND
8 C3, C4, C12, C13, C22, C34, C35,
C73
Ceramic capacitor, 0.1 µF, 50
V, 10%, X7R, 0603
Digi-Key 490-1519-1-ND
NF C36, C40, C56, C77, C84, C88,
C91, C102
Multilayer varistor, 65 V, 0603 Digi-Key P14254CT-ND
9 C37, C43, C49, C60, C78, C85,
C89, C92, C103
Ceramic capacitor, 1000 pF,
50 V, 10%, X7R, 0603
Digi-Key 490-1494-1-ND
8 C38, C41, C57, C74, C86, C90,
C93, C100
Aluminium electrolytic
capacitor frequency
converter (FC,) 105°, surface-
mount device B (SMD_B)
Digi-Key PCE3995CT-ND
1 C39, C50 Multilayer ceramic, 25 V, X7R
(1210), AECQ200
Digi-Key 490-4798-1-ND
6 C44, C54, C58, C82, C104, C105 Multilayer ceramic, 50 V, NP0
(0402)
Digi-Key 399-1011-1-ND
NF C45 Aluminium electrolytic
capacitor frequency
converter (FC), 10 µF, 50 V,
105°, radial
Digi-Key PCE4012CT-ND
4 C47, C52, C59, C64 Multilayer ceramic, 50 V, NP0
(0402)
Digi-Key 490-4756-1-ND
2 C5, C18 Aluminium electrolytic
capacitor frequency
converter (FC), 10 µF, 50 V,
105°, radial
Digi-Key PCE4012CT-ND
Rev. 0 | Page 23 of 27
UG-600 Evaluation Board User Guide
Qty1 Component Number Description Manufacturer Part Number
3 C6, C16, C87 Multilayer ceramic, 50 V, NP0
(0402)
Digi-Key 490-1283-1-ND
NF C7 Multilayer ceramic, 25 V, X7R
(1210), AECQ200
Digi-Key 490-4798-1-ND
2
C70, C71
Multilayer ceramic, 10 V, X7R
(0805)
Digi-Key
490-3905-1-ND
NF C8, C9 Multilayer ceramic, 10 V, X7R
(0805)
Digi-Key 490-3905-1-ND
1 C94 Multilayer ceramic, 25 V, NP0
(0402)
Mouser 77-VJ0402Y222JXXCBC
1 C95 Multilayer ceramic, 50 V, NP0
(0402)
Digi-Key 490-1296-1-ND
1 C97 Multilayer ceramic, 25 V, NP0
(1206)
Digi-Key 490-3361-1-ND
1 C98 Multilayer ceramic, 25 V, NP0
(0603)
Digi-Key 445-2666-1-ND
2 D1, D4 Passivated rectifier 1 A, 50 V,
metal oxide leadless face
(MELF)
Digi-Key DL4001-TPMSCT-ND
1 D2 Transient voltage suppressor
(TVS) Zener, 15 V, 600 W,
surface-mount board (SMB)
Digi-Key 1SMB15AT3GOSCT-ND
1 D3 Red diffused,
6.0 millicandela, 635 nm,
1206
Digi-Key 67-1003-1-ND
NF D5, D16 Passivated rectifier 1 A, 50 V,
metal oxide leadless face
(MELF)
Digi-Key DL4001-TPMSCT-ND
20 J1, J10 to J15, J20, J22, J27, J30,
J31, J36, J40, J41, J43, J4, J6, J49,
J51, J53
3-position, single inline
package (SIP) header
Digi-Key S1011E-03-ND
13 J16, J19, J21, J24, J29, J33, J34,
J39, J42, J44, J45, J48, J54
2-pin header, unshrouded
jumper 0.10"; use shunt Tyco
881545-2
Digi-Key S1011E-02-ND
NF J18, J23, J32, J37 20-way, unshrouded Digi-Key S2011E-10-ND
1 J2 12-way, unshrouded Digi-Key S2011E-06-ND
1 J25 16-way, unshrouded Digi-Key S2011E-08-ND
1 J26 8-way, unshrouded header,
dual row
Digi-Key S2011E-04-ND; or cut S2011E-36-ND
NF J3, J6, J7 Binding post, mini, right
angle, red, uninsulated base,
through hole (TH)
Mouser 164-6220
1 J35 RCA jack, PCB through hole
(TH) mount, right angle,
yellow
Connect-Tech Products CTP-021A-S-YEL
1 J4 Binding post, mini, right
angle, black, uninsulated
base through hole (TH)
Mouser 164-6218
1 J5 Binding post, mini, right
angle, red, uninsulated base,
through hole (TH)
Mouser 164-6219
1 J50 6-way, unshrouded header Digi-Key S2011E-03-ND
1 J52 SMA, receptacle straight,
(PCB) mount
Digi-Key ARFX1231-ND
1 J8 10-way, shroud, polarized
header
Digi-Key MHC10K-ND
5 J9, J17, J28, J38, J47 Stereo mini jack, surface-
mounted (SMT)
Digi-Key CP-3523SJCT-ND
NF JP10 2-pin header, unshrouded Digi-Key S1011E-02-ND
Rev. 0 | Page 24 of 27
Evaluation Board User Guide UG-600
Qty1 Component Number Description Manufacturer Part Number
jumper, 0.10"; use shunt Tyco
881545-2
10 JP1 to J9, JP11 2-pin header, unshrouded
jumper, 0.10"; use shunt Tyco
881545-2
Digi-Key S1011E-02-ND
NF K1 to K12 Relay Telecom, single-pole
single throw (SPST),1 A, 3 V
dc SMA
Digi-Key. Z1230-ND
1 L1 Chip ferrite bead, 100 Ω at
100 MHz
Digi-Key 587-1929-1-ND
1 L2 Inductor, 2.2 µH, 1.7 A,
SM1515
Digi-Key 490-5326-1-ND
1 L3 Inductor, 4.7 µH, 2.4 A,
surface-mount device
Digi-Key 732-1039-1-ND
1 L4 Chip ferrite bead, 600 Ω at
100 MHz
Digi-Key 445-2205-1-ND
1 L5 Chip ferrite bead, 600 Ω at
100 MHz
Digi-Key 445-2162-1-ND
6 LK1 to LK6 3-position, single inline
package (SIP) header
Digi-Key S1011E-03-ND
NF Q1 to Q12 Negative-positive-negative
(NPN), general-purpose,
transistor with bias
DDTC114EKA-7-F
Digi-Key DDTC114EKA-7-FDICT-ND
8 R105, R107, R109, R112, R114,
R116, R118, R120
Chip resistor, 1%, 125 mW,
thick film, 0805
Digi-Key P301CCT-ND
8 R106, R108, R110, R113, R115,
R117, R119, R121
Chip resistor, 1%, 125 mW,
thick film, 0805
Digi-Key P499CCT-ND
3 R11, R18, R25 Chip resistor, 0.1%, 100 mW,
thin film, 0603
Digi-Key TNP10.0KAACT-ND
NF R111 Chip resistor, 0.1%, 1 W, thick
film, 0805
Digi-Key Y1487-.01-ND
NF R131 to R132 Chip resistor, 1%, 250 mW,
thick film, 1206
Digi-Key P10.0FCT-ND
1 R14 Chip resistor, 0.1%, 100 mW
thin film, 0603
Digi-Key TNP2.21KAACT-ND
24 R1 to R4, R7, R9, R15 to R17, R27
to R34, R58, R79, R82, R84, R92,
R133, R134
Chip resistor ,1%, 63 mW,
thick film, 0402
Digi-Key P10.0KLCT-ND
2 R19, R20 Chip resistor,1%, 63 mW,
thick film, 0402
Digi-Key P2.00KLCT-ND
2 R21, R22 Chip resistor ,1%, 63 mW,
thick film, 0402
Digi-Key P2.43KLCT-ND
1
R23
Chip resistor, 1%, 125 mW,
thick film, 0805
Digi-Key
P243CCT-ND
1 R24 Chip resistor, 1%, 125 mW,
thick film, 0805
Digi-Key P2.67KCCT-ND
1 R26 Chip resistor, 1%, 63 mW,
thick film, 0402
Digi-Key P475LCT-ND
7 R35, R36, R42, R45, R52, R57,
R81
Chip resistor, 1%, 63 mW,
thick film, 0402
Digi-Key P1.00KLCT-ND
14 R37, R47, R48, R50, R51, R53 to
R56, R70, R78, R85 to R87
Chip resistor,1%, 63 mW,
thick film, 0402
Digi-Key P49.9LCT-ND
2 R38, R65 Chip resistor, 1%, 125 mW,
thick film, 0603
Digi-Key P10.0KHCT-ND
6 R39, R40, R43, R44, R46, R49 Chip resistor, 1%, 63 mW,
thick film, 0402
Digi-Key P24.9LCT-ND
NF R41 Chip resistor, 5%, 125 mW,
thick film, 0805
Digi-Key P1.0ACT-ND
Rev. 0 | Page 25 of 27
UG-600 Evaluation Board User Guide
Rev. 0 | Page 26 of 27
Qty1 Component Number Description Manufacturer Part Number
1 R5 Trim potentiometer, 10 k Ω
linear, 3 mm, single turn,
surface-mount device (SMD)
top adjust
Digi-Key 490-2644-1-ND
15 R59 to R64, R66, R67, R71 to R77 Chip resistor,1%, 63 mW,
thick film, 0402
Digi-Key P47.5KLCT-ND
3 R6, R10, R12 Chip resistor, 1%, 125 mW,
thick film, 0805
Digi-Key P10.0CCT-ND
1 R68 Chip resistor, 1%, 125 mW,
thick film, 0805
Digi-Key P110CCT-ND
1 R69 Chip resistor, 1%, 100 mW,
thick film, 0603
Digi-Key P243HCT-ND
2 R8, R13 Chip resistor, 1%, 125 mW,
thick film, 0603
Digi-Key P100KHCT-ND
1 R80 Chip resistor, 1%, 63 mW,
thick film, 0402
Digi-Key P4.87KLCT-ND
11 R83, R90, R122 to R130 Chip resistor, 5%, 63 mW,
thick film, 0402
Digi-Key P0.0JCT-ND
NF R88, R93, R95, R98, R100, R101,
R104
Chip resistor, 1%, 63 mW,
thick film, 0402
Digi-Key RHM10.0KLCT-ND
NF R89, R91 Chip resistor, 1%, 100 mW,
thick film, 0603
Digi-Key P100HCT-ND
NF R94, R96, R97, R99, R102, R103 Do not stuff OPEN OPEN
3 S1 to S2, S13 1 section, single-pole single
throw, (SPST), surface-mount
device (SMD)
Digi-Key 563-1003-1-ND
1 S27 Tact switch, 6 mm gull wing Digi-Key 450-1133-ND
3 S3 to S5 Switch glide, DP3T PC, mount
L = 4 mm
Digi-Key EG1920-ND
NF S6, S11, S14, S17, S19, S22, S24,
S28
Switch rotary, 1P5T, top
adjust through hole
Digi-Key 563-1078-ND
13 S7, S9, S10, S12, S15, S16, S18,
S20 to S21, S23, S25, S26, S29
2 section, single-pole single
throw, surface-mount device,
switch raised act
Digi-Key CT2192LPST-ND
1 S8 6 section, single-pole single
throw, surface-mount device,
switch raised act
Digi-Key CT2196LPST-ND
75 TP1 to TP11, TP15 to TP77 Mini test point, white, 1"
outer diameter
Digi-Key 5002K-ND
NF TP12 to TP14 Mini test point, white, 1"
outer diameter
Digi-Key 5002K-ND
1 U1 Dual bipolar/junction, field
effect transistor (JFET), audio
operational amplifier.
Analog Devices Inc. OP275GSZ
2 U10, U13 IC, buffer tristate,
noninverting, SC70-5
Digi-Key NC7SZ125P5XCT-ND
1 U11 Quad buffer, tristate, 14-lead
SOIC
Digi-Key 296-8453-1-ND
1 U12 IC, 4-channel ADC with
diagnostics, ADAU1977 40-
lead LFCSP
Analog Devices, Inc. ADAU1977WBCPZ
1 U16 Fiber optic transmit module,
15 Mbs with shutter
Digi-Key TOTX147L-ND
1 U17 192 kHz, Sony Philips digital
interface format (SPDIF)
transmitter
Newark In One 88H6508
1 U19 110 Ω audio, Engineering
Society/European
Broadcaster Union (AES/EBU)
Scientific Conversion Inc. SC937-02
Evaluation Board User Guide UG-600
Rev. 0 | Page 27 of 27
Qty1 Component Number Description Manufacturer Part Number
transformer
1 U2 Integrated circuit, positive
voltage regulator LM317,
adjust, D2PAK
Digi-Key LM317BD2TR4GOSCT-ND
NF U21, U22 Integrated circuit, I2C, 8-bit,
input/output expander
Digi-Key MAX7310AEE+-ND
1 U3 Step down, dc to dc, voltage
regulator, ADP2118
Digi-Key ADP2118ACPZ-R7CT-ND
1 U4 Adjustable, low dropout,
voltage regulator
Analog Devices ADP1711AUJZ-1.8-R7
2 U5, U20 Integrated circuit, 2-bit, dual
bus TXRX, 8-lead shrink small
outline package (SSOP)
Digi-Key 296-16845-1-ND
1 U6 Integrated circuit, I2C bus
repeater, 8-lead thin shrink
small outline package
(TSSOP)
Digi-Key 568-1829-2-ND
1 U8 Integrated circuit, tiny logic
inverter, NC7SZ04
Digi-Key NC7SZ04M5CT-ND
6 U9, U14, U15, U18, U23, U24 Translator, 1-bit, unidirect,
SC70-5
Digi-Key FXLP34P5XCT-ND
1 Y1 12.288 fixed, surface-mount
device (SMD) oscillator, 1.8 V
to 3.3 V voltage direct current
(VDC)
Digi-Key AP3S-12.288MHz-F-J-B
1 NF: not fitted or do not populate; ALT: alternate or equivalent.
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
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UG11751-0-8/14(0)
