1
©2007 Integrated Device Technology, Inc.
OCTOBER 2008
DSC-3821/05
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
Pin Description Summary
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBTTM,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
Features
◆◆
◆◆
◆128K x 36 memory configuration, pipelined outputs
◆◆
◆◆
◆Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized registered outputs eliminate the
need to control OE
◆◆
◆◆
◆Single R/W (READ/WRITE) control pin
◆◆
◆◆
◆Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆◆
◆◆
◆4-word burst capability (interleaved or linear)
◆◆
◆◆
◆Individual byte write (BW1 - BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆Single 3.3V power supply (±5%)
◆◆
◆◆
◆Packaged in a JEDEC standard 100-pin TQFP package
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
when CEN is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers (reads or writes) will be completed. The data bus will tri-state two
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the LBO input
pin. The LBO pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.
IDT71V546S/XS
128K x 36, 3.3V Synchronous
SRAM with ZBT™™
™™
™ Feature,
Burst Counter and Pipelined Outputs
A
0
- A
16
Address Inputs Input Synchronous
CE
1
, CE
2
, CE
2
Three Chip Enables Input Synchronous
OE Output Enable Input Asynchronous
R/WRe ad / Write Sig nal Inp ut S ync hro no us
CEN Clock Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
Indiv idual By te Write Selects Input Sync hronous
CLK Clock Input N/A
ADV/LD Advance Burst Address / Load New Address Input Synchronous
LBO Linear / Interleaved Burst Order Input Static
I/O
0
- I/O
31
, I/O
P1
- I/O
P4
Data Inp ut/Outp ut I/O Sync hronous
V
DD
3.3V Po we r Sup ply Static
V
SS
Ground Supply Static
3821 t b l 01
2
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Descri ption
A
0
- A
16
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a
co mb inatio n o f the ris ing e d ge o f CLK and ADV/ LD Lo w, CEN Low and true
chip enables.
ADV/LD Address/Load I N/A ADV/LD i s a synchro no us i nput that is use d to lo ad the internal reg iste rs wi th
new add ress and control when it is sampled low at the rising edge of clock with
the chip se le cte d. When ADV/LD is low with the chip deselecte d, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
co unter is adv anc e d for any burs t that was in p ro g res s. The e xternal ad dres se s
are ignored when ADV/LD is sampled high.
R/WRead/Write I N/A R/W si gnal is a sy nc hrono us inp ut that ide ntifie d whethe r the current load cy c le
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place two clock cycles later.
CEN Clock Enable I LOW Synchrono us Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of CEN samp led high on the device outputs is as if the low to high
clock transition d id not occur. For normal operation, CEN must b e s ampled lo w
at rising edge of clock.
BW
1
- BW
4
Indiv id ual B y te
Write Enab les I LOW Synchro no us b y te write e nab les. Enab le 9-b it b y te has its own activ e lo w b yte
write enable. On load write cycles (When R/ W and ADV/ LD are sampled low)
the appropriate byte write signal (BW
1
- BW
4
) must be valid. The byte write
signal must also be valid on each cycle of a burs t write. Byte Write signals are
igno red whe n R/W is sampled high. The appropriate byte(s) of data are written
into the de vice two cycles late r. BW
1
- BW
4
can al l be tie d lo w if al ways d o ing
write to the entire 36-bit word.
CE
1
, CE
2
Chip Enab le s I LOW S ync hrono us ac tive l o w chip enab le . CE
1
and CE
2
are used with CE
2
to
e nab le the IDT71V546. (CE
1
or CE
2
sampled high or CE
2
sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT™
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
d ese le ct is initiate d.
CE 2 Chip Enab le I HIGH Synchro no ut active hig h c hip e nab le . CE
2
is used with CE
1
and CE
2
to e n ab l e
the chip . CE
2
has inverted polarity but otherwise identical to CE
1
and CE
2
.
CLK Clock I N/ A This is the c lo ck inp ut to the IDT71V546. Ex ce pt fo r OE, all ti ming refere nce s fo r
the device are made with respect to the rising edge of CLK.
I/O
0
- I/O
31
I/O
P1 -
I/O
P4
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
LBO Line ar Bu rs t
Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is
sele cted . When LBO is low the Linear burst sequence is selected. LBO is a
static DC inp ut.
OE Outp ut Enable I LOW Asynchrono us output e nab le. OE m us t be l o w to r e ad d ata fro m the 71V 546.
When OE is hi gh the I/ O p ins ar e in a hig h-imp ed ance state . OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can
be tied low.
V
DD
Power Supply N/A N/A 3.3V power supply input.
V
SS
Gro und N/A N/ A Gro und pin.
3821 tbl 02
6.42
3
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
InputRegister
3821 drw 01
Clock
Data I/O [0:31], I/O P[1:4]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE
1
,CE
2
,CE
2
R/W
CEN
ADV/LD
BWx
LBO 128K x 36 BIT
MEMORY ARRAY
.
4
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration — 128K X 36
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DD
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DD
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DD
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DD
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DD
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DD
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DD
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DD
I/O
1
I/O
0
PK100-1
3821 drw 02
V
DD
(1)
I/O
15
I/O
P3
V
DD
I/O
P4
A
15
A
16
I/O
P1
V
DD
I/O
P2
V
SS
.
.
NC
NC
NC
NOTES:
1. Pin 14 does not have to be connected directly to VDD as long as the input voltage is > VIH.
2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively.
100 100
100 100
100 TT
TT
TQFPQFP
QFPQFP
QFP
TT
TT
Top op
op op
op VV
VV
Vieie
ieie
ieww
ww
w
6.42
5
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
100 TQFP Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol Rating Commerci al &
Industri al Val ues Unit
V
TERM
(2)
Te rminal Vo ltag e
wi th Re s p e c t to GND -0.5 to + 4.6 V
V
TERM
(3)
Te rminal Vo ltag e
wi th Re s p e c t to GND -0.5 to V
DD
+0.5 V
T
A
(4)
Commercial
Operating Ambient
Temperature 0 to + 70 oC
Industrial
Operating Ambient
Temperature -40 to + 85 oC
T
BIAS
Te mp e rature Unde r Bias -55 to +125 oC
T
STG
Storage Temperature -55 to +125 oC
P
T
Po we r Dis si p ati o n 2. 0 W
I
OUT
DC Outp ut Cur re nt 50 mA
3821 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VDD and Input terminals only.
3. I/O terminals.
4. During production testing, the case temperature equals the ambient temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 5 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
3821 tbl 06
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Grade Ambient
Temperature
(1)
V
SS
V
DD
Commercial 0
O
C to +70
O
C0V 3.3V±5%
Industrial -40
O
C to +8 5
O
C0V 3.3V±5%
3821 tb l 03
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
3. VDD needs to be ramped up smoothly to the operating level. If there are any
glitches on VDD that cause the voltage level to drop below 2.0 volts then the
device needs to be reset by holding VDD to 0.0 volts for a minimum of 100 ms.
Symbol Parameter Min. Typ. Max. Unit
V
DD
(3)
Sup p ly Vo ltag e 3.135 3.3 3.465 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
____
4.6 V
V
IH
Input High Voltage - I/O 2.0
____
V
DD
+0.3
(2)
V
V
IL
Input Low Vo ltag e -0. 5
(1)
____
0.8 V
3821 tb l 04
NOTES:
1. During production testing, the case temperature equals the ambient temperature.
6
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
Pa rtial T ruth Table for Writes(1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if either one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
CEN R/WChip
(5)
Enable ADV/LD BWxADDRESS
USED P REVI OUIS CYCLE CURRE NT CYCLE I/O
(2 cycles later)
L L Sele ct L Valid External X LOAD WRITE D
(7)
L H Select L X External X LOAD READ Q
(7)
LX X H ValidInternal LOAD WRITE/
BURST WRITE B URST WRITE
(Ad vance Burst Counte r)
(2)
D
(7)
L X X H X Inte rnal LOAD RE A D/
BURST READ BURS T RE AD
(Ad vance Burst Counte r)
(2)
Q
(7)
L X Dese le ct L X X X DESELECT or STOP
(3)
HiZ
L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUSPEND
(4)
Previous Value
3821 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Operation R/WBW
1
BW
2
BW
3
BW
4
READ H X X X X
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O [0:7], I/O
P1
)
(2)
LLHHH
WRITE BYTE 2 (I/O [8:15], I/O
P2
)
(2)
LHLHH
WRITE BYTE 3 (I/O [16:23], I/O
P3
)
(2)
LHHLH
WRITE BYTE 4 (I/O [24:31], I/O
P4
)
(2)
LHHHL
NO WRITE L HHHH
3821 tbl 08
6.42
7
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Functional Timing Diagram(1)
NOTE:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
A37
C37
D/Q35
n+29
A29
C29
D/Q27
ADDRESS
(A0 - A16)
CONTROL
(R/W, ADV/LD,BWx)
DATA
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
(2)
(2)
(2)
3821 drw 03
n+37
A37
C37
D/Q35
,
Interleaved Burst Sequence Table (LBO=VDD)
Linear Burst Sequence Table (LBO=VSS)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 10 01 00
3821 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11 00 01 10
3821 tbl 10
8
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load,
Burst, Deselect and NOOP Cycles(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
n A 0 H L L L X X X Lo ad re ad
n+1 X X H X L X X X Burst re ad
n+2 A1 H L L L X L Q0 Load read
n+3 X X L H L X L Q0+1 Desele ct or STOP
n+4 X X H XLXLQ1NOOP
n+ 5 A2 H L L L X X Z Lo ad re ad
n+ 6 X X H X L X X Z B urs t re ad
n+7 X X L H L X L Q2 De sele ct or STOP
n+8 A3 L L LLLLQ
2+1 Load wri te
n+ 9 X X H X L L X Z B urst write
n+10 A4 L L L L L X D3 Load write
n+11 X X L H L X X D3+1 Desele ct or STOP
n+12 X X H X L X X D4 NOOP
n+ 13 A5 L L L L L X Z Lo a d write
n+14 A6 H L L L X X Z Load read
n+15 A7 L L L L L X D5 Load write
n+16 X X H XLLLQ6Burst write
n+ 17 A8 H L L L X X D7 Lo ad re ad
n+18 X X H X L X X D7+1 B urst re ad
n+19 A9 L L LLLLQ8Load write
3821 tbl 11
6.42
9
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Read Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Read Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X X X L X X X Cloc k Setup Valid
n+2 X X X X X X L Q0 Co ntents of Address A0 Read Out
3821 tbl 12
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X H X L X X X Clock Setup Valid, Advance Counter
n+2 X X H X L X L Q0 Addre ss A0 Read Out, Inc. Count
n+3 X X H XLXLQ
0+1
Address A
0+1
Read O ut, Inc . Co unt
n+4 X X H XLXLQ
0+2
Address A
0+2
Read O ut, Inc . Co unt
n+5 A1 H L L L X L Q
0+3
Address A
0+3
Re ad Out, Load A1
n+6 X X H X L X L Q0 Addre ss A0 Read Out, Inc. Count
n+7 X X H X L X L Q1 Addre ss A1 Read Out, Inc. Count
n+8A2HLLLXLQ
1+1
Address A
1+1
Re ad Out, Load A2
3821 tbl 13
10
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTE:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+ 1 X X X X L X X X Cl oc k S e tup Valid
n+2 X X X X L X X D0 Write to Address A0
3821 tbl 14
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X H X L L X X Clock Setup Valid, Inc. Count
n+2 X X H X L L X D0 Address A0 Write, Inc. Count
n+3 X X H X L L X D
0+1
Address A
0+1
Wr ite , Inc . Co unt
n+4 X X H X L L X D
0+2
Address A
0+2
Wr ite , Inc . Co unt
n+5 A1 L L LLLXD
0+3
Address A
0+3
Wr ite , Loa d A 1
n+6 X X H X L L X D0 Address A0 Write, Inc. Count
n+7 X X H X L L X D1 Address A1 Write, Inc. Count
n+8 A2 L L LLLXD
1+1
Address A
1+1
Wr ite , Loa d A 2
3821 tbl 15
6.42
11
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation With Clock Enable Used(1)
NOTE:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
Cycle Address R/WADV/LD CE
(2) CEN BWxOE I/O Comments
n A0 H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Cloc k n+1 Ig nored
n+2 A1 H L L L X X X Clock Valid
n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus
n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus
n+5 A2 H L L L X L Q0 A d d re ss A0 Re ad o ut (b ut trans.)
n+6 A3 H L L L X L Q1 Add re ss A1 Re ad out (b us trans. )
n+7 A4 H L L L X L Q2 Ad d ress A2 Read out (b us trans.)
3821 tbl 16
Cycle Address R/WADV/LD CE(2) CEN BWxOE I/O Comments
n A0 L L L L L X X Address and Control meet setup
n+1 X X X X H X X X Clo ck n+1 Ig nore d
n+2 A1 L L LLLXXClock Valid
n+3 X X X X HXXXClock Ignored
n+4 X X X XHXXXClock Ignored
n+5 A2 L L LLLXD0Write data D0
n+6 A3 L L LLLXD1Write data D1
n+7 A4 L L LLLXD2Write data D2
3821 tbl 17
12
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation With Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation With Chip Enable Used(1)
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X ? Deselected
n+2 A0 H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP
n+4 A1 H L L L X L Q0 Address A0 read out. Load A1
n+5 X X L H L X X Z Deselected or STOP
n+6 X X L H L X L Q1 Address A1 Read out. Deselected
n+7 A2 H L L L X X Z Address and Control meet setup
n+8 X X L H L X X Z Deselected or STOP
n+9 X X L H L X L Q2 Address A2 read out. Deselected
3821 tbl 18
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X ? Deselected
n+2 A0 L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP
n+4 A1 L L L L L X D0 Address D0 Write In. Load A1
n+5 X X L H L X X Z Deselected or STOP
n+6 X X L H L X X D1 Address D1 Write In. Deselected
n+7 A2 L L L L L X Z Address and Control meet setup
n+8 X X L H L X X Z Deselected or STOP
n+9 X X L H L X X D2 Address D2 Write In. Deselected
3 8 21 t bl 19
6.42
13
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Sym bol P aram eter Test Co nditions
S133 S117 S100
UnitCom'lIndCom'lIndCom'lInd
IDD Operating Power
Supply Current Device Selec ted, Outp uts Open,
ADV/LD = X, VDD = Max., VIN > VIH or < VIL, f = fMAX
(2)
300 310 275 285 250 260 mA
ISB1 CM O S Standby Powe r
Supply Current Device Deselected, Outputs Open, VDD = Max., VIN >
VHD or < VLD, f = 0
(2)
40 45 40 45 40 45 mA
ISB2 Clo ck Running Po wer
Supply Current Device Deselected, Outputs Open, VDD = Max ., VIN >
VHD or < VLD, f = fMAX
(2)
110 120 105 115 100 110 mA
ISB3 Idle Po we r
Supply Current Device Selec ted, Outp uts Open, CEN > VIH VDD = Max.,
VIN > VHD or < VLD, f = fMAX
(2)
40 45 40 45 40 45 mA
3821 tbl 21
DC Electrical Characteristics Over the Opearting Temperature
and Supply V oltage Range(1)
(VDD = 3.3V +/-5%, V HD = VDD–0.2V, VLD = 0.2V)
DC Electrical Characteristics Over the Operating Temperature
and Supply V oltage Range
(VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads AC Test Conditions
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
3821 drw 05
,
1.5V
50Ω
I/O Z
0
=50Ω
3821 drw 04
+
,
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leak ag e Current V
DD
= Max., V
IN
=
0V to V
DD
___
5µA
|I
LI
|LBO Input Leak age Current
(1)
V
DD
= Max., V
IN
=
0V to V
DD
___
30 µA
|I
LO
|
Outp ut Le ak age Current CE > V
IH
or OE > V
IH
, V
OUT
= 0V toV
DD
, V
DD
= Max.
___
5µA
V
OL
Outp ut Lo w Voltag e I
OL
= 5mA, V
DD
= Min.
___
0.4 V
V
OH
Output Hig h Voltage I
OH
= -5mA, V
DD
= Min. 2.4
___
V
3821 tbl 20
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
Inp ut Pul s e Le v e ls
Inp ut Ris e /Fal l Tim e s
Inp ut Ti ming Re fe re nc e Le v e ls
Output Timing Refe renc e Leve ls
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figures 1
3821 t b l 22
14
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 2.0V and LOW below 0.8V.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
Symbol Parameter
71V546S133 71V546S117 71V546S100
Unit
Min. Max. Min. Max. Min. Max.
Cl o ck P a ram et ers
t
CYC
Clock Cycle Time 7.5
____
8.5
____
10
____
ns
t
F
(1)
Clock Fre quency
____
133
____
117
____
100 MHz
t
CH
(2)
Clock High Pulse Width 2.5
____
3
____
3.5
____
ns
t
CL
(2)
Cloc k Lo w P uls e Wi d th 2. 5
____
3
____
3.6
____
ns
Output Parameters
t
CD
Clo ck High to Valid Data
____
4.2
____
4.5
____
5ns
t
CDC
Clo ck High to Data Chang e 1. 5
____
1.5
____
1.5
____
ns
t
CLZ
(3,4,5)
Clo ck High to Outp ut A ctiv e 1. 5
____
1.5
____
1.5
____
ns
t
CHZ
(3,4,5)
Clo ck High to Data Hig h-Z 1. 5 3.5 1.5 3.5 1.5 3.5 ns
t
OE
Outp ut E nab le A cc e ss Time
____
4.2
____
4.5
____
5ns
t
OLZ
(3,4)
Outp u t Enabl e L o w to Data A c ti v e 0
____
0
____
0
____
ns
t
OHZ
(3.4)
Outp ut Enable Hi g h to Data High- Z
____
3.5
____
3.5
____
3.5 ns
Setup Tim es
t
SE
Clock Enable Setup Time 2.0
____
2.0
____
2.2
____
ns
t
SA
Add res s Setup Time 2.0
____
2.0
____
2.2
____
ns
t
SD
Data i n S e tup Ti m e 1. 7
____
1.7
____
2.0
____
ns
t
SW
Re ad / Write (R/W ) S etup Ti me 2. 0
____
2.0
____
2.2
____
ns
t
SADV
A d v anc e / Load ( ADV / LD) S e tup Tim e 2 .0
____
2.0
____
2.2
____
ns
t
SC
Chip Enable/Select Setup Time 2.0
____
2.0
____
2.2
____
ns
t
SB
Byte Write E nable (BWx) Se tup Time 2.0
____
2.0
____
2.2
____
ns
Ho ld Ti m es
t
HE
Cloc k E nab l e Ho l d Time 0. 5
____
0.5
____
0.5
____
ns
t
HA
Add res s Ho ld Time 0.5
____
0.5
____
0.5
____
ns
t
HD
Data i n Hol d Time 0.5
____
0.5
____
0.5
____
ns
t
HW
Read/Write (R/W) Ho ld Time 0.5
____
0.5
____
0.5
____
ns
t
HADV
A d v anc e / Load ( ADV / LD) Ho l d Ti me 0 .5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write E nable (BWx) Ho ld Time 0.5
____
0.5
____
0.5
____
ns
3821 tb l 23
6.42
15
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Wav eform of Read Cycle(1,2,3,4)
NOTES:
1 . Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the
burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
(CENhigh,eliminates
currentL-H clockedge)
tCD
tHADV
Pipeline
Read
(BurstWrapsaround
to initialstate)
tCDC
tCLZtCHZ
tCD
tCDC
R/W
CLK
CEN
ADV/LD
ADDRESS
OE
DATAOut
tHE
tSE
A1A2
O1(A1)O1(A2)O1(A2)
tCHtCL
tCYC
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
BurstPipelineRead
Pipeline
Read
CE
1,
CE
2(2)
Q(A
2+1
)Q(A
2+2
)Q(A
2+2
)Q(A
2+3
)
3821drw06
BW
1,
BW
4
16
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Wav eform of Write Cyc les(1,2,3,4,5)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
OE
DATAIn
tHD
tSD
tCHtCL
tCYC
tHADV
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
BurstPipelineWrite
Pipeline
Write
Pipeline
Write
tHB
tSB
(BurstWrapsaround
to initialstate)
tHD
tSD
(CENhigh,eliminates
currentL-Hclockedge)
CE
1,
CE
2
(2)
D(A
2+1
)D(A
2+2
)D(A
2+3
)
D(A1)D(A2)D(A2)
3821drw07
BW
1,
BW
4
.
6.42
17
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
DATAOutQ(A3)
Q(A1)Q(A6)Q(A7)
tCD
Read
Write
tCLZ
tCHZ
tCHtCL
tCYC
tHW
tSW
tHA
tSA
A4
A3
tHC
tSC
D(A2)D(A4)
tSDtHD
tCDC
D(A5)
tHADV
tSADV
A6A7A8
A5A9
Read
Write
Read
DATAIn
tHB
tSB
3821drw08
CE
1
,CE
2
(2)
BW
1
-BW
4
OE
.
18
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH..
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition
did not occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
BW
1
-BW
4
OE
DATAOutQ(A3)
tCD
tCLZ
tCHZ
tCHtCL
tCYC
tHC
tSC
D(A2)
tSDtHD
tCDC
A4A5
tHADV
tSADV
tHW
tSW
tHA
tSA
A3
tHB
tSB
DATAIn
3821drw09
CE2
(2)
Q(A1)
B(A2)
CE1,
Q(A1)
.
6.42
19
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3 . When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states two cycles after the initiation
of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
Timing Waveform of CS Operation(1,2,3,4)
R/W
A1
CLK
ADV/LD
ADDRESS
OE
DATAOutQ(A1)
tCD
tCLZ
tCHZ
tCDC
tCHtCL
tCYC
tHC
tSC
tSDtHD
A5
A3
tSB
DATAIn
tHE
tSE
A2
tHA
tSA
A4
tHW
tSW
tHB
CEN
tHADV
tSADV
3821drw10
Q(A2)Q(A3)
D(A3)
BW
1
-BW
4
CE
1
,CE
2
(2)
20
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA Out
tOHZ tOLZ
tOE
Valid
3821 drw 1
1
100 pin Plastic Thin Quad Flatpack (PK100-1)
S
Power
XX
Speed
PF
Package
PF
71V546
133
117
100
Clock Frequency in Megahertz
3821 drw 12
Device
Type
PART NUMBER SPEED IN MEGAHERTZt
CD
PARAMETER CLOCK CYCLE TIME
71V546S133PF
71V546S117PF
71V546S100PF
133 MHz
117 MHz
100 MHz
4.2 ns
4.5 ns
5ns
7.5 ns
8.5 ns
10 ns
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
X
Process/
Temperature
Range
Blank
I
X
Restricted hazardous substance device
G
X
XCurrent generation die step optional
First or current generation die step
Blank
100 Thin Quad Flatpack Packaging
6.42
21
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
6/15/99 Updated to new format
9/13/99 Pg. 12 Corrected ISB3 conditions
Pg. 20 Added Datasheet Document History
12/31/99 Pg. 3, 12, 13, 19 Added Industrial Temperature range offerings
11/22/05 Pg. 3,4 Moved Operating temperature & DC operating tables from page 3 to new page 5. Moved Absolute
rating & Capacitance tables from page 4 to new page 5. Add clarification note to Recommended
Operating Temperature and Absolute Max Ratings tables.
Pg. 20 Updated order information with "Restricted hazardous substance device"
02/23/07 Pg. 20 Added X generation die step to data sheet ordering information.
10/18/08 Pg. 20 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
