fax id: 4504 Using Decoupling Capacitors Introduction This application note describes some revised recommendations regarding the use of decoupling capacitors. The "conventional" recommendation of using two different values and two different types can, in many circumstances, cause less than ideal operation. Simpler, more reliable designs will often result from following the design guidelines of this note. The Problem Faster edges, more sensitive devices, higher clock rates all demand "good" decoupling of the power supplies. Decoupling: The art and practice of breaking coupling between portions of systems and circuits to ensure proper operation. Bypassing: The practice of adding a low-impedance path to shunt transient energy to ground at the source. Required for proper decoupling. What used to work for lower system speeds and slower logic may not work well when the system speed increases. The common practice of using two different values for decoupling can: * Increase the RFI/EMI problems * Reduce the reliability of operation * Reduce the noise tolerance 10.00 XL 5 nH Each physical component shown on the schematic brings with it additional electrical components determined by the design and mounting of that component into the system. Look in Figure 1 at the behavior of two ideal components, a capacitor and an inductor representing parts of the capacitor shown in Figure 2. Note that without any lead inductance or resistance, the resulting capacitive reactance approaches 0 with increasing frequency. Note also that the inductive reactance of the ideal inductor, without any stray capacitance, approaches infinity. A real capacitor includes an inductor and resistor in the form of leads, traces, and even ground planes in series with it (Figure 2). Multi-layer capacitors have approximately 5 nH of parasitic inductance when mounted on a printed circuit board. While the component drawn on the schematic (Figure 2) shows a 22-nF capacitor, the system sees the 22-nF capacitor in series with a 5-nH inductor and a 30-m resistor. The impedance curve of "Real" capacitors resembles the traces marked 22 nF and 100 pF of Figure 3. The shape of these calculated curves match the curves given in capacitor manufacturers' data sheets. This means that in a circuit, a capacitor acts as a low-impedance element only over a limited range of frequencies. A solution, proposed in many works, added a second capacitor to bypass frequencies outside the limited range of the single capacitor. This approach expected that the resulting impedance curve would look like the solid line marked "Expected" in Figure 3. This solution, however, has a significant problem at "intermediate" frequencies. These intermediate frequency problems come from the circuit shown in Figure 4. The circuit on the left represents the schematic form of a typical decoupling arrangement, a 22-nF and a 100-pF capacitor in parallel. Conventional wisdom suggests that the 100-pF should decouple the high frequencies, and the 22-nF should decouple 1.00 Schematic System 0.10 22 nF XC 22 nF 22 nF 5 nH 0.01 1.00 10.00 100.00 30 m 1000.00 Frequency (MHz) Figure 1. Z vs. f for Parts of a Real Capacitor Cypress Semiconductor Corporation * 3901 North First Street Figure 2. The "Real" Schematic * San Jose * CA 95134 * 408-943-2600 July 1994 - Revised May 11, 1995 Using Decoupling Capacitors Figure 3. Expected Impedance of "Real" Capacitors the low frequencies. However, the combination results in some unexpected interactions. The circuit on the right in Figure 4 shows a clearer representation of the system, including the parasitic inductances and resistances. This picture shows all the components necessary to create a resonant tank circuit. ance than that of a single 22-nF capacitor alone. Over this range of frequencies, the parallel combination will bypass less of the energy to ground. The height of the peak shown in Figure 5 varies inversely with the ESR of the capacitors. As board designs and components improve, the height of the resulting peak will actually increase due to a reduction of the system ESR. The exact shape and location of the parallel resonant peak will vary for each system depending on the design of the printed circuit board (PCB) and choice of capacitors. Figure 5 shows a combined plot of Z vs. frequency of this circuit. The values given for effective series resistance (ESR; 30 m) and effective series inductance (ESL; 5 nH) are achievable on real PCBs using "good" layouts and surface-mounted capacitors. Recommendations The graph of Figure 5 shows a range of frequencies where this combination of two capacitors results in a higher impedance than that of the larger capacitor alone. For the combination shown, this range includes approximately 15 MHz through 175 MHz. Notice the large peak in reactance at 150 MHz due to resonance of the two capacitors. Any energy from the rest of the system (ICs, clocks, and harmonics), over this intermediate range of frequencies, will see a higher imped- The following recommendations can improve the resulting designs: * Use only one value of capacitor. * Choose the capacitor based on the self-resonant characteristics from the manufacturers' data sheet to match the clock rate or expected noise frequency of the design. \ Schematic 22 nF 100 pF * Add as many capacitors as needed for your range of frequencies. As an example, the capacitor shown (22 nF) has a self resonant frequency of approximately 11 MHz, and a useful (less than 1) impedance range of 6 to 40 MHz. Use as many of these as needed to achieve the desired level of decoupling. System 22 nF 5 nH 30 m 100 pF * A minimum of one capacitor per power pin placed as physically close to the to the power pins of the IC as possible to reduce the parasitic impedances. 5 nH * Keep lead lengths on the capacitors below 1/4 between the capacitor endcaps and the ground or power pins. 30 m * Place the bypass capacitors on the same side of the PCB as the ICs. Figure 6 shows an example of a recommended layout for a HOTLink Transmitter and Receiver. Figure 4. The "Real" Schematic 2 Using Decoupling Capacitors 100.00 22 nF || 100 pF 100 pF 22 nF 10.00 1.00 0.10 0.01 1.00 10.00 1000.00 100.00 Frequency (MHz) Figure 5. Real Z vs. f for Parallel 22-nF and 100-pF Capacitors CY7B923 HOTLink Transmitter CY7B933 HOTLink Receiver Capacitor and Pads Ground VCC Via Signals VCC GND Via Figure 6. Sample Layouts A special note about Figure 6: in both of the layouts, only one connection is made to the VCC plane. This is done so that the noise, generated both inside the IC and external to this portion of the circuit, must go through the single via to the power plane. The additional reactance of the via helps to keep the noise from spreading throughout the rest of the system. HOTLink parts tolerate a fairly large amount of VCC noise. However, to achieve the absolute "best" performance, use these recommendations. 3 Using Decoupling Capacitors 100.00 10 nF 10.00 22 nF 22 nF || 10 nF 1.00 0.10 0.01 1.00 10.00 100.00 1000.00 Frequency (MHz) Figure 7. Real Z vs. f for Parallel 22-nF and 10-nF Capacitors When the design calls for multiple clock frequencies, split the power plane as shown in Figure 6 and use the correct value of capacitor for each section, maintaining only one value per section. An example of this technique may be found in "HOTLink Design Considerations, Power Distribution Requirements for Optical Drivers." The isolation provided by the slotted power plane keeps the noise of one section away from the sensitive parts of the other sections, and allows the separation of the capacitor values. wider low-impedance zone and allows a broad range of bypass frequencies. In Figure 7 notice that the peak in the reactance still occurs, but that the maximum impedance stays well below 1.5 and that the usable range (less than 1.5) now extends from approximately 3.25 MHz to 100 MHz. Use this multiple decoupling capacitor method only when a wide range of frequencies must be bypassed around a single integrated circuit and adequate range cannot be achieved by a single capacitor. Again, the capacitors must remain within a 2:1 range to prevent the reactance peak from exceeding useful limits. What About Variable Clock Frequencies? Conclusions Bypassing ICs when the clock rate changes over a wide range of frequencies presents the most difficult situation covered here. Fortunately, most data communications applications use only a single clock rate. Application of these techniques resulted in improving the measured optical margin of a HOTLink-based OLC (optical link card) by about 1 dB. It simplifies the Bill of Material because only one value is used instead of two. Finally, using only one value of capacitor gave the best jitter measurements of the HOTLink Transmitter. What About Multiple Clocks? When the range of operation of a single part covers a large range of frequencies, placing two capacitors that are within approximately 2:1 of each other in capacitance results in a HOTLink is a trademark of Cypress Semiconductor. (c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. 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