LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Check for Samples: LMK04000,LMK04001,LMK04002,LMK04010,LMK04011,LMK04031,LMK04033
1FEATURES
23 Cascaded PLLatinum™ PLL Architecture Support Clock Rates up to 1080 MHz
PLL1 Default Clock Output (CLKout2) at power up
Phase Detector Rate of up to 40 MHz Five Dedicated Channel Divider and Delay
Blocks
Integrated Low-Noise Crystal Oscillator
Circuit Pin Compatible Family of Clocking Devices
Dual Redundant Input Reference Clock Industrial Temperature Range: -40 to 85 °C
with LOS 3.15 V to 3.45 V Operation
PLL2 Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
Normalized [1 Hz] PLL Noise Floor of -
224 dBc/Hz APPLICATIONS
Phase Detector Rate up to 100 MHz Data Converter Clocking
Input Frequency-Doubler Wireless Infrastructure
Integrated Low-Noise VCO Networking, SONET/SDH, DSLAM
Ultra-Low RMS Jitter Performance Medical
150 fs RMS Jitter (12 kHz 20 MHz) Military / Aerospace
200 fs RMS Jitter (100 Hz 20 MHz) Test and Measurement
LVPECL/2VPECL, LVDS, and LVCMOS outputs Video
DESCRIPTION
The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and
distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a
cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family
provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal
oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-
noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured
to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and
a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise
(offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as
the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be
optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the
VCXO module or crystal used in PLL1.
The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon
power up. The input block is equipped with loss of signal detection and automatic or manual selection of the
reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a
programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on
CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or
microcontroller that programs the jitter cleaner during the system power up sequence.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PLLatinum is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMK040xx
Precision Clock
Conditioner
Recovered
³GLUW\´FORFNRU
clean clock
0XOWLSOH³FOHDQ´FORFNVDW
different frequencies
Fout
CLKout4
CLKout2A
CLKout1
CLKout0
DAC
Serializer/
Deserializer
LMX2531
PLL+VCO
ADC
> 1 Gsps
FPGA
CLKin0
Crystal or
VCXO
Backup
Reference
Clock
CLKin1
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
www.ti.com
Table 1. Device Configuration Information
2VPECL / LVPECL
NSID PROCESS LVDS OUTPUTS LVCMOS OUTPUTS VCO
OUTPUTS
LMK04000BISQ BiCMOS 3 4 1185 to 1296 MHz
LMK04001BISQ BiCMOS 3 4 1430 to 1570 MHz
LMK04002BISQ BiCMOS 3 4 1600 to 1750 MHz
LMK04010BISQ BiCMOS 5 1185 to 1296 MHz
LMK04011BISQ BiCMOS 5 1430 to 1570 MHz
LMK04031BISQ BiCMOS 2 2 2 1430 to 1570 MHz
LMK04033BISQ BiCMOS 2 2 2 1840 to 2160 MHz
NSID CLKout0 CLKout1 CLKout2 CLKout3 CLKout4
LMK04000BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04001BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04002BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04010BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL
LMK04011BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL
LMK04031BISQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS
LMK04033BISQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS
2Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
OSCin
OSCin*
R1 Divider Phase
Detector
PLL1
N1 Divider
VCO
Divider
CLKout4
CLKout4*
CLKout3B
CLKout3A
CLKout2B
CLKout2A
CLKout1
CLKout1*
CPout1
Internal VCO
Partially
Integrated
Loop Filter
Delay Mux
Delay Mux
Divider Delay Mux
Divider Delay Mux
Distribution
Path
CLK
DATA
LE
Control
Registers
PWire
Port
Device
Control LD
GOE
SYNC*
Fout
Clock Buffers
Mux
Divider
Divider
CLKin0
CLKin0*
CLKin1
CLKin1*
R2 Divider Phase
Detector
PLL2
N2 Divider
CPout2
2X
CLKout0
CLKout0*
Delay MuxDivider
LOS
LOS
LOS0
LOS1
Mux
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
Functional Block Diagram
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
4748 46 45 44 43 42 41 40 39 38 37
11
12
10
9
8
7
6
5
4
3
2
1
1413 15 16 17 18 19 20 21 22 23 24
26
25
27
28
29
30
31
32
33
34
35
36GND
Fout
Vcc1
Vcc2
Vcc3
DLD_BYP
Vcc5
Vcc6
CLKin1*
Vcc8
Vcc9
Vcc10
Vcc11
Vcc12
Vcc13
Vcc14
CLKuWire
DATAuWire
LEuWire
NC
LDObyp1
LDObyp2
GOE
LD
CLKout0
CLKout0*
GND
Vcc4
CLKin0
CLKin0*
CPout1
Vcc7
CLKin1
SYNC*
OSCin
OSCin*
CPout2
CLKin0_LOS
CLKin1_LOS
Bias
CLKout1
CLKout1*
CLKout2
CLKout2*
CLKout3
CLKout3*
CLKout4
CLKout4*
DAP
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
www.ti.com
Connection Diagram
Figure 1. 48-Pin WQFN Package
Top View
PIN DESCRIPTIONS
Pin Number Name(s) I/O Type Description
1 GND GND Ground (For Fout Buffer)
2 Fout O ANLG VCO Frequency Output Port
3 VCC1 PWR Power Supply for VCO Output Buffer
4 CLKuWire I CMOS Microwire Clock Input
5 DATAuWire I CMOS Microwire Data Input
6 LEuWire I CMOS Microwire Latch Enable Input
7 NC No Connection
8 VCC2 PWR Power Supply for VCO
9 LDObyp1 ANLG LDO Bypass, bypassed to ground with a 10 µF capacitor
10 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 µF
capacitor
11 GOE I CMOS Global Output Enable
12 LD O CMOS Lock Detect and PLL multiplexer Output
13 VCC3 PWR Power Supply for CLKout0
14 CLKout0 O LVDS/LVPECL Clock Channel 0 Output
15 CLKout0* O LVDS/LVPECL Clock Channel 0* Output
16 DLD_BYP ANLG DLD Bypass, bypassed to ground with a 0.47 µF
capacitor
17 GND GND Ground (Digital)
18 VCC4 PWR Power Supply for Digital
4Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
PIN DESCRIPTIONS (continued)
Pin Number Name(s) I/O Type Description
19 VCC5 PWR Power Supply for CLKin buffers and PLL1 R-divider
20 CLKin0 I ANLG Reference Clock Input Port for PLL1 - AC or DC
Coupled (1)
21 CLKin0* I ANLG Reference Clock Input Port for PLL1 (complimentary) -
AC or DC Coupled (1)
22 VCC6 PWR Power Supply for PLL1 Phase Detector and Charge
Pump
23 CPout1 O ANLG Charge Pump1 Output
24 VCC7 PWR Power Supply for PLL1 N-Divider
25 CLKin1 I ANLG Reference Clock Input Port for PLL1 - AC or DC
Coupled (1)
26 CLKin1* I ANLG Reference Clock Input Port for PLL1 (complimentary) -
AC or DC Coupled (1)
27 SYNC* I CMOS Global Clock Output Synchronization
28 OSCin I ANLG Reference oscillator Input for PLL2 - AC Coupled
29 OSCin* I ANLG Reference oscillator Input for PLL2 - AC Coupled
30 VCC8 PWR Power Supply for OSCin Buffer and PLL2 R-Divider
31 VCC9 PWR Power Supply for PLL2 Phase Detector and Charge
Pump
32 CPout2 O ANLG Charge Pump2 Output
33 VCC10 PWR Power Supply for VCO Divider and PLL2 N-Divider
34 CLKin0_LOS O LVCMOS Status of CLKin0 reference clock input
35 CLKin1_LOS O LVCMOS Status of CLKin1 reference clock input
36 Bias I ANLG Bias Bypass. AC coupled with 1 µF capacitor to Vcc1
37 VCC11 PWR Power Supply for CLKout1
38 CLKout1 O LVPECL/LVCMOS Clock Channel 1 Output
39 CLKout1* O LVPECL/LVCMOS Clock Channel 1* Output
40 VCC12 PWR Power Supply for CLKout2
41 CLKout2 O LVPECL/LVCMOS Clock Channel 2 Output
42 CLKout2* O LVPECL/LVCMOS Clock Channel 2* Output
43 VCC13 PWR Power Supply for CLKout3
44 CLKout3 O LVPECL Clock Channel 3 Output
45 CLKout3* O LVPECL Clock Channel 3* Output
46 VCC14 PWR Power Supply for CLKout4
47 CLKout4 O LVDS/LVPECL Clock Channel 4 Output
48 CLKout4* O LVDS/LVPECL Clock Channel 4* Output
DAP DAP DIE ATTACH PAD, connect to GND
(1) The reference clock inputs may be either AC or DC coupled.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
www.ti.com
Absolute Maximum Ratings(1)(2)(3)(4)
Parameter Symbol Ratings Units
Supply Voltage (5) VCC -0.3 to 3.6 V
Input Voltage VIN -0.3 to (VCC + 0.3) V
Storage Temperature Range TSTG -65 to 150 °C
Lead Temperature (solder 4 sec) TL+260 °C
Differential Input Current (CLKinX/X*, IIN ± 5 mA
OSCin/OSCin*)
(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test
conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) This device is a high performance RF integrated circuit with an ESD rating up to 8 KV Human Body Model, up to 300 V Machine Model
and up to 1,250 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free
workstations.
(4) Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress
ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation
sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
(5) Never to exceed 3.6 V.
Package Thermal Resistance
Package θJA θJ-PAD (Thermal Pad)
48-Lead WQFN (1) 27.4° C/W 5.8° C/W
(1) Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These
vias play a key role in improving the thermal performance of the WQFN. It is recommended that the maximum number of vias be used in
the board layout.
Recommended Operating Conditions
Parameter Symbol Condition Min Typical Max Unit
Ambient TAVCC = 3.3 V -40 25 85 °C
Temperature
Supply Voltage VCC 3.15 3.3 3.45 V
Electrical Characteristics
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
Current Consumption
ICC_PD Power Down Supply Current 1 mA
LMK04000, LMK04001,
LMK04002 380 435
(2)
Supply Current with all clocks
ICC_CLKS enabled, all delay bypassed, LMK04010, LMK04011 mA
378 435
Fout disabled. (1) (2)
LMK04031, LMK04033 335 385
(2)
CLKin0/0* and CLKin1/1* Input Clock Specifications
Manual Select mode 0.001 400
Clock Input Frequency
fCLKin MHz
(3) Auto-Switching mode 1 400
(1) Load conditions for output clocks: LVPECL: 50 Ωto VCC-2 V. 2VPECL: 50 Ωto VCC-2.36 V. LVDS: 100 Ωdifferential. LVCMOS: 10 pF.
(2) Additional test conditions for ICC limits: All clock delays disabled, CLKoutX_DIV = 510, PLL1 and PLL2 locked. (See Table 33 for more
information)
(3) CLKin0 and CLKin1 maximum of 400 MHz is guaranteed by characterization, production tested at 200 MHz.
6Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
Slew Rate on CLKin
SLEWCLKin 20% to 80% 0.15 0.5 V/ns
(4)
AC coupled to CLKinX;
Input Voltage Swing, CLKinX* AC coupled to Ground 0.25 2.0 Vpp
single-ended input (CLKinX_TYPE=0)
VCLKin (Bipolar input buffer
mode) CLKinX and CLKinX* are both
Input Voltage Swing, driven, AC coupled. 0.5 3.1 Vpp
differential input (CLKinX_TYPE=0)
DC offset voltage between
VCLKin-offset (Bipolar input Each pin AC coupled
CLKinX/CLKinX* 44 mV
buffer mode) (CLKinX_TYPE=0)
|CLKinX-CLKinX*| AC coupled to CLKinX;
Input Voltage Swing, single- CLKinX* AC coupled to Ground 0.25 2.0 Vpp
ended input (CLKinX_TYPE=1)
VCLKin (MOS input buffer
mode) CLKinX and CLKinX* are both
Input Voltage Swing, driven, AC coupled. 0.5 3.1 Vpp
differential input (CLKinX_TYPE=1)
DC coupled to CLKinX;
VCLKin-VIH (MOS input buffer Maximum input voltage CLKinX* AC coupled to Ground 2.0 VCC V
mode) (CLKinX_TYPE=1)
DC coupled to CLKinX;
VCLKin-VIL (MOS input buffer CLKinX* AC coupled to Ground 0.0 0.4 V
mode) (CLKinX_TYPE=1)
DC offset voltage between
VCLKin-offset (MOS input Each pin AC coupled
CLKinX/CLKinX* 294 mV
buffer mode) (CLKinX_TYPE=1)
|CLKinX-CLKinX*|
PLL1 Specifications
PLL1 Phase Detector
fPD 40 MHz
Frequency VCPout1 = VCC/2, 25
PLL1_CP_GAIN = 100b
VCPout1 = VCC/2, 50
PLL1_CP_GAIN = 101b
VCPout1 = VCC/2, 100
PLL1_CP_GAIN = 110b
VCPout1 = VCC/2,
PLL1 Charge Pump Source 400
ICPout1 SOURCE µA
PLL1_CP_GAIN = 111b
Current (5)
PLL1_CP_GAIN = 000b NA
PLL1_CP_GAIN = 001b NA
VCPout1=VCC/2, PLL1_CP_GAIN 20
= 010b
VCPout1=VCC/2, PLL1_CP_GAIN 80
= 011b
(4) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input
slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended
clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to
their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to
achieve optimal phase noise performance at the device outputs.
(5) This parameter is programmable
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
www.ti.com
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
VCPout1=VCC/2, PLL1_CP_GAIN -25
= 100b
VCPout1=VCC/2, PLL1_CP_GAIN -50
= 101b
VCPout1=VCC/2, PLL1_CP_GAIN -100
= 110b
VCPout1=VCC/2, PLL1_CP_GAIN
PLL1 Charge Pump Sink -400
ICPout1 SINK µA
= 111b
Current (5)
PLL1_CP_GAIN = 000b NA
PLL1_CP_GAIN = 001b NA
VCPout1=VCC/2, PLL1_CP_GAIN -20
= 010b
VCPout1=VCC/2, PLL1_CP_GAIN -80
= 011b
Charge Pump Sink / Source
ICPout1 %MIS VCPout1 = VCC/2, T = 25 °C 3 10 %
Mismatch
Magnitude of Charge Pump 0.5 V < VCPout1 < VCC - 0.5 V
ICPout1VTUNE Current vs. Charge Pump 4 %
TA= 25 °C
Voltage Variation
Charge Pump Current vs.
ICPout1 %TEMP 4 %
Temperature Variation
Charge Pump TRI-STATE
PLL1 ICPout1 TRI 0.5 V < VCPout < VCC - 0.5 V 5 nA
Leakage Current
PLL2 Reference Input (OSCin) Specifications
EN_PLL2_REF 2X = 0 250
PLL2 Reference Input (7)
fOSCin MHz
(6) EN_PLL2_REF 2X = 1 50
PLL2 Reference Clock
SLEWOSCin 20% to 80% 0.15 0.5 V/ns
minimum slew rate on OSCin AC coupled; Single-ended
Input Voltage for OSCin or
VOSCin (Single-ended) (Unused pin AC coupled to 0.2 2.0 Vpp
OSCin* GND)
VOSCin (Differential) Differential voltage swing AC coupled 0.4 3.1 Vpp
Crystal Oscillator Mode Specifications
fXTAL Crystal Frequency Range 6 20 MHz
Crystal Effective Series
ESR 6 MHz < FXTAL < 20 MHz 100 Ohms
Resistance Vectron VXB1 crystal, 12.288
PXTAL Crystal Power Dissipation (8) 200 µW
MHz, RESR < 40 Ω
Input Capacitance of
CIN -40 to +85 °C 6 pF
LMK040xx OSCin port
PLL2 Phase Detector and Charge Pump Specifications
fPD Phase Detector Frequency 100 MHz
(6) FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.
(7) The EN_PLL2_REF2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
(8) See Application Section discussion of Crystal Power Dissipation.
8Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
VCPout2=VCC/2, PLL2_CP_GAIN 100
= 00b
VCPout2=VCC/2, PLL2_CP_GAIN 400
= 01b
PLL2 Charge Pump Source
ICPoutSOURCE µA
Current (9) VCPout2=VCC/2, PLL2_CP_GAIN 1600
= 10b
VCPout2=VCC/2, PLL2_CP_GAIN 3200
= 11b
VCPout2=VCC/2, PLL2_CP_GAIN -100
= 00b
VCPout2=VCC/2, PLL2_CP_GAIN -400
= 01b
PLL2 Charge Pump Sink
ICPoutSINK µA
Current (9) VCPout2=VCC/2, PLL2_CP_GAIN -1600
= 10b
VCPout2=VCC/2, PLL2_CP_GAIN -3200
= 11b
Charge Pump Sink/Source
ICPout2%MIS VCPout2=VCC/2, TA= 25 °C 3 10 %
Mismatch
Magnitude of Charge Pump 0.5 V < VCPout2 < VCC - 0.5 V
ICPout2VTUNE Current vs. Charge Pump 4 %
TA= 25 °C
Voltage Variation
Charge Pump Current vs.
ICPout2%TEMP 4 %
Temperature Variation
ICPout2TRI Charge Pump Leakage 0.5 V < VCPout2 < VCC - 0.5 V 10 nA
PLL 1/f Noise at 10 kHz offset PLL2_CP_GAIN = 400 µA -117
PN10kHz (10). Normalized to dBc/Hz
PLL2_CP_GAIN = 3200 µA -122
1 GHz Output Frequency PLL2_CP_GAIN = 400 µA -219
Normalized Phase Noise
PN1Hz dBc/Hz
Contribution (11) PLL2_CP_GAIN = 3200 µA -224
Internal VCO Specifications
LMK040x0 1185 1296
LMK040x1 1430 1570
fVCO VCO Tuning Range MHz
LMK040x2 1600 1750
LMK040x3 1840 2160
LMK040x0, TA= 25 °C, single- 3
ended
LMK040x1, TA= 25 °C, single- 3
ended
VCO Output power to a LMK040x2, TA= 25 °C, single-
PVCO 2 dBm
50 Ωload driven by Fout ended
LMK040x3, TA= 25 °C, single- 0
ended 1840 MHz
LMK040x3, TA= 25 °C, single- -5
ended 2160 MHz
(9) This parameter is programmable
(10) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
(11) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as:
PN1HZ=LPLL_flat(f)-20log(N)-10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz
bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
www.ti.com
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
Fine Tuning Sensitivity LMK040x0 7 to 9
(The range displayed in the LMK040x1 8 to 11
typical column indicates the LMK040x2 9 to 14
lower sensitivity is typical at
KVCO the lower end of the tuning MHz/V
range, and the higher tuning
sensitivity is typical at the LMK040x3 14 to 26
higher end of the tuning
range). After programming R15 for
Allowable Temperature Drift lock, no changes to output
|ΔTCL| for Continuous Lock 125 °C
configuration are permitted to
(12) guarantee continuous lock
Internal VCO Open Loop Phase Noise and Jitter
Offset = 1 kHz -66
Offset = 10 kHz -94
LMK040x0
fVCO = 1185 MHz Offset = 100 kHz -119
SSB Phase Noise dBc/Hz
Offset = 1 MHz -139
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -158
Offset = 20 MHz -163
Offset = 1 kHz -64
Offset = 10 kHz -91
LMK040x0
fVCO = 1296 MHz Offset = 100 kHz -117
SSB Phase Noise dBc/Hz
Offset = 1 MHz -138
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -157
Offset = 20 MHz -161
L(f)Fout Offset = 1 kHz -61
Offset = 10 kHz -91
LMK040x1
fVCO = 1440 MHz Offset = 100 kHz -117
SSB Phase Noise dBc/Hz
Offset = 1 MHz -138
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -158
Offset = 20 MHz -160
Offset = 1 kHz -58
Offset = 10 kHz -89
LMK040x1
fVCO = 1560 MHz Offset = 100 kHz -115
SSB Phase Noise dBc/Hz
Offset = 1 MHz -137
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -157
Offset = 20 MHz -162
(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was
at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register,
even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if
the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to
ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the
frequency range of -40 °C to 85 °C without violating specifications.
10 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
Offset = 1 kHz -63
Offset = 10 kHz -91
LMK040x2
fVCO = 1600 MHz Offset = 100 kHz -115
SSB Phase Noise dBc/Hz
Offset = 1 MHz -137
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -156
Offset = 20 MHz -161
Offset = 1 kHz -61
Offset = 10 kHz -90
LMK040x2
fVCO = 1750 MHz Offset = 100 kHz -114
SSB Phase Noise dBc/Hz
Offset = 1 MHz -136
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -155
Offset = 20 MHz -160
L(f)Fout Offset = 1 kHz -58
Offset = 10 kHz -88
LMK040x3
fVCO = 1840 MHz Offset = 100 kHz -113
SSB Phase Noise dBc/Hz
Offset = 1 MHz -135
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -155
Offset = 20 MHz -158
Offset = 1 kHz -54
Offset = 10 kHz -84
LMK040x3
fVCO = 2160 MHz Offset = 100 kHz -110
SSB Phase Noise dBc/Hz
Offset = 1 MHz -132
PLL2 = Open Loop
Measured at Fout Offset = 10 MHz -154
Offset = 20 MHz -157
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
www.ti.com
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO
Offset = 1 kHz -111
Offset = 10kHz -119
LMK040x0 (13) Offset = 100 kHz -121
fVCO = 1200 MHz
SSB Phase Noise Offset = 1 MHz -133 dBc/Hz
PLL2 = Closed Loop Offset = 10 MHz -157
Measured at Fout Offset = 20 MHz -162
Offset = 40 MHz -165
Offset = 1 kHz -110
Offset = 10 kHz -117
LMK040x1 (14) Offset = 100 kHz -120
fVCO = 1500 MHz
SSB Phase Noise Offset = 1 MHz -132 dBc/Hz
PLL2 = Closed Loop Offset = 10 MHz -156
Measured at Fout Offset = 20 MHz -160
Offset = 40 MHz -163
L(f)Fout Offset = 1 kHz -111
Offset = 10 kHz -118
LMK040x2 (15) Offset = 100 kHz -120
fVCO = 1600 MHz
SSB Phase Noise Offset = 1 MHz -132 dBc/Hz
PLL2 = Closed Loop Offset = 10 MHz -156
Measured at Fout Offset = 20 MHz -162
Offset = 40 MHz -165
Offset = 1 kHz -107
Offset = 10 kHz -114
LMK040x3 (16) Offset = 100 kHz -117
fVCO = 2000 MHz
SSB Phase Noise Offset = 1 MHz -126 dBc/Hz
PLL2 = Closed Loop Offset = 10 MHz -152
Measured at Fout Offset = 20 MHz -156
Offset = 40 MHz -160
(13) For LMK040x0, fVCO = 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
(14) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
(15) For LMK040x2, fVCO = 1600 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 8, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
252 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
(16) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW
= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
12 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
LMK040x0 (13) BW = 12 kHz to 20 MHz 105
fVCO = 1200 MHz BW = 100 Hz to 20 MHz 110
Integrated RMS Jitter
LMK040x1 (14) BW = 12 kHz to 20 MHz 100
fVCO = 1500 MHz BW = 100 Hz to 20 MHz 105
Integrated RMS Jitter
JFout fs
LMK040x2 (15) BW = 12 kHz to 20 MHz 95
fVCO = 1600 MHz BW = 100 Hz to 20 MHz 100
Integrated RMS Jitter
LMK040x3 (16) BW = 12 kHz to 20 MHz 105
fVCO = 2000 MHz BW = 100 Hz to 20 MHz 110
Integrated RMS Jitter
CLKout's Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO
Offset = 1 kHz -125
LMK040x0 (17)
fCLKout = 250 MHz Offset = 10 kHz -130
SSB Phase Noise Offset = 100 kHz -132
Measured at Clock Outputs Offset = 1 MHz -148
Value is average for all output
types Offset = 10 MHz -157
Offset = 1 kHz -126
LMK040x1 (18)
fCLKout = 250 MHz Offset = 10 kHz -133
SSB Phase Noise Offset = 100 kHz -136
Measured at Clock Outputs Offset = 1 MHz -147
Value is average for all output
types Offset = 10 MHz -156
L(f)CLKout dBc/Hz
Offset = 1 kHz -127
LMK040x2 (19)
fCLKout = 250 MHz Offset = 10 kHz -133
SSB Phase Noise Offset = 100 kHz -134
Measured at Clock Outputs Offset = 1 MHz -145
Value is average for all output
types Offset = 10 MHz -157
Offset = 1 kHz -125
LMK040x3 (20)
fCLKout = 250 MHz Offset = 10 kHz -132
SSB Phase Noise Offset = 100 kHz -135
Measured at Clock Outputs Offset = 1 MHz -145
Value Is average for all output
types Offset = 10 MHz -156
(17) For LMK040x0, fVCO = 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
251 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
(18) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = 2. CLKout_DLY = OFF.
(19) For LMK040x2, fVCO = 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
354 kHz, PM = 73°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
(20) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW
= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = 4. CLKout_DLY = OFF.
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
www.ti.com
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
LMK040x0 (21) BW = 12 kHz to 20 MHz 130
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 135
Integrated RMS Jitter
LMK040x1 (22) BW = 12 kHz to 20 MHz 115
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 120
Integrated RMS Jitter
JCLKout fs
LVPECL/2VPECL/LVDS LMK040x2 (23) BW = 12 kHz to 20 MHz 130
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 135
Integrated RMS Jitter
LMK040x3 (24) BW = 12 kHz to 20 MHz 125
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 130
Integrated RMS Jitter
LMK040x0 (21) BW = 12 kHz to 20 MHz 140
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 145
Integrated RMS Jitter
LMK040x1 (22) BW = 12 kHz to 20 MHz 110
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 115
Integrated RMS Jitter
JCLKout fs
LVCMOS LMK040x2 (23) BW = 12 kHz to 20 MHz 130
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 135
Integrated RMS Jitter
LMK040x3 (24) BW = 12 kHz to 20 MHz 120
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 125
Integrated RMS Jitter
CLKout's Internal VCO Closed Loop Jitter Specifications using a Commercial Quality VCXO
(21) For LMK040x0, fVCO = 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
251 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
(22) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = 2. CLKout_DLY = OFF.
(23) For LMK040x2, fVCO = 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
354 kHz, PM = 73°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
(24) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW
= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = 4. CLKout_DLY = OFF.
14 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Links: LMK04000 LMK04001 LMK04002 LMK04010 LMK04011 LMK04031 LMK04033
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com
SNOSAZ8J SEPTEMBER 2008REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V VCC 3.45 V, -40 °C TA85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA= 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
LMK040x0 (25) (26) BW = 12 kHz to 20 MHz 140 200
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 185
Integrated RMS Jitter
LMK040x1 (27) (26) BW = 12 kHz to 20 MHz 130 200
fCLKout = 250 MHz BW = 100 Hz to 20 MHz 190
Integrated RMS Jitter
JCLKout fs