NJU26202 Digital Signal Processor for Car Audio General Description Package The NJU26202 is a digital signal processor that provides the function of Circle Surround Automotive, Hall Simulator, 7Band PEQ / GEQ, and Time Alignment. The applications of NJU26202 are suitable for multi-channel products such as Car Audio small speakers system. NJU26202FN2 Features -Software SRS Circle Surround Automotive TruBass FOCUS Hall Simulator 7Band PEQ / GEQ Time Alignment Sampling Frequency - 16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz (Stereo Input Mode and Multi Input Mode) - 32kHz/44.1kHz/48kHz (CS Auto Mode) -Hardware 24bit Fixed-point Digital Signal Processing Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit Digital Audio Interface : 4 Input ports / 3 Output ports Digital Audio Format : I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs Master / Slave Mode Microcomputer Interface - I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps) - 4 -Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data) Operating Voltage : VDD = VDDPLL = 1.8V : VDDIO = 3.3V Input Terminal : 5.0V Input tolerant Package : QFP48-N2 (Pb-Free) * The detail hardware specification of the NJU26202 is described in the " NJU26200 Series Hardware Data Sheet". Ver.2007-02-26 -1- NJU26202 Block Diagram AD1/SDIN NJU26202 AD2/SSb SERIAL AUDIO INTERFACE 24bit Fixed-point DSP Core SCL/SCK SERIAL HOST INTERFACE SDA/SDOUT BCKO PROGRAM CONTROL LRO 24-BIT x 24-BIT MULTIPLIER ALU RESETb MCK TIMING GENERATOR / PLL CLK CLKOUT FL/FR SDO1 C/SW SDO2 RL/RR SDO3 ADDRESS GENERATION UNIT SDIO-3 BCKI LRI DATA RAM PROC FIRMWARE ROM MUTEb General I/O INTERFACE SEL WDC Fig. 1 NJU26202 Hardware Block Diagram Function Block Diagram OUT IN L/R Multi Input Mode SDI0 L/R Phantom Center SDI0 or SDI1, L/R , C/SW , LS/RS Time Alignment Front L/R (L/R) C/SW LS/RS SDO1 SDI2 , SDI3 L/R SDI1 CS Auto Mode Input Trim C/SW Master Volume C/SW CS Auto SDI0 or SDI1 LS/RS & Channel Trim SDI2 LS/RS SDI3 Mode SDI0 or SDI1 Front L/R Front L/R (L/R) Stereo Input PEQ/GEQ 7Band Hall * Simulator (L/R) FOCUS TruBass Rear L/R (LS/RS) Time * Alignment SW & Smooth C/SW SDO2 Rear L/R (LS/RS) SDO3 Rear L/R (LS/RS) *Hall Simulator and Time Alignment do not work at the same time. Fig. 2 NJU26202 Block Diagram -2- Ver.2007-02-26 NJU26202 VDD 29 AD1/SDIN VSS 30 25 VSSIO 31 AD2/SSb VDDIO 32 26 MCK 33 SCL/SCK BCKO 34 27 LRO 35 28 SDA/SDOUT SDO3 36 Pin Configuration SDO2 37 24 TEST SDO1 38 23 TEST TEST 39 22 TEST VDDIO 40 21 RESETb VSSIO 41 20 VDDIO VSS 42 19 VSSIO VDD 43 18 CLK SDI3 44 17 CLKOUT SDI2 45 16 VDD SDI1 46 15 VSS SDI0 47 14 VSSPLL LRI 48 13 VDDPLL 1 2 3 4 5 6 7 8 9 10 11 12 VDDIO BCKI VSSIO VSS VDD TEST MUTEb WDC PROC VSSIO VDDIO SEL NJU26202 Fig. 3 NJU26202 Pin Configuration Ver.2007-02-26 -3- NJU26202 Pin Description Table 1 Pin Description Pin No. Symbol 1,11,20,32,40 VDDIO 2 BCKI 3,10,19,31,41 VSSIO 4,15,30,42 VSS 5,16,29,43 VDD 6 TEST 7 MUTEb * 8 WDC * 9 PROC * 12 SEL 13 VDDPLL 14 VSSPLL 17 CLKOUT 18 CLK 21 RESETb 22 TEST 23,24 TEST 25 AD1/SDIN 26 AD2/SSb 27 SCL/SCK I/O I I I OD I I O I I I I I I I 28 SDA/SDOUT I/O 33 34 35 36 37 38 39 44 45 46 47 48 MCK BCKO LRO SDO3 SDO2 SDO1 TEST SDI3 SDI2 SDI1 SDI0 LRI O O O O O O O I I I I I Function I/O Power Supply +3.3V Bit Clock Input I/O GND Core GND Core Power Supply +1.8V for test (connected to VSSIO through 3.3k resistance.) Master Volume level, After Reset DSP ("1" : 0dB "0" : Mute) Clock for Watch Dog Timer (Open Drain Output) After Reset DSP. ( "1" : Normal "0" : Wait from Command ) Select I2C or Serial bus ( `1' : Serial / `0' : I2C-Bus) PLL Analog Power Supply +1.8V PLL Analog GND OSC Output X'tal Clock Input (12.288MHz) Reset (RESETb='0' : DSP Reset) for Test (Connect to VDDIO) for Test (Connect to VSSIO) I2C Address / Serial Input I2C Address / Serial Enable I2C Clock / Serial Clock I2C I/O (Open Drain output) / Serial Output (CMOS output) I2C Bus mode : SDA pin requires a pull-up resistance. 4-wire Serial mode : SDOUT does not require a pull-up resistance. Master Clock Output (CLK Terminal=27pin Buffer Out) Bit Clock Output LR Clock Output Audio Data Output 3 ( Rear Lch / Rch ) Audio Data Output 2 ( Center / Subwoofer ) Audio Data Output 1 ( Front Lch / Rch ) for Test ( No connect : OPEN ) Audio Data Input 3 ( SL / SR ) Audio Data Input 2 ( Center / Subwoofer) Audio Data Input 1 ( Front Lch / Rch ) Audio Data Input 0 ( Front Lch / Rch ) LR Clock Input Note : I : Input O : Output OD : Open Drain Output I/O : Bi-directional Pins symbol with * : Connect with VDDIO or VSSIO through 3.3k resistance -4- Ver.2007-02-26 NJU26202 Audio Interface The NJU26202 audio interface provides industry serial data formats of I2S, MSB-first Left-justified or MSB-first Right-justified. The NJU26202 audio interface provides two data inputs, SDI0 and SDI1, and three data outputs, SDO0, SDO1 and SDO2, as shown in table 2 and 3. The input serial data is selected by the firmware command. Table 2 Serial Audio Input Pin Pin No. Symbol Description 47 SDI0 Lch / Rch Audio Data Input 0 46 SDI1 Lch / Rch Audio Data Input 1 45 SDI2 Cch / SWch Audio Data Input 2 44 SDI3 LSch / RSch Audio Data Input 3 Table 3 Serial Audio Output Pin Pin No. Symbol Description 38 SDO1 Front Lch/Rch Audio Data Output 1 37 SDO2 Cch / SWch Audio Data Output 2 36 SDO3 Rear Lch/Rch Audio Data Output 3 Host Interface The NJU26202 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or 4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. The detail I2C bus and 4-Wire Serial bus information are described in the `NJU26200 Series Hardware Data Sheet'. Table 4 Serial Host Interface Pin Descriptions Pin No. Symbol Setting Host Interface 2 Low I C Bus Interface 12 SEL High 4-Wire Serial Interface Table 5 Pin No. 25 26 27 28 Serial Host Interface Pin Description I2C bus Interface Symbol 2 (I C /Serial) AD1/SDIN I2C Address Select Bit1 AD2/SSb I2C Address Select Bit2 SCL/SCK Serial Clock SDA/SDOUT Serial Data Input/Output (Open Drain output) 4-Wire Serial Interface Serial data input Slave select Serial Clock Serial data output (CMOS Output) Note: When 4-Wire Serial bus is selected, The SDA/SDOUT pin is CMOS output. The SDOUT pin does not require a pull-up resistance. When I2C Bus is selected, this pin is a bi-directional Open Drain output. This pin, which is assigned for I2C Bus, requires a pull-up resistance. The SDA/SDOUT pin isn't 5.0V Input tolerant. Ver.2007-02-26 -5- NJU26202 I2C Bus When the NJU26202 is configured for I2C bus communication in SEL="Low", the serial host interface transfers data on the SDA pin and clocks data on the SCL pin. SDA is an open drain pin requiring a pull-up resistance. Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) Table 6 I2C-Bus Interface Slave address bit7 0 0 0 0 bit6 0 0 0 0 bit5 1 1 1 1 Start bit bit4 1 1 1 1 bit3 1 1 1 1 AD2 AD1 bit2 0 0 1 1 bit1 0 1 0 1 R/W bit Slave Address ( 7bit ) R/W bit0 R/W ACK * SLAVE address is 0 when AD1/2 is "Low". SLAVE address is 1 when AD1/2 is "High". Note: The serial host interface supports "Standard-Mode (100kbps)" and "Fast-Mode (400kbps)" I2C bus data transfer. Moreover, after sending S ("START" condition), Sr (repeated "START" condition) is not received but it becomes the waiting for the P ("STOP" condition). Therefore, please be sure to send P ("STOP" condition). 4-Wire Serial Interface The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1="High" during the Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting SSb = "Low". Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is latched on the falling transitions of SSb. The SDOUT pin is always CMOS output. This pin does not require a pull-up resistance. SSb SCK SDIN bit7 bit6 bit5 bit1 MSB SDOUT unstable bit7 bit0 LSB bit6 bit5 bit1 bit0 unstable Fig. 4 4-Wire Serial Interface Timing Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb="High". When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data that is received via SDIN until SSb becomes "High". -6- Ver.2007-02-26 NJU26202 Pin setting The NJU26202 operates default command setting after resetting the NJU26202. In addition, the NJU26202 restricts operation at power on by setting PROC pin and MUTEb pin (Table 7). These pins are input pin. However, these pins operate as bi-directional pins. Connect with VDDIO or VSSIO through 3.3k resistance. Table 7 Pin setting Pin No. Symbol Setting "High" 9 PROC "Low" 7 MUTEb "High" "Low" Function The NJU26202 operates default setting after reset. The NJU26202 does not operate after reset. Sending start command is required for starting operation. Master volume is set 0dB after reset. Master volume is set mute after reset. WatchDog Clock The NJU26202 outputs clock pulse through WDC (Pin No.8) during normal operation. The WDC clock is useful to check the status of the NJU26202 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26202. When the WDC clock pulse is lost or not normal clock cycle, the NJU26202 does not operate correctly. Then reset the NJU26202 and set up the NJU26202 again. The output toggle cycle from a WDC pin is set as about 100ms. The WDC pin is open drain output. The WDC pin setting (Table 8) Table 8 WDC pin setting Pin No. Symbol WDC pin is used. 8 WDC WDC pin is not used. Setting Connect with VDDIO through 3.3k resistance Connect with VSSIO through 3.3k resistance. Do not open WDC pin. Note: The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing. In slave mode, when there is no input of BCKI/LRI, the WDC pin can't output. It is required to set up a sampling rate correctly. Ver.2007-02-26 -7- NJU26202 Firmware Command Table Table 9 NJU26202 Command No. Command 1 Set Task 2 Circle Surround Config 3 Circle Surround Automotive Config 4 TruBass Config 5 TruBass Size Select 6 TruBass Gain Control 7 FOCUS Config 8 FOCUS Gain Control 9 Input Trim Control 10 Master Volume Control 11 Channel Trim Control 12 Delay Control 13 Stereo Input Mode Config 14 Hall Simulator Input Select 15 Hall Simulator HPF fc 16 Hall Simulator LPF fc 17 Hall Simulator Early Reflection Start Time 18 Hall Simulator Early Reflection End Time 19 Hall Simulator Reverb Start Time 20 Hall Simulator HF Dump 21 Hall Simulator Reverb Time No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Command Hall Simulator Surround Hall Simulator Effect Output Trim Hall Simulator Balance Trim EQ Mode Select EQ f0 Control EQ Q Control EQ Gain Control Time Alignment SW LPF fc Sample rate Select Smooth Control Config Input Select Phantom Center Config TruBass Input Select Input Mode Config System State Firmware Version Number Request DSP Reset Start Nop Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser (SRS Labs. Inc.) is required. -8- Ver.2007-02-26 NJU26202 Package Dimensions ( QFP48-N2, Pb-Free ) BASE OF MOLDING MOLD MATERIAL : EPOXY RESIN Ver.2007-02-26 -9- NJU26202 License Information 1. The "Circle Surround Automotive", "FOCUS", "TruBass" technology rights incorporated in the NJU26202 are owned by SRS Labs, a U.S. Corporation and licensed to New Japan Radio Co., Ltd.. Purchaser of NJU26202 must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the NJU26202 must be send to SRS Labs for review. "Circle Surround Automotive", "FOCUS", "TruBass" are protected under US and foreign patents issued and/or pending. "Circle Surround Automotive", "FOCUS", "TruBass", SRS and symbol are trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the NJU26202, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technology. SRS Labs requires all set marks to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual separately provided. For further information, please contact:: SRS Labs, Inc. 2909 Daimler Street. Santa Ana, CA 92705 USA Tel: 949-442-1070 Fax: 949-852-1099 http://www.srslabs.com [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 10 - Ver.2007-02-26