NJU26202
-
-Ver.2007-02-26
Pin Description
Table 1 Pin Description
Pin No. Symbol I/O Function
1,11,20,32,40 VDDIO - I/O Power Supply +3.3V
2 BCKI I Bit Clock Input
3,10,19,31,41 VSSIO - I/O GND
4,15,30,42 VSS - Core GND
5,16,29,43 VDD - Core Power Supply +1.8V
6 TEST I for test (connected to VSSIO through 3.3kΩ resistance.)
7 MUTEb * I Master Volume level, After Reset DSP (“1” : 0dB “0” : Mute)
8 WDC * OD Clock for Watch Dog Timer (Open Drain Output)
9 PROC * I After Reset DSP. ( “1” : Normal “0” : Wait from Command )
12 SEL I Select I2C or Serial bus ( ‘1’ : Serial / ‘0’ : I2C-Bus)
13 VDDPLL - PLL Analog Power Supply +1.8V
14 VSSPLL - PLL Analog GND
17 CLKOUT O OSC Output
18 CLK I X’tal Clock Input (12.288MHz)
21 RESETb I Reset (RESETb=’0’ : DSP Reset)
22 TEST I for Test (Connect to VDDIO)
23,24 TEST I for Test (Connect to VSSIO)
25 AD1/SDIN I I2C Address / Serial Input
26 AD2/SSb I I2C Address / Serial Enable
27 SCL/SCK I I2C Clock / Serial Clock
28 SDA/SDOUT I/O
I2C I/O (Open Drain output) / Serial Output (CMOS output)
I2C Bus mode : SDA pin requires a pull-up resistance.
4-wire Serial mode : SDOUT does not require a pull-up resistance.
33 MCK O Master Clock Output (CLK Terminal=27pin Buffer Out)
34 BCKO O Bit Clock Output
35 LRO O LR Clock Output
36 SDO3 O Audio Data Output 3 ( Rear Lch / Rch )
37 SDO2 O Audio Data Output 2 ( Center / Subwoofer )
38 SDO1 O Audio Data Output 1 ( Front Lch / Rch )
39 TEST O for Test ( No connect : OPEN )
44 SDI3 I Audio Data Input 3 ( SL / SR )
45 SDI2 I Audio Data Input 2 ( Center / Subwoofer)
46 SDI1 I Audio Data Input 1 ( Front Lch / Rch )
47 SDI0 I Audio Data Input 0 ( Front Lch / Rch )
48 LRI I LR Clock Input
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3kΩ resistance