DSP16410CG - Agere Systems, Inc.

Advisory

December 2002

DSP16411 SEMI Design Exception

Overview

Agere Systems’ DSP16411 is the next-generation digi-

tal signal processor based on the DSP16000 core

architecture offering increased speed and on-chip

memory. The system and external memory interface

(SEMI) interfaces both cores and the direct memory

access unit (DMAU) to external memory and I/O

devices. It may be interfaced directly to pipelined syn-

chronous ZBT® SRAMs and asynchronous SRAMs.

An exception has been found affecting the SEMI and

its interface to external devices.

Description

The SEMI can support a mix of synchronous and asyn-

chronous devices in EROM, ERAM, and EIO memory

spaces. For example, ZBT SRAMs may be mapped to

ERAM space and an asynchronous ASIC may be

mapped to EIO space. The EROM component is syn-

chronous if the ERTYPE pin is logic 1. The ERAM

component is synchronous if the YTYPE field

(ECON1[9]) is set, and the EIO component is synchro-

nous if the ITYPE field (ECON1[10]) is set. The ECKO

(programmable external clock output) pin is provided to

clock external synchronous devices. The ECKOB[1:0]

and ECKOA[1:0] fields of the ECON1 register deter-

mine the state of the ECKO output clock pin.

The SEMI exception affects the condition when

ECKO = CLK/3 or ECKO = CLK/4 (CLK is the internal

processor clock). The ECKO = CLK/3 mode is non-

functional with either synchronous or asynchronous

devices and the ECKO = CLK/4 mode works only with

synchronous devices. The ECKO = CLK and

ECKO = CLK/2 modes are unaffected and function in a

manner consistent with the SEMI operation of the

DSP16410. Asynchronous devices can be used with

either ECKO = CLK or ECKO = CLK/2 modes.

Interfacing to synchronous memories requires opera-

tion in the ECKO = CLK/2 or CLK/4 modes.

There are no plans to correct this exception at this

time. Designs using the DSP16411 can work around

this issue with proper timing evaluation.

Design Implications

As stated above, the ECKO = CLK/3 mode must not be

used and the ECKO = CLK/4 mode should only be

used with synchronous devices present on the SEMI.

Hardware consideration must include careful timing

evaluation to ensure that timing requirements are met.

In so me cases, th is may require the selection of faster

memory to meet setup and hold times. When possible,

the user may also run the DSP16411 processor clock

at a slower speed to meet timing requirements.

The user should also ensure that the DSP16411 is

properly configured. The state of the ERTYPE pin and

the ECON1 register should agree with the supported

SEMI operational modes. The following tables should

be used when programming the DSP16411 SEMI

ECON1 register.

Advisory

DSP16411 SEMI Design Exception December 2002

2Agere Systems Inc.

Design Implications (continued)

Table 1. ECON1 (External Control 1) Register Encoding

The memory address for this register is 0x40002.

15—14 13 12 11 10 9 8

Reserved BHPDIS BHEDIS WEROM ITYPE YTYPE NOSHARE

765 43—2 1—0

Reserved EREADY EACKN EREQN ECKOB[1:0] ECKOA[1:0]

Bit Field Value Description R/W Reset

Value

15—14 Reserved 0 Reserved-write with zero. R/W 0

13 BHPDIS 0 Enable the bus hold circuits on the PD[15:0] and PADD[3:0] pins. R/W 0

1 Disable the bus hold circuits on the PD[15:0] and PADD[3:0] pins.

12 BHEDIS 0 Enable the bus hold circuits on the ED[31:0], EA[18:0], and

ESEG[3:0] pins R/W 0

1 Disable the bus hold circuits on the ED[31:0], EA[18:0], and

ESEG[3:0] pins.

11 WEROM 0 The external portion of Y-memory and Z-memory space is ERAM. R/W 0

1 The ex t e rn al po rt i on of Y-me mo ry an d Z -m e mo ry spac e i s ERO M .

10 ITYPE 0 EION is asynchronous SRAM. R/W 0

1 EION is pipelined, synchronous SRAM.

9 YTYPE 0 ERAMN is asynchronous SRAM. R/W 0

1 ERAMN is pipelined, synchronous SRAM.

8 NOSHARE 0 SEMI works as a bus-shared interface and asserts EACKN in

response to EREQN. R/W 0

1 SEMI ignores requests for the external bus and does not assert

EACKN.

7 Reserved 0 Reserved—write with zero. R/W 0

6 EREADY 0 The ERDY pin indicates an external device is requesting the

SEMI to extend the current asynchronous external memory

access.

* The state (P) is a reflec tion of the state of the external pins and is unaffect ed by reset.

† The state of this field is ignored unless ECKOB[1:0] = 00.

1 The ERDY pin indicates an external device is not requesting the

SEMI to extend the current asynchronous external memory

access.

5 EACKN 0 The EACKN pin indicates the SEMI acknowledges a request by

an external device for access to external memory. R1

1 The EACKN pin indicates the SEMI does not acknowledge a

request by an external device for access to external memory.

4 EREQN 0 The EREQN pin indicates an external device is requesting access

to external memory. RP

1 The EREQN pin indicates an external device is not requesting

access to external memory.

3—2 ECKOB[1:0] 00 The ECKOA[ 1:0] field determ ines the configur ati on of the ECKO

pin. R/W 00

01 Reserved.

10 Reserved.

11 The ECKO pin is CLK/4 for synchronous operation of the SEMI.

Advisory

Decem ber 200 2 DSP16411 SEMI Design Exception

Agere Systems Inc. 3

Design Implications (continued)

* The state (P) is a reflec tion of the state of the external pins and is unaff ected by reset.

† The state of this field is ignored unless ECKOB[1:0] = 00.

If any of the external memory components (ERAM, EROM, or EIO) are configured as synchronous, the ECKO pin

must be configured as CLK/2 or CLK/4.

Conclusion

The DSP16411 SEMI contains a design error resulting in the following restrictions:

!ECKO = CLK/3 mode must be avoided. This option has been removed from the ECKOB[1:0] field of the ECON1

!ECKO = CLK/4 mode supports synchronous operations only. A mix of synchronous and asynchronous devices

on SEMI must be avoided in this mode.

The DSP16411 data sheet will be rewritten to include this information. All data sheets prior to October 2002 are

affected. The user must ensure that the ECON1 register and the ERTYPE pin agree with these restrictions if the

SEMI is used.

Please contact your Agere Systems Applications Engineer if you have questions related to this issue.

Table 1. ECON1 (External Control 1) Register Encoding (continued)

Bit Field Value Description R/W Reset

Value

1—0 ECKOA[1:0]†00 The ECKO pin is CLK/2 for synchronous operation of the SEMI. R/W 00

01 The ECKO pin is the internal clock CLK.

10 The ECKO pin is the buffered input clock pin CKI.

11 The ECKO pin is held low.

Table 2. ECKO Output Clock Pin Configuration

ECKOB[1:0] ECKOA[1:0] ECKO Pin

ECON1[3] ECON1[2] ECON1[1] ECON1[0]1 State Description

0000CLK/2

* Default after reset. After reset, CLK = CKI, so ECKO = CKI/2.

Frequency of CLK† divided by two.

† CLK is the internal (core) clock.

0 0 0 1 CLK Frequency of CLK.

0 0 1 0 CKI Input clock pin.

0 0 1 1 0 Logi c zero.

01XXReserved —

10XXReserved —

1 1 X X CLK/4 Frequency of CLK divided by four.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of the ir use or application. Agere,

Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

December 2002

AY03-007WINF

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-41 06)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo ), KORE A: ( 82) 2- 767-1850 (Seoul), SINGAPORE: ( 65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44) 1344 296 400

ZBT is a regis ter ed trademark of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., and

Motorola, Inc.

Advisory

December 2002

DSP16411 Speed and Core Voltage Migration

Overview

This document describes the migration of the Agere

Systems DSP16411 from a core supply voltage (VDD1,

VDD1A) of 1.0 V nominal to 1.2 V nominal. Associated

with this increase in core supply voltage is a corre-

sponding increase in operating frequency. Otherwise,

the feature set and timing of this device remains

unchanged. Please refer to the DSP16411 Digital Sig-

nal Processor Advance Data Sheet (document number

DS02-037WINF, last released in April 2002) for a com-

plete description of this device.

Device Identification

The DSP16411 with a core voltage of 1.0 V can be

identified by the following package marking:

M-16411A1 BA Y 240 I E

The M denotes models versus production devices. The

M is absent for a production-qualified DSP16411

device. The 240 in this part number is the maximum

rated operating frequency (240 MHz). The E at the end

of this part number identifies this device as requiring a

1.0 V core supply.

The DSP16411 with a core voltage of 1.2 V can be

identified by the following package marking:

M-16411A1 BA Y 240 I J

The J at the end of this part number identifies this

device as requiring a 1.2 V core supply. The 240 in this

part number is the maximum rated operating frequency

(240 MHz) and is subject to change. The target maxi-

mum operating frequency of this device is 285 MHz,

which will be verified during device characterization in

early 2003. The data sheet will be updated as a result

of device characterization. A maximum operating fre-

quency of no less than 240 MHz is guaranteed.

Changes

The DSP16411 with 1.2 V core voltage is fit, form, and

function compatible with the 1.0 V core voltage device,

and the IO voltage (VDD2) remains the same (3.3 V).

Timing for these devices is the same at the same oper-

ating frequency. However , the 1.2 V device will differ in

these char act er ist ics :

!Increased supply voltage from 1.0 V to 1.2 V.

!Increase in typical core power dissipation from

0.40 W @ 1.0 V @ 240 MHz to approximately

0.58 W @ 1.2 V @ 240 MHz. Please refer to Section

9.3 of the DSP16411 Digital Signal Processor Data

Sheet to determine how this impacts package ther-

mal considerations.

!Increased max im um ope ratin g frequ ency from

240 MHz to TBD. Applications that make use of

external memory must verify SEMI timing character-

istics that are operating frequency dependent (those

timing characteristics that contain T, the internal

clock period) for the period of the desired operating

frequency to ensure proper operation.

For questions, please contact your local Agere Sys-

tems Field Applications Engineer.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of the ir use or application. Agere,

Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

December 2002

AY 03-006W I NF (Must Ac com pany DS02-037W INF)

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-41 06)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo ), KORE A: ( 82) 2- 767-1850 (Seoul), SINGAPORE: ( 65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44) 1344 296 400

Advisory

April 2002

DSP16000 Core

In the DSP16000 core, the contents of the internal do

loop cache are also accessible as memory (at loca-

tion 0x1ffc0 in most DSP16000 devices) in order to

facilitate saving and restoring of the cache contents

on a subroutine call or context switch.

It is accessible in both the X and Y address space, pri-

marily in order to allow the use of the block move

pipelin ed ins tructi on for faster loa din g/s aving.

It has been determined that while both X and Y

accesses to this area work correctly, a simultaneous

access of both X and Y to this area does not work.

The bank-conflict wait-state does not get sequenced

properly in this case, and the X-side data is returned

undefined. For example, if the following instruction:

nop y=*r0++ x=*pt0++

is executed with both r0 and pt0 pointing to the inter-

nal cache area, the value returned to the x register will

be undefined.

Since the only reason to access this area is for the

purpose of saving and restoring the cache contents, a

simultaneous read of this area should not be required.

Agere Systems Inc. reser ves the r ight to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere,

Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

April 2002

AY02-020WINF (Must accomp any DA02-001WINF, DA0 1-003WINF, DS02-037WINF, DS02-020WMA,

DS01-152WMA, DS01-070WTEC, and DS98-032WTEC)

For additional informatio n, co nta ct you r Agere Systems Account Ma na ger or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 ( In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2 020

CHINA: (86) 21-5 047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), ( 86) 755-695-7224 (S h enz hen)

JAPAN: (81) 3- 54 21-1600 (Tokyo), KOREA: (82 ) 2-76 7-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (4 4) 7000 624624, FAX (44) 1344 488 045

Advance Data Sheet

April 2002

DSP16411 Digital Signal Processor

1 Features



Twin DSP160 00 dual-MA C cores perform up to

960 million MACs per second at 240 MHz



Low power:

—1.0 V internal supply for power efficiency

—3.3 V I/O pin supply for compatibility



322K x 16 on-chip RAM



Centralized direct memory access unit (DMAU):

—T ransparent peripheral-to-memory and memory-

to-memory transfers

—Better utilization of DSP M IPS

—Simplifies man agem ent of system data flow



16-bit parallel interface unit (PIU) with direct mem-

ory access (DMA) provid es host a cce ss to all DSP

memory



Two enhanc ed serial I/O units (SIU0 and SIU1)

with DMA:

—Compat ible with TDM highways such as T1/E1

and ST-bus

—Hardware support for µ-law and A-law com-

panding



Core messaging units (MGU0 and MGU1) for inter-

processor comm uni cation



On-chip, programmable, PLL clock synthesizer

elim inates need for high-spee d clock input



Two 7-bit control I/O interfaces (BIOs) for

increased flexibility and lower system costs



32-bit system and external memory interface

(SEMI) supports 16-bit or 32-bit synchronous or

asynchronous memories



Two

IEEE

® 1149.1 test ports (JTAG boundary

scan)



Full-spee d, in-circuit emulation hardware for each

core with eight address and two data watchpoint

units for efficient application development



Supp orted by DSP16411 software and hardware

development tools



208-ball PBGA package (17 mm x 17 mm; 1.0 mm

ball pitch) for s m all footprint

2 Description

The DSP16411 is a digital signal processor (DSP)

optimized for communi c ations infrastruc ture applica-

tions. Large, on-chip memory enables it to be pro-

gramme d to perform numerous fixed-point signal

processing func tions, including equali zation, chan-

nel coding, compres sion, and speech coding . The

DSP16411 features twin DSP16000 dual-MAC DSP

cores and enhanced DM A capabi lities. Together,

these features deliver the performance required for

second- and third-generat ion infrastruct ure equip-

ment.

The DSP16411 extends the performance of the

DSP16410C with a higher maximum clock rate and

additional on-chip RAM, while maintaining low power

consumption, efficient software code density, and

small physical size. The DSP16411 is board design,

pinout, and code compatible with the DSP16410C to

protect investments in hardware and software devel-

opment.

Note: This data sheet contains advance information

that is preliminary and subject to change .

Advance Data Sheet
DSP16411 Digital Signal Processor April 2002
Table of Contents
Contents Page
2A gere System s— P rop rietary Agere  Systems In c.
Use
p
ursuant to Com
p
any instructions
➤1 Features...........................................................................................................................................................1
➤2 Description.......................................................................................................................................................1
➤3 Notation Conventions ....................................................................................................................................14
➤4 H a rdwar e  Ar ch itectu r e........................................................................ .................................................... .......14
➤4.1 DSP1 6411 Archi tectural Overview..... ...................................................... . ...........................................14
➤4.1.1 DSP16000 Cores .................... ........................ ..................... ........................ ...........................17
➤4.1 .2 Clock Synthesizer (PLL )..........................................................................................................17
➤4.1.3 Triport RAMs (T PR AM〈0—1〉).................................................................................................17
➤4.1 .4 Shared Local Me mory (SLM)..................................................................................................17
➤4.1.5 Internal Boot ROMs (IROM〈0—1〉) .........................................................................................17
➤4.1.6 Messaging Units (MGU〈0—1〉) ...............................................................................................17
➤4.1 .7 System an d External Memory Interface (SEMI)......................................................................18
➤4.1.8 Bit Input/Output Units (BIO〈0—1〉)..........................................................................................18
➤4.1.9 Timer Units (TIMER0_〈0—1〉 and TIMER1_〈0—1〉)...............................................................18
➤4.1 .10 Direct Memory Acce ss Unit (DMAU).......................................................................................18
➤4.1.11 Interrupt Multiplexers (IMUX〈0—1〉)........................................................................................18
➤4.1 .12 Parallel Interface Unit (PIU) ....................................................................................................18
➤4.1.13 Serial Interface Units (SIU〈0—1〉)...........................................................................................18
➤4. 1. 1 4 Test Access Po rts (JTAG〈0—1〉)............................................................................................18
➤4.1.15 Hardware Developmen t Systems (HDS〈0—1〉)......................................................................18
➤4.2 DSP1 6000 Core Architect ural Overview.................................................. ............................................19
➤4.2.1 System Control and Cache (SYS) ..................... . ................ ..................... ........................ ........19
➤4.2 .2 Data Arithmetic Unit (DAU).....................................................................................................19
➤4.2 .3 Y-Memory Space Address Arithmetic Unit (YAAU).................................................................20
➤4.2 .4 X-Memory Space Address Arithmetic Unit (XAAU).................................................................20
➤4.2 .5 Core Block Diag ram................................................................................................................21
➤4.3 Device Reset ........................................................................................................................................23
➤4.3 .1 Reset After Po werup or Power Interruption ............................................................................23
➤4.3 .2 RSTN Pin R eset......................................................................................................................23
➤4.3 .3 JTAG Controller Reset............................................................................................................24
➤4.4 In te r r u p ts a nd Trap s..... ................................................................................................... .....................25
➤4.4.1 Hardware Interrupt Logic ................ ........................ ..................... ........................ ....................25
➤4.4 .2 Hardware Interrupt Multiplexing..............................................................................................28
➤4.4.3 Clearing Core Interrupt Requests .................... .......... ....... .. ....... .......... .. ....... ....... .......... .. .......30
➤4.4 .4 Host Interrupt Output...............................................................................................................30
➤4.4.5 Globally Enabling and Disabling Hardware Interrupts.......................... ....... .. ....... .......... ....... ..30
➤4.4.6 Individually Enabling, Disabling, and Prioritizing Hardware Interrupts................ ....................31
➤4.4 .7 Hardware Interrupt Status.......................................................................................................32
➤4.4 .8 In terrupt a nd T rap Ve ctor Table..............................................................................................32
➤4.4 .9 Software Interrupts..................................................................................................................34
➤4.4 .10 INT [3:0] and TRAP Pins..........................................................................................................34
➤4.4 .11 Nesting Interrupts....................................................................................................................35
➤4. 4.12 Inter ru p ts a nd Cac he Usa g e.................................... ...............................................................37
➤4. 4.13 Inter ru p t Po ll ing... ..................................................................................................... ...............37
➤4.5 Memory Maps......................................................................................................................................38
➤4.5 .1 Private Internal Mem ory..........................................................................................................39
➤4.5 .2 Shared Internal  I/O..................................................................................................................39
➤4.5 .3 Shared External I/O and Memory............................................................................................39
➤4. 5.4 X-Memor y Map.............................................................................................................. ..........40
➤4. 5.5 Y-Memor y Map s............................................................................................................... .......41
➤4.5 .6 Z-Memory M aps......................................................................................................................42

Table of Contents (continued)
Contents Page
Advance Data Sheet
Apr il 2002 DSP16411 Digital Signal Processor
Agere Syst e ms Inc. Agere S ystems—Prop rieta ry 3
Use
p
ursuant to Com
p
any instructions
➤4.5.7 Internal I/O Detailed Memory Map..........................................................................................43
➤4.6 Triport Random-Access Memory (TPRAM) ...... ................. ............... ........... .............. ............... ...........44
➤4.7 Shared Local Memory (SLM) ...............................................................................................................45
➤4.8 Interprocessor Communication............................................................................................................46
➤4.8.1 Core-to-Core Interrupts and Traps........................ ..................... ........................ .....................47
➤4.8.2 Message Buffer Data Exchang e .......... ........................ ..................... ........................ ..............47
➤4.8.2.1 Mess age B uffer Write Protocol ................................................ . ..............................48
➤4.8.2.2 Mess age B uffer Read Protocol.. ....................................... . .....................................48
➤4.8.3 DMAU Data Transfer...............................................................................................................49
➤4.9 Bit Input/Output Units (BIO〈0—1〉).......................................................................................................50
➤4.10 Timer Units (TIMER0_〈0—1〉 and TIMER1_〈0—1〉) ...........................................................................53
➤4.11 Hardware Development System (HDS〈0—1〉).....................................................................................56
➤4.12 JTAG Test Port (JTAG〈0—1〉).............................................................................................................57
➤4.12.1 Port Identification ....................................................................................................................57
➤4.12.2 E mulation Interface Signals to the DSP16411. ................... . ............. ................... . ................ ..58
➤4.12 .2.1 TCS 14- Pin Header............................................ .....................................................58
➤4.12.2.2 JCS 20-Pin Header. ............. ........................ ..................... ........................ ..............59
➤4.12.2.3 HDS 9-Pin, D-Type Connector ................................................................................60
➤4.12 .3 Multiproce ssor JTAG Connections.... ......................................................................................61
➤4.12.4 Boundary Scan................................................. .................................................... . ..................62
➤4.13 Direct Memory Acce ss Unit (DMAU)....................................................................................................64
➤4.13.1 Overview .................................................................................................................................64
➤4.13.2 Registers.................................................................................................................................67
➤4.13 .3 Da ta  Str u ctures................................................................................................. ......................83
➤4.13.3.1 One-Dimension al Data Structure (SWT Channels) ...................... ........................ ..83
➤4.13.3.2 Two-Dimension al Data Structure (SWT Channels) ...................... ........................ ..84
➤4.13.3.3 Memory-to-Memory Block T ransfers (MMT Channels)................ ....... ..... ....... ....... .86
➤4.13.4 The PIU Addressing Bypass Channel..................................................... ................... .............86
➤4.13.5 Single -Word Transfer Channels (SWT) ..................................................................................87
➤4.13.6 Me mory-t o-Memory Transf er Channels (MMT).............. ........................ ..................... ............90
➤4.13 .7 Interr u p ts a nd Priority Resolutio n....................................................................................... .....92
➤4.13.8 E rror Reporting and Recovery ............. . ................ ..................... ........................ .....................94
➤4.13 .9 Program mi ng Exa mples..................................................................................................... .....95
➤4.13.9.1 SWT Example 1: A Two-Dimensi onal Array ....... . ............. ........................ ..............95
➤4.13.9.2 SWT Example 2: A One-Dimen sional Array ............ ................ . ................ ..............97
➤4.13.9.3 MMT Example.........................................................................................................99
➤4.14 System and Extern al Memory Interfa ce (SEMI).................................................................................100
➤4.14 .1 Externa l Interfa ce.......................................................................................................... ........101
➤4.14.1.1 Configuration.........................................................................................................102
➤4.14.1.2 Asynchronous  Me mory Bus Arbitr ation . ...................................................... . .........1 03
➤4.14.1.3 Enables and Strobes........... ................... ................... .............. ................... ...........104
➤4.14.1.4 Extern al Clock.......................................................................................................105
➤4.14.1.5 Address and Data ......... . ................................ . ..................................... . ................1 06
➤4.14.1.6 Address and Data ......... . ................................ . ..................................... . ................1 08
➤4.14.2 16-Bit External Bus Accesses...............................................................................................109
➤4.14.3 32-Bit External Bus Accesses...............................................................................................109
➤4.14.4 Registers...............................................................................................................................110
➤4.14.4.1 ECON0 Register... ...................................... ..........................................................111
➤4.14.4.2 ECON1 Register... ...................................... ..........................................................112
➤4.14.4.3 Segment Registers ...............................................................................................114
➤4.14 .5 Asynchr o nous  Memor y .. .......................................................................................... .............116

Table of Contents (continued)
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➤4.14.5.1 Functional Timi ng ........................................................ . ..................................... . ...1 16
➤4.14.5.2 Extending Acce ss Time Via the ERDY Pin...........................................................1 20
➤4.14 .5.3 Interf a cing Example s .. ..........................................................................................122
➤4.14.6 Synchronous Memory ... ....... .. ....... .......... ....... .. .......... ....... .. ....... .......... ....... .. ....... .......... .. .....124
➤4.14.6.1 Functional Timi ng ........................................................ . ..................................... . ...1 24
➤4.14 .6.2 Interf a cing Example s .. ..........................................................................................126
➤4.14.7 Performance..........................................................................................................................128
➤4.14.7.1 System  Bus...........................................................................................................128
➤4.14.7.2 External Memory, Asynchronous Interface.... ............. ........................ ..................1 29
➤4.14.7.3 External Memory, Synchronous In terface. .................. ........................ ..................1 31
➤4.14.7.4 Summary of Access Times...................................................................................1 33
➤4.14.8 Priority...................................................................................................................................134
➤4.15 Parallel Interface Unit (PIU)...............................................................................................................1 35
➤4.15.1 Registers...............................................................................................................................135
➤4.1 5.2 Hardware In terface ................................................................................................................139
➤4.15.2.1 Enables and Strobes........................................... ................... .............. .................140
➤4.15.2.2 Address and Data Pins........................................................... ..............................1 41
➤4.15.2.3 Flags, Interr upt, and Ready Pins ..... .......... ....... ....... .. .......... ....... .. ....... .......... .......142
➤4.15.3 Hos t Data Read and Write Cycles ............. ........................ ..................... ........................ ......1 43
➤4.15.4 Hos t Register Read and Write Cycles . . ............. ........................ ..................... .......................1 45
➤4.15.5 Hos t Commands .............. . ............. ........................ ..................... ................... . ......................147
➤4.15.5.1 Status/Control/Addres s Register Read Comma nds................ . ............. ................148
➤4.15.5.2 Status/Control/Addres s Register Write Commands..................... ..................... ....1 48
➤4.15.5.3 Memory Read Commands............. .. .......... ....... ....... .. .......... ....... .. ....... .......... .......149
➤4.15.5.4 Flow Control for Me mory Read Com ma nds.......................... ................ . ...............1 50
➤4.15.5.5 Memory Write Commands........ ................... .............. ................... ................... .....151
➤4.15.5.6 Flow Control for Control/Status/Address Register and Memory Write
Commands ........................................................................................................151
➤4.15.6 Hos t Command Exam ple s ...... ................... . ................ ..................... ..................... ................152
➤4.15.6.1 Download of Program or Data . ..................... ........................ ..................... ...........152
➤4.15.6.2 Upload of Data. .................................................... . ................................ . ...............152
➤4.1 5.7 PIU Interrupts........................................................................................................................153
➤4.16 Serial In terface Un it (SIU)..................................................................................................................1 54
➤4.1 6.1 Hardware In terface ................................................................................................................156
➤4.16.2 P in Conditioni ng Logic, Bit Clock Selection Logi c, and Frame Sync S election Logic...........157
➤4.16.3 Basic Input Processing..................................... ................... ................... .............. .................159
➤4.1 6.4 Basic Outpu t Processin g.......................................................................................................1 60
➤4.16.5 Clock and Frame Sync Generation.................. ................... ................... .............. .................161
➤4.1 6.6 ST-Bus Timing Examples ......................................................................................................166
➤4.16.7 S IU Loopbac k. ................ ..................... ........................ ..................... ..................... ................168
➤4.1 6.8 Basic Frame Structure ..........................................................................................................168
➤4.16.9 A ssigning SIU Logical Channels to DMAU Channels . ..................... . ............. .......................1 69
➤4.1 6.10 Frame Error Detection and Reporting...................................................................................1 70
➤4.1 6.11 Frame Mode..........................................................................................................................1 70
➤4.16.12 Channel Mode—32 Channels or Less in Two Subframe s or Less ......... . .............................1 71
➤4.16.13 Channel Mode —Up to 128 Channels in a Maxi mum of Eight Subfram es ............................1 77
➤4.1 6.14 SIU Examples .......................................................................................................................180
➤4.16.14.1 Single-Chann el I/O ..................... ........................ ..................... ........................ ......1 80
➤4.16.14.2 ST-Bus Interface...................................................................................................181
➤4.16.15 Registers...............................................................................................................................184
➤4.17 Internal Clock Selection .....................................................................................................................2 00

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➤4.18 Clo ck Syn th e sis................................................................................................................ .......... ........201
➤4.18.1 PLL Operating Frequency................................................................ ................... ..................201
➤4.18.2 PLL L OCK Flag Generation..................................................................................................201
➤4.18 .3 PL L  Register s.......... ................................................................................................... ...........202
➤4.18.4 PLL Programming Examp le..................................................................................................203
➤4.18.5 Powering Down the PLL........................................................................................................203
➤4.18.6 Phase-Lock Loop (PLL) Frequency Accuracy and Jitter.................. ................... ..................203
➤4.19 External Clock Selection....................................................................................................................204
➤4.20 Power  Man age men t.... .......................................... .............................................................. ...............205
➤5 Processor Boot-Up and Memory Download......... ................. ................................. ......... ................. ............208
➤5.1 IROM Boot Ro utine and H ost Download Via PIU ..............................................................................2 08
➤5.2 EROM Boot Routine and DMAU Downl oad...... . ................ ..................... ........................ ...................209
➤6 So ftware Architect u re . .............. .......................................................................................... .........................210
➤6.1 Instruction Set Quick Reference........................................................................................................2 10
➤6.1.1 Condi tions Based on the State of Flags................................................... .............................226
➤6.2 Registers............................................................................................................................................227
➤6.2.1 Directly Program-Accessible (Register-Mapped) Registers...... ..... ....... .. .......... ....... ....... ......227
➤6.2.2 Memory-M apped Regi sters....................... ..................... ........................ ..................... ..........231
➤6.2.3 Register Encod in g s... ...................................... ............................................................... .......235
➤6.2.4 Reset States... ............................................................................................................ ...........249
➤6.2.5 RB Field Encoding ................................................................................................................252
➤7 Ball Grid Array Information ..........................................................................................................................2 53
➤7.1 208-Ball PBGA Package........................... ................... .............. ................... ................... ..................253
➤8 Signal Descriptions......................................................................................................................................256
➤8.1 Sy ste m Inte r face........................................................................................................................ ........257
➤8.2 BIO Interfac e................................................................................................................ ......................257
➤8.3 System and Extern al Memory Interfa ce.............................................................................................2 57
➤8.4 SIU0 Interface....................................................................................................................................2 60
➤8.5 SIU1 Interface....................................................................................................................................2 61
➤8.6 PIU Interface......................................................................................................................................262
➤8.7 JTAG0 Test Interface.........................................................................................................................2 63
➤8.8 JTAG1 Test Interface.........................................................................................................................2 63
➤8.9 Power and Ground.......... ....... ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ..................264
➤9 D e vice Characte ristics..... ............................................................................................................................265
➤9.1 Absolute Maxi mum Rat ings ...............................................................................................................265
➤9.2 Handling Precau tions. ................................ . ................................ . ......................................................265
➤9.3 Recom me nded Operating  Condit ions. . ................................ . ................................ . ............................265
➤9.3.1 Packa ge T hermal Considerations.........................................................................................2 66
➤10 Electrical Characteristics and Requiremen ts........................ ................ . ................ ..................... .................267
➤10.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs...............................268
➤10.1.1 M aintenance of Valid Logic Levels on the SEMI Interface....................................................268
➤10.1.2 M aintenance of Valid Logic Levels on the PIU Interface.................. ................... ..................269
➤10.2 Analog Power Supply Decoupling......................................................................................................2 70
➤10.3 Power  Dissipat ion .. ................... .........................................................................................................271
➤10.3.1 Internal Power Dissipation ....................................................................................................2 71
➤10.3.2 I/O Power Dissipation............................................................................................................272
➤10.4 Power Supply Sequencing Issues......................................................................................................2 73
➤10.4.1 Powerup Sequence.................................................................... ...........................................273
➤10.4.2 P owerdown S equence ................ ..................... ........................ ..................... ........................273
➤11 Timing Characteristics and Requiremen ts....................... . ............. ................... . ............. .............................274
➤11.1 Phase - L o ck L oop................................................................................... ......................... ...................275

Table of Contents (continued)

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➤11.2 Wake-Up Latency...............................................................................................................................276

➤11.3 DSP Clock Gene ration.......................................................................................................................277

➤11.4 Reset Circuit... ....................................................................................................................................278

➤11.5 Reset Syn ch r o n ization... ....................................................................................................................279

➤11.6 JTAG..................................................................................................................................................280

➤11.7 Interrupt and Trap..............................................................................................................................281

➤11.8 Bit I/O.................................................................................................................................................282

➤11.9 System and Exte rnal Memory Interface.............................................................................................2 83

➤11.9 .1 Asynchr o nous In te rface .. .................................................................................................... ..284

➤11.9.2 Synchronous Interface................................................. .............. ................... ........................287

➤11.9.3 ERDY Interface.....................................................................................................................289

➤11.10 PIU.....................................................................................................................................................290

➤11.11 SIU.....................................................................................................................................................294

➤12 Appendix—Naming Inconsistencies............................................................................................................3 04

➤13 Outline Diagram— 208-Ball PBGA................. ................... . ................ ..................... ..................... ................305

➤14 Index............................................................................................................................................................306

List of Figures
Figure Page
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April 2002 DSP16411 Digital Signal Processor
Agere  Systems In c. Agere Systems—P ropri etary 7
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➤Figure 1. DS P16411 B lock Diagram..................... ..................... ........................ ..................... ..........................15
➤Figure 2. DS P16000 Core Bl ock Diagram..................... ........................ ..................... ........................ ..............21
➤Figure 3. CORE 0 and CORE1 In terrupt Logic Block Diagram ......... ........................ ..................... ...................26
➤Figure 4. IMUX Block Diagra m.........................................................................................................................29
➤Figure 5. Fun ctiona l Timing for INT[3:0] and TRAP. ............................................ . ................................ . ...........34
➤Figu r e 6. X- Memo ry Ma p........................................................................................................... .......................40
➤Figu r e 7. Y- Memo ry Ma p s.......................................................................................................... ......................41
➤Figure 8. Z-M emory Maps ................................................................................................................................42
➤Figu r e 9. Internal I/O Memory  Map......................................................................................................... ..........43
➤Figure 10. Interleave d Internal TPRAM..............................................................................................................44
➤Figure 11. Example Memory Arrangement............ .. ....... .......... .. ....... ....... .......... .. ....... ....... ..... ....... ....................44
➤Figure 12. Interprocessor Communicatio n Logic in MG U0 and MGU1 ..............................................................46
➤Figure 13. Timer Block Diagram.........................................................................................................................54
➤Figure 14. TCS  14-Pin Connect or ....... ..................... ........................ ..................... ........................ .....................58
➤Figure 15. J CS 20-Pin Conne ctor. ..................... ........................ ..................... ..................... ...............................59
➤Figure 16. HDS 9-Pin Conn ector........................................................................................................................60
➤Figure 17. Typical  Multiprocessor JTA G Connection with Single Scan Chain ........... ..................... ...................61
➤Figure 18. DMAU Interconnections and Channels ......... .......... .. ....... ....... .......... .. ....... ....... ..... ....... ....... .............65
➤Figure 19. DMAU Block Diagram ........................................................................................................................66
➤Figure 20. One-Di me nsional Data Structure  for B uffe ring 
n
 Channels.......... ....... ....... ....... ..... ....... ....... ..... ....... .83
➤Figure 21. Two-Di mensional Data Structure for Double-Buffering 
n
 Channels..................................................84
➤Figure 22. Memory-to-Memory Block Transfer...................................................................................................86
➤Figure 23. Example of a Two-Dimensional Double-Buffered Data Structure ................... ....... ....... ..... ....... ....... .95
➤Figure 24. E xampl e of One-Dimensional Data Structure.................. ..................... . ............. ................... . ...........97
➤Figure 25. Memory-to-Memory Block Transfer...................................................................................................99
➤Figure 26. SEMI Interface Block Diagram ........................................................................................................100
➤Figu r e 27. As yn ch r o nous  Memor y Cycles........................................................................................................117
➤Figure 28. Asynchronous Memory Cycles (RSETUP = 1, WSETUP = 1) ........................................................1 18
➤Figure 29. Asynchronous Memory Cycles (RHOLD = 1, WHOLD = 1) ............................................................1 19
➤Figure 30. Us e of ERDY Pin to Extend Asynchronous Accesses. ............. ........................ ..................... ..........120
➤Figure 31. Exampl e of Using the ERDY Pin.....................................................................................................121
➤Figure 32. 32-Bit External Interface with 16-Bit Asynchronous SRAMs ... .......... .. ....... ....... .......... .. ....... .......... .123
➤Figure 33. 16-Bit External Interface with 16-Bit Asynchronous SRAMs ... .......... .. ....... ....... .......... .. ....... .......... .123
➤Figure 34. Synchronous Memory Cycles...................... ....... ....... ..... ....... .. .......... ....... ....... .. .......... ....... .............125
➤Figure 35. 16-Bit External Interface with 16-Bit Pipelined, Synchronous 
ZBT
 SRAMs .... ................................126
➤Figure 36. 32-Bit External Interface with 32-Bit Pipelined, Synchronous 
ZBT
 SRAMs .... ................................127
➤Figure 37. 32-Bit PA Register Host and Core Access......................................................................................138
➤Figure 38. P IU Functional Timing for a Data Read and Write Operation...................... ................... . ................144
➤Figure 39. P IU Functional Timing for a Register Read and Write Operation......... . ............. ........................ .....146
➤Figure 40. SIU Block Dia gram..........................................................................................................................1 55
➤Figure 41. Pin Conditioning Logic,  Bit Clock Selection Logic, and Frame Sync S elect ion Logic .....................1 58
➤Figure 42. Default Serial Input Functional Timing..................... ....... .. ....... .......... .. ....... ....... .......... .. ..................159
➤Figure 43. Default Serial Output Fu nctional Timing..........................................................................................160
➤Figure 44. Frame Sync to Data Delay Timing ...................................................................................................1 63
➤Figure 45. Clock  and Frame Sync Generat ion with External Clock and Synchronization
(AG EXT = AGSYNC = IFSA = IFSK = 1 and Timing Requires No Resynchronization)..................1 66
➤Figure 46. Clock  and Frame Sync Generat ion with External Clock and Synchronization
(AGEXT = AGSY NC = IFSA = IFSK = 1 and Timing Requires Resynchroni zation)........................167
➤Figure 47. Basic Frame Structure.....................................................................................................................168
➤Figure 48. Basic Frame Structure with Idle Time..............................................................................................1 69
➤Figure 49. Channel Mode on a 128-Channel Frame ....... ........................ ..................... ........................ ............171

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DSP16411 Digital Signal Processor April 2002
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➤Figure 50. S ubframe and Chann el Selection in Channel  Mode....................... ........................ ..................... ....176
➤Figure 51. Genera ting Interrupts on Subframe Boundari es. ...................................................... . ......................178
➤Figu r e 52. ST- Bu s Single-Ra te  Cloc k................ ................................................................................. ..............183
➤Figure 53. ST-Bus Double-Rate Clock .............................................................................................................1 83
➤Figure 54. Internal  Clock Selection Logic........... ........................ ..................... ........................ .........................200
➤Figure 55. Clock Synthesizer (PLL) Block Diagram ..........................................................................................201
➤Figure 56. P ower Mana gem ent and Clock Distribution ..................... . ............. ........................ .........................206
➤Figure 57. Interpretation of the Instru ction Set Summary Table.......................................................................2 11
➤Figure 58. DS P1 6411 Program-Ac ces sible Registers for Each Core................... ..................... .......................2 28
➤Figure 59. Example Memory-Mapped Registers........... ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... .. .......... .......231
➤Figure 60. 208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View).......... .......... .. .....253
➤Figure 61. DS P1 6411 Pinout by Interface.... ............. ........................ ..................... ........................ ..................256
➤Figure 62. Analog Supply Dec oupl ing .. . ................................ . ................................ . .........................................270
➤Figure 63. Reference Voltag e Level for Timing Characteristics and Requ irements for Inputs and Ou tputs ....274
➤Figure 64. I/O Clock Timing Dia gram...............................................................................................................277
➤Figure 65. P owerup and Device Res et Timing Diagram . ............. ........................ ..................... .......................278
➤Figure 66. Reset Synchronization Timi ng.........................................................................................................2 79
➤Figure 67. JTAG I/O Timing Diagram ..............................................................................................................280
➤Figure 68. Interrupt and Trap Tim ing Diagram .................................................................................................2 81
➤Figure 69. Write Out put s Followed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristic s...2 82
➤Figure 70. Enable and Write Strobe Transition Tim ing. ...................................................... ..............................283
➤Figure 71. Timin g Diagram for EREQN and EACKN........................................................................................2 84
➤Figure 72. A synchrono us Read Timing Diagram (RHOLD = 0 and RSET UP  = 0).................... .......................2 85
➤Figure 73. Asynchronous W rite Timing Diagram (WHOLD = 0, WSETUP = 0) ................................................286
➤Figure 74. Synchronous Read Timing Diagram (Read-Read-Write Sequence).............. .. ....... ....... ..... ....... .....287
➤Figure 75. Synchronous Write Timing Diagram........ .......... ....... .. .......... ....... ....... .. .......... ....... .. ....... .................288
➤Figure 76. ERDY Pin Timin g Diagram..............................................................................................................289
➤Figure 77. Host Data Write to PDI Timing Dia gram..........................................................................................290
➤Figure 78. Host Data Read from PDO Timing Diagram............... .......... .. ....... ....... .......... .. ....... ....... ..... ....... .....291
➤Figure 79. Hos t Register Write (PAH, PAL, PCON, or  HSCRATCH) Timing Diagram.....................................292
➤Figure 80. Hos t Register Read (PAH, PAL, PCON, or DSCRATCH) Timing D iagram .....................................293
➤Figure 81. SIU Passive F rame and Chan nel Mode Input Timing Diagram.......................................................294
➤Figure 82. S IU Passive Frame Mode Out put Timing Diag ram . ..................... ..................... ........................ ......295
➤Figure 83. S IU Passive Channel Mode Out put  Timing Diagram .. ........................ ..................... .......................2 96
➤Figure 84. SCK External Clock Source Input Timing Diagram.........................................................................297
➤Figure 85. S IU Active Frame and Channe l Mode Input Timing Diagram ... ............. ........................ ..................2 98
➤Figure 86. SIU Active Frame Mod e Output Ti ming Diagram ............................................................................300
➤Figure 87. S IU Active Channel Mode  Output Timing Diagram. ..................... ..................... ........................ ......301
➤Figure 88. ST-Bus 2x Input Timing D iagram ....................................................................................................302
➤Figure 89. ST-Bus 2x Output T iming Diagra m..................................................................................................3 03

List of Tables
Table Page
Agere  Systems In c. Agere Systems—P ropri etary 9
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April 2002 DSP16411 Digital Signal Processor
➤Table 1. DSP16411 B lock Diagram Legend...................... ..................... ........................ ..................... ........... 16
➤Table 2. DSP16000 Core Bloc k Diagram Legend......................... ..................... ........................ ................... . 2 2
➤Table 3. State of Device Output and Bidirectional Pins During and After Res et ....... ........................ ............. 24
➤Table 4. Hardware Interrupts.......................................................................................................................... 27
➤Table 5. imux (Interrupt Multiplex Control) Register...................................................................................... 28
➤Table 6. Global Disabling and Enabling  of Hardware Interrupts ............. ........................ ..................... ........... 30
➤Table 7. inc0 and inc1 (Interrupt Control) Registers 0 and 1...................... ..................... ........................ ...... 31
➤Table 8. ins (Interrupt Status) Register.......................................................................................................... 32
➤Table 9. Interrupt and Trap Vector Table ....................................................................................................... 33
➤Table 10. psw1 (Processor Status Word 1) Register....................................................................................... 35
➤Table 11. DSP16411 Me mory Component s................... . ................ ..................... ........................ .................... 38
➤Table 12. signal Register................................................................................................................................. 47
➤Table 13. Full-Duplex Data Transfer Code Through Core-to-Core Message Buffer. ..................... .................. 48
➤Table 14. DMAU MMT Channel Interrupts.............. ................................. ............... ........... .............................. 49
➤Table 15. DMA Intracore and Intercore Transfers Example..................... ........................ ..................... ........... 49
➤Table 16. sbit (BIO Status/Control) Register ................................................................................................... 50
➤Table 17. cbit (BIO Control) Reg ister ............................................................................................................... 51
➤Tabl e 18. BIO Oper a tions................................................................................................................................. 52
➤Table 19. BIO Flags.......................................................................................................................................... 52
➤Table 20. timer〈0,1〉c (T I MER〈0,1〉 Control) Register..................................................................................... 55
➤Table 21. timer〈0,1〉 (TIMER〈0,1〉 Running Count) Register.......... ..................... ........................ .................... 56
➤Table 22. ID (JTAG Identification) Reg ister...................................................................................................... 57
➤Table 23. TCS 14-Pin So cket Pinout................................................................................................................ 58
➤Table 24. JCS 20-Pin Sock et Pinout................................................. . ................................ . ............................. 59
➤Table 25. HDS 9-Pin, Su bminiature, D-Type  Plug  Pinout............................................................................. ... 60
➤Table 26. JTAG0 Boundary-Scan Regist er . . ............................................ ........................................................  62
➤Table 27. JTAG1 Boundary-Scan Regist er . . ............................................ ........................................................  63
➤Table 28. DMAU Channel Assign men t.. ................ ..................... ........................ ..................... ......................... 64
➤Table 29. DMAU Memo ry-Mappe d Registers ........................... ..................... ..................... .............................. 67
➤Table 30. DSTAT (DMAU Status) Register....................................................................................................... 69
➤Table 31. DMCON0 (DMAU Master Control 0) Register.................................................................................. 71
➤Table 32. DMCON1 (DMAU Master Control 1) Register.................................................................................. 72
➤Table 33. Colle ctive Designa tio ns Used in Tab le 34........................................................................................ 73
➤Table 34. CTL〈0—3〉 (SWT〈0—3〉 Control) Registers...................................................................................... 74
➤Table 35. Colle ctive Designa tio ns Used in Tab le 36........................................................................................ 76
➤Table 36. CTL〈4—5〉 (MMT〈4—5〉 Con trol) Registers .....................................................................................  76
➤Table 37. SADD〈0—5〉 and DADD〈0—5〉 (Channels 0—5 Source and Destination Address) Registers........ 77
➤Table 38. SCNT〈0—3〉 (SWT〈0—3〉 Source Count er) Registers............. ........................ ..................... ........... 78
➤Table 39. SCNT〈4—5〉 (MMT〈4—5〉 Source Counter) Registers..................................................................... 78
➤Table 40. DCNT〈0—3〉 (SWT〈0—3〉 Destination Counter) Registers .................. ................... . ............. ........... 79
➤Table 41. DCNT〈4—5〉 (MMT〈4—5〉 Destination Counter) Registers........... ..................... ........................ ...... 79
➤Table 42. LIM〈0—3〉 (SWT〈0—3〉 Limit) Regi sters .......................................................................................... 80
➤Table 43. LIM〈4—5〉 (MMT〈4—5〉 Limit) Registers..........................................................................................  80
➤Table 44. SBAS〈0—3〉 (SWT〈0—3〉 So urce  Base Address) Registers ........................................................... 81
➤Table 45. DBAS〈0—3〉 (SWT〈0—3〉 Destination Base Address) Registers..................................................... 81
➤Table 46. STR〈0—3〉 (SWT〈0—3〉 Stride) Registers........................................................................................ 82
➤Table 47. RI〈0—3〉 (SWT〈0—3〉 Reindex) Registers ....................................................................................... 82
➤Table 48. SWT-Specific Memory -Mapped Regist ers ............... ..................... ..................... ........................ ..... . 8 8
➤Table 49. MMT-Spe cific Memory-Mapped Registers...................... ..................... ........................ .................... 91
➤Table 50. DMAU Interrupts............................................................................................................................... 92
➤Table 51. Overview of SEMI Pi ns................................................................................................................... 101

List of Tables (continued)
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DSP16411 Digital Signal Processor April 2002
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➤Table 52. Configuration Pins for the SEMI External Interface........................................................................ 102
➤Table 53. Asynchronous Memory Bus Arbi tration Pins.................................................................................. 103
➤Table 54. Enable and Strobe Pins for the SEMI External  Interface... ................................ . ............................ 104
➤Table 55. ECKO Output Clock Pin Configuration..................................................................................... ...... 105
➤Table 56. Address and Data Bus Pins for the SEMI External Interface ......................................................... 106
➤Table 57. 16-Bit External Bus Configuration ....................................................................................... ........... 109
➤Table 58. 32-Bit External Bus Configuration ....................................................................................... ........... 109
➤Table 59. SEMI M emory-Mapped R egisters ............................................................................................ ...... 110
➤Table 60. ECON0 (External Control 0) Register............................................................................................. 111
➤Table 61. ECON1 (External Control 1) Register............................................................................................. 112
➤Table 62. ECKO Output Clock Pin Configuration..................................................................................... ...... 113
➤Table 63. EXSEG0 (CORE0 External  X Se gment Address Extension) R egister........................................... 114
➤Table 64. EXSEG1 (CORE1 External  X Se gment Address Extension) R egister........................................... 114
➤Table 65. EYSEG0 (CORE0 External  Y Se gment Address Extension) R egister........................................... 115
➤Table 66. EYSEG1 (CORE1 External  Y Se gment Address Extension) R egister........................................... 115
➤Table 67. System Bus Minimum Access Times ............................................................................................ . 128
➤Table 68. Access Time Per SEMI Transaction, Async hronous Interface, 32-Bit Data Bus........... ................. 133
➤Table 69. Access Time Per SEMI Transaction, Async hronous Interface, 16-Bit Data Bus........... ................. 133
➤Table 70. Access Time Per SEMI Transaction, Synchronous  Interface, 32-Bit Data Bus . ........................ ..... 133
➤Table 71. Access Time Per SEMI Transaction, Synchronous  Interface, 16-Bit Data Bus . ........................ ..... 133
➤Table 72. Example Average Acce ss Time Per SEMI Transaction, 32-Bit Data Bus.............. ..................... . .. 134
➤Table 73. Example Average Acce ss Time Per SEMI Transaction, 16-Bit Data Bus.............. ..................... . .. 134
➤Table 74. PIU Registers................................................................................................................................. 135
➤Table 75. PCON (PIU Control) Register......................................................................................................... 136
➤Table 76. PDI (PIU Data In) Register......................................................................................................... .... 137
➤Table 77. PDO (PIU Data Out) Register......................................................................................................... 137
➤Table 78. HSCRATCH (Host Scra tch) Register............................................................................................. 137
➤Table 79. DSCRATCH (DSP Scratch) Register............................................................................................. 137
➤Table 80. PA (Paralle l Address) Register...................................................................................................... . 138
➤Table 81. PIU External Inte rface.................................................................................................................... 139
➤Table 82. Enable and Strobe Pins..................... . ..................................... . ................................ . ..... ................ 140
➤Table 83. Address and Data Pins...................................................................................................... ............. 141
➤Table 84. Flags, Interrupt, and Ready Pins.............. ........................ ..................... ........................ ................. 142
➤Table 85. Summary of Host Commands ......... ..................... ........................ ..................... ............................. 147
➤Table 86. Status/Control/Address Register Read Commands ... .......... ....... ....... .. .......... ....... .. ....... .......... ...... 148
➤Table 87. Status/Control/Address Regist er Write Commands ......... . ............. ........................ ..................... ... 148
➤Table 88. Memory Read Comma nds. ..................... ..................... ........................ ..................... ........... ........... 149
➤Table 89. Memory Write Commands .............................................................................................................. 151
➤Table 90. SIU External Inte rface.................................................................................................................... 156
➤Table 91. Control Register Fields for Pin Conditioning, Bit Clock Selection, and Frame Sync Selection . ..... 157
➤Table 92. A Summa ry of Bit Clock and Fra me Sync Control Register Fields................................................. 164
➤Table 93. Examples of Bi t Clock and Frame Sync Control Register Fields.................................................... 165
➤Table 94. Subframe Definition...................................................................................................... .................. 172
➤Table 95. Location of Control Fields Used i n Channel M ode.................. ........................ ..................... .......... 174
➤Table 96. Description of Control Fields Used in Channel Mode... ................ ..................... ........................ ..... 174
➤Table 97. Subframe Selection...................................................................................................... .................. 175
➤Table 98. Channel Activation Within a Selec ted Subfram e................................... . ..................................... ... 175
➤Table 99. Channel Masking Wi thin a Selected Su bframe................................................. . ............................ 175
➤Table 100. Control Register and Field Configuration for ST-Bus Interface ... .. ....... ..... ....... ....... ....... ..... ....... .... 181
➤Table 101. Control Register and Fields That Are Configured as Required for ST-Bus Interface................ ..... 182
➤Table 102. SIU Registers ...................... ..................... ................... . ................ ..................... ...... ....................... 184

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➤Table 103. SCON0 (SIU Input/Output  General  Control) Register................... ..................... ........................ .... 185
➤Table 104. SCON1 (SIU Input Frame Control) R egister .................................................................................. 186
➤Table 105. SCON2 (SIU Output F rame Control) Register................................................................................ 187
➤Table 106. SCON3 (SIU Input/Output Subframe Contro l) Register ................................................................. 188
➤Table 107. SCON4 (SIU Input Even Subframe Valid Ve ctor Contro l) Register................................................ 189
➤Table 108. SCON5 (SIU Input Odd Subframe Valid Vector Control) Register................................................. 189
➤Table 109. SCON6 (SIU Output Even Subframe Valid Vector Control) Register............................................. 190
➤Table 110. SCON7 (SIU Output O dd Subframe Valid Vector Control) Register.............................................. 1 90
➤Table 111. SCON8 (SIU Output Even Subframe Mask Vector Control) Register............................................ 190
➤Table 112. SCON9 (SIU Output O dd Subframe Ma sk Vector Control) Register .............................................. 190
➤Table 113. SCON10 (SIU Input/Output Genera l Co ntrol ) Register.................................................................. 1 91
➤Table 114. SCON11 (SIU Inpu t/Output Active Cl ock Control) Register ........................................................... 194
➤Table 115. SCON12 (SIU Input/Output Active Frame Sync Control) Registe r................................................. 195
➤Table 116. SIDR (SIU Input Data) Register...................................................................................................... 196
➤Table 117. SODR (SIU Output Data) Register................................................................................................. 196
➤Table 118. STAT (SIU Input/Ou tput General Statu s) Register........................ ..................... ........................ .... 197
➤Table 119. FSTAT (SIU Input/Output Frame Status) Register ......... .. ....... .......... .. ....... ....... .......... .. ....... .......... 197
➤Table 120. OCIX〈0—1〉 and ICIX〈0—1〉 (SIU Output and Input Channel Index) Registers ........................ ..... 198
➤Table 121. OCIX〈0—1〉 (SIU Output Channel Index) Registers...................................................... ................. 198
➤Table 122. ICIX〈0—1〉 (SIU Input Channel Index) Registers .................... ..... ....... ....... ....... ..... ....... ....... ..... ..... 199
➤Table 123. Source Clock Selection .................... ........................ ..................... ..................... ............................ 200
➤Table 124. pllcon (Phase-Lock Loop Control) Register ................................................................................... 202
➤Table 125. pllfrq (Phase-Lo ck Loop Frequenc y Control) Register...................... ..................... ....................... 202
➤Table 126. pllfrq1 (Phase-Lock Loop Frequency Control 1) Register ......................... ................... ................. 202
➤Table 127. plldly (Phase-Lock Loop Delay Control) Register............ ....... .......... .. ....... ....... .......... .. ....... .......... 202
➤Table 128. ECKO Out put Clock Pin Configuration................ ..................... ........................ ......................... ..... 204
➤Table 129. Wake-Up Latency  and Power Consumpt ion for Low-Power Standby Mode ........... ....................... 207
➤Table 130. Core Boot-Up After Res et. ..................... ..................... ................... . ............. .................. ................. 208
➤Table 131. Content s of IROM0 and IROM 1 Boot ROM s...................................................... . ........................... 208
➤Table 132. DSP16411 Instruc tion Groups................. . ................ ................ . ................ ..................... .... ............ 210
➤Table 133. Instruction Set Summary .... ................... ..................... ........................ ..................... ....................... 212
➤Table 134. Notation Conventions for Instruction Set Descriptions ... ....... ....... ....... ..... ....... .. .......... ....... ....... ..... 218
➤Table 135. Overall Replacement Table....................................... .............. ................... ................... ... .............. 219
➤Table 136. F1 Instruction Syntax......................................................... . ................................ . ........................... 222
➤Table 137. F1E Function S tatement  Syntax........................................................... . ......................................... 224
➤Table 138. DSP16411 Condi tional Mne monics..................... ..................... ........................ ......................... ..... 226
➤Table 139. Program-Acc essible (Register-Ma pped) Registers by Type, Listed Alphabetica lly. ....................... 229
➤Table 140. DMAU Memo ry-Mappe d Registers . ..................... ..................... ................... . ................ .................. 232
➤Table 141. SEMI Memory-Mapped Registers .......... ................... .............. ................... ................... ................. 233
➤Table 142. PIU Registers .. ..................... ................... . ................ ..................... ..................... ............................ 234
➤Table 143. SIU Memory-Mapped Regi s ters................... ..................... ................... . ............. ............................ 234
➤Table 144. alf (AWAIT Low-Power and F lag) Register.................................................................................... 235
➤Table 145. auc0 (Arithmetic Unit C ontrol 0) Register ....................................................................................... 236
➤Table 146. auc1 (Arithmetic Unit C ontrol 1) Register ....................................................................................... 237
➤Table 147. cbit (BIO Contro l) Register ........................................................................................................... .. 238
➤Table 148. cloop (Cac h e Loop)  Regi ster.................... ..................................................................................... 239
➤Table 149. csave (Cache Save) Register........................................................................................................ 239
➤Table 150. cstate (Cache State) Register........................................................................................................  239
➤Table 151. imux (Interrupt Multiplex Control) Register.................................................................................... 240
➤Table 152. ID (JTAG〈0—1〉 Ide ntification ) Registers........................................................................................  241
➤Table 153. inc0 and inc1 (Interrupt Control) Registers 0 and 1...................... . ............. ........................ ........... 241

List of Tables (continued)
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➤Table 154. ins (Interrupt Sta tus) Register........................................................................................................ 242
➤Table 155. mgi (Core-to-Core Message Input) Register....... ..... .. ..... ..... .. ..... .. ..... .. ..... ..... .. ..... ..... .... ..... ..... .. .... 242
➤Table 156. mgo (Core-to-Core Me ssage  Output) Register.............................................................................. 242
➤Table 157. pid (Processor Ide ntification) Register........................................................................................... 242
➤Table 158. pllcon (Phase-Lock Loop Control) Register................................................................................... 243
➤Table 159. pllfrq (Phase-Lo ck Loop Frequenc y Control) Register........... . ............. ........................ ................. 243
➤Table 160. pllfrq1 (Phase-Lock Loop Frequency Control 1) Register ............................................. ................ 243
➤Table 161. plldly (Phase-Lock Loop Delay Control) Register...... .......... .. ....... ....... ..... ....... ....... ....... ..... ....... .... 243
➤Table 162. psw0 (Processor Statu s Word 0) Register ..................................................................................... 244
➤Table 163. psw1 (Processor Status Word 1) Register..................................................................................... 245
➤Table 164. sbit (BIO Status/Control) Register ................................................................................................. 246
➤Table 165. signal (Core-to-Core Signal) Register ........................................................................................... 246
➤Table 166. timer0c and timer1c (TIMER〈0,1〉 Control) Registers................................................................... 247
➤Table 167. timer0 and timer1  (TIMER〈0,1〉 Running Count) Registers .................................. ............ ............ 248
➤Table 168. vsw (Viterbi Support Word) Register.............................................................................................. 248
➤Table 169. Core Register States After Rese t—40-Bit Registers...................................................................... 249
➤Table 170. Core Register States After Reset—32-B it Registers.... ................ ..................... ........................ ..... 249
➤Table 171. Core Register States After Reset—20-B it Registers.... ................ ..................... ........................ ..... 250
➤Table 172. Core Register States After Reset—16-B it Registers.... ................ ..................... ........................ ..... 250
➤Table 173. Off-Core (Peripheral) Register Reset V alue s.............. ........................ ..................... ...................... 250
➤Table 174. Memory-M apped Regi ster Reset Values—32-Bit Registe rs . ................ ........................ ................. 251
➤Table 175. Memory-M apped Regi ster Reset Values—20-Bit Registe rs . ................ ........................ ................. 251
➤Table 176. Memory-M apped Regi ster Reset Values—16-Bit Registe rs . ................ ........................ ................. 251
➤Table 177. RB Field................. ..................... ........................ ..................... ........................ .... ........................... 252
➤Table 178. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol....................... ................... .... 254
➤Table 179. Absolute Maximum Ratings....... ....... ....... .......... .. ....... .......... .. ....... ....... .......... .. ....... ....... ................ 265
➤Table 180. Minimum ESD Voltage Thresholds...................... ................... .............. ................... ....................... 265
➤Table 181. Recom me nded Operating Conditions .... ........................................................... ............................. 265
➤Table 182. Packag e Therm al Consideration s . .......................................... . ................................ . ............. ........ 266
➤Table 183. Electrical Characteristics and Requirements....... ..... ....... ....... ..... ....... ....... ....... ..... ....... .. ........ ........ 267
➤Table 184. Effect of EYMODE  Pin and BHED IS Field .. ...................................................... . ............................ 268
➤Table 185. Typical Internal Power Dissipation at 1.0 V  and 240 MHz . .................. ..................... ...................... 271
➤Table 186. Typical I/O Power Dissipation at 3.3 V and 240 MHz......................... ....... ....... ..... ....... ....... ....... .... 272
➤Table 187. Reference Vol tage Leve l for Timing Characteristics and Requirem ents for Inputs and Outputs ... 274
➤Table 188. PLL Requirement s...................... . ............. ........................ ..................... ................... ...................... 275
➤Table 189. Wake-Up Latency..................... ................ . ................ ..................... ........................ ........................ 276
➤Table 190. Timing Requirements for Input Clock....................... .. .......... ....... .. ....... .......... ....... .. ....... ................ 277
➤Table 191. Timing Characteristics for Output Clock....... ....... ....... .......... .. ....... ....... ..... ....... ....... ....... ..... ........... 277
➤Table 192. Timing Requirements for Powerup and Device Reset................. .. ....... .......... ....... .. ....... .......... .. .... 278
➤Table 193. Timing Characteristics for Device Reset ......... .... ..... .. ..... ..... .. ..... .. ..... .. ..... ..... .. ..... .. ..... .. ..... ........... 278
➤Table 194. Timing Requirements for Reset Synchronization Timing ................... .. .......... ....... ....... .. .......... ...... 279
➤Table 195. Timing Requirements for JTAG I/O..................... ....... .......... ....... .. ....... .......... .. ....... ....... ..... ........... 280
➤Table 196. Timing Characteristics for JTAG I/O......................... .. .......... ....... ....... .. .......... ....... .. ....... ................ 280
➤Table 197. Timing Requirement s for Interrupt and Tr ap .. ............. ........................ ..................... ...................... 281
➤Table 198. Timing Requirement s for BIO Input Read ................... ........................ ..................... ...................... 282
➤Table 199. Timing Characteristics for BIO Output............... ....... .. .......... ....... .. ....... .......... ....... .. ....... ................ 282
➤Table 200. Timing Characteristics for 
ERWN 
and Memory En ables.... ......... ................................................... 283
➤Table 201. Timing Requirement s for EREQN . ..................... ..................... . ............. ................... . ..................... 284
➤Table 202. Timing Characteristics for EACKN and SEMI Bus Disable .... ....... ..... ....... ....... ..... ....... ....... ....... .... 284
➤Table 203. Timing Requirement s for Asynchronous Me mory Read Operation s................. ........................ ..... 285
➤Table 204. Timing Characteristics for A sy nchronous M emo ry Read Ope rations................ ................... . ......... 285

List of Tables (continued)

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➤Table 205. Timing Characteristics for A sy nchronous M emo ry Write Operations. ..................... . ............. ......... 286

➤Table 206. Timing Requirement s for Synchronous Read Op erations......................... ..................... ................ 287

➤Table 207. Timing Characteristics for Synchronous Read Operations................ ....... .. ....... .......... ....... .. .......... 287

➤Table 208. Timing Characteristics for Synchronous Write Operations................ .. ....... ....... ..... ....... ....... .......... 288

➤Table 209. Timing Requirement s for ERDY Pin.. ............. . ................ ..................... ........................ .................. 289

➤Table 210. Timing Requirement s for PIU Data Write Operations . . ............. ........................ ..................... ......... 2 90

➤Table 211. Timing Characteristics for PIU Data Write Operations........ .... ..... ..... .. ..... .. ..... .. ..... ..... .. ..... .. ..... ..... 290

➤Table 212. Timing Requirement s for PIU Data Read Operations ..... ..................... ........................ .................. 291

➤Table 213. Timing Characteristics for PIU Data Read Operations................. ....... ....... ..... ....... ....... ....... ..... ..... 291

➤Table 214. Timing Requirement s for PIU Register Writ e Operations................... ..................... ....................... 292

➤Table 215. Timing Characteristics for PIU Register Write Operations .... .. .......... ....... ....... .. .......... ....... .. .......... 292

➤Table 216. Timing Requirement s for PIU Register Read Operations ..................... . ............. ........................ .... 293

➤Table 217. Timing Characteristics for PIU Register Read Operations.................. ....... ....... ..... ....... ....... .......... 293

➤Table 218. Timing Requirements for SIU Passive Frame Mode Input ........... ....... ..... ....... ....... ....... ..... ....... ..... 294

➤Table 219. Timing Requirements for SIU Passive Channel Mode Input............... ....... ....... .......... .. ....... .......... 294

➤Table 220. Timing Requirements for SIU Passive Frame Mode Output ... ..... ....... ....... ..... ....... ....... ....... ..... ..... 295

➤Table 221. Timing Characteristics for SIU Passive Frame Mode Output..................... ....... ..... ....... ....... .......... 295

➤Table 222. Timing Requirements for SIU Passive Channel Mode Output ........................ .. .......... ....... ....... ..... 296

➤Table 223. Timing Characteristics for SIU Passive Channel Mode Output....................... .. .......... ....... .. .......... 296

➤Table 224. Timing Requirements for SCK External Clock Source............ .......... ....... .. ....... .......... .. ....... .......... 297

➤Table 225. Timing Requirements for SIU Active Frame Mode Input.......................... ....... .. .......... ....... ....... ..... 298

➤Table 226. Timing Characteristics for SIU Active Frame Mode Input............. ....... ....... ..... ....... ....... ....... ..... ..... 298

➤Table 227. Timing Requirements for SIU Active Channel Mode Input...... ..... ....... ....... ....... ..... ....... ....... ..... ..... 299

➤Table 228. Timing Characteristics for SIU Active Channel Mode Input............... .. ....... ....... ..... ....... ....... .......... 299

➤Table 229. Timing Requirements for SIU Active Frame Mode Output ................ .. ....... ....... ..... ....... ....... .......... 300

➤Table 230. Timing Characteristics for SIU Active Frame Mode Output................. ....... ....... .......... .. ....... .......... 300

➤Table 231. Timing Requirements for SIU Active Channel Mode Output.................... .. ....... .......... ....... .. .......... 301

➤Table 232. Timing Characteristics for SIU Active Channel Mode Output................... ....... ....... ....... ..... ....... ..... 301

➤Table 233. ST-Bus 2x Input Timing Requirement s........................................................ . .................................. 302

➤Table 234. ST-Bus 2x Output Timing Requi reme nts. ........................................................... ............................ 303

➤Table 235. ST-Bus 2x Output Timing Charact eristics .... ..................... ........................ ..................... ......... ....... 303

➤Table 236. Pin Name Inconsistenc ies........................................................ . ..................................... .... ..... ....... 304

➤Table 237. Register Name Inconsistencies............ ....... .. .......... ....... ....... .. .......... ....... .. ....... .......... ................... 304

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14 A gere System s— P rop rietary Agere Systems In c.

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3 Notation Conventions

The following notation conventions apply to this data

sheet. Table 134 on page 218 specifies the notation

conventions for the DSP16000 instruction set.

lower-case Registers that are directly writable or

readable by DSP16411 core i ns truc-

tions are lower-case.

UPPER-CASE Device fla gs, I/O pins, control register

fields, and registers that are not directly

writable or readable by DSP16411 core

instructions are upper-case.

boldface Register name s and DSP16411 core

instructions are printed in boldface

when used in text descriptions.

italics

Document ation variables that are

replaced are printed in ita lics.

courier DSP16411 program examples or

C-language representations are pri nted

in courier font .

[ ] Square bracke ts enclose a range of

numbers that represents multiple bits in

a single register or bus. T he range of

numbers is delimited by a colon. For

example, imux[11:10] are bits 11 and

10 of the program-accessible imux reg-

ister.

〈〉 Angle brackets enclose a list of items

delimited by commas or a range of

items delimited by a dash (—), one of

which is selected if used in an

instruction. Fo r example, SADD〈0—3〉

represents the four memory-mapped

registers SADD0, SADD1, SADD2,

and SADD3, and the general instruc-

tion aTE〈h,l〉=RB can be replaced

with a 0 h = time r0.

4 Hardware Architecture

4.1 DSP16411 Architectural Overview

The DSP16 411 device i s a 16-bit fixed-point program-

mable digital signal processor (DSP). The DSP16411

consi sts of two DSP16000 cores together with on-chip

memory and peripherals. Advanced architectural fea-

tures with an expanded instruction set deliver a dra-

matic increase in performance compared to traditional

DSP architectures for signal coding algorithms . This

increase in performance, together with an efficient

design implementation, results in an extremely cost-

efficient and power-efficient sol ution for wireless and

multimedia applications.

Figure 1 on page 15 shows a block diagram of the

DSP16411.

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April 2002 DSP16411 Digital Signal Processor

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4 Hardware Architecture (continued)

4.1 DSP16411 Architectural Overview (continued)

DSP16411B Block Diagram

Figure 1. DSP 16411 Bl ock Diagra m

YDB YAB XDB XAB

IDB

XAB0

XDB0

YAB0

YDB0

YAB1

YDB1 32 20 32 32 20 32 20

CORE0

SAB

SDB

ZEAB

ZEDB

ZIDB ZIAB

SDB SAB

ZEDB

ZEAB

SDB SAB

32 20

TPRAM0

IROM0

PAB DPI

27 16

PIU SIU0

DMAU DSI0

DSI1

IMUX0

imux

32 MGU0

signal

jiob

BOUNDARY SCAN

JTAG0

TIMER0_0

TIMER1_0

TIMER0_1

TIMER1_1

BIO0

pid 16

HDS0

cbit

PD[15:0] PODS PCSNPIDS

PADD[3:0] PRWN

PRDYMD

POBE PIBF PRDY PINT

SDB

SAB

SIU1

SICK0

SID0

SIFS0

SOCK0

SOD0

SOFS0

SCK0

SICK1

SID1

SIFS1

SOCK1

SOD1

SOFS1

SCK1

ED[31:0]

EA[18:0]

ERAMN

EROMN

EION

ERWN[1:0]

ECKO

EREQN

EACKN

ERDY

EXM

ERTYPE

ESIZE

INT[3:0]

TCK0

TMS0

TDO0

TDI0

TRST0N

CKI

RSTN

TRAP

IO0BIT[6:0] IO1BIT[6:0]

TCK1

TMS1

TDO1

TDI1

TRST1N

INT[3:0]

SEMI

CLK

DDO

DDO DDODSI

DSI

DDO

XABXDBYABYDB

IDB

CORE1

(160K x 16)

MGU1 IMUX1

imux

CLOCK/CONTROL

pllcon

XAB1

XDB1

ZSEGZSEG 4

YDB YAB XDB XAB

ZIDB ZIAB

TPRAM1

(160K x 16)

IROM1

SLM

(2K x 16)

32 20

SDB SAB

32 20

PAB DPI

ESEG[3:0]

16 16

BIO1

SDB SAB

32 20

TO IMUX1

TO HDS1/MGU1 TRAP

ZIABZIDB

sbit cbit

timer1

timer1c timer1

timer1c

timer0

timer0c timer0

timer0c

mgi

mgo mgo

mgi

signal

pid

pllfrq

plldly

jiob

BOUNDARY SCAN

JTAG1

HDS1

KEY: OFF-CORE REGISTER-MAPPED REGISTERS

ACCESSIBLE BY CORE0

sbit

OFF-CORE REGISTER-MAPPED REGISTERS

ACCESSIBLE BY CORE1

pllfrq1

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4 Hardware Architecture (continued)

4.1 DSP16411 Architectural Overview (continued)

Table 1. DSP 16411 Bl ock Diagra m Legend

Symbol Description

BIO〈0—1〉Bit I/O Units. One for each core.

cbit 16-Bit BIO Contro l Regi ster .

CLK Internal Clock Signal.

CORE0 DSP16000 Core— System Master.

CORE1 DSP16000 Core— System Slave.

DDO DMA Data Out. (For transferring data from DMAU to PIU, SIU0, and SIU1.)

DMAU Direct Memory Access Unit.

DPI DMA Parallel In. (For transferring 16-bit data from PIU to DMAU.)

DSI0 DMA Serial Data In Zero. (For transferring data from SIU0 to DMAU.)

DSI1 DMA Seri al Data In One. (For transferri ng data fr om SIU1 to DMAU.)

HDS〈0—1〉Hardware Development System s. One for each core.

ID JTAG Port Identificati on Register Accessible Via the JTAG Port. One for each of t he two JTAG 〈0—1〉

ports.

IDB Internal Data Bus. One for each cor e.

imux 16-Bit IMUX Control Register.

IMUX〈0—1〉Inte rr upt Mult iplexers. O ne for each core; se lects ten interrupts fr om DMAU, SIU0, SIU1, PIU, INT[3:0],

TIMER〈0—1〉, and MGU.

IROM〈0—1〉Inte rnal Read-Only Memori es (one for each core) for Boot and HDS Code.

jiob 32-Bit JTAG Test Register.

JTAG〈0—1〉JTAG Test Ports. One for each core.

mgi 16-Bit Core-t o-Core Message Inp ut Register.

mgo 16-Bi t Core-to-Core Message Output Register.

MGU〈0—1〉Core-t o-Core Messaging Unit. One for eac h core.

PAB 27-Bit Parallel Address Bus. (For DMAU/PIU communications.)

pid 16-Bi t Pro cessor ID Register (CORE0: 0x0 000; CORE1: 0x0001).

PIU Parallel Interface Unit. (16-bit paral lel host int erface.)

pllcon 16-Bi t Phase-Lock Loop Cont rol Register.

pllfrq 16-Bit Phase-Lock Loop Fr equency Control Register.

pllfrq1 16-Bit Phas e-Lock Loop Frequen cy Control 1 Register.

plldly 16-Bi t Phase-Lock Loop Del ay Control Register .

SAB 20-Bit System Address Bus. Addre ss for system bus (S-bus) accesses.

sbit 16-Bit BIO Status/Control Register.

SDB 32-Bit System Dat a Bus. Data for system bus (S-bus) accesses.

SEMI Sys tem and External Memor y Int erface.

signal 16-Bit Si gnal Regis ter for Core-to-Core Communication.

SIU0 Serial Input/Output Unit Zero.

SIU1 Serial Input/Output Unit One.

SLM 2 Kword Shared Local Memory.

timer0 16-Bit Timer Runni ng Count Register for TIMER0.

TI MER 0_0 Pro g ram ma ble Tim er 0 fo r CO RE 0.

TI MER 0_1 Pro g ram ma ble Tim er 0 fo r CO RE 1.

timer0c 16-Bit Timer Control Register for TIMER0.

timer1 16-Bit Timer Runni ng Count Register for TIMER1.

TI MER 1_0 Pro g ram ma ble Tim er 1 fo r CO RE 0.

TI MER 1_1 Pro g ram ma ble Tim er 1 fo r CO RE 1.

Table 1. DSP 16411 Bl ock Diagra m Legend (continued)

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 17

Use

ursuant to Com

any instructions

4 Hardware Architecture (continued)

4.1 DSP16411 Architectural Overview (continued)

4.1.1 DSP16000 Cores

The two DSP16000 cores (CORE0 and CORE 1) are

the signal-processing engi nes of the DSP16411. The

DSP16000 is a modified Harvard architecture with sep-

arate sets of buses for t he instruction /coefficient

(X-memory) and data (Y-memory) spaces. Each set of

buses has 20 bits of address and 32 bits of data. The

core contains data and address arithmet ic units and

control for o n-ch ip memory and periphe rals.

4.1.2 Clock Synthesizer (PLL)

The DSP16411 powers up with an input clock (CK I) as

the source for the processor clock (CLK). An on-chip

clock synthesizer (PLL) that runs at a frequency multi-

ple of CKI c an also be used to generate CLK. T he

clock synthesizer is deselected and powered down on

reset. The selection of the clock source is under soft-

ware control of CORE0. See S ec tion 4 .17, begin ning

on page 200, for details.

4.1.3 Triport RAMs (TPRAM〈0—1〉)

Each core has a private block of TPRAM consisting of

160 banks (banks 0—159 ) of zero wait-state memory.

Each bank consists of 1K 16-bit words and has three

separate address and data ports: one port to the core’s

instruction/coefficient (X -m emo ry) space, a second

port to t he core’s data (Y-m em ory) space, and a third

port to the DM A (Z-mem ory) space. TPRA M0 is

accessible by CORE0, TPRAM1 is accessible by

CORE1, and both TPRAM0 and TPRAM1 are accessi-

ble by the DMAU. TPRA M is organized into even and

odd interleaved ban ks for which each even/odd

address pair is a 32-bit wide module (see Section 4.6

on page 44 for details). The TPRAMs support single-

word, aligned double -word, and misaligned double -

word accesses.

4.1.4 Shared Local Memo ry (SLM )

The SLM consists of two banks of memory. Each bank

consi sts of 1K 16-bit words. The SLM can be

accessed by both cores and by the DM A U and PIU

over the system bus (SAB, SDB). The SLM supports

single-word (16-bit) and aligned double-word (32-bit)

accesses. Misaligned double-word accesses are not

supported. An acce ss to the SLM takes mult iple clock

cycles to com plete, and a core a ccess to th e SLM

causes the core to incur wait-states. See

Section 4.14.7.1 on page 128 for det ails o n syste m bu s

performance.

4.1.5 Internal Boot ROMs (IRO M 〈0—1〉)

Each core has its own boot ROM that contains a single

boot routine and software to suppo rt the Agere hard-

ware development system (HDS). The code in IROM0

and IROM1 is identical. See Section 5 on page 208 for

details.

4.1.6 Mes saging Units (MGU〈0—1〉)

The DSP16411 provides an MGU for each core: MGU0

for CORE0 and MGU1 for CORE1. The MGUs provide

interprocessor (core-to-core) communication and inter-

rupt generation. See Section 4.8 on page 46 fo r

details.

timer1c 16-Bit Timer Control Register for TIMER1.

TPRAM〈0—1〉160 Kword Three-Port Random -Access Memories (one for each core). Private code (X), dat a (Y), and

DMA (Z).

XAB〈0—1〉20-Bi t X-Memory Space Address Bus. One fo r each core.

XDB〈0—1〉32-Bi t X-Memory Space Data Bus. One for eac h core.

YAB〈0—1〉20-Bi t Y- M emory Space Address Bus. One for each core.

YDB〈0—1〉32-Bit Y-Memory Space Data Bus. One f or each core.

ZEAB 20-Bit External Z-Mem ory Space Addre ss Bus. Int erf aces DMAU to SEMI.

ZEDB 32-Bit External Z-Memory Space Data Bus. Int erfaces DMAU to SEMI.

ZIAB 20-Bit Internal Z-Memory Space Address Bus. I nterfaces DMAU to TPRAM0 and TPRAM1.

ZIDB 32-Bit Inter nal Z-Memory Space Data Bus. Inte rf aces DMAU to TPRAM0 and TPRAM1.

ZSEG External Segment Address Bits Associated wi th ZEAB. Inter faces DMAU to SEMI.

Symbol Description

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

18 A gere System s— P rop rietary Agere Systems In c.

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any instructions

4 Hardware Architecture (continued)

4.1 DSP16411 Architectural

Overview (continued)

4.1.7 System and External Memory Interface

(SEMI)

The SEMI interfaces both cores and the DMAU to

external memory and I/O devices. It interfaces directly

to pipelined synchronou s

ZBT

™

SRA Ms and asyn-

chronous SRAMs. The SEMI also interfaces the cores

and the DMAU to the internal SLM and to memory-

mapped registers in the DMAU, PIU, SIU0, and SIU1

via the internal system bus or S-bus (SAB and

SDB). See Section 4.14, beginning on page 100, for

details.

4.1.8 Bit Inp ut/Output Units (BIO〈0—1〉)

The DSP1641 1 provides a BIO unit for each core: BIO0

for CORE0 and BIO1 for CORE1. Each BIO unit pro-

vides convenient and efficient monitoring and control of

seven individually configurable pins. If configured as

outputs, the pins can be individually set, cleared, or

toggled. If configu red as inputs, individual pins or c om-

binations of pins can be tested for patterns. Flags

returned by the BIO can be tested by conditional

instructions. See Section 4.9 on page 50 f or details.

4.1.9 Timer Units (TIMER0_〈0—1〉 and

TIMER1_〈0—1〉)

The DSP16411 provides two timer units for each core:

TIMER0_0 and TIMER1_0 for CORE0, and TIMER0_1

and TIMER1_1 for CORE1. Each timer can be used to

provide an interrupt, either single or repetitive, at the

expiration of a programmed interval. More than nine

orders of magnitude of interval selection are p rovided.

See Sec tion 4.10 on page 53 for more information.

4.1.10 Direct Memory Access Unit (DMAU)

The direct memory access unit (DMAU) manages data

transfers in t he DSP1 6411 memory space. Data can

be moved between DSP16411 memory and peripher-

als and between different memory spaces in the

DSP16411. Once initiated, DMAU transfers occur with-

out core intervention. T he DM AU supports concurrent

core execution and I/O processing. See Section 4.13,

beginning on page 64, for det ails.

4.1.1 1 Interrupt Multiplexers (IMUX〈0—1〉)

The DSP16411 provides an interrupt multiplexer unit

for each core: IMUX0 for CORE0 and IMUX1 for

CORE1. Each IMUX multiplexes the 26 hardware

interrupts into the 20 available hardware interrupt

reques ts for each core. See Sec tion 4.4.2 on page 28

for details.

4.1.12 Pa rallel Interface Unit (PIU)

The parallel interface unit (PIU) is a 16-bit parallel port

that provides a host processor direct access to the

entire DSP16411 memory system (including memory-

mapped peripheral registers). See Section 4.15,

beginning on page 135, for details.

4.1.13 Se rial Interface Units (SIU 〈0—1〉)

The DSP164 11 provides two identical SIUs. E ach S IU

is a full-duplex, double-buffered serial port with inde-

pendent input and output frame and bit clock control.

Clock and frame signa ls can be generated exte rnally

(passive) or by on-chip clock and frame generation

hardware (active). The SIU features mu ltiple-channel

TDM mode for ST-bus (1x and 2x compa tible) and

T1/E1 com patibility. E ac h SIU is provided a DMAU

interface for data transfer to memory (TPRAM0,

TPRAM1, SLM, memory-mapped registers, or external

memory) without core intervention. See Section 4.16,

beginning on page 154, for details.

4.1.14 Test Access Ports (JTAG〈0—1〉)

The DSP16411 provides a JTAG unit for each core:

JTAG 0 for CORE0 and JTA G1 for CORE1. See

Section 4.12 on page 57 for details.

4.1.15 Ha rdw are Devel op ment S ystem s

(HDS〈0—1〉)

The DSP16 411 provides an HDS unit for each core:

HDS0 for CORE0 and HDS 1 for CORE1. Each HDS is

an on-chip hardware module available for debugging

assem bly-lan guage program s that execu te on the

DSP16000 core in real-time. The main capability of the

HDS is in allowing controlled visibility into the core’s

state during program execution. The HDS is enhanced

with powerful debugging capabi lities such as complex

breakp ointing condition s, multiple data /address watc h-

point registers, and an intelligent trace mechanism for

recording discontinuities. See Section 4.11 on page 56

for details.

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 19

Use

ursuant to Com

any instructions

4 Hardware Architecture (continued)

4.2 DSP16000 Core Architectural Overview

The DSP16411 contains two identical DSP1600 0

cores. As shown in F igure 2 on page 21, each core

consists of four major blocks : syst em c ontrol and cache

(SYS), data arithmetic unit (DA U), Y-memo ry space

address arithmetic unit (YAAU), and X-memory space

address arithmetic unit (XAAU). Bits within the auc0

and auc1 registers configure the DAU mode-controlled

operations. S ee t he

D SP160 00 D igital Signal Proces-

sor Core

Information Manual for a complete description

of the DSP16000 core.

4.2 .1 System Control and Cache (SYS)

This section consists of the control block and the

cache.

The control block provides overall system coordination

that is m os tly invisible to the user. The cont rol block

includes an instruction decoder and sequencer, a

pseudorandom sequence generator (PSG), an inter-

rupt and trap handler, a wait-state generator , and low-

power standby mode control logic. An interrupt and trap

handler provides a user-locatable vecto r table and

three levels of user-assigned interrupt priority.

SYS contains the alf register, which is a 16-bit register

that contains AWAIT, a power-saving standby mode

bit, and peripheral flags. The inc0 and inc1 registers

are 20-bit interrupt control registers, and ins is a 20-bit

interrupt status register.

Programs use the instruction cache to store and exe-

cute repetitive operations such as those found in an

FIR or IIR filter section. The cache can contain up to

thirty-one 16-bit and 32-bit instructions. The code in the

cache can repeat up to 216 – 1 tim es without looping

overhead. Operations in the cache that require a coeffi -

cient access execute at twice the normal rate because

th e XAAU and i ts as so ciate d bus are not needed for

fetching instructions. The cache greatly reduces the

need for writing in-l ine repetitive code and, therefore,

reduces instruction/coefficient memory size require-

ments. In addition, the use of cache reduces power

consum ption becaus e it eliminates memo ry accesse s

for instruction fetch es.

The cache provides a convenient, low-overhead loop-

ing structure t hat is interruptible, savable, and restor-

able. The cache is addressable in both the X and Y

memory spaces . An interrupt or trap handli ng routine

can save and restore cloop, cstate, csave, and the

contents of the cache. The cloop register controls the

cache loop count. The cstate register contains the cur-

rent state of the cache. The 32-bit csave register holds

the opcode of the instruction following the loop instruc-

tion in program memory.

4.2.2 Data Arithmetic Unit (DAU)

The DAU is a power-effici ent, dual-MAC (multiply/accu-

mulate), parallel-pipelined structure that is tailored to

comm unicat ions appli cations . It can perform two dou-

ble-word (32-bit) fetches, two multiplications, and two

accumulations in a single instruction cycle. The dual-

MAC parallel pipeline begins with two 32-bit registers,

xand y. The pipeline treats the 32-bit registers as four

16-b it signed registers if used as i nput to two signed

16-bit x 16-bit multipliers. Each multiplier produces a

full 32-bit result stored into registers p0 and p1. The

DAU can direct the output of each multiplier to a 40-bit

ALU or a 40-bit 3-input ADDER. The ALU and ADDER

results are each stored in one of eight 40-bit accumula-

tors, a0 through a7. Both the ALU and ADDER include

an ACS (add/compare/select) function for Viterbi

decoding. The DAU can direct the output of each accu-

mulator to the ALU/ACS, the A DDER/ AC S, or a 40-bit

BMU (bit manipulation unit) .

The ALU implements 2-input addition, subtraction, and

various logical operations. The ADD ER implements

2-input or 3-input addition and subtraction. To support

Viterbi decoding, the ALU and ADDER have a split

mode in which two simul taneous 16-bit additions or

subtractions are performed. This mode, available in

speci alized dual-MA C instructions, is used to compute

the distance between a received symbol and its esti-

mate.

The ACS provides the add/compare/ select function

required for V iterbi decoding. This unit provides flags to

the traceb ack encoder for implemen ting mode-con-

trolled side-effects for ACS operations. The source

operands for the ACS are any two accumulators, and

results are written back to one of the source accumula-

tors.

The BMU implements barrel-shift, bit-field insertion, bit-

field extraction, exponent extraction, normalization, and

accum ulator shuffli ng operat ions. ar0 through ar3 are

auxiliary registers whose main function is to control

BMU operations.

The user can enab le overflow saturation to affect the

multipl ier output and the results of the three arithmetic

units. Overflow saturation can also affect an accumula-

tor value as it is transferred to memory or other

coding standa rd s such as GSM-FR, GSM-HR, and

GSM- EFR. Shifting in the arithmetic pipeline occu rs at

several stages to accommodate various standa rds for

mixed-precision and double-precision multiplications.

Advance Data Sheet

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20 A gere System s— P rop rietary Agere Systems In c.

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any instructions

4 Hardware Architecture (continued)

4.2 DSP16000 Core Architectur al

Overview (continued)

4.2.2 Data Arithmetic Unit (DAU) (continued)

The DAU contains control and status registers auc0,

auc1, psw0, psw1, vsw, and c0—c2.

The arithmetic unit control registers auc0 and auc1

select or deselect v ario us modes of DAU operation.

These modes include scaling of products, saturation on

overflow, feedback to the x and y re giste rs from accu-

mu lato rs a6 and a7, simultaneous loading of x and y

registers with the sam e value (used for single-cycle

squaring), and clearing the low half of registers when

loading the high half to f acili tate fixed-point operations .

The processor status word registers psw0 and psw1

contain fl ags set by ALU/ACS, ADDER, or BMU opera-

tions. They also include information on the current sta-

tus of t he interrupt controller.

The vsw register is the Viterbi support word associated

with the traceback encoder. The traceback encoder is a

specialized block for accelerating Viterbi decoding. The

vsw cont rols side-effects for three com pare functions:

cmp0( ), cmp1( ), and cmp2( ). These instructions are

part of t he M AC group that utilizes the t racebac k

encoder. The side-effects allow the DAU to store, with

no overhead, state information necessary for traceback

decoding. Side-effects use the c1 counter , the ar0 and

ar1 auxiliary registers, and bits 1 and 0 of vsw.

The c1 and c0 counters are 16-bit signed regist ers

used to count events such as the numbe r of times the

program has executed a sequence of code. The c2

instructions control these counters and provide a con-

venient method of program loo ping.

4.2.3 Y-M em or y Space Add ress Arithmeti c Unit

(YAAU)

The YAAU supports high-speed, register-indirect, data

memory addressing with postincremen t of the address

read or wri te addresses for t he data (Y-memory) space.

Two sets of 20-bit regist ers (rb0 and re0; rb1 and re1)

define the upper and lower boundaries of two zero-

overhead circular buffers for efficient f ilter implem enta-

ti o n s . T h e j and k registers are two 20-bit signed regis-

ters that are used t o hold user-defined post increm ent

values for r0—r7. Fixed increm ents of +1, –1, 0, +2,

and –2 are also available. (Postincrement options 0

and –2 are not available for some specialized transfers.

See the

DSP16000 Digital Signal Processor Core

Infor-

mat ion Manual for details.)

The YA AU includes a 20-bit stack pointer (sp). The

data mov e group includes a set of stack instructions

that consists of push, pop, stack-relative, and pipelined

stack-relative operations. The addressing mode used

for the stack-relative instructions is register-p lus-dis-

placem ent ind irect addressing (the displacem ent is

optional). The displacement is specified as either an

immediate value as part of the instruction or a value

stored in j or k. The YAAU compute s the address by

adding the displacement to sp and leaves the contents

of sp unchanged. The data move group also includes

instructions with register-plus-displacement indirect

addressing for the pointer registers r0—r6 in addition

to sp.

The dat a move group of instructions includes instruc-

tions for loading and storing any YAAU register from or

to memory or another core registe r. It also inclu des

instructions for loading any YAAU register with an

immedia te value stored with the i ns truction. The

pointer arithmetic group of instructions allows adding of

an immediate value or the contents of the j or k register

to any YAA U pointer register and storing the re su lt to

any YAAU register.

4.2.4 X-Memory Space Address Arithmetic Unit

(XAAU)

The XAAU contains registers and an adder that control

the sequencing of instructions in the processor. The

program count er (PC) automatic ally increm ents

through the instruction space. The interrupt return reg-

ister pi, the subroutine return register pr, and the trap

return register ptrap are auto matically loaded with the

return address of an interrupt service routine, subrou-

tine, and trap service routine, respectively. High-speed,

postincrem enting is done with the pt0 and pt1 regis-

ters. The signed registers h and i are used to hold a

user-define d signed posti ncremen t value. Fixed post in-

crem ent values of 0, +1, –1, +2, and –2 are also avail-

able. (Postincrement options 0 and –2 are available

only if the target of the data transfer is an accumulator.

See the DSP16000 Digital Signal Processor Core

Infor-

mat ion Manual f or details.)

The dat a move group include s instructions for loading

and storing any XAAU registe r from or to me mory or

another core register. It also includes instructions for

loading any XAAU register with an immediate value

stored with the instruction.

vbase is the 20-bit vector base of fset register . The user

programs this register with the base address of the

interrupt and trap vector table.

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 21

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ursuant to Com

any instructions

4 Hardware Architecture (continued)

4.2 DSP16000 Core Architectural Overview (continued)

4.2.5 Core Block Diagram

DSP16000 Cor e Block Diagram

Figure 2. DSP16000 Core Block Diagram

pr (20)

ptrap(20)

DAU

XAAU

SINGLE

–1, 0, 1

MUX

YAAU

MUXCOMPARE

SYS

cstate (16)

csave (32 )

CACHE CONTROL

(32)

IMMEDIATE

OFF-

CORE

SHIFT(2, 1, 0, –2)/SAT.

16 MULTIPLY 16

16 MULTIPLY

SPLIT /MUX

SAT.

ALU/ACS ADDER/ACS BMU

MUX MUX

MUX/EXTRACT

ENCODER

TRACEBACK

SHIF T(0, –1) SHIF T(0, –1)

SWAP MUX

SHIFT(0, –1)

SHIFT

(0, –14)

SAT.

SHIFT(0, –15, –16)

SAT. SAT.

SHIF T(2, 1, 0, –2)/SA T.

KEY:

PROGRAM-ACCESSIBLE REGISTERS

MODE-CONTROLLED OPTIONS

PSG

BUSES

VALUE

‡

SAT.SAT. SAT.

ar0 ( 16)

ar1 ( 16)

ar2 ( 16)

ar3 ( 16)

c0 (16)

c1 (16)

c2 (16)

vsw (16 )

auc0 (16)

auc1 (16)

psw0 (16)

psw1 (16)

y (32) x (32)

p0 (32) p1 (32)

a0 (40)

a2 (40)

a3 (40)

a4 (40)

a5 (40)

a6 (40)

a7 (40)

a1 (40)

ins (20)

inc0 (20)

inc1 (20)

cloop (16)

PC (20)

pt0 (20)

pt1 (20)

pi (20)

vbase (20)

(20) (20)

XDB (32)

IDB

(32)

YAB YAB

(20) (20)

re0 (20)

re1 (20) rb0 ( 20)

rb1 ( 20)

r0 (20)

r1 (20)

r2 (20)

r3 (20)

r4 (20)

r5 (20)

r6 (20)

r7 (20)

sp (20)

k (20)

j (20)

DOUBLE

–2, 0, 2

31 INSTRUCTIONS

alf (16)

(32)

XDB

IDB

(32)

SINGLE

–1, 0, 1

MUX

IMMEDIATE

VALUE

†

i (20)

h (20) DOUBLE

–2, 0, 2

† Associated with

-relative branch addressing.

XAB

(20)

YAB

(20)

MEMORY

FROM

MEMORY

TO/FROM

MEMORY

(32)

IDB

(32)

PERIPH-

ERAL

XDB

YDB

XABXAB

‡ Associated with register-plus-displacement indirect addressing.

MUX

k (20)

j (20)

re0 (20)

re1 (20) rb0 ( 20)

rb1 ( 20)

r0 (20)

r1 (20)

r2 (20)

r3 (20)

r4 (20)

r5 (20)

r6 (20)

r7 (20)

sp (20)

ar0 ( 16)

ar1 ( 16)

ar2 ( 16)

ar3 ( 16)

c0 (16)

c1 (16)

c2 (16)

vsw (16 )

auc0 (16)

auc1 (16)

psw0 (16)

psw1 (16)

y (32) x (32)

p0 (32) p1 (32)

a0 (40)

a2 (40)

a3 (40)

a4 (40)

a5 (40)

a6 (40)

a7 (40)

a1 (40)

SHIFT(2, 1, 0, –2)/SAT.

SAT.

SAT. SAT.

SHIF T(2, 1, 0, –2)/SA T.

SAT.SAT. SAT.

pr (20)

ptrap(20)

cstate (16)

csave (32 )

ins (20)

inc0 (20)

inc1 (20)

cloop (16)

pt0 (20)

pt1 (20)

pi (20)

vbase (20)

alf (16)

i (20)

h (20)

MUX

DEMUX

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

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Use

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any instructions

4 Hardware Architecture (continued)

4.2 DSP16000 Core Architectural Overview (continued)

4.2.5 Core Block Diagram (continued)

Table 2. DSP 16000 Core Block Diagram Le gen d

Symbol Name

16 x 16 MULTIPLY 16-Bit x 16-Bit Multiplier .

a0—a7 40-Bit Accumulators 0—7.

ADDER/ACS 3-Input 40-Bit Adder/Subtractor and Add/Compar e/Select Function . Used in Viter bi decodi ng.

alf 16-Bit AW AIT Low-Power and Flags Register.

ALU/ACS 40-Bit Ari thmetic Logic Unit and Add/Compare/Se lect Function. Used in Vi terbi decoding.

ar0—ar3 16-Bit Auxiliary Regi sters 0—3.

auc0, auc1 16-Bit Arithmet ic Unit Contr ol Regis ters.

BMU 40-Bit Manipulation Unit.

c0, c1 16-Bi t Counters 0 and 1.

c2 16-Bit Counter Holding Register .

cloop 16-Bit Cache Loop Count Register.

COMPARE Comparator. Used for circular buffer addressing.

csave 32-Bit Cache Save Register.

cstate 16- Bit Cache State Register.

DAU Data Arithmeti c Unit.

h20-Bit Pointer Postincr ement Register for the X-Memory Space.

i20-Bit Pointer Postincr ement Register for the X-Memory Space.

IDB 32-Bit Internal Data Bus.

inc0, inc1 20-Bit Int errupt Control Registers 0 and 1.

ins 20-Bit Int errupt Status Register.

j20-Bit Poin ter Postincrement/ Offset Regist er for the Y-Memory Space.

k20-Bit Poin ter Postincrement/ Offset Regist er for the Y-Memory Space.

MUX Multiplexer.

p0, p1 32-Bit Product Register s 0 and 1.

PC 20-Bit Program Counter.

pi 20-Bit Progr am Int errupt Return Regi ster .

pr 20-Bit Program Return Register.

PSG Pseudorandom Sequence Gener ator.

psw0, psw1 16-Bit Proce ssor Status Word Regi sters 0 and 1.

pt0, pt1 20-Bit Poin ters 0 and 1 to X-Memory Space.

ptrap 20-Bit Program Trap Return Register.

r0—r7 20-Bit Pointers 0—7 to Y-Memory Space.

rb0, rb1 20-Bit Circular Buff er Poi nters 0 and 1 (begin address).

re0, re1 20-Bit Circular Buffer Pointers 0 and 1 (end address).

SAT Saturation.

SHIFT Shifting Operation.

sp 20-Bit Stack Pointer.

SP LIT/ M UX Split/Multiplexer . Routes the appropr iate ALU/ACS, BMU, and ADDER/ACS outputs to the appropriate

accumulator.

SWAP MUX Swap Multi plexer. Routes the app ropr iate data to the appropriate multi plier input.

SYS System Control and Cache.

vbase 20-Bit Vector Base Offset Register.

vsw 16-Bit Viterbi Support Word. Ass ociated with the t raceback encoder.

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4 Hardware Architecture (continued)

4.2 DSP16000 Core Architectural Overview (continued)

Table 2. DSP 16000 Core Block Diagram Le gend (continued)

4.2.5 Core Block Diagram (continued)

4.3 Device Reset

The DSP16411 has three negative-assertion external

reset input pins: RSTN, TRST0N, and TRST1N. RSTN

is used to reset both CORE0 and CORE1. The primary

function of TRST0N and TRST1N is to reset t he JTAG0

and JTAG1 cont rollers.

4.3.1 Reset After Powerup or Power Interru ption

At initial powerup or if power is interrupted, a reset is

required and RSTN, TRST0N, and TRST1N must all

be asserted (low) simultaneously for at least seven CKI

cycle s (see Se ction 11. 4 on page 278 for details). The

TRST0 N and TRS T1N pins mus t be asserted even if

the JTAG controllers are not used by the application.

Failure to properly reset the device on powerup or after

a power interruption can lead to a loss of communica-

tion with the DSP16411 pins.

4.3.2 RSTN Pin Reset

The device is properly reset by asserting RSTN (low)

for at least seven CKI cycles and then deasserting

RSTN. Reset initiali zes the st ate of user registers, syn-

chroniz es the internal clocks, and initiates code execu-

tion. See Section 6.2.4, beginning on page 249, for the

values of the user registers after reset.

After RSTN is deasserted, there is a d elay of several

CKI cycles befo re the DSP16000 cores begin execut-

ing instructions (see Section 11.5 on page 279 for

details). The state of the EXM pin on the rising edge of

RSTN controls the boot program address for both

cores, as described in Section 5 on page 208.

x32-Bit Multiplier Input Register.

XAAU X-Memory Space Addr ess Arithmetic Unit.

XAB X-Memory Space Address Bus.

XDB X-Memory Space Dat a Bus.

y32-Bit Multiplier Input Register.

YAAU Y-Me mo ry Space Addre ss Ari thmetic Unit.

YAB Y-Memory Spac e Address Bus.

YDB Y-M emory Space Data Bus.

Symbol Name

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4 Hardware Architecture (continued)

4.3 Device Reset (continued)

4.3.2 RSTN Pin Reset (continued)

Table 3 defines the states of the output and bidirectional pins both during and after reset. It does not include the

TDO0 and TDO1 output pins because their state is not affected by RSTN. The state of TDO0 and TDO1 are

affec ted only by the JTAG0 and JTAG1 controllers.

4.3.3 JTA G Control ler Reset

The recommended m etho d of resetting the JTAG c ontroll ers is to assert RS TN, TRS T0N, and TRST1N low simul-

taneously. An alternate method is to clock TCK〈0,1〉 through at least five cycles wit h TMS〈0,1〉 held high. Both

methods ensure that the user has control of the device pins. JTAG controller reset places it in the test logic reset

(TLR) state and does not initialize user regist ers, synchronize internal clocks, or initiate code execution unless

RSTN is also asserted (see S ection 6.2 .4 on page 249).

Table 3. St ate of Device Output and Bidirectional Pins During and After Reset

Type Pin Condition State of Pi n

During Reset (RSTN = 0) Initial State of Pin

After Reset (RSTN = 1)

Output PIBF, PINT — logic low logic low

PRDY PRDYMD = 0 logi c l ow l ogic low

PRDYMD = 1 logic high logic high

EACKN, EION, ERAMN,

EROMN, ERWN0, ERWN1 IN T 0 = 0

(deasserted) logic hig h in itial i n a c tiv e s t ate

INT 0 = 1

(asserted) 3-state

POBE — logic high logic high

SOD0, SO D1 — 3-state 3-state

ECKO INT0 = 0

(deasserted) logic low CKI/2

INT 0 = 1

(asserted) 3-state

EA[18:0]†

† The output/bidirectional pins EA[18:0], ESEG[3:0], ED[31:0], and PD[15:0] include bus hold circuits. If BHEDIS (ECON1[12]—Table 61 on

page 112) = 0, the bus hold circuits on EA[18:0], ESEG[3:0], and ED[31:0] are activated. If BHPDIS (ECON1[13]) = 0, the bus hold circuits on

PD[15:0] are activated. The bus hold circuits are enabled and activated (BHEDIS = BHPDIS = 0) during and after reset. Activated bus hold cir -

cuits affect the electrical characteristics of the associated pins. See Section 10.1, beginning on page 268, and Table 183 o n page 267 for

details.

INT 0 = 0

(deasserted) logi c low initial inactive state

INT 0 = 1

(asserted) 3-state

ESEG[3:0]†IN T 0 = 0

(deasserted) logi c low logic low

INT 0 = 1

(asserted) 3-state

Bidirectional

(Input/Output) IO0BIT[6:0], IO1BIT[6:0],

PD[15:0]†, SICK0, SICK1,

SIFS0, SIFS1, SOCK0,

SOCK1, SOFS0, SOFS1,

TRAP

— 3-state configured as input

ED[31:0]†EYMODE = 0 3-state 3-state

EYMODE = 1 output output

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps

Each core in the DSP16411 supports the following

interrupts and traps:



26 hardware interrupts with three levels of user-

assign ed priority:

— 1 core-to-core interrupt.

— 10 general DMAU interrupts.

— 1 D MAU interrupt under control of the other core.

— 4 SIU interrupts.

— 3 PIU interrupts.

— 1 MGU interrupt.

—2 timer interrupts.

— 4 external interrupt pins.



64 software interrupts for each core, generated by

the executi on of an icall IM6 inst ru cti o n.



The TRA P pin.



The core-to-core trap.

Because the DSP16000 core supports a maximum of

20 hardware interrupts and the DSP16411 p rovides

26 hardware interrupt s, each core has an associated

programma ble interrupt multiplexer (IMUX〈0,1〉).

The interrupt and trap vectors are in contiguous loca-

tions in memory, and the base (starting) address of the

vectors is c onfigurab le in the core’s vbase re giste r.

Each interrupt and trap source is preassigned to a

unique vector offset that differentiates its service rou-

tine.

The core must reach an interruptible or trappable state

(completion of an interruptible or trappable instruction)

before it servi c es an interrupt or tra p. If the core ser-

vices a n inte rru pt or trap, it saves the conten ts of it s

program counter (PC) and begins executing instruc-

tions at the corresponding location in its vector table.

Fo r i n te r ru p ts, th e co r e saves i ts PC in its program

interrupt (pi) reg ister. For traps, the core saves its PC

in its program trap (ptrap) register. After servicing the

interrupt or trap, the servicing routine must return to the

interrupted or trapped program by executing an ireturn

or treturn instruction.

The core’s ins register (see Table 8 on page 32) con-

tains a 1-bit status field for each of its hardware inter-

rupts. If a hardware interrupt occurs, the core sets the

corresponding ins field to indicate that the interrupt is

pending. If the core services that interrupt, it clears the

corresponding ins field. The psw1 register (see

Table 10 on page 35) includes control and status bits

for the core’s hardware interrupt logic.

If a hardware interrupt is disabl ed, the core does not

service it. If a hardware interrupt is e nabled , the core

services it according to its priority. Device reset glo-

bally disables hardware interrupts. A n application can

globall y enable or disable hardware interrupts and can

individually enable or disable each hardware interrupt.

An appl ication globally enables hardware interrupt s by

executing the ei (enabl e interrupts) instruction and glo-

bally disables th em by executing the di (disable inter-

rupts) instruction. (Within an interrupt service ro utine

(ISR), the execution of an ireturn instruction also glo-

bally enable s hardware interrupts.) An application can

individually enable a hardware interrupt at an assigned

priority or i ndividu ally disable a hardware interrupt by

configu ring the inc0 or inc1 register (see Table 7 on

page 31).

Software interrupts emulate hardware interrupts. The

core services software interrupts even if hardware

interrupts are globally disabled.

A trap is similar to an interrupt but has the highest pos-

sible priority. An application cannot disable traps by

executing a di instruction or by any other means. Traps

do not nest, i.e., a trap service routine (TSR) cannot be

interrupted or trapped. A trap does not affect the state

of the psw1 register.

The

DSP16000 Digital Signal Processor Core

Info rma-

tion Manual provides an extensive discussion of inter-

rupts and traps. The remainder of Section 4.4

describ es the interrupts and traps for the DSP16411.

4.4. 1 Hardware In terrupt Logi c

Figure 3 on page 26 illu str a t es t he pa th of ea c h in ter-

rupt from its generating peripheral or pin to the interrupt

logic of CORE0 and CORE1. Some of the interrupts

conn ect directly to the cores, and others connect via

the IMUX〈0,1〉 block . Som e of the interrup ts are spe-

cific to a core, and some are commo n to both cores.

The program me r can configure IMUX〈0,1〉 using the

corresponding imux register. T he program m er can

divide proces sing of the multiplexed interru pts PIBF,

POBE, S〈O,I〉INT〈0,1〉, DSINT[3:0], DDINT[3:0],

DMINT[5:4], and INT[3:2] between CORE0 and

CORE 1, or cause some of these interrupts to be com-

mon to both cores by defining the fields in each core’s

imux register. See Section 4.4.2 on page 28 for

details on interrupt multiplexing.

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.1 H ardware Interrupt Logic (continued)

Interrupt B lock Di agram

† These interrupts are specific to a core, not common to both cores.

‡ Each of the MXI[9:0] interrupts can be either specific to a core or common to both cores, determined by how each interrupt is configur e d in

imux (se e Table 5 on page 28).

Figure 3. CORE0 and CORE1 Interrupt Logic Block Diagram

TIMER0_0

IMUX0

MGU0

PIUDMAU

CORE0 CORE1

IMUX1

MGU1

TIMER1_0 TIMER0_1 TIMER1_1

PIBF (PIU)

POBE (PIU)

INT[3:2]

DSINT[3:0], DDINT[3:0], DMINT[5:4]

S〈O,I〉INT〈0,1〉

XIO†

MXI[9:0]‡XIO†

10 10

MGIBF†SIGINT†

INT[1:0]

PHINT MXI[9:0]‡MGIBF†

SIGINT†DMINT[5:4]PHINT

TIME0†TIME1†TIME0†TIME1†INT[1:0]

DMINT[5:4]

INT[1:0]

(SIU〈0,1〉)

inc0

imux

KEY: PROGRAM-ACCESSIBLE REGISTER

inc1

ins

inc0

inc1

ins

imux

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.1 H ardware Interrupt Logic (continued)

Table 4 summarizes each hardware interrupt in the DSP16411, inc lud ing whether it is internal or external, which

module generates it, and a brief description. For details on the operation of each internal interrupt, see the section

that describes the correspondi ng block.

Tab le 4. H a rdware In te rru pts

Interrupt Type Name Description

DSINT0 Inter nal DMAU Source Interrupt for SWT0 (for SIU0 ) Channe l SWT0† source (output) inter rupt request.

DDINT0 Internal DMAU Destination Interrupt for SWT0 (for SIU0) Channel SWT0† destination (input) inter rupt request.

DSINT1 Inter nal DMAU Source Interrupt for SWT1 (for SIU0 ) Channe l SWT1† source (output) inter rupt request.

DDINT1 Internal DMAU Destination Interrupt for SWT1 (for SIU0) Channel SWT1† destination (input) inter rupt request.

DSINT2 Inter nal DMAU Source Interrupt for SWT2 (for SIU1 ) Channe l SWT2† source (output) inter rupt request.

DDINT2 Internal DMAU Destination Interrupt for SWT2 (for SIU1) Channel SWT2† destination (input) inter rupt request.

DSINT3 Inter nal DMAU Source Interrupt for SWT3 (for SIU1 ) Channe l SWT3† source (output) inter rupt request.

DDINT3 Internal DMAU Destination Interrupt for SWT3 (for SIU1) Channel SWT3† destination (input) inter rupt request.

DMINT4 Internal DMAU Interrupt for MMT4 Channel MMT4‡ interrupt request.

DMINT5 Internal DMAU Interrupt for MMT5 Channel MMT5‡ interrupt request.

INT[3:0] External External Interrupt Requests An external device has request ed service b y asserting

the corresponding INT[3:0] pin (0-t o-1 transition).

MGIBF Internal MGU Input Buffer Full The MGU input buffer (mgi) is full.

PHINT Internal PIU Host I nterrupt The host sets the HINT fi eld (PCON[4]).

PIBF Internal PIU Input Buffer Full PDI cont ains dat a from a previou s host write operat ion.

POBE Internal PIU Output Buffer Empty The data in PDO has been read by the host.

SIGINT Internal Signal Interru pt (Core-to-Core) The other core set s it s signal[0] fiel d.

SIINT0 Int ernal SIU0 Input Interrupt Based on the II NTSEL[1:0] field (SCON10[12:1 1]),

asserted if:



Input frame sync detected.



Input subf rame transfe r complete.



Input channel transfer com plete.



Input error occurs.

SIINT1 Internal SIU1 Input Interrupt

SOINT0 Internal SIU0 Output Interrupt Based on the OINTSEL[1:0] field (SCON10[14:13]):



Out put fra me sync detected.



Output subframe transfer complete.



Output channel transfer complete.



Output error occurs.

SOINT1 Intern al SIU 1 Outpu t Inter r upt

TIME0 I nternal TIM ER0 Delay/Inter val Reached TIMER0 has reached zero count.

TIME1 I nternal TIM ER1 Delay/Inter val Reached TIMER1 has reached zero count.

XIO Internal Core-to- Core DMAU Int errupt Based on the other core’s XIOC[1: 0] fi eld:



Zero (l ogic low).



DMINT4 (MMT4 transfer complete).



DMINT5 (MMT5 transfer complete).

† An SWT channel is a single-word transfer channel used for both input and output by an SIU. It transfers single words (16 bits).

‡ An M MT cha nn el is a mem or y-t o-m emo r y chan ne l us ed by the cor es t o co py a bloc k f rom an y a rea o f me mor y to an y othe r ar e a of me mory . It

transf ers single words (1 6 bits) or double words (32 bits).

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.2 Hardware Interrupt Multiplexing

The total number of DSP16411 hardware interrupt sources (26) exceeds the number of interrupt requests sup-

ported by the DS P 160 00 core (20). Therefore, each core includes an interrupt multiplexer block (IM UX ) and asso-

ciated control register (imux) t o permit the 26 interrupts to be multiplexed into the 20 available hardware interrupt

requests. Each core supports ten dedicated interrupt requests. Each core’ s IMUX block multiplexes the remaining

16 hardware requests into the ten remaining hardware interrupt re ques t lines.

Table 5 describes the imux register and Figure 4 on page 29 illustrates the IMUX block.

Table 5. i mux (Interrupt Multiplex Con trol ) Register

15—14 13—12 11—10 9—8 76543210

XIOC[1:0]†Reserved IMUX9[1:0] IMUX8[1:0] IMUX7 IMUX6 IMUX5 IMUX4 IMUX3 IMUX2 IMUX1 IMUX0

Bit Field Controls

Multiplexed

Interrupt

Value Interrupt

Selected Description R/W Reset

Value

15—14 XIOC[1:0]†XIO 00 0 (logi c low) —R/W00

01 DMINT4 DMAU interrupt for MMT4.

10 DMINT5 DMAU interrupt for MMT5.

11 Reserved Reserved.

13—12 Reserved — 0 — Reserved—write with zero. R/W 0

11—10 IMUX9[1:0] MXI9 00 INT3 Pin. R/W 00

01 POBE PIU output buffer empty.

10 PIBF PIU in put buffer full.

11 Reserved Reserved.

9—8 IMUX8[1:0] MXI8 00 INT2 Pin. R/W 00

01 POBE PIU output buffer empty.

10 PIBF PIU in put buffer full.

11 Reserved Reserved.

7 IMUX7 MXI7 0 SIINT1 SI U 1 input interrupt. R/W 0

1 DDINT2 DM AU destination interr upt for SWT2 (SIU1).

6 IMUX6 MXI6 0 SOINT1 SIU1 output int err upt. R/W 0

1 DSINT2 DMAU sour ce interrupt for SWT2 (SI U1).

5 IMUX5 MXI5 0 SIINT0 SI U 0 input interrupt. R/W 0

1 DDINT0 DM AU destination interr upt for SWT0 (SIU0).

4 IMUX4 MXI4 0 SOINT0 SIU0 output int err upt. R/W 0

1 DSINT0 DMAU sour ce interrupt for SWT0 (SI U0).

3 IMUX3 MXI3 0 DDINT2 DMAU destination interrupt for SWT2 (SIU1). R/W 0

1 DDINT3 DM AU destination interr upt for SWT3 (SIU1).

2 IMUX2 MXI2 0 DSINT2 DMAU source interrupt for SWT2 (SIU1). R/W 0

1 DSINT3 DMAU sour ce interrupt for SWT3 (SI U1).

1 IMUX1 MXI1 0 DDINT0 DMAU destination interrupt for SWT0 (SIU0). R/W 0

1 DDINT1 DM AU destination interr upt for SWT1 (SIU0).

0 IMUX0 MXI0 0 DSINT0 DMAU source interrupt for SWT0 (SIU0). R/W 0

1 DSINT1 DMAU sour ce interrupt for SWT1 (SI U0).

† The XIOC[1:0] field controls the XIO interrupt for the other core.

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.2 Hardware Interrupt Multiplexing (continued)

IMUX Block Diagram

Figure 4. IMUX Block Diagram

MUX

MXI0

DSINT0

DSINT1

MUX0 (imux[0])

XIO (TO OTHER CORE)

DMINT4

DMINT5

XIOC[1:0] (imux[15:14])

MXI8

INT2

POBE

PIBF

IMUX8[1:0] (imux[9:8])

MXI9

INT3

POBE

PIBF

IMUX9[1:0] (imux[ 11:10])

MXI1

DDINT0

DDINT1

IMUX1 (imux[1])

MXI2

DSINT2

DSINT3

IMUX2 (imux[2])

MXI3

DDINT2

DDINT3

IMUX3 (imux[3])

MXI4

SOINT0 DSINT0

IMUX4 (imux[4])

MXI5

SIINT0 DDINT0

IMUX5 (imux[5])

MXI6

SOINT1 DSINT2

IMUX6 (imux[6])

MXI7

SIINT1 DDINT2

IMUX7 (imux[7])

MUX

IMUX

〈

0,1

〉

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.3 Clearing Core Interrupt Reque sts

Internal hardware interrupt signals are pulses that the core latches into its ins register (s ee Section 4.4.7 on

page 32). Therefore, the user software need not clear the interrupt request. However, in the case of the PIU host

interrupt, PHINT, the user software must clear th e HINT field (PCON[4]) to allow the host to request a subsequent

interrupt. See S ect ion 4.15.7 on page 15 3 for details.

4.4.4 H ost Interrupt Ou t put

The DSP16411 provides an interrupt output pin, PINT, that can interrupt a host processor connected to the PIU. A

core can assert this p in by setting the PINT field (PCON[3]). The host must clear the PINT field to allow a co re to

request a subseque nt interrupt. See Section 4.15.7 on page 153 for details.

4.4.5 Glob a lly En a bli ng and D is a bl ing H ardware Inte rr upt s

A device reset globally disables interrupts, i. e., the core does not service interru pts by default after reset. The

application must execute an ei instruction to globally enable interrupts, i.e., t o caus e the core to se rvice interrupts

that are individually enabled. Secti on 4.4.6 on page 31 describes individually enabl ing and disabl ing

interrupts. Executing the di instruction globally disables interrupts.

The core automatically globally disables interrupts if it begins servicing an interrupt, i.e., interrupt nesting is dis-

abled by default. When the ireturn instruction that the programmer must place at the end of the ISR is executed,

the core automatically globally re-enables interrupts. Therefore, the programmer does not need to explicitly re-

enable interrupts by executing an ei instruc tion before exiting the I S R. An interrupt service routine (ISR) can allow

nesting, i.e., c an be i nterrupted by a hi gher-pri ority interrupt, if i t globally enables interrupts i n the correct sequence

as described in Section 4.4.11 on page 35, Nes ting Interrupts.

The one-bit IEN field (psw1[ 14]—see Table 10 on page 35) is c lea red if hardware interrupts are globally

disabled. T he IEN field is s et if interrupts are globally e nabled .

Table 6 summarizes global disabling and enabling of hardware interrupts.

Table 6. Global Disablin g and Enabling of Hardw are Interru pts

Condition Caused By Indicated By Effect

Ha rd w a re in te rr u p ts

globally† disabled



Device re se t



Execution of a di in s truct ion



The core begins to service an interrup t

IEN (psw1[14]) = 0 Core does not service

interrupts.

Ha rd w a re in te rr u p ts

globally† enabled



Execution of an ei instruction



Execution of an ireturn instru ctio n

IEN (psw1[14]) = 1 Core services individually

enabled interrupts.

† With the exception o f devic e reset, CO RE 0 and CORE1 are independent with respect to global disabling and enabling of hardware interrupts.

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.6 I ndi vi duall y En abl i ng, Disabl in g, and P rio ri tizi ng H ardware Inter r up t s

An application can individually disabl e a hardware interrupt by clearing both bits of its c orrespondi ng 2-bit field in

the inc0 or inc1 register (see Table 7). Reset cle ars t he inc0 and inc1 registers, individually disabling all hardware

interrupts by default. An application can individually enable a hardware interrupt at one of three priority levels by

setting one or both bits of it s correspond ing 2-bit field in the inc0 or inc1 register.

The following are the advantages of interrupt prioritization:



An ISR can service concurrent interrupts according to their priority.



Interrupt nesting is supported, i.e., an interrupt can interrupt a lower-priority ISR. See Section 4.4.11 on page 35

for details on interrupt nesting.

If m ul tiple concurrent interrupts with the same assigned priority occur, the c ore first services the interrupt that has

its status field in the relative least significant bit location of the ins register (see Table 8 on page 32), i.e., the core

first services the interrupt with the lowest vector address (see Table 9 on page 33).

Note: If interrupts are globally enabled (see Section 4.4.5 on page 30), an application must not change inc〈0—1〉,

because doing so can cause a potential race condition between the detection of the interrupts and the deter-

mination of their relative priorities. Prior to changing inc〈0—1〉, the application must globally disable inter-

rupts by executing a di instruction. After changing inc〈0—1〉, the application can globally re-enable interrupts

by executing an ei instruction.

The following code segment is an example of properly changing inc〈0—1〉:

di // Globally disable interrupts (default after reset).

inc1=0x00001 // Enable MGIBF at level 1 priority.

ei // OK to globally re-enable interrupts.

di // Before changing inc1, first globally disable interrupts.

inc1=0x00006 // Change MGIBF priority to level 2...

// Enable SIGINT at level 1 priority.

ei // OK to globally re-enable interrupts.

Table 7. i nc 0 an d inc1 (Interrupt Control) Reg isters 0 and 1

19—18 17—16 15—14 13—12 11—10 9—8 7—6 5—4 3—2 1—0

inc0 INT1[1:0] INT0[1:0] DMINT5[1:0] DMINT4[1:0] MXI3[1:0] MXI2[1:0] MXI1[1:0] MXI0[1:0] TIME1[1:0] TIME0[1:0]

inc1 MXI9[1:0] MXI8[1:0] MXI7[1:0] MXI6[1:0] MXI5[1:0] MXI4[1:0] PHINT[1:0] XIO[1:0] SIGINT[1:0] MGIBF[1:0]

Field Value Description R/W Reset

Value

INT〈0—1〉[1:0]

DMINT〈4—5〉[1:0]

MXI〈0—9〉[1:0]†

TIME〈0—1〉[1:0]

PHINT[1:0]

XIO[1:0]

SIGINT[1:0]

MGIBF[1:0]

00 Disable the selected interrupt (no priorit y). R/W 00

01 Enable the selected interrupt at prio ri ty 1 (lowe st).

10 Enable the selected interrupt at prio ri ty 2.

11 Enable the selected interrupt at prio ri ty 3 (hig hest).

†See Table 5 on page 28 for definition of MXI〈0—9〉 (IMUX〈0—9〉).

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.7 Hardwar e Interrupt Status

If a hardware interrupt occurs, the core sets the corre-

sponding bit in the ins register ( Table 8) to indi cate t hat

the interrupt is pending. If the core services the inter-

rupt, it clears the ins bit. Alternatively , if the application

uses interrupt polling (Section 4.4.13 on page 37), the

application program m ust explicitly clear the ins bit b y

writing a 1 to t hat bit and a 0 to every ot her ins bit.

Writ ing a 0 to an ins bit leaves that bit unchanged. A

reset clears the ins regis ter, indicating that no inter-

rupts are pending.

If a hardware interrupt occurs, the core sets its ins bit

(i.e., l atches the interrupt as pending) regardless of

whether the interrupt is enabled or disabled. If a hard-

ware interrupt occurs while it is disabled and the inter-

rupt is lat er enabled, the core services the interrupt

after servicing any other pending interrupts of equal or

higher priority.

Note: The DSP16000 core globally disables interrupts

when it begins executing instructions in the vec-

tor table. If the ISR does not globally enable

interrupts by following the procedure specified in

Section 4.4.11 on page 35, Nes ting Inter rupts,

and the same interrupt reoccurs while the core is

executing t he ISR, the interrupt is not latched

in to ins and is therefore not recognized by the

core.

4.4.8 Interrupt and Trap Vector Table

The interrupt and trap vectors for a core are in contigu-

ous locations in memory. The base (starting) address

of the vectors is configurable in the core’s vbase

assig ned to a unique vector offs et within a 352-word

vector table (see Table 9 on page 33). The program -

mer can place at the vector location an instruction that

branches to an interrupt service routine (ISR) or trap

service routine (TSR). After servicing the interrupt or

trap, the ISR or TSR must return t o the interrupted or

trapped program by executing an ireturn or treturn

instruct ion. Al ternatively, the programme r can place at

the vector location up to four words of instructions t hat

service the interrupt or t rap, the last of which must be

an ireturn or treturn.

Table 8. i ns (Interrupt Status) Register

19 18 17 16 15 14 13 12 11 10

MXI9 MXI8 MXI7 MXI6 MXI5 MXI4 PHINT XIO SIGINT MGIBF

9 8765432 1 0

INT1 INT0 DMINT5 DMINT4 MXI3 MXI2 MXI1 MXI0 TIME1 TIME0

Field Value Description R/W Reset Value

MXI〈0—9〉†

PHINT

XIO

SIGINT

MGIBF

INT〈0—1〉

DMINT〈4—5〉

TIME〈0—1〉

0 Read—corresponding interrupt not pending.

Wr ite—no effect. R/Clear 0

1 Read—corresponding interrupt is pending.

Wr it e—clears bit and changes corresponding inter rupt status to not

pending.

†See Table 5 on page 28 for definition of MXI〈0—9〉 (IMUX〈0—9〉).

Advance Data Sheet
April 2002 DSP16411 Digital Signal Processor
Agere  Systems In c. Agere Systems—P ropri etary 33
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p
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any instructions
4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.8 Interrupt and Trap Vector Tab le (continued)
Table 9. Inter rup t and Trap  Vector Tabl e
Vector Description Vector Address†Priority
Hexadecimal Decimal
Reserved vbase + 0x0 vbase + 0 —
PTRAP‡vbase + 0x4 vbase + 4 6 (Highest)
UTRAP§vbase + 0x8 vbase + 8 5
Reserved vbase + 0xC vbase + 12 —
TIME0 vbase + 0x10 vbase + 16 0—3††
TIME1 vbase + 0x14 vbase + 20 0—3††
MXI0 (DSINT0 or DSINT1‡‡)vbase + 0x18 vbase + 24 0—3††
MXI1 (DDI NT0 or DDINT1‡‡)vbase + 0x1C vbase + 28 0—3††
MXI2 (DSINT2 or DSINT3‡‡)vbase + 0x20 vbase + 32 0—3††
MXI3 (DDI NT2 or DDINT3‡‡)vbase + 0x24 vbase + 36 0—3††
DMINT4 vbase + 0x28 vbase + 40 0—3††
DMINT5 vbase + 0x2C vbase + 44 0—3††
INT0 vbase + 0x30 vbase + 48 0—3††
INT1 vbase + 0x34 vbase + 52 0—3††
MGIBF vbase + 0x38 vbase + 56 0—3††
SIGINT vbase + 0x3C vbase + 60 0—3††
XIO vbase + 0x40 vbase + 64 0—3††
PHINT vbase + 0x44 vbase + 68 0—3††
MXI4 (SOINT0 or DSINT0‡‡)vbase + 0x48 vbase + 72 0—3††
MXI5 (SIINT0 or DDINT0‡‡)vbase + 0x4C vbase + 76 0—3††
MXI6 (SOINT1 or DSINT2‡‡)vbase + 0x50 vbase + 80 0—3††
MXI7 (SIINT1 or DDINT2‡‡)vbase + 0x54 vbase + 84 0—3††
MXI8 (INT2, POBE, or PIBF ‡‡)vbase + 0x58 vbase + 88 0—3††
MXI9 (INT3, POBE, or PIBF ‡‡)vbase + 0x5C vbase + 92 0—3††
ica ll 0 §§ vbase + 0x60 vbase + 96 —
icall  1 vbase + 0x64 vbase + 100 —
—
icall 62 vbase  + 0x158 vbase + 344 —
icall 63 vbase + 0x15C vbase + 348 —
†vbase contains t he base  address of th e 352-word ve ct or tab l e.
‡ Driven by TRAP pin (see Section 4.4.10 on page 34) or c ore-to-c ore t rap (see Section 4.8.1 on page 47).
§ Reserved for HDS.
†† The programmer specifies the relative priority levels 0—3 for hardware interrupts via inc0 and inc1 (see Ta bl e 7 on  page 31). Level 0 indicates a dis-
abled interrupt. If multiple concurrent interrupts with the same assigned priority occur , the core first services the interrupt th at   has  i ts statu s field  i n th e 
r elat i v e  l eas t signifi can t bit lo c ation of   t he ins regi st er (s ee  Table 8 on page 32); i.e., the core first services the interrupt with the lowest vector address.
‡‡ The choice of  i nter rupt is  sel ected by t he  imux re giste r  (see Ta bl e 5 on page 2 8).
§§ Rese rved f or sys tem serv i ces.
…
…
…

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DSP16411 Digital Signal Processor April 2002

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.9 Software Interrupts

Software interrupts emulate hardware interrupts. A

software interrupt is always enable d and has no

assigned priority and no corresponding field in the ins

cuting an icall IM6 instruction, where IM6 is replaced

with 0—63. Whe n a software interrupt is s erviced, the

core saves th e contents of PC in th e pi register and

transfers control to the interrupt vector defined in

Table 9 on page 33.

CAUTION: If a software interrupt is inserted into an

ISR, it is explicitly nested in the ISR and

therefore the ISR must be structured for

nesting. See Section 4.4.11 on page 35

and the

D SP160 00 Digital Signal Pro-

cessor Core

Inform a tio n Manual for

more information about nesting .

4.4.10 INT[3:0] and TRAP Pins

The DSP16 411 provides f our positive-as sertion edge-

detected interrupt pins (INT[3:0]) and a bidirectional

positive-assertion edge-d etected trap pin (TRAP).

The TRA P pin is used by an application to gain c on trol

of both processors for asynchronous event handling,

typically for catastrophic error recovery. It is a 3-state

bidirectional pin that connects to both cores and both

HDS blocks. TRAP is connected directl y to bot h cores

via the PTRAP signal. After reset, TRAP is configured

as an input; it can be configured as an output under

JTAG control to support HDS multiple-device debug-

ging.

Figure 5 is a functional ti mi ng diagram for the INT[3:0]

and TRAP pins. A low-to-high transition of one of these

pins asserts the corresponding interrupt or trap.

INT[3: 0] or TRAP must be held high for a min imu m of

two CLK cycles and must be held low for at least tw o

CLK cycles before being reasserted. If INT[3:0] or

TRAP is asserted and stays high, the core services the

interrupt or trap only once.

A minim um of f our cycle s1 af ter INT[3:0] or PT RA P is

asserted, the core services the interrupt or trap by exe-

cuting instruc tions starting at the vector location as

defined in Table 9 on page 33 . In the case of PTRAP, a

maximum of three instructions are allowed to execute

before the core services the trap.

Functional Timing for INT[3:0] and TRAP

Fi gure 5 . Func t ion al Ti m ing for INT [3:0] and TR AP

1. The number of cycles depends on the number of wait-states incurred by the interrupted or trapped instruction.

ECKO

†

INT[3:0]/TRAP

‡

† ECKO is programmed to be the internal clock CLK (the ECKOB[1:0] field (ECON1[3:2]—see Table 61 on page 112) is programmed to 00 and

the ECKOA[1: 0] field (ECON1[1:0]) is programmed to 01).

‡ The INT[3:0] or TRAP pin must be held high for a minimum of two CLK cycles and must be held low for a minimum of two CLK cycles bef or e

being reasserted.

Notes:

A. The DSP16411 synchronizes INT[ 3:0] or TRAP on the falling edge o f the internal clock CLK.

B. A minimum four-cycle delay before the core services the interrupt or trap (executes instructions starting at the vector location). For a trap, the

core executes a maximum of three instructions before i t services the trap.

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.11 Nesting Interrupts

The psw1 register (see Table 10) contains the IPLC[ 1:0] and IPLP[1:0] fields that are used for interrupt

nesting. See the

DSP16000 Digital Signal Process or Core

Information M anual for details on these fields.

Table 10. psw1 (Processor Status Word 1) Register

15 14 13—12 11—10 9—7 6 5—0

Reserved IEN IPLC[1:0] IPLP[1:0] Reserved EPAR a[7:2]V

Bit Field Value Description R/W Reset

Value†

15 Reserved 0 Reserved—write with zero. R/W 0

14 IEN‡0 Hardware interrupts are gl obally disabled. R 0

1 Hardware interrupts are gl obally enabled.

13—12 IPLC[1:0] 00 Current hardware interrupt priori ty l evel is 0; core handl es pending interrupts of

priority 1, 2, or 3. R/W 00

01 Current hardware int errupt priority level is 1; cor e handles pending interrupts of

priority 2 or 3.

10 Current hardware int errupt priority level is 2; cor e handles pending interrupts of

priority 3 only.

11 Current hardware int errupt priority level is 3; cor e does not handle any pendi ng

interrupts.

11—10 IPLP[1:0] 00 Previous hardware interrupt priority level§ was 0. R/W XX

01 Previous har dware i nterrupt priority level§ was 1.

10 Previous har dware i nterrupt priority level§ was 2.

11 Previous har dware i nterrupt priority level§ was 3.

9—7 Reserved 0 Reserved—write with zer o. R/W X

6 EPAR 0 Most recent BMU or special f unction shift result has odd parity. R/W X

1 Most recent BMU or special functi on shift result has even parity.

5 a7V 0 The current contents of a7 are not mat hematically overflowed. R/W X

1 The current contents of a7 are mathemat ically overf lowed.††

4 a6V 0 The current contents of a6 are not mathemat ically overf lowed. R/W X

1 The current contents of a6 ar e mathem atically overf lowed.††

3 a5V 0 The current contents of a5 are not mathemat ically overf lowed. R/W X

1 The current contents of a5 ar e mathem atically overf lowed.††

2 a4V 0 The current contents of a4 are not mathemat ically overf lowed. R/W X

1 The current contents of a4 ar e mathem atically overf lowed.††

1 a3V 0 The current contents of a3 are not mathemat ically overf lowed. R/W X

1 The current contents of a3 ar e mathem atically overf lowed.††

0 a2V 0 The current contents of a2 are not mathemat ically overf lowed. R/W X

1 The current contents of a2 ar e mathem atically overf lowed.††

† In this co l um n, X ind i cates unkn own on powerup res et and unaff ected on subs equent reset .

‡ The user clears this bit by executing a di instruc t io n and set s it by ex ecuti ng an ei or ireturn instruction. The core clears this bit whenever it begins to

service an interrupt.

§ Previous in t errupt pr i ority level is the priori ty lev el of th e in terr upt most re cent l y serv i ced prior t o the curr ent interr upt. This f ield i s use d for interr upt

nesting.

†† The mo st recent DAU result that was wri t ten t o t hat ac cumul ator result ed i n mathem atical overfl ow (LMV) with FS AT = 0.

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.11 Nesting Interrupts (continued)

Caution: The procedure for nesting interrupts described below is different than that described in

S e c t ion 5 .4.9 of the

DSP16000 Di gital Signal Processo r Core

Information Manua l. The DSP16411

contains version 2 of the DSP16000 core, and the manual describes version 1 of the core. See the

DSP16K V2 Core Nested Interrupt Design Exception

Advisory (AY 01-0 33WI NF) for details.

The DSP16000 core automatically globally disables interrupts when it begins servicing an interrupt, disabling inter-

rupt nesting by default. To allow interrupt nesting, the interrupt s ervice routine (ISR) must perform the steps speci-

fied in the following ISR code example. The code segment highlighted in bold glob ally enable s interrupts in the

proper sequence. This code se gme nt replaces the ei instruction in the ISR code example described in

Section 5.4.11 of the

DSP16000 Digital Signal Pro ce ssor Core

Information Manual. (The code example in

Section 5. 4.11 of the information m anual contains additional instructions needed if the main body of the IS R use s

cache loops. These instructions hav e been om itted from the following exam ple for simplicity.)

// Save Context:

ISR: push pi // Save pi to stack - needed for nesting.

push psw1 // Save psw1 to stack - needed for nesting.

push cstate // Save cstate to stack - needed for nesting.

cstate=0 // Clear cstate - needed for nesting.

// (The cstate register must be saved and cleared so that, if this ISR has interrupted

// a cache loop and this ISR is interrupted by a higher-priority interrupt, the ireturn

// in the higher-priority ISR returns to this ISR and not to the cache loop.)

// Save (push) any other registers to stack that will be used in BODY below.

// If required, execute noninterruptible user code here.

// Globally enable interrupts -- replaces ei instruction and is needed for nesting.

push psw1 // Save current state of IPLC and IPLP.

pi=JMP // Set jump location for ireturn.

psw1=0x3C00 // Set IPLC=IPLP=3 (set core to highest priority level) so that

// no interrupts will be accepted until psw1 is restored.

ireturn // Globally enable interrupts and goto pi (JMP).

JMP: pop psw1 // Restore psw1 -- restore core to correct priority level.

////////////////////////////////////////////////////////////////////////////////////

// BODY -- Main body of ISR that services the interrupt. Can be interrupted //

// by an interrupt of higher priority. //

////////////////////////////////////////////////////////////////////////////////////

di // Globally disable interrupts for restoring state.

// If required, execute noninterruptible user code here.

// Restore (pop) any other registers from stack that have been saved (pushed).

pop cstate // Restore cstate from stack.

pop psw1 // Restore psw1 from stack.

pop pi // Restore pi from stack.

ireturn // Return from interrupt and globally enable interrupts.

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4 Hardware Architecture (continued)

4.4 Interrupts and Traps (continued)

4.4.12 Interrupts an d Cache Usage

If an ISR or TSR uses cache (do or redo) loops, then it must first save t he state of the cache and then restore it

before returning to normal program execution. This is necessary because the interrupt or trap can occur during the

execution of a cache loop. See Section 3.5.2.7 and Section 5.4.11 of the

DSP16000 Digital Signal Processor Core

Information Man ual for details on saving and restoring the state of the c ache.

4.4 .13 Interr upt Polling

If a core disables an interrupt and tests its ins field, it can poll that int errupt instead of automatically servicing

it. This procedure, however, costs in the amoun t of code that must be written and executed to replace what the

DSP16000 core does by design.

The programmer can poll an interrupt source by checking its pending status in ins. The program can clear an inter-

rupt and change its status from pending to not pending by writing a 1 to its corresponding ins field. This clears the

field and leaves the remaining fields of ins unchanged. The example code segment below polls the MGU input

buff er full (MGIBF):

poll: a0=ins // Copy ins register contents to a0.

a0=a0&0x00000400 // Mask out all but bit 10.

if eq goto poll // If bit 10 is zero, then MGIBF not pending.

... // Interrupt is now pending -- service it.

ins=0x00400 // Clear MGIBF; don’t change other interrupts.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.5 Memory Maps

The DSP16000 core is a modified Harvard architecture with s ep arate program and data mem ory spaces

(X-memory space and Y-memory spac e). The core differentiates between the X- and Y-memory sp aces by the

addressing unit used for the access (XAAU vs. YAA U) and not by the physical memory accessed. The core

accesses its X-memory space via its 20-bit X address bus (XAB) and 32-bit X data bus (XDB). The core accesses

its Y-memory space via its 20-bit Y address bus (YAB) and 32-bit Y data bus (YDB).

The DMAU accesses pr ivat e intern a l memory (TPRAM〈0—1〉) via its 20-bi t internal Z address bus (ZIAB) and

32-bit internal Z data bus (ZIDB) and shared external memory1 (EIO and ERAM) via its 20-bit external Z address

bus (ZEAB) and 32-bit external Z data bus (Z ED B).

Although DSP16 411 memory is 16-bit word-addressable, data or ins truction widths can be ei ther 16 bits or 32 bits

and applications can access the memorie s 32 bits at a t ime.

Table 11 summ arizes the componen ts of the DSP16411 mem ory. The table specifies the name and size of each

component , whether it is internal or external, whether it is private to a core or shared by both cores, and in which

memory space(s) i t resides. The five memory spaces are CORE0’s X -memory space, CORE0’s Y-memory space,

CORE1’s X-memory space, COR E1’s Y -m em ory space, and the DMAU’s Z-memory space.

Table 11. DSP16411 M em ory Componen ts

The remainder of this section consists of the following:



Sect ion 4.5.1, Private Internal Mem ory, on page 39.



Sect ion 4.5.2, Sha red Internal I/O, on page 39.



Sect ion 4.5.3, Sha red External I/O and M emo ry, on page 39.



Section 4.5.4, X-Memory Map, on page 40.



Section 4.5.5, Y-Memory Maps, on page 41.



Sect ion 4.5.6, Z-M emo ry Maps, on page 42.



Section 4.5.7, Internal I/O Detailed Memory Map, on page 43.

1. Z EAB and ZEDB connect to EIO and ER AM thr ough the SEM I.

Type Memory

Component Size CORE0 CORE1 DMAU

X-Memory

Space Y-Memory

Space†X-Memory

Space Y-Memory

Space†Z-Memory

Space†

Private Int ernal TPRAM0 160 Kwords ✓ ✓ ✓

CACHE0 62 words ✓ ✓

IROM0 4 Kwords ✓

TPRAM1 160 Kwords ✓ ✓ ✓

CACHE1 62 words ✓ ✓

IROM1 4 Kwords ✓

Shared Int ernal Internal I/O‡128 Kwords ✓ ✓ ✓

Shared External EIO 128 Kwords ✓ ✓ ✓

ERAM 512 Kwords ✓ ✓ ✓

EROM 512 Kwords ✓ ✓

† Assumes that WEROM is 0 for normal operation. If WEROM is 1, ERAM is replaced by EROM in the memory space, allowing the normally

read-only EROM section to be written. WEROM is discussed in detail in Se ction 4.5.3 on page 39.

‡ The internal I/O section consists of 2 Kwords of SLM and memory-mapped registers in the SEMI, DMAU, PIU, SIU0, and SIU1 blocks. Only a

s m all portion of the 128 Kwords reserved for internal I/O is actually populated with memory or registers.

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4 Hardware Architecture (continued)

4.5 Memory Maps (continued)

4.5.1 Private Internal Memo ry

Each core has its own private internal memories for

program and data storage. CORE0 has IROM0,

CACHE0, and TPRAM0. CORE1 has IRO M1,

CACHE1, and TPRAM1. A core cannot directly access

the other core’s private memory. However , the DMAU

can access both TPRAM0 and TPRAM1 and can move

data between these two memories to facilitate core-to-

core communication (see Section 4.8 on page 46 ).

TPRAM is described in more detail in Secti o n 4.6 o n

page 44. Cache memory is described in detail in the

DSP16000 Digital Signal Processor Core

Information

Manual. IRO M contains boot and HDS code and is

described in Section 5 on page 208 .

4.5.2 Shared Interna l I/O

The 128 Kword internal I/O mem ory component is

accessible by both cores in their Y-memory spaces and

by the DMAU in its Z -memory space. Any access to

this memory component is made over the system bus

and is arbitrated by the SEMI. The internal shared I/O

memory component consists of:



2 Kwords of shared local memory (SLM). SLM can

be used for core-to-core communication (see

Section 4.8 on page 46). S LM is descr ibed in

Sect ion 4.1.4 on page 17.



Mem ory-map ped control and data registers within

the following peripherals:

—DMAU

—SEMI

—PIU

—SIU0

—SIU1

Only a small portion of the 128 Kwords reserved for

internal I/O is actually populated with memory or regis-

ters. Any access to the internal I/O memo ry compo-

nent takes multiple cycles to complete. DSP core or

DMAU writes take a m inimum of two CLK cycles to

comple te. DSP core or DMAU reads take a minimum

of five CLK cycles to complete .

4.5.3 Shared External I/O and Memory

External I/O and memory consists of three shared com-

ponents: EIO, ERAM, and EROM. EIO and ERAM are

accessible in the Y-memory spaces of both cores and

also in the DMAU’s Z-memory space. EROM is nor-

mally read-only and accessible only in the X-memory

spaces of both cores. If the programmer sets the

WEROM field in the memory-mapped ECON1 register

(see Table 61 on page 112), EROM takes the place of

ERAM in the Y-memory spaces of both cores and in

the DMAU’s Z-memory space (see Sect i on 4.5.5 on

page 41 and Section 4.5.6 on page 42 for details).

This allows the EROM compone nt to be written for pro-

gram downl oads to external X memory.

The phys ical size of the EIO, ERAM, and ERO M com -

ponent s can be expanded from the sizes defined in

Table 11 on page 38 by em ploying the ESEG[3: 0]

pins. The external memory system can use ESEG[3:0]

in either of the following ways:

1. ESEG[3:0] can be interpreted by the external mem-

ory system as four separate decoded add ress

enable signal s. Each ESEG[3:0] pin individually

selects one of four segments for each memory

component. This results in four glueless 512 Kword

(1 Mbyte) ERAM segments, four glueless 512 Kword

(1 Mbyte) EROM segment s, and four glueless

128 K word (256 KB) EIO segments .

2. ESEG[3:0] can be interpreted by the external mem-

ory system as an extension of the address bus, i.e.,

the ESEG[3:0] pins can be concatenated with the

EAB[18:0] pins to form a 23-bit address. This results

in one glueless 8 Mword (16 Mbytes) ERAM seg-

ment, one glueless 8 Mword (16 Mbytes) EROM

segment, and one glueless 2 Mword (4 Mbytes) EIO

segment.

See Section 4.14.1.5 on page 106 for details on c onfig-

uring the ESEG [3:0] pins.

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4 Hardware Architecture (continued)

4.5 Memory Maps (continued)

4.5.4 X-Memo ry M ap

Fi gure 6 . X-Memory Ma p

INTERNAL

EXTERNAL

0x00000

0x30FFF IROM

(PRIVATE†)

4 Kw ords

.................... ...

0x31000

0x80000

0x2FFFF

XMAP

.......................................

0x7FFFF

16 bits

0xFFFFF

..................................................

EROM (SHARED)‡

0x3FFFE

CACHE

(PRIVATE†)

RESERVED

0x27FFF 0x28000

0x3FFBF

62 words

†

is 0 for CORE0 or 1 for CORE1. Private memory can be accessed by the core with which it is associated. TPRAM0, CACHE0, and IROM0

c annot be accessed directly by COR E1. TPRAM 1, CACHE1, and IROM 1 can not be access ed directly by CORE0. Both TPRAM0 and

TPRAM1 can be accessed by the DMAU and PIU.

‡EROM can be configured as four glu eless 512 Kword (1 Mbyte) segments or one 8 Mword (16 Mbytes) segm ent. See Se ction 4.14.4.3 begin-

ning on page 114 for details. EROM is share d, i.e., is ac cess ible by both CO RE0 and CORE1, and is also accessible by the DMAU and the

PIU.

RESERVED

TPRAM

(PRIVATE†)

160 Kwords

0x30000

0x3FFC0

0x3FFFD

.......

0x3FFBF

0x28000

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4 Hardware Architecture (continued)

4.5 Memory Maps (continued)

4.5.5 Y-Memory Map s

Figure 7. Y -Memory Maps

†

is 0 f or COR E0 or 1 fo r CORE1 . Pr iv ate me mo ry can be a cce ssed by th e co re wit h wh ic h it is asso ci at ed. TPR AM0, CACHE 0 , and I RO M0

cannot be accessed direct ly by CORE1. TPRAM1, CACHE1, and IROM1 cannot be accessed directly by CO RE0. Both TPRAM0 and

TPRAM1 can be accessed by the DMAU and PIU.

‡ Internal I/O consists of shared local memory (SLM) and internal memory-mapped registers. See Section 4.5 .7 on page 43 for details.

§ A shared memory space is accessible by both CORE0 and CORE1, and is also accessible by the DMAU and the PIU.

†† EROM and ERAM can each be conf igured as four glueless 512 Kword (1 Mb yte) segments or one 8 Mword (16 Mbyt es) segment. EIO can

be configure d as four glueless 1 28 Kw ord ( 256 Mbytes) segment s or one glueless 2 Mword (4 Mbytes) segment. (S ee Section 4.14.4.3 on

page 114.)

CACHE

(PRIVATE

†

)

62 words

...................

0x3FFFE

0x3FFFF

RESERVED

0x3FFBF

YMAP

(WER OM = 0)

RESERVED

..............

0x7FFFF

16 bits

EIO

††

(SHARE D

)

0xFFFFF

...........................................

0x60000

INTERNAL I/O

‡

(SHARED

)

ERAM

††

(SHARE D

)

128 Kwords

TPRAM

(PRIVATE

†

)

160 Kwords

..............

0x40000

0x28000

128 Kwords

0x27FFF

0x80000

0x00000

...................

0x3FFC0

0x3FFFD

0x5FFFF

INTERNAL

EXTERNAL

CACHE

(P R IVAT E

†

)

62 words

...................

0x3FFFE

0x3FFFF

RESERVED

0x3FFBF

YMAP

(WER OM = 1)

RESERVED

..............

0x7FFFF

16 bits

EIO

††

(SHARE D

)

0xFFFFF

...........................................

0x60000

INT ERN AL I/O

‡

(SHARED

)

EROM

††

(SHARE D

)

12 8 K w ords

TPRAM

(PRIVATE

†

)

160 Kwords

..............

0x40000

0x28000

12 8 K w ords

0x27FFF

0x80000

0x00000

...................

0x3FFC0

0x3FFFD

0x5FFFF

Advance Data Sheet

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4 Hardware Architecture (continued)

4.5 Memory Maps (continued)

4.5.6 Z-Memory Map s

Figure 8. Z-Memory Maps

INTERNAL

EXTERNAL

† T he CMP[2:0] field in the DMAU address register (SADD〈0—5〉 or DADD〈0—5〉—Table 37 on page 77) or in the parallel address register

(PA—Ta ble 80 on page 138) selects either TPRAM0 or TPRAM1.

‡ Internal I/O consists of shared local memory (SLM) and internal memory-mapped registers. See Section 4.5 .7 on page 43 for details.

§ A shared memory space is accessible by both CORE0 and CORE1, and is also accessible by the DMAU and the PIU.

†† EROM and ERAM can each be conf igured as four glueless 512 Kword (1 Mb yte) segments or one 8 Mword (16 Mbyt es) segment. EIO can

be configure d as four glueless 1 28 Kw ord ( 256 Mbytes) segment s or one glueless 2 Mword (4 Mbytes) segment. (S ee Section 4.14.1.3 on

page 104.)

...................

0x3FFFF

RESERVED

ZMAP

(WE ROM = 0)

..............

0x7FFFF

16 bits

EIO

††

(SHARED

)

0xFFFFF

...........................................

0x60000

INT ER NAL I/O

‡

(SHARED

)

ERAM

††

(SHARED

)

128 Kwords

..............

0x40000

0x28000

128 Kwords

0x27FFF

0x80000

0x00000

.............................

0x5FFFF

TPRAM0† (160 K words)

TPRAM1† (160 K words)

0x28000

...................

0x3FFFF

RESERVED

ZMAP

(WER OM = 1)

..............

0x7FFFF

16 bits

EIO

††

(SHARE D

)

0xFFFFF

...........................................

0x60000

INT ERN AL I/O

‡

(SHARED

)

EROM

††

(SHARE D

)

12 8 K w ords

..............

0x40000

0x28000

12 8 K w ords

0x27FFF

0x80000

0x00000

.............................

0x5FFFF

TPRAM0† (160 Kwords)

TPRAM1† (160 Kwords)

0x28000

Advance Data Sheet

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4 Hardware Architecture (continued)

4.5 Memory Maps (continued)

4.5 .7 Internal I/O Detailed Me mory Map

Figure 9 is a detailed view of the 128 Kword internal I/O memory component shown in Figures 7 and 8. It consists

of a 4 Kword block for the memory-mapped registers of each peripheral and a 2 Kword block for the SLM . The

internal I/O memory component is directly accessible by both cores and by the DMAU and PIU. The SEMI controls

access to the internal I/O memory com ponent, which is subject to wait-state and c on tention penalties. T he SEM I

permits only 16-bit and aligned 32-bit accesses to the internal I/O memory component. The SEMI does not per m i t

misaligned 32-bit accesses (double-word acces ses with an odd address ) for the internal I/O m em ory component

because they produ ce undefined resu lts. An access to t he internal I/O memory componen t takes multiple clock

cycles to complete and a core access to the internal I/O memory component causes that core to incur wait-

states. See Section 4.14.7.1 on page 128 for details on system bus performance.

Figure 9. Internal I/O Memory Map

The memory-mapped registers located in their associated peripherals are each mapped to an even address. The

sizes of these registers are 16 bits, 20 bit s, or 32 bits. A regist er that is 20 bits or 32 bits mus t be accessed as an

aligned double word. A register that is 16 bits can be accessed as a single word with an even address or as an

aligned double word. If a register that is 16 bits or 20 bits is accessed as a double word, the contents of the register

are right-justified. Sec tion 6.2.2 on page 231 details the memory-mapp ed registers.

0x40000

0x40FFF

......

16 bits

SEMI REGIST ERS

†Although 4 Kwords are reserved for the memory-mapped registers of each peripheral, not all of the 4 Kwords are actually used.

PIU REGISTERS

DMAU REGISTERS

SIU0 REGISTERS

SIU1 REGISTERS

SLM (2 Kwords)

0x42000

0x42FFF

......

0x44000

0x44FFF

......

0x45800

0x5FFFF

...........................

0x41000

0x41FFF

......

0x43000

0x43FFF

......

0x45000

0x457FF

(4 Kwords†)

RESERVED

(106 Kwords)

Advance Data Sheet

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4 Hardware Architecture (continued)

4.6 Tripo rt Random -A cc ess Mem ory (TPRAM )

Each core has a private block TPRAM (TPRA M 0 and TPRAM1) consisting of 160 banks (banks 0—159) of zero

wait-state memory. Eac h bank co nsists of 1K 16-bit words and has three separate address and data ports: one

port to the core’ s instruction/coeff icient (X-memory) space, a second port to the core’s data (Y-memory) space, and

a third port to the DMAU’s (Z-memory) space. TPRAM is organized into even and odd interleaved banks for which

each even/odd addres s pair is a 32-bit wi de mod ule as illustrated in Figure 10. The core’s data buses (XDB and

YDB) and the DMAU’s data bus (ZIDB) are each 32 bits wide, and therefore 32-bit data in the TPRAM with an

aligned (even) address can be accessed in a single cycle. Typically, a misaligned double word is a ccessed in two

cycles.

Figure 10. Interl eave d Interna l TPRAM

Figure 11 illustrates an example arrangement of single words (16 bits) and double words (32 bits) in memory. It

also illustrates an aligned double word and a misaligned double word. See the

DSP16000 Digital Signal Processor

Core

Information Manual for details on word alignment and mi salignment w ait-states.

Example Me mory Ar rangement

Figure 11. Example Memory Arrangement

0x000

0x003

0x001

0x002

0x7FF0x7FE

11 LSBs

16 bits 16 bits

32 bits

EVEN BANK ODD BANK

ADDRESS

11 LSBs

ADDRESS

TPRA M MODULE

1K x 32 bits

(2 Kwords)

LESS SIGNIFICANT WORDMORE SIGNIFICANT WORD

SINGLE WORDSINGLE WORD0

SINGLE WORD

6LESS SIG NIF ICANT WORD SINGLE WORD

ADDRESS ADDRESS

ALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS

MISALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS

KEY:

16 bits

32 bits

EVEN BANK ODD BANK

LEAST SIGNIFICANT WORDMOST SIGNIFICANT WORD2

5MOST SIGNIFICANT WORD

LEAST SIGNIFICANT WORD

Advance Data Sheet

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4 Hardware Architecture (continued)

4.6 Tripo rt Random -A cc ess Mem ory

(TPRAM) (continued)

The core’s X and Y ports and the DM A U’s Z port c an

access separate mod ules within a T PR AM simu lta-

neously with no wait-states incurred by the core. If the

same module of TPRAM is accessed from multiple

ports simultaneously, the TPRAM automatically

sequences the accesses in the following priority order:

X port (instruction/coefficient), Y port (data), then Z

port (DMAU). This sequencing can cause the core to

incu r a conf li ct wait-s ta te . Because the co re must co m -

plete any consecutive accesses to a module of TPRAM

before the DMAU can access that module , the DMAU

can be blocked from accessing that module for a signif-

ican t n umb er of cycles.

4.7 Shared Local Memory (SLM)

Each core, the DMAU, and the PIU can access SLM

(shared local memory) through th e SEM I and the sys-

tem buse s (SAB and SDB). SL M is a 2 Kword block

located in the internal I/O memory component . SLM

supp orts both 16-bit and aligned 32-bit accesses, but

not 32-bit misaligned accesses .

The SEMI controls access to t he SLM, which is subject

to wait-state and contention penalties; see

Sect ion 4.14.7.1 on page 128 for details. Becaus e

access to the SLM is subject to wait -state and conten-

tion pena lties, it is not an efficient method for transfer-

ring large blocks of data between the cores. (An

efficient method is to use th e DMAU memory -to-mem -

ory (MMT) channel .)

Advance Data Sheet

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4 Hardware Architecture (continued)

4.8 Interprocessor Communication

Effective interprocessor (core-to-core) comm unication

requires synchronizat ion and acce ss to required data.

The following hardware mechanism s suppo rt access

synchronization:



The MGU provides core-to-core interrupts and traps.



The MGU provides message buffer interrupts and

flags.



DMAU interrupts.

The following mechani sms sup port data access:



The MGU can control the occurrence of a synchro-

nizing event (interrupt/trap) for in formation/s tatus

transfer.



The MGU provides data transfer through its full-

duplex mess age buffers (mgi and mgo).



The DMAU can copy data from one core’s TPRAM to

the other core’s TPRA M.



Cores can directly share data in external memory

(ERAM, EROM , or EIO spaces).



Cores can directly share data in the S LM .

Figure 12 illustrates the interprocessor communication

logic provided by MGU0 and MGU1.

Inter-Processor Communication Logic in MGU0 and MGU1

Figure 12. Interprocessor Communication Logic in MGU0 and MGU1

CORE0

MGU0

mgi

mgo

signal

pid

PTRAPMGOBF MGIBE MGIBF

FLAGS

DMINT[5:4]

(INTERRUPTS

FROM DMAU)

INTERRUPTS

SIGINTXIO

MUX

BIT 1 BIT 0

TRAP

CORE1

MGU1

mgi

mgo

signal

pid

PTRAP MGOBFMGIBEMGIBF

FLAGS

INTERRUPTS

SIGINT XIO

BIT 1BIT 0

imux

2 2

MUX

IMUX0 IMUX1

KEY: PROGRAM-ACCESSIBLE REGISTERS

imux

Advance Data Sheet

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4 Hardware Architecture (continued)

4.8 Interprocessor Communication (continued)

Note: Sharing data directly through external memory

(ERAM, EROM , or EIO spaces) or th e SLM is

the least efficient means of interprocessor com-

munication involving large blocks of data. It is

more eff icient to perform block memory-to-mem-

ory moves using a DMAU MMT channel. See

Section 4.7 on page 45 f or details on SLM and

Section 4.5.3 on page 39 for details on ERAM,

EROM, or EIO.

4.8.1 Core-to-Core Interrupts an d Traps

Software executing on one core can interrupt the other

core by writing a 1 to its own MGU signal register bi t 0

(Table 12). This causes the assertion of the other

core’s SIGINT interrupt signal.

The code seg men t below illustrates the code running

on one core to assert the SIGINT interrupt of the other

core:

signal=1 // interrupt other core

Software executing on one core can trap the other core

by writing a 1 to its own signal register bit 1. This

causes th e assertion of the other core’s PTR AP. As

shown in Figure 12 on page 46, the signal register bit 1

is logically ORed with the TRAP pin and the res ul t is

input to the other core’s PTRAP signal. (See

Section 4.4.10 on page 34 for more information on

PTRAP). Se e the code segment below:

signal=2 // trap other core

To ensure c orrect operation, the execut ion of the

signal register write instruction must be followed by the

execution of any instruction other than another signal

Table 12. signal Register

4.8.2 Messag e Buffer Data Exchan ge

Each core can use its MGU message buffers to transmit and receive status information to and from the other core.

A core can send a message to another core by writing to its own 16-bit output message register mgo. A core can

receive a message from anot her core by reading its own 16-bit input message register mgi.

If t he trans mitting core writes mgo, the following steps occur:

1. After two instruction cycles of latency, the transmitting core’s message output buffer full (MGOBF) condition flag

is set.

2. After an additional two instruction cycles of latency:



The DSP16411 copies the contents of the transmitting core’s mgo to the receiving core’s input message reg-

ister mgi.



The DSP16411 clears the receiving core’s message input buffer empty (MGIBE) condition flag.



The DSP16 411 asserts the receiving core’s m es sage input buffer ful l (MGIBF) interrupt.

15—11 1 0

Reserved SIGTRAP SIGINT

Bit Field Value Description R/W Reset

Value

1 5—11 Reser ved 0 Reserved—write w ith zero. W 0

1 SIGTRAP 0 No effect. W 0

1 Trap the oth er core by asserting it s PTRAP signal.

0 SIGINT 0 No effect. W 0

1 Interrupt the oth er core by asserting it s SIGINT int err upt.

Note: If th e program set s the SIGT RA P or SIGI NT fiel d, the M G U automa ticall y clears the field after ass erting th e t rap or i nter r upt. Therefore, the pro-

gram must not explicitly clear the field.

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4 Hardware Architecture (continued)

4.8 Interprocessor Communication (continued)

4.8.2 Messag e Buffer Data Exchan ge (continued)

The receiving core can use interrupt s or polling to

detect the presence of an incoming message. When

the receiving core reads mgi, t he foll owing steps occur:

1. After o ne in struction cycle of latency, the DSP16411

set s the recei ving core’ s MGIBE flag .

2. After an additional instruction cycle of latency, the

DSP16411 clears the transmitting core’ s MGOBF

flag.

4.8.2.1 Message Buffer Write Protocol

To ensure an older message has been processed by

the receiving core, the transmitting core must not write

a new message to mgo until its MGOBF flag is c leared.

The example code segm ent below is executed by the

transmitting core :

if mgobf goto . // Wait for old message

// to be read.

mgo=*r0++ // Write new message.

4.8.2.2 Messa ge Buffer Read Protocol

The receiving core can detect an incoming message by

enabling the MGIBF interrupt in the inc1 register

(Table 153 on page 241). T he following is an example

of a simple interrupt servic e routine f or the receiving

core:

ISR: a0h=mgi

*r0++=a0h // Read new message and

// clear MGIBF.

ireturn

As an alternative to the interrupt-directed message

buffer read protocol described above, the receiving

core can poll its MGIBE flag for th e arrival of a ne w

mess age. The example code s egm ent below is exe-

cuted by the receiving core:

if mgibe goto . // Wait for new

// message.

a0h=mgi

*r0++=a0h // Read new message.

The DSP16 411 can operate a full-duplex communica-

tion channel between CORE0 and CORE1, with each

core using its own mgi and mgo registers and its own

MGO B F and MGIBE flags. Table 13 illustrates two

code segments for a full-duplex data exchange of

words between CORE0 and CO RE1 . This segment

exchan ges two words (one input, one output) between

the two cores every 18 CLK cycles.

Table 13. F ull -Duplex Data Transfer Code Thro ugh Core -to-Core Messag e Buffer

CORE0 Message Buf fer Transfer Code CORE1 Message Buffer Transfer Code

c0=1-N

xfer: if mgobf goto .

mgo=* r0++ //W rite me ssag e to

//CORE 1 and set MG OBF.

//4 cycles latency

//unti l CORE1’ s MGIBE

//is cleared.

if mgibe goto . //Wait for CORE1

//message to arrive.

a0h=mgi

*r1++=a0h // Read CORE1 message

//and cl ear CORE 1’s

//MGOBF.

if c0lt goto xfer

c0=1-N

xfer: if mgobf goto .

mgo=*r0++ //Write message to

//CORE0 and set MGOBF.

//4 cycles latency

//until CORE0’s MGIBE

//is cl eared.

if mgibe goto . //Wait for CORE0

//message to arrive.

a0h=mgi

*r0++=a0h //Read CORE0 message

//and clear CORE0’s

//MGOBF.

if c0lt goto xfer

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4 Hardware Architecture (continued)

4.8 Interprocessor Communication (continued)

4.8.3 DMAU Data Transfer

The most effi c ient mechani sm for synchronous ly trans-

ferring l arge data blocks between the two cores is

through the two DM A U memory-to -memory (MMT)

channels, MMT4 and MMT5, described in detail in

Section 4.13.6, beginning on page 90. For example,

one core uses one MMT chan nel to transfer data and

the other core uses the ot her c hannel . In this way, a

transmitting core writes a message block via its MMT

channel and an interrupt notifies the receiving core

after the DMA transfer is complete. Table 14 summa-

rizes the MMT interrupts, DMINT4 and DMINT5, used

to synchronize DMAU tra nsfers. Both cores can moni-

tor both DMINT4 and DMINT5.

Table 14. DMAU MMT Channel Interrupts

If an MMT channel is dedicated to intercore transfers

and not used for intracore transfers, the tra ns mitting

and receiving cores can use the DMINT4 and DMINT5

interrupts directly to synchronize transfers. For exam-

ple, MMT4 ca n be dedicated to CORE0-to-CORE1

transfers and MMT5 can be dedicated to CORE1-to-

CORE0 transfers. In this case, DMINT4 interrupts

CORE1 if a message block from CORE0 is in memory,

and likewise, DMINT5 interrupts CORE0 if a message

block from CORE1 is in memory.

If an MMT channel is used for both intracore and inter-

core transfers, DMINT4 or DMI NT5 is used for synchro-

nizing intraco re transfers and the XIO interrupt is used

for synchronizing intercore transfers. Ea ch core pro-

grams the XIO interrupt for the other core via its

imux register (Table 5 on page 28). The XIOC[1:0]

field (imux[15:14]) selects XIO for the other core as

either zero (XIOC[1:0] = 0), DM INT4 (XIOC[1: 0] = 1),

or DMINT5 (X IOC[1:0] = 2).

Table 15 illustra tes an example confi guration for intrac-

ore and intercore transfers via DMA. This example

assig ns CORE0 to MMT4 and COR E1 to MMT5.

Table 15. DMA Intracore and Intercore Transfers Example

If a core uses an M MT c hannel for in tr acore t ransfers, i. e., not for transfers with t he ot her core, i t must first program

its XIOC[1:0] field (imux[15:14]) to zero. This prevents the MMT interrupt from disturbing the other core via its XIO

interrupt. The core must enable the corresponding MMT interrupt (DMINT4 or DMINT5) in i ts inc0 register

(Table 153 on page 241).

If a core uses its MMT channel for intercore transfers, i .e., f or tr ansmitting to the ot her core, i t must first program it s

XIOC[1:0] fi e ld (imux[ 15:14] ) to either 1 or 2 (DMINT4 or DMINT5). The receiving core must enable its XIO inter-

rupt in its inc1 reg ister (Table 153 on page 241) . The transmitting core must disable the corresponding MMT inter-

rupt (DMINT4 or DMINT5) in its own inc0 register.

DMAU

Channel Interrupt

Name Description

MMT4 DMINT4 MMT4 transfer complet e.

MMT5 DMINT5 MMT5 transfer complet e.

DMAU

Channel Intrac ore Intercore (Core-to-Core)

Transmitting Receiving

Core Interrupt imux[XIOC[1:0]] Core imux[XIOC[1:0]] Core Interrupt

MMT4 CORE0 DMINT4 0

(CORE1’s XIO = 0) CORE0 1

(CORE1’s XIO = DMINT4) CORE1 XIO (DMINT4)

MMT5 CORE1 DMINT5 0

(CORE0’s XIO = 0) CORE1 2

(CORE0’s XIO = DMINT5) CORE0 XIO (DMINT5)

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4 Hardware Architecture (continued)

4.9 Bit Input/Output Units (BIO〈0—1〉)

The DSP16411 has two bit I/O units, BIO0 f or CORE 0

and BIO1 for CORE1. Each BIO unit connects to

seven bidirectional pins, IO0BIT[6:0] for BIO0 and

IO1BIT[6:0] for BIO1. User software running in CORE0

controls and monitors BIO0 via its sbit and cbit regis-

ters. User software running in CORE1 controls and

monitors BIO1 via its sbit and cbit registers. The soft-

ware can:

■Individ ually configure each pin as an input or output.

■Read the current state of the pins.

■Test the comb ined state of input pins.

■Individ ually set, clear, or toggle output pins.

The DIREC[6:0] fiel d (sbit[14:8]—see Table 16) con-

trols the direction of the corresponding IO〈0,1〉BIT[6:0]

pin; a logic 0 configures the pin as an input or a logic 1

configures it as an output. Reset clears the

DIREC[6:0] field, configuring all BIO pins as inputs by

default. T he read-only VALUE[ 6: 0] field (sbit[6:0])

contains the current state of the corresponding pin,

regardless of whether the pin is configured as an i nput

or outp ut.

The cbit register ( Ta ble 17 on page 51) contains two

7-bit fields, MODE [6:0]/MASK[ 6:0] and

DATA[6:0]/PAT[6: 0]. The m eanin g of the individual

bits in these fields, MODE[

]/MASK[

] and

DATA[

]/PAT[

], is based on whet her the correspond-

ing IO〈0,1〉BIT[

] pin is configured as an input or an

output. If IO〈0,1〉BIT[

] is conf igured as an input, the

fields are MASK[

] and PAT[

]. If IO〈0,1〉BIT[

] is

configu red as an output, the fields are MODE[

] and

DATA[

]. Table 18 on page 52 summ arizes the func-

tion of the MODE[6:0]/MAS K[6:0] and

DATA[6:0]/PAT[6:0] fields.

If the software configures an IO〈0,1〉BIT[

] pin as an

output and:

■If the s oftware clears MODE[

] and clears DATA[

the BIO〈0,1〉 drives the pin low.

■If the software clears MODE[

] and sets DATA[

], the

BIO〈0,1〉 drives the pin high.

■If the software sets MODE[

] and clears DA T A[

], the

BIO does not change the state of the pin.

■If the software sets MODE[

] and sets DATA[

], the

BIO〈0,1〉 toggles (inverts) the state of the pin.

If an IO〈0,1〉BIT[

] pin is configured as an input and

the software sets MASK[

], the BIO〈0,1〉 tests the

state of t he pin by compa ring it to the PAT [

] (pattern)

field. B IO〈0,1〉 sets or clears its flags bas ed on the

result of the compariso n of all its t ested inputs:

■ALLT (all true) is set if all of th e tested inputs match

the test pattern.

■ALLF (all false) is set if all of the tested inputs do not

match the test pattern.

■SOMET (some true) is set if some or all of t he tested

inputs match the test pattern.

■SOMEF (some false) is set if some or all of the

tested inputs do not match the test pattern.

Table 16. s bit (BIO Statu s/C ontrol ) Register

15 14—8 7 6—0

Reserved DIREC[6:0] Reserved VALUE[6:0]

Bit Field Value Description R/W Reset

Value†

15 Reserved X Reserved—writing to this field has no functional effect. R/W 0

14—8 DIREC[6:0]

(Con trols direc-

tion of pins)

0Configure the corresponding IO〈0,1〉BIT[6:0] pin as an input. R/W 0

1Configure the corresponding IO〈0,1〉BIT[6:0] pin as an output.

7 Reserved X Reserved— value is read-only and is undefined. R 0

6—0 VALUE[6:0]‡

(Current va lue of

pins)

0The current state of the corresponding IO〈0,1〉BIT[6:0] pin is logic 0. RP

1The current state of the corresponding IO〈0,1〉BIT[6:0] pin is logic 1.

† For this column, X indicates unknown on powerup reset and unaffected on s ubseq uent reset.

‡ This field is read-only; writing the VALUE[6:0] field of sbit has no effect. I f the user software toggles a bit in the DIREC[6:0] f ield, there is a

latency of one cycle until the VALUE[6:0] field reflects the curr ent state of the corresponding IO〈0,1〉BIT[6:0] pin. If an IO〈0,1〉BIT[6:0] pin is

c o nfigured as an output (DIREC[6: 0] = 1) and the user software wri tes cbit to change the state of the pin, there is a latency of two cycl es until

the VALUE[6:0] field reflects the current state of the corresponding IO〈0,1〉BIT [6:0] output pin.

§ The IO〈0,1〉BIT[6:0] pins are configured as inputs after reset. If external circuitry does not drive an IO〈0,1〉BIT[

] pin, the VALUE[

] field is

undefined after reset.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.9 Bit Input/Output Units (BIO〈0—1〉)(continued)

Table 17. cbit (BIO Con trol) Registe r

If all the IO〈0,1〉BIT[6:0] pins are configured as outputs

or if the MASK[

] fie ld is cleared for all pins that are

configured as inputs, the BIO〈0,1〉 sets the ALLT and

ALLF flags and clears the SOMET and SOMEF flags.

Table 19 on page 52 summ arizes the BIO flags, which

software can test with conditional instructions (see

Table 138 on page 226) . S o ftw a r e can te st, save, o r

restore the s tat e of the flags by readi ng or writing the

alf register (see Table 144 on page 235). As illustrated

in Table 19 on page 52, ALLT is the logical inverse of

SOMEF and ALLF is the logical inverse of SOMET.

If an IO〈0,1〉BIT[

] pin is configured as an input and

the soft ware writes cbit to change the MASK[

] or

PAT[

] field , there is a late n cy of tw o cycle s until the

DSP16411 updates the BIO flags to reflect t he change.

The following code segment illustrates this latency by

the use of the two nop instructions:

sbit=0 // All pins are inputs.

cbit=0 // Test no inputs.

...

cbit=0x0302 // Test IOBIT[1:0].

2*nop // Any 2 instructions.

if allt goto OK // Branch if IOBIT1...

// is 1 and IOBIT0 is 0.

15 14—8 76—0

Reserved MODE[6:0]/MASK[6:0] Reserved DATA[6:0]/PAT[6:0]

Bit Field Value Description R/W Reset

Value

15 Reserved 0 Reserved—write with zero. R/W 0

14—8 MODE[6:0]

(outputs†)

†An IO〈0,1〉BIT[ 6:0] pi n i s confi gured as an out put if t he corres pondi ng DI REC [6: 0] field (sbit[1 4 : 8]) has be en se t by the us er s oftwa r e. An

IO〈0,1〉BIT[6: 0] pi n i s confi gured as a n inpu t if the cor responding DI REC[6: 0] fiel d has been cleared by the user sof twa re or by device r eset.

0 The BIO drives the corresponding IO〈0,1〉BIT[6:0] output pin to the corre-

sponding value in DATA[6:0]. R/W 0

1■If the corr espo nding DAT A[ 6: 0] fiel d is 0, the BIO does not change the st ate

of the corresponding IO〈0,1〉BIT[6:0] output pin.

■If the corresponding DATA[6: 0] f ield is 1, the BI O toggles ( inverts) th e state

of the corresponding IO〈0,1〉BIT[6:0] output pin.

MASK[6:0]

(inputs†)0 The BIO does not te st the s tate of the co rrespon din g IO〈0,1〉BIT[6:0] i nput pin

to determine the state of the BIO flags‡.

‡ The BI O flags ar e ALLT, ALLF, SO M ET, and SOME F. See Table 19 on page 52 f o r d etails on BIO flags.

1 The BIO compares th e state of the corr espon ding IO〈0,1〉BIT[6:0] i nput pin to

the corr espondi ng value in the P AT[6:0] fiel d to deter mine the st ate of the BIO

flags‡; tr ue if pin matches or false if pin doesn’t match.

7 Reserved 0 Reserved—write with zero. R/W 0

6—0 DATA[6:0]

(outputs†)0■If the corresponding MODE[6:0] field is 0, the BIO drives the corr esponding

IO〈0,1〉BIT[6:0] output pin to log ic 0.

■If the cor responding MODE[6: 0] fi eld is 1, the BIO does not change the

state of the corresponding IO〈0,1〉BIT[6:0] output pin.

R/W 0

1■If the corresponding M ODE[6:0] f ield is 0, the BI O drives the correspo nding

IO〈0,1〉BIT[6:0] output pin to log ic 1.

■If the cor responding MODE[6: 0] fi eld is 1, the BIO toggl es (inverts) t he

state of the corresponding IO〈0,1〉BIT[6:0] output pin.

PAT[6:0]

(inputs†)0 If the corresponding MASK[6: 0] fie ld i s 1, the BIO tests the state of the cor re-

sponding IO〈0,1〉BIT[6:0] input pin to dete rmine the state of t he BIO fl ags ‡;

true i f pi n is l ogic 0 or false if pin is logic 1.

1 If the corr esponding MASK[6: 0] fie ld i s 1, the BIO tests the state of the cor re-

sponding IO〈0,1〉BIT[6:0] input pin to dete rmine the state of t he BIO fl ags ‡;

true i f pi n is l ogic 1 or false if pin is logic 0.

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

52 A gere System s— P rop rietary Agere Systems In c.

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4 Hardware Architecture (continued)

4.9 Bit Input/Output Units

(BIO〈0—1〉)(continued)

If an IO〈0,1〉BIT[

] pin is configured as an output and

the soft ware writes cbit to change the state of the pin,

there is a latency of one cycle until the DSP1641 1

changes the state of the pin and a latency of an a ddi-

tional cycle until the VALUE[

] field (sbit[6:0]) reflects

the change. The use of two nop in s t ru c tions in t he fol-

lowing code segment illustrates this latency:

sbit=0x1000 // IOBIT4 is an output.

cbit=0x0010 // Drive IOBIT4 high.

nop // IOBIT4 goes high.

nop // VALUE4 is updated.

a0h=sbit // Bit 4 of a0h is 1.

If t he sof tware writes sbit to change an IO〈0,1〉BIT[

]

pin from an input to an output or from an outpu t to an

input, there is a lat ency of one cycle before the

VALUE[

] field of sbit is updated to reflect the state of

the pin. If the software writes sbit to change an

IO〈0,1〉BIT[

] pin from an output to an input and back

to an output, the B I O drives the pin with its original out-

put value.

The following code segment illustrates the latency

describ ed in the previous paragraph:

sbit=0x0F00 // IOBIT[3:0] - output.

cbit=0x000A // IOBIT[3:0] = 1010

// ...after 1 cycle.

cbit=0x0101 // Toggle IOBIT0...

// IOBIT[3:0] = 1011

// ...after 1 cycle.

sbit=0 // IOBIT[3:0] - input.

sbit=0x0F00 // IOBIT[3:0] - output.

// IOBIT[3:0] = 1011

// ...after 0 cycles.

nop // Any instruction.

a0h=sbit // a0h[3:0] = 1011.

Table 18. BIO Operatio ns

Table 19. BIO Flags

DIREC[

]†

†0 ≤ n ≤ 6.

MODE[

MASK[

]†DATA[

PAT[

]†BIO Action

(Output) 00

Clear IO〈0,1〉BIT[

1Se t IO 〈0,1〉BIT[

Do not change

IO〈0,1〉BIT[

1Toggle IO〈0,1〉BIT[

(Input) 0X

Do not test ‡

IO〈0,1〉BIT[

‡ The B IO te sts the state of input pins to determine the sta tes of the

BIO flags. See Table 19 for details on the BIO flags.

Test‡ IO〈0,1〉BIT[

]

fo r logic ze ro.

1Test‡ IO〈0,1〉BIT[

]

for l ogic one.

Condition ALLT

(alf[0]) ALLF

(alf[1]) SOMET

(alf[2]) SOMEF

(alf[3])

All or som e of the

IO〈0,1〉BIT[6:0] pins are

configured as inputs.†

† For at least one pin IO〈0,1〉BIT[

], DIREC[

]=0.

All tested inputs match the pattern.‡

‡ For every pin IO〈0,1〉BIT[

] with DIREC[

] = 0 an d MA S K [

]=1, IO〈0,1〉BIT[

]=PAT[

101 0

All tested inputs do not match the patt ern.§

§ For every pin IO〈0,1〉BIT[

] with DIREC[

] = 0 an d MA S K [

]=1, IO〈0,1〉BIT[

]≠PAT[

010 1

Some (but not all) of the tested input s match the pattern.††

†† For at least one pin IO〈0,1〉BIT[

] with DIREC[

] = 0 and MAS K[

]= 1, IO〈0,1〉BIT[

]=PAT[

], and for at least one pin IO〈0,1〉BIT[

] with

DIREC[

] = 0 and MASK[

] = 1, IO〈0,1〉BIT[

]≠PAT[

001 1

All of the in puts are not tested.‡‡

‡‡ For all pins IO〈0,1〉BIT[

] with DIREC[

]= 0, MASK[

]=0.

110 0

All IO〈0,1〉BIT[6:0 ] pins are configur ed as outputs. §§

§§ DIR EC [ 6:0 ] ar e all on es .

110 0

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4 Hardware Architecture (continued)

4.10 Timer Units (TIMER0_〈0—1〉 and

TIMER1_〈0—1〉)

The DSP16411 provides two timer units for each core:

TIMER0_0 and TIMER1_0 for CORE0 and TIMER0_1

and TIMER1_1 for CORE1. Each TIM ER provides a

programmable single interval interrupt or a programma-

ble periodic interrupt. Figure 13 on page 54 is a block

diagram of a TIMER that contains:

■A 16-bit control register timer〈0,1〉c (see Table 2 0

on page 55).

■A running count register timer〈0,1〉 (see Table 21 on

page 56) consisting of a 16-bit down counter and a

16-b it period register.

■A prescaler that divides the internal clock (CLK) by

one of 16 programmed values in the range 2 to

65536. T he pres caler output clock decre men ts the

timer〈0,1〉 down count er. The program me d pres-

cale value and the value written to timer〈0,1〉 deter-

mine the interrupt int erval or period.

By default after device reset1, the DSP16411 clears

timer〈0,1〉c and powers up the TIMER. To save power

if the TIMER is n ot in use, the software can set the

PWR_DWN field (timer〈0,1〉c[6]). Until the user soft-

ware writes to timer〈0,1〉c and timer〈0,1〉, the TIMER

does not operate or generate interrupts.

Note: The software can read or write timer〈0,1〉 only if

the TIMER is powered up (PWR_DWN = 0).

If t he sof tware reads timer〈0,1〉, the value read is the

output of the down counter. If the software writes

timer〈0,1〉, the T IME R loads the write value into the

down counter and into the period register simulta-

neously.

The prescaler consists of a 16-bit up counter and a

multiplexer controlled by the PRESCALE[ 3:0] field

(timer〈0,1〉c[3:0]). PRESCALE[3:0] contains a

value N that selects the period of the prescaler output

clock a s:

where fCLK is the frequency of the internal clock (s ee

Section 4.17 on page 200 ).

To operate the TIMER (i.e., for the prescaler to decre-

ment the timer〈0,1〉 down counter), the user software

must perform the following steps.

■Write timer〈0,1〉c to program its fields as follows:

—Write 0 to the PWR_DWN field.

— Write 0 to the RELOAD field (timer〈0,1〉c[5]) fo r a

single interval interrupt or write 1 to the RELOAD

field for periodic interrupts.

— W rite 1 to t he COUNT field (timer〈0,1〉c[4]) to

enable the prescaler output clock.

— P rogram the PRE SCALE[ 3:0] field to configure

the frequenc y of the prescaler output clock.

■Write a nonzero value to timer〈0,1〉 to enable the

down counter input clock.

The software ca n perform the above steps in either

order, and the TIMER starts after the second step.

If the TIMER is operating and the timer〈0,1〉 down

counter reaches zero, the TIMER asserts its interrupt

reques t pulse TIME〈0,1〉 (see Section 4.4, beginning

on page 25, for details on interrupts). The interval from

starting the TI M ER to the occurrence of the first int er-

rupt is the following:

If the down counter reaches zero and RELOAD is 0,

the TIMER disables the input clock to t he down

coun ter, causing the down counter to hold its current

value of zero. The user software can restart the

TIME R by writing a nonzero value to timer〈0,1〉.

If the down counter reaches zero and RELOAD is 1, a

prescale period elapses and the TIMER reloads the

down counter from the timer〈0,1〉 period register.

Another presc ale period elapses and the prescaler

decrem ents the down counter. Th erefore , the subse-

quent interval between periodic interrupts i s the follow-

ing:

Software can read or write timer〈0,1〉 while the timer is

running. If the software writes timer〈0,1〉, the TIMER

loads the write value into the down counter and period

16-bit up counter. Bec ause the TIME R initializes the

prescaler if the software writes timer〈0,1〉, the interval

from writing timer〈0,1〉 to decrem ent ing the down

counter is one complete prescale period.

Clearing COUNT disables the clock to the prescaler,

causi ng the down counter to hold its current v al ue and

the prescaler to retain its c urrent state. If the TIMER

remains powered up (PWR_DWN = 0), software can

stop and restart the TIMER at any time by clearing and

setting COUNT.

1. After device reset, the DSP16411 clears the down counter of timer〈0,1〉 and leaves the period register of timer〈0,1〉 un change d.

2N1+

fCLK

-------------

timer〈0,1〉2N1+

fCLK

-------------------------------------------------

timer〈0,1〉1+()2N1+

fCLK

---------------------------------------------------------------

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

54 A gere System s— P rop rietary Agere Systems In c.

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any instructions

4 Hardware Architecture (continued)

4.10 Timer Units (TIMER0_〈0—1〉 and TI ME R 1 _〈0—1〉)(continued)

Figure 13. Timer Block Diagram

15—7 6 5 4 3—0

RESERVED PWR_DWN RELOAD COUNT PRESCALE[3:0]

16-bit RELOAD VALUE

16-bit DOWN COUNTER

timer〈0,1〉c

timer〈0,1〉

(PERIOD) REGISTER

16-bit

COUNTER

MUX

CLR

MUX

CLK

PRESCALER

COUNTER = 0 (LEVEL)

CLK

N1+

-------------

LOAD

timer〈0,1〉

TIME

〈0,1〉

INTERRUPT

PULSE

IDB[15:0]

TO CORE

KEY: PROGRAM-ACCESSIBLE

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4 Hardware Architecture (continued)

4.10 Timer Units (TIMER0_〈0—1〉 and TI ME R 1 _〈0—1〉)(continued)

Table 20. timer〈0,1〉c (TIMER〈0,1〉 Contr ol) Reg ister

15—7 6 5 4 3—0

Reserved PWR_DWN RELOAD COUNT PRESCALE[3:0]

Bit Field Value Description R/W Reset

Value

15—7 Reserved 0 Reserved— write with zer o. R/W 0

6 PW R_DWN 0 Power up the timer. R/W 0

1 Power dow n the timer†.

5 RELOAD 0 Stop decrementing the down counter aft er i t reaches zero. R/W 0

1 Automatically reload the down coun ter fr om the period regist er after

the counter r eaches zero and cont inue decrem enting the counter

indefinitely.

4 COUNT 0 Hold the down counter at its curr ent value , i.e., stop th e ti me r. R/W 0

1 Decrement the down counter, i.e., run the timer.

3—0 PRESCALE[3:0] 0000 Controls the count er prescaler to determ ine the fre-

quency of the timer, i.e., the frequency of the clock

appli ed to the tim er down counter. This freq uency is a

ratio of t he internal clock frequency fCLK.

fCLK/2 R/W 0000

0001 fCLK/4

0010 fCLK/8

0011 fCLK/16

0100 fCLK/32

0101 fCLK/64

0110 fCLK/128

0111 fCLK/256

1000 fCLK/512

1001 fCLK/1024

1010 fCLK/2048

1011 fCLK/4096

1100 fCLK/8192

1101 fCLK/16384

1110 fCLK/32768

1111 fCLK/65536

† If TIMER〈0,1〉 is powered down, timer〈0,1〉 cannot be read or written. While the timer is powered down, the state of the down counter and

period register remain unchanged.

Advance Data Sheet

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56 A gere System s— P rop rietary Agere Systems In c.

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4 Hardware Architecture (continued)

4.10 Timer Units (TIMER0_〈0—1〉 and TI ME R 1 _〈0—1〉)(continued)

Table 21. timer〈0,1〉 (TIMER〈0,1〉 Running Count) Register

4.11 Hardware Development System

(HDS〈0—1〉)

The DSP16411 prov ides an on-chip hardware develop-

ment module for each of the two cores (HDS〈0—1〉).

Each HDS is available for debugging assembly-

language programs that execute on the DSP16000

core at the core’s rated speed. The main capability of

the HDS is allowing controlled visibility into the core’s

state during program executio n.

The fundament al steps in debugging an appl ication

using the HDS include the following:

1. S etup : Download program code and data into the

correct memory regions and set breakpointing con-

ditions.

2. Run: Start execution or single step from a desired

starting point (i.e ., allow device to run under simu-

lated or real-tim e conditions).

3. Break: Break program execution on satisfying break-

pointing conditions; upload and allow user accessi-

bility to int ernal sta te of the device and its pins.

4. Res um e: Res um e execution (normal ly or single

step) after hitting a breakpoint and finally upload

internal state at the end of execution.

A power ful deb ugging capab ilit y of the HDS is the abil-

ity to break program exec ution on comple x breakpoint-

ing conditions . A complex breakpoint condition, for

example, can be an instruction that executes from a

particular instruction-address location (or f rom a partic-

ular instruction-address range suc h as a subroutine)

and accesses a coefficient/data element from a spe-

cific memory location (or from a memory region such

as inside an array or outside an array). Complex condi-

tions can also be chained to form more complex break-

point conditions. For example, a complex breakpoint

condition can be defined as the back-to-back execution

of two different subroutines.

The HDS also provides a debugging feature that allows

a number of complex breakpoin ts to be ignored. Th e

number of breakpoints ignored is programmable by t he

user.

An intelligent trace mechanism for recording disconti-

nuity poin ts during program executio n is also available

in the HDS. This mechani sm allows unambi guous

reconstr uction of program flow involving discontinuit y

points such as gotos, calls, returns, and interrupts. The

trace mechanism com presse s single-level (non-

nested) loops and records them as a single discontinu-

ity. Th is feature prev ents single-level loops from filling

up the trace buffers. Also, cache loops do not get reg-

istered as discontinuit ies in the trace buff ers. There-

fore, two-level loops with inner cache loops are

registered as a single discontinuity.

The HDS provides a 32-bit cy cle count er for accurate

code profiling during program development. The cycle

counter records processor CLK cycles between a user-

defin ed start point and end point. The cycle cou nter

can optionally be used to break program execution

after a user-specified num ber o f clock cycles.

15—0

TIMER〈0,1〉 Down Counter

TIMER〈0,1〉 Period Register

Bit Field†Description R/W‡Reset

Value§

15—0 Down Counter If the COUNT field (timer〈0,1〉c[4]) is set, TIMER〈0,1〉 decrements this portion

of the timer〈0,1〉 register every prescale period. When the down counter

reaches zero, TIMER〈0,1〉 generates an interrupt.

R/W 0

15—0 Period Register If the COUN T field (timer〈0,1〉c[4]) and the RELOAD field (timer〈0,1〉c[5]) are

both set and the down counter contains zero, TIMER〈0,1〉 reloads the down

counter with the contents of this portion of the timer〈0,1〉 register.

† If the user program writes to the timer〈0,1〉 register, TIMER〈0,1〉 loads the 16-bit write value into the down counter and into the period register

simultaneously. If the user program reads the timer〈0,1〉 register, TIMER〈0,1〉 returns the current 16-bit value from the down counter.

‡ To read or write the timer〈0,1〉 register, TIMER〈0,1〉 must be powered up, i.e., the PWR_DWN field (timer〈0,1〉c[6]) must be cleared.

§ For this column, X indicates unknown on powerup reset and unaffected on s ubseq uent reset.

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4 Hardware Architecture (continued)

4.12 JTAG Test Port (JTAG〈0—1〉)

The DSP16411 prov ide s an on-chip

IEEE

1149.1 com-

pliant JTAG port for each of the t wo cores

(JTAG〈0—1〉). JTAG is an on-chip hardware module

that controls the HDS. All communication between the

HDS software, running on the host computer, and the

on-chip HDS is in a bit-serial manner through the JTAG

port. The JTAG port pins consist of test data input,

TDI〈0—1〉, test data output, TDO〈0—1〉, test mo de

select , TM S〈0—1〉,

test clock, TCK〈0—1〉, an d test

reset, TRST〈0—1〉N.

The set of test registers includes the JTAG identif ica-

tion register (ID), the boundary-scan register, and the

scanna ble periphe ral registers.

4.12.1 Port Identification

Each JTAG port has a read-only identification register,

ID, as defined in Table 22. As specified in the table, the

contents of the ID regi ster for JTAG0 is 0x1C81532 1

and the cont ents of the ID register for JTAG1 is

0x0C 815321.

Table 22. ID (JTAG Identification) Register

31—28 27—19 18—12 11—1 0

DEVICE OPTIONS ROMCODE PART ID AGERE ID One

Bit Field Value Description R/W Reset Value

31—28 DEVICE OPTIONS 0x1 JTAG0— device options. R 0x1

0x0 J TAG 1—d evice options. 0x0

27—19 ROMCODE 0x190 ROMCODE of device. 0x190

18—12 PART ID 0x15 Part ID—DSP1 6411. 0x15

11—1 AGERE ID 0x190 Agere identificati on. 0x190

0 On e 1 Logic one. 1

Advance Data Sheet

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4 Hardware Architecture (continued)

4.12 JTAG Test Port (JTAG〈0—1〉)(continued)

4.12.2 Emulation Interface Signals to th e DSP16411

For in-circuit e mul ation and application software

debugging, the Agere

TargetView

™ Commu nicat ion

System (TCS) provides communication between a host

PC and one or more DSP16411 devices. Users of the

TCS hardware have the option of using one of three

connectors to interface this tool wit h DSP16411

devices on the target application. The pinouts for these

connectors are described in the following three sec-

tions.

4.12.2.1TCS 14-Pin Header

The TCS interface pod provides a 14-pin, dual-row

(0.10 in. x 0.10 in.) socket (female) for connection to

the user’s target hardware. Figure 14 illu st ra t es the

pinout of this connector. Table 23 describes the signal

names and their relationship to the DSP16411 si gnals.

Figu re 14 . TCS 1 4- P in Co nn e ct or

5-7333 (F)

PIN 1 PIN 13

PIN 2 PIN 14

Table 23. T CS 14-Pin Socke t Pinout

TCS Pin

Number TCS Signal

Name Description TCS

I/O DSP16411

Pin Number DSP16411

Signal Name DSP16411

I/O

1 TCK Test clock O F4 and L13 TCK0 and TCK1 I

2 NC No connect NA N A NA NA

3 Ground System ground G See Se cti on 7 on page 253 VSS G

4 Ground System ground G See Secti on 7 on page 253 VSS G

5 TMS Test mode select O G2 and K15 TMS0 and TMS1 I

TARG Target I/O vol tage I See Secti on 7 on page 253 VDD2P

7 NC No connect NA N A NA NA

8 NC No connect NA N A NA NA

9 TDO Test data output I F1 or L16 (not both) TDO0 or TDO1 (not both) O

10 TDI Test data input O G1 or K16 (not both) TDI0 or TDI1 (not both) I

11 Ground System ground G See Secti on 7 on page 253 VSS G

12 Ground System ground G See Secti on 7 on page 253 VSS G

13 NC No connect NA NA NA NA

14 NC No connect NA NA NA NA

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4 Hardware Architecture (continued)

4.12 JTAG Test Port (JTAG〈0—1〉)(continued)

4.12.2 Em ulation Interface Signals to the

DSP16411 (continued)

4.12.2.2 JCS 20-Pin Header

The TCS tools provide an interface adapter to convert

the 14-pin interface pod to a 20-pin dual-row

(0.05 in. x 0.10 in.) socket (female,

® part number

82020-6 006) for connection to the user ’s target hard-

ware. Figure 15 illustra te s the pinout of th is

connector. Table 24 describes the signal names and

their relationship to the DSP16411 signals. This con-

nector is also compatible with the Agere JTAG comm u-

nications system (JCS) tools.

Figure 15. JCS 20-P in Connector

5-7334 (F)

PIN 19

PIN 20

PIN 1

PIN 2

Table 24. JCS 20-Pin Socket Pinout

JCS Pin

Number JCS Signal

Name Description JCS I/ O DSP16411

Pin Num ber DSP16411

Signal Name DSP16411 I/O

1 NC No connect NA NA NA NA

2 Ground System ground G See Section 7 on page 253 VSS G

3 NC No connect NA NA NA NA

4 NC No connect NA NA NA NA

5 NC No connect NA NA NA NA

6 TMS Test mode sel ect O G2 and K15 TMS0 and TMS1 I

7 Ground System ground G See Section 7 on page 253 VSS G

TARG Target I/O voltage I See Section 7 on page 253 VDD2P

9 NC No connect NA NA NA NA

10 Ground System ground G See Section 7 on page 253 VSS G

11 NC No connect NA NA NA NA

12 TDI Test data input O G1 or K16 (not both) TDI0 or TDI1 (no t both) I

13 Ground System ground G See Section 7 on page 253 VSS G

14 TCK Test clock O F4 and L13 TCK0 and TCK1 I

15 Ground System ground G See Section 7 on page 253 VSS G

16 TDO Test data output I F1 or L16 (not bot h) TDO0 or TDO1 (not bot h) O

17 NC No connect NA NA NA NA

18 Ground System ground G See Section 7 on page 253 VSS G

19 NC No connect NA NA NA NA

20 NC No connect NA NA NA NA

Advance Data Sheet

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4 Hardware Architecture (continued)

4.12 JTAG Test Port (JTAG〈0—1〉)(continued)

4.12.2 Em ulation Interface Signals to the

DSP16411 (continued)

4.12.2.3 HDS 9-Pin, D-Type Connector

The TCS tools also provide an interface adapter to con-

vert the 14-pin interface pod to a 9-pin, subminiature,

D-type plug (male) for connection to the user ’s target

hardware. Figure 16 illustrates the pinout of this

connector. Table 25 desc ribes th e signal names and

their relationship to the DSP16411 signals. T his con-

nector is also compatible with the Agere JTAG comm u-

nications system (JCS) and hardware developme nt

system (HDS) tools.

Figu re 1 6. HDS 9 -Pi n C o nnec tor

5-7335 (F)

PIN 5

PI N 9

PIN 1

PIN 6

Table 25. HDS 9-Pin, Subminiature, D-Type Plug Pinout

HDS Pin

Number HDS Signal

Name Description HDS I/O DSP16411

Pin Number DSP16411

Signal Name DSP16411

I/O

1 Ground System ground G See Sectio n 7 on page 253 VSS G

2 TCK Test clock O F4 and L13 TCK0 and TCK1 I

3 NC No connect NA NA NA NA

4 TMS Test mode sel ect O G2 and K15 TMS0 and TMS1 I

5 Ground System ground G See Section 7 on page 253 VSS G

6 TDO Test data output I F1 or L16 (not both) TDO0 or TDO1

(not bot h) O

7 TDI Test data input O G1 or K16 (not both) TDI0 or TDI1

(not bot h) I

TARG Target I/O vol tage I See Sectio n 7 on page 253 VDD2P

9 NC No connect NA NA NA NA

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4 Hardware Architecture (continued)

4.12 JTAG Test Port (JTAG〈0—1〉)(continued)

4.12.3 Multiprocessor JT AG Connections

The DSP16411 has two JTAG ports , one for each

DSP16000 core. The user can daisy chain these ports

onto the same scan chain, potentially with other

DSP16411 devices, or interface to each JTAG port indi-

vidually for debuggin g. If multiple JTAG ports are inter-

faced together on the same scan chain, TMS and TCK

are broadcast to all DS Ps in t he scan chain. TDI of the

first JTAG port in the chain is then c onne cted to TDI of

the TCS connector on the user’ s board, TDO of the first

JTAG port is connected to TDI of the next JTAG port in

the chain, and so on. TDO of the last J TAG port in the

chain is then tied to TDO of the TCS connector. If

more than six JTAG ports are in the same scan chain,

TMS and TCK must be buffered to ensure compatibility

with t155 and t156 (See Table 195 on page 280). In

the typica l application, the user’s board ties the

DSP1641 1 JTAG reset signals, TRST0N and TRST1N,

to the device reset, RSTN. Figure 17 illustrates a typi-

cal daisy-chain connection between the TCS hardware

and the two cores of a single DSP16411.

Note: CORE0 is DSP1 on the scan chain and CORE1 is DSP2 on the scan chain. For multiple DSP16411 device s on a single sc an chain,

maintain the CORE0-to-CORE1 daisy-chain.

Figur e 17 . Typical Multiprocess or JTAG Connecti on with Single Sca n Chain

JCS/TCS

TDOTCK TMS TDI

TCK0 TMS0 TDI0 TDO0 TCK1 TMS1 TDI1 TDO1

CORE1CORE0

RESET

TRST0N

TRST1N

RSTN DSP16411

Advance Data Sheet

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4 Hardware Architecture (continued)

4.12 JTAG Test Port (JTAG〈0—1〉)(continued)

4.12.4 Boundary Scan

JTAG0 c ontains a full boundary- scan register as described in Table 26 and JTAG1 contains a single-bit boundary-

scan register as described in Table 27 on page 63. As described in Section 4.12.3 on page 61, JTAG0 and JTAG1

of multiple DSP16411 devices c an be chained together with full boundary-scan capabilities.

Table 26. J TAG0 Boundary -Sca n Register

Cell Type†Signal Name/

Function Control

Cell Cell Type†Signal Name/

Function Control

Cell

0 I ERTYPE — 87 DC I O1BIT[1] direction control —

1 I EXM — 88 I/O IO1BIT[1] 87

2 I ESI ZE — 89 DC IO 1BIT[2] direction control —

3 I EREQN — 90 I/O IO1BIT[2] 89

4 I ERDY — 91 DC IO1BIT[3] directi on control —

20—5 I/O ED[15:0] 21 92 I/O IO1BIT[3] 91

21 DC ED[15:0] direction control — 93 DC IO1BIT[4] di rection control —

37—22 I/O ED[31:16] 38 94 I/O IO1BIT[4] 93

38 DC ED[31:1 6] di rection control — 95 DC IO1BIT[5] direction control —

39 O EACKN 65 96 I/O IO1BIT[5] 95

41—40 O ERWN[1:0] 45 97 DC IO1BIT[6] direct ion contro l —

42 O EROMN 45 98 I/O IO1BIT[6] 97

43 O ERAMN 45 99 DC IO1BIT[7] directi on control‡ —

44 O EION 45 100 I/O IO1BIT[7]‡99

45 OE EION, ERAMN, EROMN,

ERWN[1:0] 3-state control — 104—101 I PADD[3:0] —

64—46 O EA[18:0] 65 105 I PCSN —

65 OE EA[18:0] 3-state contr ol — 106 I PRWN —

69—66 O ESEG[3:0] 70 107 I PIDS —

70 OE ESEG [3:0] 3-state control — 108 I PODS —

71 OE ECKO and EACKN

3-state control — 109 I PRDYMD —

72 O ECKO 71 110 O PINT 114

73 OE SOD1 3-state control — 111 O P RDY 114

74 O SOD1 73 112 O PIBF 114

75 I SID1 — 113 O POBE 114

76 I SCK1 — 114 OE PINT, PRDY, PIBF,

POBE 3-state control —

77 DC SOFS1 di rection contr ol — 130—115 I/O PD[15:0] 131

78 I/O SOFS1 77 131 DC PD[15:0] direction control —

79 DC SOCK1 direction cont rol — 132 I EYMODE —

80 I/O SOCK1 79 133 DC IO0BIT[0] direct ion control —

81 DC SIFS1 directi on cont rol — 134 I/O IO0BIT[0] 132

82 I/O SIFS1 81 135 DC IO 0BIT[1] direct ion control —

83 DC SICK1 direction contr ol — 136 I/O IO0BIT[1] 134

84 I/O SICK1 83 137 DC IO0BIT[2] dir ection cont rol —

85 DC IO1BIT[ 0] di rection co ntr ol — 138 I/O IO0BIT[ 2] 13 6

86 I/O IO1BIT[0] 85 139 DC IO0BIT [3] directi on control —

† Key to this column: I = input; OE = 3- state control cell; O = output; D C = bidirec tional control cell; I/O = input/output.

‡ There is no pin a ssociated with this signal.This is a pad only and is not connected in the package.

Advance Data Sheet

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Agere Systems In c. Agere Systems—P ropri etary 63

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4 Hardware Architecture (continued)

4.12 JTAG Test Port (JTAG〈0—1〉) (continued)

4.12.4 Boundary Scan (continued)

140 I/O IO0BIT[3] 138 153 DC SOFS0 direction control —

141 DC IO0BIT[4] di rection co ntrol — 154 I/O SOFS0 152

142 I/O IO0BIT[4] 140 155 DC SOCK0 directi on cont rol —

143 DC IO0BIT[5] di rection co ntrol — 156 I/O SOCK0 154

144 I/O I O0BIT[5] 142 157 DC SIFS0 direction control —

145 DC IO0BIT[6] di rection co ntrol — 158 I/O SIFS0 156

146 I/O I O0BIT[6] 144 159 DC SICK0 direction control —

147 DC IO0BI T[7] directi on control‡— 160 I/O SICK0 158

148 I/O IO0BIT[7]‡146 164—161 I INT[3:0] —

149 OE SOD0 3-stat e control — 165 DC TRAP direc ti on control —

150 O SOD0 148 166 I/O TRAP 164

151 I SID0 — 167 I RSTN —

152 I SCK0 — 168 I CKI —

Table 27. JTAG1 Boundary -Sca n Register

Cell Function Control Cell

0 Interna l Cel l —

Table 26. JTAG0 Boundary -Sca n Register (continued)

Cell Type†Signal Name/

Function Control

Cell Cell Type†Signal Name/

Function Control

Cell

† Key to this column: I = input; OE = 3- state control cell; O = output; D C = bidirec tional control cell; I/O = input/output.

‡ There is no pin a ssociated with this signal.This is a pad only and is not connected in the package.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU)

The DMAU (direct memory access unit) manages

movemen t of data to or from the DSP16411 internal or

exter nal memory with min imal core intervent io n:



The DMAU can move data between memory and the

I/O uni ts:

— The DMAU provides four single-word transfer

(SWT) channels for moving data between memory

and SIU〈0—1〉. A core initially defines the data

structure and the DMAU provides address genera-

tion, compare, and update functions. Two-dimen-

sional array capability facilitates applications such

as TDM channel multiplexing/demultiplexing.

Each SWT channel allows an SIU to access mem-

ory one word (16 bits) at a time.

— The DMAU provides a single addressing bypass

channel for moving data between memory and the

PIU. Unlike the SWT channels, the bypass chan-

nel does not provide address generation, com -

pare, and update functions. The bypass channel

allows a host to address and access memory one

word (16 bits) at a tim e.



The DMAU can move data between two blocks of

memory. It provides two memory-to-memory (MMT)

chan nels for which a core initially defines the data

structure. The DMAU provides address generation,

compare, and update functions for each channel.

The DMAU c an perform a block transfer either a sin-

gle word (16 bits) at a time or a double word (32 bits)

at a time.

4.13.1 Overview

The DMAU has six independent channels and an

addressing bypass channel as deta iled in Table 28.

These chann els can access any DSP16411 memory

component, including TPRAM0, TPRAM1, and external

memory.

Figure 18 on page 65 is a functional overview of the

DMAU channels and their interconnections to the

peripherals and m emo ry buses. The DMAU arbitrates

among the seven channels for access to the memory.

For an SWT channel, a core can define a data struc-

ture (array) in DSP16411 memory by programming

DMAU memory-mapped registers. The DMAU can

then perform source or destination transfers. A source

transfer is defined as a series of read operations fr o m

the memory array to an SIU. A destination transfer is

defined as a series of write operations to the memory

array from an SIU. A transfer consists of a seri es of

transactions in re spons e to SIU requests. A source

transaction is defined as reading a word (16 bits) from

the array, writing the word to the SIU output data regis-

ter (SODR), and updating the appropriate DMAU

registers. A destination transaction is defined as

reading a word from the SIU input data register (SIDR),

writing the word to the array , and updating the appropri-

ate DMAU registers. See Section 4.13.5, beginning on

page 87, f or details on SWT transac tions.

The DMAU also provides two channels for memory-to-

memory transfers (MMT). These channels allow a

user-defined block of data to be transferred between

any two DSP16411 memory blocks, including external

memory. Each MMT channel transfers data between a

source block and a des tinatio n bloc k . The DM AU

can perform a block transfer either a single word

(16 bits) at a time or a double word (32 bits) at a

time. See Section 4.13.6, beginning on page 90, fo r

details on memory-to-memory block transfers.

Finally, the DMAU provides an addressing bypass

chan nel that is dedicated to the PIU. This channel

bypasses the DMAU address generation, compare,

and update processes. The DMAU relies on the PIU to

provide the memo ry address for each PIU transaction

(data transfer between a host and the DSP16411).

The address ing bypass channel provides a hos t with

fast access to any DSP16411 memory space. See

Section 4.13.4 on page 86 f or more details.

Table 28. D MAU Chann el Assignment

DMAU Channel Descri ption Associated With

SWT0 Single-word (16-bit) transfer s SIU0

SWT1 Single-word (16-bit) transfer s

SWT2 Single-word (16-bit) transfer s SIU1

SWT3 Single-word (16-bit) transfer s

MMT4 Single-word (16-bit) or double-word (32-bit) transfer s Memory

MMT5 Single-word (16-bit) or double-word (32-bit) transfer s

Bypass Singl e-word (16-bit ) tr ansfers PIU

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.1 Overview (continued)

DMAU Channels

Figure 18. DMAU Interconnections and Channels

Figure 19 is a block diagram of the DMAU. T he DMAU include s 55 memory-mapped registers that it us es in pro-

cessing source transfers, destination transfers, and memory-to-mem ory block transfers. These regist ers are con-

figured by programs running in the cores that access the registers. The registers control the DMAU and contain its

current status. See Section 4.13.2, beginn ing on page 67, for details on these registers. Although the DMAU reg-

isters are memory-mapped, they are physically located in the DMAU and are accessible by either core vi a the

SEMI and the SDB (system data bus).

TPRAM0

TPRAM1

SEMI

ZEDB

ZIDB

Z-BUS

ARBITER

SWT0

SWT1

SWT2

SWT3

PIU

CHANNEL

DMAU

DESTINATION

DATA

SOURCE

DATA

DESTINATION

DATA

SOURCE

DATA

BYPASS

CHANNEL

DATA

16/32

DESTINATION

DATA

16/32

SOURCE

DATA

16/32

DESTINATION

DATA

16/32

SOURCE

DATA

SIU1

SIU0

MMT4

CHANNEL

MMT5

CHANNEL

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.1 Overview (continued)

DMAU Block Diagram

Figure 19. DMAU Block Diagram

DMAU

SAB SDB ZSEG ZEAB ZEDB

DPI

PAB

DDO

DSI0

8 CONTROL REGIST ERS

DMCON

〈

0—1

〉

16 bits

CTL

〈

0—5

〉

4 STRIDE REGISTERS

16 bits

STR

〈

0—3

〉

4 REINDEX REGISTERS

〈

0—3

〉

20 bits

8 BASE REGISTERS

SBAS

〈

0—3

〉

DBAS

〈

0—3

〉

20 bits

6 LIMIT REGISTERS

LIM〈0—5〉

20 bits

12 COUNTER REGISTERS

SCNT〈0—5〉

DCNT〈0—5〉

20 bits

12 ADDRESS REGISTERS

32 bits

SADD〈0—5〉

DADD〈0—5〉

ADDRESS

COMPARE

UPDATE

DSINT[3:0], DDINT[3:0], DMINT[5:4]

20 420

32 32

SEMI TPRAM〈0,1〉SEMI

1 STATUS REGISTER

32 bits

DSTAT

DDO PIU

SIU0

DDO

DSI1

SIU1

(TO CORES)

PIU ADDRESSING

BYPASS CHANNEL

SOCIX1

SICIX1

SOCIX0

SICIX0

REQUEST

ZIAB ZIDB

3220

MMT

SOURCE

LOOK-AHEAD

BUFFER

(6 x 32 FIFO)

Z-BUS

ARBITER

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s

Table 29 lists the DMAU memory-m apped registers in functional order, not in address order. Section 6.2.2 on

page 231 des cribes addres sing of memory -map ped registers. The DM A U contains a status register and two mas-

ter control registers for all SWT and MMT channels: DMCON0, DMCON1, and DSTAT. Every DMAU channel has

a corresponding control register CTL〈0—5〉, source and destination address register (SADD〈0—5〉 and

DADD〈0—5〉), source and destination counter register (SCNT〈0—5〉 and DCNT〈0—5〉), and limit register

(LIM〈0—5〉). In addition, each SWT channel has a corresponding source and destination base address register

(SBAS〈0—3〉 and DBAS〈0—3〉), reindex register (RI〈0—3〉), and stride regis ter (STR〈0—3〉).

Table 29. DMAU Memory-Mapped Registers

Type Register

Name Channel Address Size

(Bits) R/W Type Signed/

Unsigned Reset

Value†

DMAU Status DSTAT All 0x4206C 32 R status unsigned X

DMAU Master Control 0 DMCON0 All 0x4205C 16 R/W control unsigned 0

DMAU Master Control 1 DMCON1 All 0x4205E

Channel Cont rol CTL0 SWT0 0x42060 16 R/W control unsigned X

CTL1 SWT1 0x42062

CTL2 SWT2 0x42064

CTL3 SWT3 0x42066

CTL4 MMT4 0x42068

CTL5 MMT5 0x4206A

Source Address SADD0 SWT0 0x42000 32 R/W address unsigned X

Destination Address DADD0 0x42002

Source Address SADD1 SWT1 0x42004

Destination Address DADD1 0x42006

Source Address SADD2 SWT2 0x42008

Destination Address DADD2 0x4200A

Source Address SADD3 SWT3 0x4200C

Destination Address DADD3 0x4200E

Source Address SADD4 MMT4 0x42010

Destination Address DADD4 0x42012

Source Address SADD5 MMT5 0x42014

Destination Address DADD5 0x42016

Source Count SCNT0 SWT0 0x42020 20 R/W data unsigned X

Destination Count DCNT0 0x42022

Source Count SCNT1 SWT1 0x42024

Destination Count DCNT1 0x42026

Source Count SCNT2 SWT2 0x42028

Destination Count DCNT2 0x4202A

Source Count SCNT3 SWT3 0x4202C

Destination Count DCNT3 0x4202E

Source Count SCNT4 MMT4 0x42030

Destination Count DCNT4 0x42032

Source Count SCNT5 MMT5 0x42034

Destination Count DCNT5 0x42036

† For this colum n, X indicate s unkn own on powerup res et and unaff ect ed on subse quent res et. Any re served fi el ds wi t hi n t he regi ster are reset to zero.

‡ T he rei ndex register s are in sign-m agni tud e format.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

Table 29. DMAU Memory-Mapped Registers (continued)

4.13.2 Re g ister s (continued)

Note: The remainder of Section 4.13.2 describes the detailed encoding for each register.

Limit LIM0 SWT0 0x42050 20 R/W data unsigned X

LIM1 SWT1 0x42052

LIM2 SWT2 0x42054

LIM3 SWT3 0x42056

LIM4 MMT4 0x42058

LIM5 MMT5 0x4205A

Source Base SBAS0 SWT0 0x42040 20 R/W address unsigned X

Destination Base DBAS0 0x42042

Source Base SBAS1 SWT1 0x42044

Destination Base DBAS1 0x42046

Source Base SBAS2 SWT2 0x42048

Destination Base DBAS2 0x4204A

Source Base SBAS3 SWT3 0x4204C

Destination Base DBAS3 0x4204E

Stride STR0 SWT0 0x42018 16 R/W data unsigned X

STR1 SWT1 0x4201A

STR2 SWT2 0x4201C

STR3 SWT3 0x4201E

Reindex RI0 SWT0 0x42038 20 R/W data signed‡X

RI1 SWT1 0x4203A

RI2 SWT2 0x4203C

RI3 SWT3 0x4203E

Type Register

Name Channel Address Size

(Bits) R/W Type Signed/

Unsigned Reset

Value†

† For this colum n, X indicate s unkn own on powerup res et and unaff ect ed on subse quent res et. Any re served fi el ds wi t hi n t he regi ster are reset to zero.

‡ T he rei ndex register s are in sign-m agni tud e format.

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

The DMAU status register (DSTAT) reports current DMAU channel activity for bo th source and destination opera-

tions and reports channel errors. T his register can be read by the user soft ware exec uting in either core to deter-

mine if a specifi c DMAU channel is already in use, or if an error has occurred that may result in data corruption.

The ERR[5:0] fields of the DSTAT register reflect DMAU protocol errors. S ee Sec tion 4.13. 8 on page 94 for infor-

mation on error reporti ng and recove ry.

Table 30. DSTAT (DMAU Status) Register

The memory address for this register is 0x4206C.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RBSY5 RBSY4 SBSY5 DBSY5 SRDY5 DRDY5 ERR5 SBSY4 DBSY4 SRDY4 DRDY4 ERR4 SBSY3 DBSY3 SRDY3 DRDY3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ERR3 SBSY2 DBSY2 SRDY2 DRDY2 ERR2 SBSY1 DBSY1 SRDY1 DRDY1 ERR1 SBSY0 DBSY0 SRDY0 DRDY0 ERR0

Bits Field Value Description R/W Reset

Value†

31 RBSY5 1 MMT5 is busy comple ting a reset operation‡.RX

0 MM T5 is not completing a reset operation.

30 RBSY4 1 MMT4 is busy completing a reset operation‡.RX

0 MM T4 is not completing a reset operation.

29 SBSY5 1 MMT 5 is reading memo ry. R X

0 MM T5 is not reading memory.

28 DBSY5 1 MMT5 is writing memory. R X

0 MM T5 is not writing memory.

27 SRDY5 1 MMT 5 has a source transacti on pending. R X

0 MM T5 does not have a source transact ion pending.

26 DRDY5 1 MM T5 has a destination transaction pending. R X

0 MM T5 does not have a destination transaction pending.

25 ERR5 1 MMT5 has detect ed a protocol error (source or des ti nation) . Er ror repor t i s cleared by

writi ng a 1 to this bit. R/Clear X

0MMT5— no errors.

24 SBSY4 1 MMT 4 is reading memo ry. R X

0 MM T4 is not reading memory.

23 DBSY4 1 MMT4 is writing memory. R X

0 MM T4 is not writing memory.

22 SRDY4 1 MMT 4 has a source transacti on pending. R X

0 MM T4 does not have a source transact ion pending.

21 DRDY4 1 MM T4 has a destination transaction pending. R X

0 MM T4 does not have a destination transaction pending.

20 ERR4 1 MMT4 has detect ed a protocol error (source or des ti nation) . Er ror repor t i s cleared by

writi ng a 1 to this bit. R/Clear X

0 MM T4—no errors.

19 SBSY3 1 SWT3 is re ading memo ry. R X

0 SW T3 is not reading memory.

18 DBSY3 1 SWT3 is writing memory. R X

0 SW T3 is not writing memory.

† F or this co l um n, X indi cate s unkn own on powe rup reset and unaffect ed on su bsequent reset.

‡ A cor e rese ts MMT 5 by sett i ng the R ESET5 f i el d (DMCON1[5]—Table 32 on page 72 ) and reset s MMT4 by se tt i ng th e RES E T 4 fiel d ( DMCON1[4]).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

Table 30. D STAT (DMAU S tatus) Register (continued)

4.13.2 Re g ister s (continued)

17 SRDY3 1 SWT3 has a source transac tion pending. R X

0 SW T3 does not have a source transact ion pending.

16 DRDY3 1 SW T3 has a destination transaction pending. R X

0 SW T3 does not have a destination transaction pending.

15 ERR3 1 SWT3 has detected a protocol e rror (source or destination). Error report is cleared by

writi ng a 1 to this bi t. R/Clear X

0SWT3—no errors.

14 SBSY2 1 SWT2 is re ading memo ry. R X

0 SW T2 is not readi ng memory.

13 DBSY2 1 SWT2 is writing memory. R X

0 SW T2 is not writing memory.

12 SRDY2 1 SWT2 has a source transac tion pending. R X

0 SW T2 does not have a source transact ion pending.

11 DRDY2 1 SW T2 has a destination transaction pending. R X

0 SW T2 does not have a destination transaction pending.

10 ERR2 1 SWT2 has detected a protocol e rr or (source o r destination). Error report is cl eared by

writi ng a 1 to this bit. R/Clear X

0 SW T2—no errors.

9 SBSY1 1 SWT 1 is reading memo ry. R X

0 SW T1 is not reading memory.

8 DBSY1 1 SW T1 is writing memory. R X

0 SW T1 is not writing memory.

7 SRDY1 1 SWT1 has a source transact ion pending. R X

0 SW T1 does not have a source transact ion pending.

6 DRDY1 1 SW T1 has a destination transaction pending. R X

0 SW T1 does not have a destination transaction pending.

5 ERR1 1 SWT1 has de tected a protocol error (source o r destinati on). Error report is cl eared by

writi ng a 1 to this bit. R/Clear X

0 SW T1—no errors.

4 SBSY0 1 SWT 0 is reading memo ry. R X

0 SW T0 is not reading memory.

3 DBSY0 1 SW T0 is writing memory. R X

0 SW T0 is not writing memory.

2 SRDY0 1 SWT0 has a source transact ion pending. R X

0 SW T0 does not have a source transact ion pending.

1 DRDY0 1 SW T0 has a destination transaction pending. R X

0 SW T0 does not have a destination transaction pending.

0 ERR0 1 SWT0 has de tected a protocol error (source o r destinati on). Error report is cl eared by

writi ng a 1 to this bit. R/Clear X

0 SW T0—no errors.

Bits Field Value Description R/W Reset

Value†

† F or this co l um n, X indi cate s unkn own on powe rup reset and unaffect ed on su bsequent reset.

‡ A cor e rese ts MMT 5 by sett i ng the R ESET5 f i el d (DMCON1[5]—Table 32 on page 72 ) and resets MMT4 by se tting the RESET4 field (DMCON1[4]).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

The DMAU master control registers, DMCON0 and DMCON1, control the reset, enable, or disable of individual

DMAU channel s. DMCON0 also controls the enabling of the source look-ahead buffer for pipelined MMT reads of

a sou rce block.

Table 31. DMCON0 (DMAU M aster Control 0) Register

The memory address for this register is 0x4205C.

15 14 13 12 11 10 9 8 7—4 3—0

HPRIM MINT XSIZE5 XSIZE4 TRIGGER5 TRIGGER4 SLKA5 SLKA4 DRUN[3:0] SRUN[3:0]

Bits Field Value Definition R/W Reset

Value

15 HPRIM 0 If MMT channel inter ruption is enabl ed (if MINT is set), this bit indicates MMT4 is

the higher-priority channel. R/W 0

1 If MMT cha nnel interruption is enabl ed (if MINT is set), this bit indicates MMT5 is

the higher-priority channel.

14 MINT 0 If t he DMAU has b egun pro cess ing an MM T channe l, i t trans fers a ll t he data fo r that

MMT channel wit hout interruption by the other MMT channel. Any SWT or PIU

bypa ss channel reque sts interrupt the active MMT channel.

R/W 0

1 The higher-priori ty MMT cha nnel indi cated by HPRIM can preempt the l ower-prior-

ity MMT channel. If the DMAU has begun processing the higher-prior ity MMT

channel, it trans fers all the data for that MMT channel without in terruption by the

lower-priorit y MMT channel. Any SWT or PIU bypass channel requests interrupt

the active MMT channel.

13 XSIZE5 0 MMT5 tra nsfers single words (16-bit valu es). R/W 0

1 MMT5 transfers aligned double words (32-bit values)†.

12 XSIZE4 0 MMT4 tra nsfers single words (16-bit valu es). R/W 0

1 MMT4 transfers aligned double words (32-bit values)†.

11 TRIGGER5 0 If the DMAU begins a bloc k transf er usi ng MMT5, it aut om atically clears thi s bit. If a

core wri tes a 0 to this bit position , i t has no effect and does not change the DMAU

acti vity. The cores can cause the DMAU to ter minate chann el acti vity by set ting th e

RESET5 field (DMCON1[5]—Table 32 on page 72).

R/W 0

1 Set by core software to request the DMAU to b egin a block transfer using MM T5.

10 TRIGGER4 0 If the DMAU begins a bloc k transf er usi ng MMT4, it aut om atically clears thi s bit. If a

core wri tes a 0 to this bit position , i t has no effect and does not change the DMAU

acti vity. The cores can cause the DMAU to ter minate chann el acti vity by set ting th e

RESET4 field (DMCON1[4]—Table 32 on page 72).

R/W 0

1 Set by core software to request the DMAU to b egin a block transfer using MM T4.

9 SLKA5 0 Force source and destination accesses f or MM T5 to occur in order (source look-

ahead disabled). R/W 0

1 Permit source reads for MMT5 to be launched before older destination writes

(source look-ahead enabled). This maximizes block transfer throughput.

8 SLKA4 0 Force source and destination accesses f or MM T4 to occur in order (source look-

ahead disabled). R/W 0

1 Permit source reads for MMT4 to be launched before older destination writes

(source look-ahead enabled). This maximizes block transfer throughput.

† The corresponding source and destination addresses must be even.

‡ Each bit of DRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, DRUN3 corresponds to SWT3.

§ Each bit of SRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, SRUN2 corresponds to SWT2.

4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

Table 31. DMCO N0 (DMAU Master Con trol 0) Register (continued)

4.13.2 Re g ister s (continued)

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Table 32. D MCO N1 (DM AU M aster Control 1) Register

7—4 DRUN[3: 0] 0 The DMAU clears t his fi eld if it has comp leted a destination transfer and the corre-

sponding AUTOLO AD fi eld (CTL〈0—3〉[0]—Table 34 on page 74) is cleared. If a

core wri tes a 0 to this bit position , i t has no effect and does not change the DMAU

acti vity. The cores can cause the DMAU to ter minate chann el acti vity by set ting th e

corresponding RESET[3: 0] f ield (DMCON1[3:0]—Tab le 32 on page 72).

Set 0

1 The software running in a core set s thi s fi eld to cause th e DMAU to ini ti ate a new

destination tra nsfer for the corr esponding SWT channel‡.

3—0 S RUN[3:0] 0 The DMAU clea rs this field if it has complet ed a source trans fer and the corre-

sponding AUTOLO AD fi eld (CTL〈0—3〉[0]—Table 34 on page 74) is cleared. If a

core wri tes a 0 to this bit position , i t has no effect and does not change the DMAU

acti vity. The cores can cause the DMAU to ter minate chann el acti vity by set ting th e

corresponding RESET[3: 0] f ield (DMCON1[3:0]—Tab le 32 on page 72).

Set 0

1 The software running in a core set s thi s fi eld to cause th e DMAU to ini ti ate a new

source transfer for the corresponding SWT channel§.

The memory address for this register is 0x4205E .

15—7 6 5—4 3—0

Reserved PIUDIS RESET[5:4] RESET[3:0]

Bits Field Value Definition R/W Reset

Value

15—7 Reserved 0 Reserved—write with zero. R/W 0

6 P IUDIS 0 The DMAU processes PIU requests. R/ W 0

1 The DMAU ignores PIU requests.

5—4 RESET[5: 4] 0 The corresponding MMT channel† is unaffected.

† RESET5 correspo nds t o MMT5 a n d RESET 4 co r resp o nds t o MMT4 . Setting RESE T [5: 4] doe s no t a ffect t he state of any D M AU reg iste r s. RESET[5:4]

is typical l y use d for error recov ery—see S ecti on 4.1 3.8 on page 9 4 for det ai l s.

R/W 0

1 The software running in a core sets th is field to cause t he DMAU to uncondi-

tionally terminate all channel activity for the corresponding MMT channel†.

3—0 RESET[ 3:0] 0 The corresponding SWT channel‡ is un affect ed.

‡ Each bi t of RESET[3: 0] corr esponds to one of the SWT〈0—3〉 channels. For example, RESET3 corresponds to SWT3. Setting a RESET[3:0] field does

not affect the state of any DMA U regist ers, inc l udi ng th e st ate of t he SRU N[ 3:0]/DR UN[3:0] fiel ds (DMCON0[7:0]—Table 31). RE SE T [3:0] is t ypi cally

used for er ror recov ery—see Se ct i on 4.1 3. 8 on page 94 fo r details.

R/W 0

1 The software running in a core sets th is field to cause t he DMAU to uncondi-

tionally terminate all channel activity for the corresponding SWT channel‡.

Bits Field Value Definition R/W Reset

Value

† The corresponding source and destination addresses must be even.

‡ Each bit of DRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, DRUN3 corresponds to SWT3.

§ Each bit of SRUN[3:0] corresponds to one of the SWT〈0—3〉 channels. For example, SRUN2 corresponds to SWT2.

Advance Data Sheet

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 34 on page 74 describes the SWT〈0—3〉 control

registers, CTL〈0—3〉. Each of the CTL〈0—3〉 registers

controls the behavior of the corresponding SWT chan-

nel and determines the following:

1. Whet her the access takes place in row-major (two-

dimensional array) or column-major (one-dimen-

sional array) order.

2. Whether the autoload feature is enabled or disabled.

If enabled, this feature causes the DMAU to auto-

matically reload the address registers with the con-

tents of the base register after an ent ire array has

been proc essed .

3. T he point in the operation when a DMAU interrupt

reques t is generated.

The control register for a specific SWT chann el deter-

mines these attributes for both the source and destina-

tion transfers for that channel. T herefo re, if the SWT

channel is used for bidirectional transfers, the source

and destination data must have the same array size

and structure. As a result, each SWT channel has only

one stride (STR〈0—3〉) and one reindex (RI〈0—3〉)

common to both SWT source and destination transfers

and are given as common references. Table 33 maps

the common ref erences used in Table 34 to their spe-

cific attribute.

Table 33. Collective Design ations Used in Table 34

Collective

Designation De scription Register or Register Field See

RUN Source Channel Enable for SWT〈3—0〉SRUN[3:0] (DMCON0[3:0]) Table 31 on page 71

Desti nation Channel Enable for SWT〈3—0〉DRUN[3:0] (DMCON0[7:4])

ADD Source Address SADD〈0—3〉Table 37 on page 77

Destination Address DADD〈0—3〉

ROW Source Row Counter SROW[ 12:0] (SCNT〈0—3〉[19:7]) Table 38 on page 78

Destination Row Counter DROW[12:0] (DCNT〈0—3〉[19:7]) Table 40 on page 79

COL Sour ce Column Counter SC OL[6 :0 ] ( SCNT〈0—3〉[6:0]) Table 38 on page 78

Destination Column Counter DCOL[6:0] (DCNT〈0—3〉[6:0]) Table 40 on page 79

LASTROW Row Limit LA STROW [12:0] (LIM〈0—3〉[19:7]) Table 42 on page 80

LASTCOL Colum n Limit LASTCOL[6:0] (LIM〈0—3〉[6:0])

BAS Source Base Register SBAS〈0—3〉Table 44 on page 81

Destination Base Register DBAS〈0—3〉Table 45 on page 81

STR Stride Register STR〈0—3〉Table 46 on page 82

RI Reindex Register RI〈0—3〉Table 47 on page 82

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 34. CTL〈0—3〉 (SWT〈0—3〉 Control) Registers

See Table 29, starting on page 67, for the memory addresses of these registers.

15—6 5—4 3—1 0

Reserved POSTMOD[1:0] SIGCON[2:0] AUTOLOAD

Bit Field Value Definition R/W Reset

Value†

15—6 Reserved 0 Reserved—wr ite with zer o. R/W 0

5—4 P OS TMO D [1: 0] 00 The DMAU performs no pointer or counter update operations. R/W XX

01 Select two-dimensional array accesses. Aft er every transaction:



If the col umn counter has not expired, the DMAU increm ents it by one

and increments the add ress by the con tents of the stride registe r.

(If C O L≠LASTCOL, then COL=COL+1 and ADD=ADD+STR.)



If t he row counter has not expired and the column counter has expired,

the DMAU increments the row cou nter by one, clears the colum n

counter, and incre me nts the ad dress by the contents of t he sign-magni -

tude r eindex re giste r . ( If ROW≠LASTROW and COL=LASTCOL, t hen

ROW=ROW+1, COL=0, and ADD=ADD+RI.)



If both the row counter and the column counter have ex pired and the

AUTO LOAD field is se t, the DMAU clears th e row and col umn counter s

and rel oads the addres s with the bas e value. (If ROW=LASTROW and

COL=LASTCOL and AUTOLOAD=1, then ROW=0, COL=0, and

ADD=BAS.)



If both the row counter and the column counter have ex pired and the

AUTO LO AD fie ld i s cleared, the DMAU deac ti vates the chann el.

(If ROW=LASTROW and COL=LASTCOL and AUTOLOAD=0, then

RUN=0.)

10 Select one- dimensional arr ay accesses. After every transaction:



If the row counter has not expired, the DMAU increments the counter

and the address. (If ROW≠LASTROW, then ROW=ROW+1 and

ADD=ADD+1.)



If t he row counter has expired a nd the col um n counter has not expired,

the DMAU clears the r ow counter and increments the column cou nter

and the address. (If ROW=LASTROW and COL≠LASTCOL, th en

ROW=0, COL=COL+1, and ADD=ADD+1.)



If both the row counter and the column counter have ex pired and the

AUTO LOAD field is se t, the DMAU clears th e row and col umn counter s

and rel oads the addres s with t he base value. (If ROW=LASTROW and

COL=LASTCOL and AUTOLOAD=1, then ROW=0, COL=0, and

ADD=BAS.)



If both the row counter and the column counter have ex pired and the

AUTO LO AD fie ld i s cleared, the DMAU clears the row and colum n

counter s, relo ads the address with the base val ue, and deacti vates the

channel. (If ROW=LASTROW and CO L=LASTCOL and

AUTOLOAD=0 , then ROW=0, CO L=0, ADD=BAS, and RUN=0.)

11 Reserved.

† F or this co l um n, X indi cate s unkn own on powe rup reset and unaffect ed on su bsequent reset.

‡ The DMAU hardware performs the division as a one-bit right shift. Therefore, the least significant bit is truncated for odd values of LASTROW or LAST-

COL.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

Table 34. CTL〈0—3〉 (SWT〈0—3〉 Control) Reg isters (continued)

4.13.2 Re g ister s (continued)

MMT block transfers are unidirectional only, but are lis ted as common references for consistenc y with the SWT

channels. Each of the CTL〈4—5〉 registers described in Table 36 on page 76 c ontrols the behavior of the corre-

sponding MMT channel. The control register of a specific MMT channel determines the point in the block transfer

when a DMAU interrupt request is generated. Table 35 on page 76 maps the common references used in Table 36

on page 76 to their specific attribute.

3—1 SIGCON[2:0] 000 The DMAU generates an interrupt request aft er each single word has

been transferred. R/W XXX

001 Th e DMAU generates an i nterr upt reques t foll owing compl etion of a trans-

fer with ROW equal to LASTROW/2‡.

010 Th e DMAU generates an i nterr upt reques t foll owing compl etion of a trans-

fer with COL equal t o LASTC OL.

011 Th e DMAU generates an i nterr upt reques t foll owing compl etion of a trans-

fer with COL equal t o LASTC OL and ROW equal to LASTROW/2‡.

100 Th e DMAU generates an i nterr upt reques t foll owing compl etion of a trans-

fer with ROW equal to LASTROW.

101 Th e DMAU generates an i nterr upt reques t foll owing compl etion of a trans-

fer with COL equal t o LASTC OL and ROW equal to LASTROW.

110 Th e DMAU generates an i nterr upt reques t foll owing compl etion of a trans-

fer with COL equal t o LASTC OL/2‡ and ROW equal to LASTROW.

111 Reserved.

0 AUTOLOAD 0 After th e DMAU transf ers an entire arr ay, it dea ctivates the channel.

(If ROW=LASTROW and COL=LASTCOL, th en RUN=0.) The software

can reactivate the channel by setting the RUN field.

R/W X

1After the DMAU transfers an entire array, it reloads the channel’s counter

and address regist ers with their base values and i niti ates another array

transfer without core intervention. (If ROW=LASTROW and

COL=LASTCOL, then ROW=0, COL=0, and ADD=BAS.)

Bit Field Value Definition R/W Reset

Value†

† F or this co l um n, X indi cate s unkn own on powe rup reset and unaffect ed on su bsequent reset.

‡ The DMAU hardware performs the division as a one-bit right shift. Therefore, the least significant bit is truncated for odd values of LASTROW or LAST-

COL.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 35. Collective Design ations Used in Table 36

Table 36. CTL〈4—5〉 (MMT〈4—5〉 Con trol) R egisters

Collective

Designation Description Register or Register Field See

XSIZE Transfer Size for MMT4 XSIZE4 (DMCON0[12])

(0 for 16 bits or 1 for 32 bits) Table 31 on page 71

Transfer Size for MMT5 XSIZE5 (DMCON0[13])

(0 for 16 bits or 1 for 32 bits)

ADD Source Addr ess SADD〈4—5〉Table 37 on page 77

Desti nation Address DADD〈4—5〉

ROW Sour ce Row Counter SROW[ 12:0] (SCNT〈4—5〉[19:7]) Table 39 on page 78

Destination Row Counter DROW[12:0] ( DCNT〈4—5〉[19:7]) Table 41 on page 79

LASTROW Row Limit LASTROW[12:0 ] (LIM〈4—5〉[19:7]) Table 43 on page 80

See Table 29, starting on page 67, for the memory addresses of these registers.

15—6 5—4 3—1 0

Reserved POSTMOD[1:0] SIGCON[2:0] Reserved

Bit Field Value Definition R/W Reset

Value†

15—6 Res erved 0 Reserved—write with zero. R/W 0

5—4 POSTMOD[1:0] 00 The DMAU perf orms no pointer or counter update operations. R/W XX

01 Reserved.

10 After every transaction:



If t he row counter has not expired, the DMAU increments it and incr e-

ments the address by the element size‡. (If ROW≠LASTROW, then

ROW=ROW+1 and ADD=ADD+1+XSIZE.)



If the row counter has ex pired, the DMAU clears the row cou nter, incre-

ments the address by the element size‡, and deactivat es the channel.

(If ROW=LASTROW, then ROW=0 and ADD=ADD+1+XSIZE.)

11 Reserved.

3—1 SIGCON[2:0] 000 The DMAU generates an interrupt request aft er each element‡ has been

transferred. R/W XXX

001 The chan nel generates an interr upt request following completi on of a

transfer with ROW equal to LASTROW/2.

01X Reserved.

100 The chan nel generates an interr upt request following completi on of a

transfer with ROW equal to LASTROW.

101 Reserved.

11X Reserved.

0 Reserved 0 Reserved—writ e wit h zer o. R/W 0

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

‡ The element size is 1 for single -word tr ansac t i ons (X SIZE = 0) or 2 fo r doubl e-word tra nsac ti ons ( XS IZE = 1 ).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 37. SADD〈0—5〉 and DADD〈0—5〉 (Channels 0—5 Source and Destination Address) Registers

See Table 29, starting on page 67, for the memory addresses of these registers.

31—27 26—23 22—20 19—0

Reserved ESEG[3:0] CMP[2:0] ADD[19:0]

Bit Field Value Description R/W Reset

Value†

31—27 Reser ved 0 Reser ved—write with zero. R/W 0

26—23 ESEG[3:0] 0x0

0xF

External memory addre ss extension. If the DMAU accesses external

memory (CMP[2:0] = 100), it cau ses the SEMI to pl ace the value in this

field onto the ESEG[3 :0] pins.

R/W X

22—20 CM P[2: 0] 000 The sel ected memory component is TPRAM0. R/W XXX

001 The selected memory component is TPRAM1. R/W

01X Reserved. R/W

100 The selected memory component is ERAM‡, EIO, or internal I/O. R/W

101 Reserved. R/W

11X Reserved. R/W

19—0 ADD[19:0] 0x00000

0xFFFFF

The addres s wi thin the se lec ted memo ry component . For an M MT〈4—5〉

channel, if the corresponding XSIZE[5:4] field (DMCON0[13:12]—see

Table 31 on page 71) is set, this value must be even.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

‡ If the WE ROM fiel d (ECON1[11]—Table 61 on page 112) is set, EROM is selec t ed in place of ERAM.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 38. SCNT〈0—3〉 (SWT〈0—3〉 Source Counter) Register s

Table 39. SCNT〈4—5〉 (MMT〈4—5〉 Source Counter) Registers

See Table 29, starting on page 67, for the memory addresses of these registers.

19—7 6—0

SROW[12:0] SCOL[6:0]

Bit Field Description R/W Reset

Value†

19—7 SROW[12:0] The row counter of t he one-dimensional or two-dimensional source array for

the corresponding SW T channel (read data). The DMAU updates this fi eld

as the tr ansfer proc eeds and automatically clear s it upon the completi on of

the tr ansfer.

R/W X

6—0 SCOL[6:0] The colum n counter of the one-dimens ional or two-dimensio nal source ar ray

for t he correspondi ng SW T channel (read data). The DMAU updates this

fie ld as the transf er proce eds and aut omatic ally cl ears it upon th e comple tion

of the t ransfer.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset . SCNT〈0—3〉 ar e not cleare d by a res et of the DM AU

channel vi a t he DMCON1 r egi ste r (Table 32 on page 72). Bef ore an S WT channel can be use d, the progra m must clear t he corres ponding

SCNT〈0—3〉 regist er aft er a DSP16411 de vi ce res et . O therw i se, the value of this regist er is undef i ned.

See Table 29, starting on page 67, for the memory addresses of these registers.

19—7 6—0

SROW[12:0] SCOL[6:0]

Bit Field Description R/W Reset

Value†

19—7 SROW[12:0] The row counter of t he source block for the corresponding MMT channel

(read data) . The DMAU increm ents this fie ld as the transfer proce eds and

automatically clears it upon the compl etion of the tran sfer.

R/W X

6—0 SCOL[6:0] The column counter of the source block for the cor responding MMT channel

(read data) . Typically, the user has programmed the LASTCOL[ 6:0] field

(LIM〈4—5〉[6:0]—Table 43 on page 80 ) with zero, and therefore, the DMAU

does not update thi s fi eld.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset . SCNT〈4—5〉 ar e not cleare d by a res et of the DM AU

channel vi a t he DMCON1 r egi ste r (Table 32 on page 72). Bef ore an MM T channel can be us ed, the program m ust cl ear th e correspondi ng

SCNT〈4—5〉 regist er aft er a DSP16411 de vi ce res et . O therw i se, the value of this regist er is undef i ned.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 40. DCNT〈0—3〉 (SWT 〈0—3〉 Destination Counter) Registers

Table 41. DCNT〈4—5〉 (MMT〈4—5〉 Destin ati on Counter) Registers

See Table 29, starting on page 67, for the memory addresses of these registers.

19—7 6—0

DROW[12:0] DCOL[6:0]

Bit Field Description R/W Reset

Value†

19—7 DROW[12: 0] The row coun ter of t he one-di mensiona l or two- dime nsional desti nation array

for t he correspondi ng SW T channel (write dat a). The DMAU updates this

fie ld as the transf er proce eds and aut omatic ally cl ears it upon th e comple tion

of the t ransfer.

R/W X

6—0 DCOL[6: 0] The column counter of the one-di me nsional or two-di m ensional des ti nation

array for the correspond ing SWT channel (write data) . The DMAU updates

this field as the transfer proceeds and automatically clears it upon the com-

pletion of the transfer.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset . DCNT〈0—3〉 are n ot cl eared by a reset of t he DM AU

channel vi a t he DMCON1 r egi ste r (Table 32 on page 72). B efor e an SWT c hannel can be use d, the progra m must clear t he corres ponding

DCNT〈0—3〉 register after a DS P16411 device reset . Otherw i se, the value of thi s regist er i s unde fined.

See Table 29, starting on page 67, for the memory addresses of these registers.

19—7 6:0

DROW[12:0] DCOL[6:0]

Bit Field Description R/W Reset

Value†

19—7 DROW[12: 0] The row count er of the d estination block for the corresponding MMT channel

(write data). The DMAU increm ents this field as the transfer proceeds and

automatically clears it upon the compl etion of the tran sfer.

R/W X

6—0 DCOL[6:0] The column counter of the destination block for the corresponding MMT

channel (write data). Typical ly, the user has program m ed the LASTCOL [6: 0]

fi eld ( LIM〈4—5〉[6:0]—Table 43 on page 80) with zero, and therefore, the

DMAU does not update this field.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset . DCNT〈4—5〉 are n ot cl eared by a reset of t he DM AU

channel vi a t he DMCON1 r egi ste r (Table 32 on page 72). B efor e an M M T channel can be us ed, the program m ust cl ear th e correspondi ng

DCNT〈4—5〉 register after a DS P16411 device reset . Otherw i se, the value of thi s regist er i s unde fined.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 42. L I M〈0—3〉 (S WT〈0—3〉 L imit) Registers

Table 43. LIM〈4—5〉 (MMT〈4—5〉 Lim it) Re gi st ers

See Table 29, starting on page 67, for the memory addresses of these registers.

19—7 6—0

LASTROW[12:0] LASTCOL[6:0]

Bit Field Description R/W Reset

Value†

19—7 LASTRO W[12:0] The last row count f or both the source and destination arrays for the corre-

sponding SWT channel. The source and destination arrays are either one-

dimensional or two-dimensi onal. For a single- buffered array, this field is pro-

gramm ed wit h the n umber of ro ws i n each si ngle buffer m inus one (

–1). For

a double-buf fered two-dimensional array, this field is programmed with two

times the number of ro ws in each sing le buffer minus one ((2 ×

)–1).

R/W X

6—0 LASTCOL[6:0] The last col um n count for both t he source and desti nation arrays for the cor-

responding SWT channel. The source and desti nation arrays are either one-

dimensional or two-dimensional. This field is programm ed wit h the number

of columns minus one (

–1).

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

See Table 29, starting on page 67, for the memory addresses of these registers.

19—7 6—0

LASTROW[12:0] LASTCOL[6:0]

Bit Field Description R/W Reset

Value†

19—7 LASTRO W[12:0] The last row count f or both the source and destination blocks for the corre-

sponding MMT channel. This field is typically programm ed with th e number

of rows‡ in t he block minus one (

–1).

R/W X

6—0 LASTCOL[6:0] The last col um n count for both t he source and desti nation blocks for the cor-

responding MMT channel. The user typically progra ms thi s fi eld wit h zero§.R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

‡ Each row con tains one elem ent . The elem ent size is ei t her 16 bits or 32 bits , base d on the program m in g of the XS I Z E4 or XS I Z E5 field

(DMCON0[13:12]—Table 31 on page 71).

§ This document assumes that the LASTCOL[6:0] field is programmed with zero.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 44. SBAS〈0—3〉 (SWT〈0—3〉 Source Base Address) Registers

Table 45. DBAS〈0—3〉 (SWT〈0—3〉 Destination Base Address) Registers

See Table 29, starting on page 67, for the memory addresses of these registers.

19—0

Source Base Address

Bit Field Description R/W Reset

Value†

19—0 Source Base

Address The program must in it ialize the SBAS〈0—3〉 register with the starting address of the

one-dimensional or two-dimensi onal source array for the corresponding channel

(read data). I f the corresponding AUTOLOAD field (CTL〈0—3〉[0]) is set, the DMAU

copies the contents of SBAS〈0—3〉 to t he correspondi ng SADD〈0—3〉 register after

the transfer of an ent ir e array i s com plete. The DMAU does not m odify SBAS〈0—3〉.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

See Table 29, starting on page 67, for the memory addresses of these registers.

19—0

Destination Base Address

Bit Field Description R/W Reset

Value†

19—0 Destination

Base Address The program must initialize the DBAS〈0—3〉 register with the starting addres s of th e

one-dimensiona l or two-d imensional desti nation array for the corresponding chan nel

(write data). If the corresponding AUTOLOAD field (CTL〈0—3〉[0]) is set, the DMAU

copies the contents of DBAS〈0—3〉 to th e correspondi ng DADD〈0—3〉 r egister after

the tran sfer of an entire array is complete. The DMAU does not modify DBAS〈0—3〉.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.2 Re g ister s (continued)

Table 46. STR〈0—3〉 (SWT〈0—3〉 Stride) Registers

Table 47. RI〈0—3〉 (SWT〈0—3〉 Re index) Registers

See Table 29, starting on page 67, for the memory addresses of these registers.

15—14 13—0

Reserved Stride

Bit Fie ld Va lue Description R/W Reset

Value†

15—14 Reserv ed 0 Reserved—wr ite with zero. R/W 0

13—0 Stride ≤16, 383 If the cor responding SWT channel is programmed for one- dimensional array

access es (i f the POSTMOD[1: 0] field (CTL〈0—3〉[5:4]) is 0x2), thi s field is i gnored.

If the cor responding SWT channel is programmed for two-dimensional array

accesses (if the POST MOD[1:0] field (CTL〈0—3〉[5:4]) is 0x1), the DMAU adds

the contents of this register to the cor respondin g source and dest ination address

registers (SADD〈0—3〉 and DADD〈0—3〉) unt il it proc esses the last colu m n in the

array. T he program must ini ti alize this re gister with the numbe r of memory loca-

tions between corresponding rows (elements) of consecutive columns (buf fers).

T y pical ly, the columns (b uf fers ) are back- to-back (conti guous) in memory, and this

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

See Table 29, starting on page 67, for the memory addresses of these registers.

19 18—0

Sign Bit M agnitude

Bit Field Value Description R/W Reset

Value†

19 Sign Bit 1 If the corresponding SW T channel is programmed for one-dimensional

array accesses (if the POSTMOD[1:0] fiel d (CTL〈0—3〉[5:4]) is 0x2), this

field is ignored.

If t he correspondi ng SWT channel is programm ed for two- dimensional

array accesses (if the POSTMOD[1:0] fiel d (CTL〈0—3〉[5:4]) is 0x1), this

bit must be set . This causes the reindex value to be negative and the

DMAU to subtract the reindex magnitude from SADD〈0—3〉 and

DADD〈0—3〉.

R/W X

18—0 Magnitude ≤262,143 If t he correspondi ng SWT channel is programm ed for one-dimensional

array accesses (if the POSTMOD[1:0] fiel d (CTL〈0—3〉[5:4]) is 0x2), this

field is ignored.

If t he correspondi ng SWT channel is programm ed for two- dimensional

array accesses (if the POSTMO D[1: 0] fi eld (CTL〈0—3〉[5:4]) is 0x1), the

DMAU subtracts this value from the corresponding address register

(SADD〈0—3〉 or DADD〈0—3〉) after accessi ng the last column in the

array. For a singl e-buffered array of

rows and

col umns (

> 1), the

magn itude of the rei ndex value is (

×(

– 1)) – 1. For a double -buffered

arra y of

rows and

column s (

> 1), the magnit ude of the r eindex val ue

is (2

×(

–1))–1.

R/W X

† For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.3 Data Structures

The DMAU moves data in one-dimensional array , two-dimensional array , and block transfer patterns. The following

sections outline these three types of data st ructures and the methods for programmi ng the DMAU registers t o

establish them.

4.13.3.1 One-Dimensional Data Structure (SWT Channels)

Figure 20 illustrates the structure of a one-dimensional array for an SWT channel. The array consists of

columns

(buff ers), each containing

rows (elements). The columns must be contiguous (back-to-back) in memory. See

Section 4.13.5, beginning on page 87, for more information about SWT channels. See Section 4.13.9.2, beginning

on page 97, for an example of a transfer using a one-dimensional array.

A One-D imensional D at a St ructure for Bufferi ng

Input Channels

Fi gure 20. One-Dimensi onal Da ta St ruct ure f or Buffer ing

Channels

One-dimensional data structures for data transfers use

the address, base, limit, counter, and control registers

associated with the SWT channel carrying the data

between an SIU and memory.

CTL〈0—3〉:The user software m ust initialize the cor-

responding control register with the POSTMOD[1:0]

field programme d to 0x2 to enable one-dimensiona l

array accesses, the SIGCON[2:0] field programmed to

a value that defines when interrupts are generated, and

the AUTOLOAD field set to one so that no further core

interaction is needed.

DADD〈0—3〉 and SADD〈0—3〉:The user software

must initialize the corresponding destination and

source address registers to the top of the input (desti-

nation) and output (source) arrays located i n mem ory.

The DMAU automatically increments these registers as

the transfer proceeds.

DBAS〈0—3〉 and SBAS〈0—3〉:The user software

must also initialize the corresponding destination and

source base registers to the top of the input (destina-

tion) and out put (sou rc e) ar ray s locate d in

memory. These registers are used with the autoload

feature of the associated SW T channe l.

LIM〈0—3〉:The user software must initialize the cor-

respon ding limit register with the dim ensio ns of the

array. The number of rows (or elements) is

; therefore,

the LAST ROW [12 :0] field is programmed to

– 1. The

numbe r of column s,

, is the same as the number of

buffers; therefore, LASTCOL[6:0] field is programmed

–1.

DCNT〈0—3〉 and SCNT〈0—3〉:The corresponding

destination and source count registers contain the row

and column counters for one-dimensional array

accesses. T he use r software must initially clear these

registers. The DMAU automatically clears these regis-

ters upon the completion of an SWT transfer , and incre-

ments the row and column counter fields of these

registers as the transfer proceeds.

DMCON0: T he us er software must set the corre-

sponding SRUN[3:0] and DRUN[3:0] fields in DMCON0

to enable source and destination tran sfers.

SOURCE

BUFFER

COMPLETE

SBAS〈0—3〉

AUTOLOAD

OUTPUT SOURCE ARRAY INPUT DESTINATION ARRAY

ROW=0

ROW=1

ROW=

–1

ROW=0

ROW=1

ROW=

–1

COL=0COL=

–1

SOURCE

BUFFER

COMPLETE

DESTINATION

BUFFER

COMPLETE

DBAS〈0—3〉

AUTOLOAD

ROW=0

ROW=1

ROW=

–1

ROW=0

ROW=1

ROW=

–1

COL=0COL=

–1

DESTINATION

BUFFER

COMPLETE

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

84 A gere System s— P rop rietary Agere Systems In c.

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any instructions

4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.3 Data Structures (continued)

4.1 3.3.2 Tw o-Dimensional Data Structure (SWT Channels)

Figure 21 illustrates the structure of a two-dimensional double-buffered array for an SWT channel. This structure is

useful for TDM channel multiplexing and demultiplexing. The array consists of

columns (double buffers), each

containing 2

rows (elements). The columns are typically contiguous (back-to-back) in memory, but this is not

required. See Se ction 4. 13. 5, beginning on page 87 , for more information about SW T channel s. See

Section 4. 13.9. 1, beginning on page 95, for an example of a transfer using a two-dimensio nal array.

A Two-Dimensional Data Structure for Doub le-Buffering

Channels

Figure 21. Two-Dimensional Data Structure for Double-Buffering

Channels

Two-dimensional data structures for data transfers use

address, base, limit, counter, stride, reindex, and con-

trol registers associated with the SWT channel carrying

the data between an SIU and memory.

CTL〈0—3〉:The user software m ust initialize the cor-

responding control register with the POSTMOD[1:0]

field programme d to 0x1 to enable two-dimensio nal

array accesses, the SIGCON[2:0] field programmed to

a value that defines when interrupts are generated, and

the AUTOLOAD field set to one so that no further core

interaction is needed.

DADD〈0—3〉 and SADD〈0—3〉:The user software

must initialize the corresponding destination and

source address registers to the top of the input (desti-

nation) and output (source) arrays located i n

memory. The DMAU automatically updates these reg-

isters in a row-major order as the transfer proceeds .

DBAS〈0—3〉 and SBAS〈0—3〉:The user software

must also initialize the corresponding destination and

source base regist ers to the top of the inp ut (destina-

tion) and output (source) arrays located in

memory. These registers are used with the autoload

feature of the associated SW T channe l.

COL=0COL=1

〈

0—3

〉

STR

〈

0—3

〉

SBAS〈0—3〉

SOURCE

AUTOLOAD

DESTINATION

OUTPUT SOURCE ARRAY INPUT DESTINATION ARRAY

SINGLE

SOURCE DESTINATION

FRAME

COMPLETE

BUFFER

COMPLETE

ARRAY

COMPLETE

FRAME COMP LETE

(SIGCON=0x2)

BUFFER COMPLETE

(SIGCON=0x3)

ARRAY COMPLETE

(SIGCON=0x5)

BUFFER

DOUBLE

BUFFER

ROW=0

ROW=1

ROW=2

–1

ROW=

–1

COL=

–1

ROW=0

ROW=1

ROW=2

–1

ROW=

–1

ROW=0

ROW=1

ROW=2

–1

ROW=

–1

COL=0COL=1

〈

0—3

〉

STR

〈

0—3

〉

DBAS〈0—3〉

AUTOLOAD SINGLE

BUFFER

DOUBLE

BUFFER

ROW=0

ROW=1

ROW=2

–1

ROW=

–1

COL=

–1

ROW=0

ROW=1

ROW=2

–1

ROW=

–1

ROW=0

ROW=1

ROW=2

–1

ROW=

–1

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.3 Data Structures (continued)

4.13.3.2 T wo-Dimensional Data Structure (SWT

Channels) (continued)

LIM〈0—3〉:The u s er s oft w ar e must initialize the co r-

responding limit register with the d imens ions of the

array. The number of rows (or elements) is

For a sin-

gle-buffered array, the LASTROW[ 12: 0] field is pro-

grammed to

– 1. For a double-buffered array

(Figure 21 on page 84), the LASTROW[ 12:0 ] field is

programmed to (2×

) – 1. The number of columns (

)

is the same as the number of buf fers. Therefore, the

LASTCOL [6:0] field is programmed to

–1.

DCNT〈0—3〉 and SCNT〈0—3〉:The corresponding

destination and source count registers contain the row

and column counters for two-dimensional array access.

The user software must initially clear these registers.

The DMAU automatically clears these registers upon

the completion of an SWT transfer and increments the

row and column counter fields of these registers as the

transfer proceeds.

STR〈0—3〉:The user software must initialize the cor-

respon ding stride register with the num ber of memo ry

locations between common rows (elements) of different

columns (buf fers). T ypical data structures have buf fers

that are contiguous in memory. In this case, the stride

is the same as the buffer length (number of rows per

column ). If the current column is not the last column,

the DMAU increm ents the contents of DADD〈0—3〉

and SADD〈0—3〉 by the stride value after each t rans-

action, i.e., increments the address registers in row-

majo r order. This caus es DADD〈0—3〉 and

SADD〈0—3〉 to address the common row in the next

column.

RI〈0—3〉:The user software must initialize the corre-

sponding reindex register to the sign-magnitude pointer

postmodification value to be applied to SADD〈0—3〉

and DADD〈0—3〉 after the DMAU has accessed the

last column. For a single-buff ered array of

rows and

colum ns (

> 1), the magnitude of the reindex value

is (

×(

– 1)) – 1. Fo r a double-buffered array of

rows and

colum ns (

> 1), the magnitude is

×(

– 1)) – 1. Because the reindex value is always

negative for a two-dimensional array , the user software

must set the sign bit of RI〈0—3〉.

DMCON0: T he us er software must set the corre-

sponding SRUN[3:0] and DRUN[3:0] fields in DMCON0

to enable source and destination tran sfers.

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

86 A gere System s— P rop rietary Agere Systems In c.

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any instructions

4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.3 Data Structures (continued)

4.13.3.3 Me m ory-to-Memo ry Block Tran sfers (MMT

Channels)

Figure 22 illustrate s a me mo ry-to-memory block trans-

fer using an MMT channel. See Section 4.13.6, begin-

ning on page 90, for more informat ion about MMT

channels. See Sec t ion 4.13.9.3 on page 99 for an

example of a memory-to-memory block data transfer

using an MMT chann el.

Memory-to-memory block data structures for data

transfers use address, limit, counter, and control regis-

ters associated with the MMT channel transferring the

data between two memories.

DADD〈4—5〉 and SADD〈4—5〉:The user software

must initialize the corresponding destination and

source address registers to the top of the input (desti-

nation) and output (source) blocks located in

memory. The DMAU automatically updates these reg-

isters as the transfer proceeds.

LIM〈4—5〉:The user software must initialize the cor-

respon ding limit register with the dim ensio ns of the

array. The number of rows (or elemen ts) is

. There-

fore, the user software writes

– 1 to

LASTROW[12: 0]. The array is s truc tured as one col-

umn (one buffer). Therefore, the user software writes

zero to LASTCOL[6:0].

DCNT〈4—5〉 and SCNT〈4—5〉:The corresponding

destination and source count registers contain the row

and column counters for memory-to-memory block

transfe rs. The user soft ware must initially clear these

registers. The DMAU automatically clears these regis-

ters upon the complet ion of an MMT source trans fer,

and updates these registers as the source transfer pro-

ceeds.

CTL〈4—5〉:The user software must write the c ontrol

when interrupts are generated.

DMCON0: The user software must set the corre-

spon ding TRIGG ER[5:4] field in DMCON0 to enable

MMT transfers.

Me m o ry - t o -M e m or y B l oc k Tr an s f er

Figure 22. Memory-to-Memory Block Transfer

4.13.4 The PIU Addressing Bypass Channel

If the PIUDIS field (DMCON1[6]—Table 32 on page 72) is cleared, a host microproces sor connect ed to the

DSP16411 PIU port c an gain access to t he ent ire memory spac e of the DSP16411. The access is arbitrated by

the DMAU. If PIUDIS is set to one, PIU requests are ignored by the DMAU.

All PIU transactions are handled through the address ing bypass channel. Hos t requests are independent of both

cores and add no overhead to core processing. The host can issue commands, read status information, read and

write DSP16411 mem ory, and send mess ages v ia the host parallel port. Speci fic transactions are accompl ished

by host commands issued to the PIU. See Section 4.15.5, beginning on page 147, for m ore det ails.

DESTINATION ARRAYSOURCE ARRAY TRANSFER INITIAL VALUEIN ITI AL VALUE

TRANSFER

OF SADD〈4—5〉OF DADD〈4—5〉

ROW=0

ROW=1

ROW=

–1

ROW=(

–1)>>1

COL=0

ROW=0

ROW=1

ROW=

–1

ROW=(

–1)>>1

COL=0

1/2 COMPLETE

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 87

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.5 Single-Word Transfer Channels (SWT)

The DMAU provides a total of four SWT channels.

SWT0 and SWT1 are dedicated to SIU0, and SWT2

and SWT3 are dedica ted to SIU1. Each S WT channel

is bidirectional and can transfer data to/from either

TPRAM 0, TPRAM1, or external memory as defined by

the associated channel’ s source and destination

address registers (SADD〈0—3〉 and DADD〈0—3〉).

Two SWT channels are dedica ted to each SIU so tha t

data from a single S IU can be rou ted to se parat e mem-

ory spaces at any ti me. Each SIU’s ICIX〈0—1〉 and

OCIX〈0—1〉 cont rol registers define the mappi ng of

serial port data to one of the two SWT channels dedi-

cated to that SIU. For example, this provides a method

for routing logical channel data on a TDM bit stream

to/from either TPRAM on a tim e-s lot basis.

If a specific SIU issues a request for service (input

buff er full or output buffer empty), an SWT channel per-

forms a transaction. SWT channels provide both

source and destination transfers. A source transac-

tion is de fined as a read from DSP16411 m em ory and

write to an SIU output register with the update of the

appropriate DMAU registers. A destination transac-

tion is defined as the read of an SIU input register and

write to DSP16411 memory with the update of the

appropriate DMAU registers. For a specific SWT chan-

nel, the size and structure of the data to be trans ferred

to/from the SIU m us t be the same. A s an alternative,

the source or destination transfer for a specific channel

can be disabled, allowing separate DMAU channels to

be used for the source and destination transfers. F or

example, SWT0 can be used to service SIU0 input and

SWT1 for SIU0 output.

The DMAU supports address and counter hardware for

one- and two-dimensional memory accesses for each

SWT channel. The basic data structure is called an

array, which consists of columns (or buffers) and rows

(or elements). An array can be traversed in either row-

major (two-dim ensio nal array) or column-major (one-

dimensional array) order, as defined by the DMAU con-

trol registers for that channel (CTL〈0—3〉—Table 34 on

page 74). Each SWT chann el has two dedicated inter-

rupt signals; one to represent the status of a s ource

transfer and another to represent the status of a desti-

nation transfer. These signals can be used to create

interrupt sources to either core . (S ee Sect ion 4.13.7,

beginning on page 92, for details.)

The SIGCO N [2:0] field (CTL〈0—3〉[3 :1]) r e g i sters

defin e the exact meaning associated with both the

source and dest ination transfer interrupts. See

Table 50 on page 92 for a list of DMAU interrupts and

Table 34 on page 74 for th e CTL〈0—3〉 bit field defini-

tions.

The following steps are taken during a source

transaction:

1. O ne of the cores sets the appropriate SRUN[3:0]

field (DMCON0[3:0]—Table 31 on page 71) to ini-

tiate transfers.

2. I f the SIU 16-bit output data register (SODR) is

empty, the S I U requests data from the DMAU . The

DMAU reads one data word over the Z-bus from the

appropriate DSP16411 memory location using the

SWT channel’s source address register,

SADD〈0—3〉.

3. T he DMAU transfers the data word to the corre-

spon ding SODR register over the peripheral data

bus, DDO.

4. The DMAU updat es the SWT channel’s source

addres s register, SADD〈0—3〉, and the source

coun ter register, SCNT〈0—3〉.

5. T he DMAU can generat e a core interrupt, based on

the value of the SIGCON [2:0] field (CTL〈0—3〉[3:1]).

6. I f this is not the last l oc ation of the source array

(SCNT〈0—3〉≠LIM〈0—3〉), t he DMAU returns to

step 2. I f this is the l as t location of the source array:



If the AUTOLOAD field (CTL〈0—3〉[0]—Table 34

on page 74) is cleared, the DMAU clears

SCNT〈0—3〉, clears the corresponding

SRUN[3:0] fi eld (DMCON0[3:0]—Table 31 on

page 71), and terminates the source transfer.



If the AUTOLOAD field is set:

—The DMAU reloads SADD〈0—3〉 with the value

in the source base address register,

SBAS〈0—3〉.

—The DMAU clears the value in the source

counter register (SCNT〈0—3〉 is written with 0).

—The DMAU initiates a new source transfer with-

out core intervention.

The steps taken for a destination trans action are:

1. One of the cores sets the appropriate DRUN[3:0]

field (DMCON0[7:4]) to initiate transfe rs.

2. If the SIU 16-bit input data register (SIDR) is full, the

SIU requests that the DMAU read the data. After the

DMAU acknowledges the request, the SIU places

the conte nts of SIDR onto the data bus (DSI).

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

88 A gere System s— P rop rietary Agere Systems In c.

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.5 Single-Word Transfer Channels

(SWT) (continued)

3. The DMAU transfers this data word over the Z-bus to

the appropriate DSP16411 memory location as

defined by the channe l’s destinat ion address regis-

ter, DADD〈0—3〉.

4. The DMAU updates the channel’s destination

address register, DADD〈0—3〉, and the destinat ion

counter, DCNT〈0—3〉.

5. The DMAU can generate a core interrupt, based on

the value of the SIGCON[2:0] field

(CTL〈0—3〉[3:1]—Table 34 on page 74).

6. If this is not the l as t location of the destination array

(DCNT〈0—3〉≠LIM〈0—3〉), the DMAU returns to

step 2. If this is the last location of the destination

array:



If the AUTOLOAD field (CTL〈0—3〉[0]—Table 34

on page 74) is cleared, the DMAU clears

DCNT〈0—3〉, clears the corresponding

DRUN[3:0] field (DMCON0[7:4]—Table 31 on

page 71), and termina tes the destination transfe r.



If the AUTOLOAD field is set:

—The DMAU reloads DADD〈0—3〉 with the value

in the destination base address register,

DBAS〈0—3〉.

— The DMAU clears the value in the des tination

counter register (DCNT〈0—3〉 is written with 0).

— The DMAU initiates a new destination transfer

without core intervention.

The DMAU’s control and address registers determine

the data structure and access pattern supported by a

particular channel and reflect the status of the transfer.

These SWT channel registers are described in

Table 48, with additional detail provided in

Sect ion 4.13.2, beginning on page 67.

Table 48. S WT-Speci fic Memory -Map ped Registers

SADD〈0—3〉Source

Address 32-bit The program must initialize the SADD〈0—3〉 regist er with the starting address of the

sou rce array† for the correspondi ng channel ( read data) . The DMAU updates the regis-

ter wi th the addre ss of the next memor y location to be read by the corresponding SWT

channel as the transfer pr oceeds. Table 37 on page 77 descri bes the bit fiel ds of the

SADD〈0—3〉 registers.

SBAS〈0—3〉Source

Base

Address

20-bit The program must initialize the SBAS〈0—3〉 register with the starting address of the

source array† for the corresponding channel (r ead data). If t he correspondi ng AUTO-

LOAD fiel d ( CTL〈0—3〉[0] ) is set, the DMAU copies the contents of SBAS〈0—3〉 to the

corresponding SADD〈0—3〉 regist er after the transf e r of an entire array is complete.

The DMAU does not modify SBAS〈0—3〉.

SCNT〈0—3〉Source

Counter 20-bi t This re gister contains the row and column counter of the source arr ay† for the corre-

spondi ng chann el ( read d ata). The DMAU u pdates th e regi ster as the transf er proc eeds

and automatically clears the register upon the completion of the transfer. The source

row (SROW) is encoded in SCNT〈0—3〉[19:7], and the source column (SCOL) is

encoded in SCNT〈0—3〉[6:0].

Note: SCNT〈0—3〉 are not cleared by a reset of the DMAU channel via the DMCON1

gram must clear t he corresponding SCNT〈0—3〉 register after a DSP16411

device reset. Otherwise, the value of th is regi ster is u ndefined.

DADD〈0—3〉Destination

Address 32-bit The program must initialize the DADD〈0—3〉 regis ter with the star ti ng address of the

destination array† for the correspond ing channel (write data). Th e DMAU updates the

regi ster wi th the a ddress of th e next mem ory loc ation t o be wri tten by the corr espondi ng

SWT channe l as the tr ansfer proceeds. Table 37 on page 77 describes the bit fields of

the DADD〈0—3〉 registers.

DBAS〈0—3〉Destination

Base

Address

20-bit The program must initialize the DBAS〈0—3〉 regist er with the starting address of the

destination array† for the correspond ing channel (write data). If the cor responding

AUTO LO AD fi eld (CTL〈0—3〉[0]) is set , the DMAU copies the contents of DBAS〈0—3〉

to the corresponding DADD〈0—3〉 register after the tr ansfer of an entire arr ay is com -

plete. The DMAU does not modify DBAS〈0—3〉.

† The array can be either one-dimensional or two-dimensional.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

Table 48. SW T-Speci fic Memory -Map ped Registers (continued)

4.13.5 Single-Word Transfer Channels (SWT) (continued)

DCNT〈0—3〉Destination

Counter 20-bit This r egist er conta ins the r ow and co lumn count er of t he desti nation array† for t he corre-

sponding channel ( write data). The DMAU update s the register as the transfer pro-

ceeds and automatica ll y clears the regi ster upon the compl etion of the tran sfer. The

destination row (DROW) is encoded in DCNT〈0—3〉[19:7], and the destination column

(DCOL) is encoded in DCNT〈0—3〉[6:0].

Note: DCNT〈0—3〉 are not cleared by a reset of the DMAU channel via the DMCON1

gram must clear t he corresponding DCNT〈0—3〉 register after a DSP16411

device reset. Otherwise, the value of th is r egister is undefined.

LIM〈0—3〉L imit 20- bi t The user pro grams LIM〈0—3〉 with the l as t row cou nt and t he last col umn count f or bot h

the so urc e and dest inati on arrays† f or th e corr espond ing chan nel . For a singl e- buff ered

array, LIM〈0—3〉[19:7] i s programmed with the number of rows in each single buffer

minu s one (

– 1). For a double-buffered two-dim ensional a rray, LIM〈0—3〉[ 19:7] is pro-

gramme d with two tim es the number of rows in each single buffer minus one

((2 ×

) – 1). The number of colum ns m inus one (

– 1) is encoded in LIM〈0—3〉[6:0].

Refer to Secti on 4.13.9 on page 95 for examples.

STR〈0—3〉Stride

correspondin g STR〈0—3〉 register.

For an SWT channel with two-dimensional array accesses, the user softwar e assigns

the n umber of m emory l ocati ons between c ommon r ows (element s) of di ff erent colum ns

(buffers). Typical ly, this value e quals the number of rows per c olumn, whi ch places t he

buffers back -to-back ( contiguous) in mem ory. Refer to Section 4.13.9.1 on page 95 for

details.

RI〈0—3〉Re index 20-bit For an SW T channel with one-dimensional array ac cesses, the p rogram must clear the

correspondin g RI〈0—3〉 register.

For an SWT channel with two-dimensional array accesses, the DMAU adds the sign-

magnitude value in the corresponding RI〈0—3〉 r egister to the cor responding address

tions) after the last colu mn has been accessed. The magnitude of the r eindex val ue for

an array of

rows and

col umns (

>1) is (

×(

– 1) ) – 1. The magnitude of the

rein dex va lue for a t wo-d imensio nal arr ay that empl oys do uble buf fer s lik e that s hown in

Figur e 2 1 on page 84 is (2

×(

– 1)) – 1. Because the rei ndex val ue is al way s nega-

tive, set the sign bit (bit 19) of RI〈0—3〉.

CTL〈0—3〉Control 16-bit CTL〈0—3〉 controls the followi ng it em s for the corresponding SWT channel:



E nabling or disabl ing of AUTOLOAD for t he starting address.



Deter mining the point in the transa ction when a DMAU interr upt reques t is generat ed.



Determining whether the access takes pl ace in row- m ajor (two-di m ensional array) or

column-major (one-dimensional array) order.

CTL〈0—3〉 det ermines these at tr ibutes for both the sour ce and destinat ion arra ys for

the corresponding SW T channel. See Tab le 34 on page 74 for the field descriptions of

CTL〈0—3〉.

† The array can be either one-dimensional or two-dimensional.

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

90 A gere System s— P rop rietary Agere Systems In c.

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.5 Single-Word Transfer Channels

(SWT) (continued)

The two 16-bit DMAU master control registers,

DMCON0 and DMCON1, also influence the operation

of the SWT channels. The 32-bit DMAU status register ,

DSTAT, reflects the status of any SWT transfer . The bit

field definition of the DMAU control and status registers

is given in S ect ion 4.13.2, beginning on page 67.

4.13.6 Mem ory-to-Memory Transfer Channels

(MMT)

The DSP16411 DMAU provides two MMT channels for

block transfers called MMT4 and M MT5. E ach M MT

channel moves data between a source bloc k and a

desti nat i on bl oc k. Both the source and destination

blocks must be one-dimensional arrays with the same

size and structure, as defined by the MMT channel’ s

control register, CTL〈4—5〉 (see Table 36 on

page 76). The user software initiates an MMT block

transfer request by writing a one to the corresponding

TRIGGER5 or TRIGGER4 field (DMCON0[1 1,10]—see

Table 31 on page 71). Each transfer can be 16 bits or

32 bits, as determined by the corresponding XSIZE5 or

XSIZE4 fi eld (DMCON0[13, 12]). If the transfers are

32 bits, the source and destination addresses as speci-

fied by SADD〈4—5〉 and DADD〈4—5〉 must both be

even.

Once initiated, MMT channel block transfers proceed to

completion and then stop. The DMAU pauses an MMT

block transfer to allow an S WT or bypass channel

transaction to complete, and then automatically

resumes the MMT block transf er. Th is prevents I/O

latencies and possible data ov erwrites due to long

MMT blocks. Each MMT channel has a dedicat ed

interrupt request that can be enabled in either core.

The SIG CON[2:0] field (CTL〈4—5〉[3:1]) determines

the exact meaning associated with the interrupt. See

Table 50 on page 92 and Table 34 on page 74 for more

information.

To optimize throughput , MM T channel read operation s

can be pipelined. This allows the DMAU to initiate mul-

tiple fetches from the source block before an associ-

ated write to the destination block is performed. The

DMAU stores the data f rom the multiple fetches into an

internal source look-ahead buffer. The user enables

multiple fetches into t he sourc e look-ahead buffer for

an MM T channel by setting the correspond ing SLKA5

or SLKA4 field (DMCON0[9,8]).

Assuming that source look-ahead is disabled , the

DMAU performs the following steps during an MMT

block transfer:

1. T he us er software executing in one of the cores

writes a one to the corresponding TRIGGE R5 or

T R IGGE R4 fie l d ( DMCON0[ 11 ,10]) to in iti a te t h e

block transfer. The DMAU aut om atically clears the

TRIGGER5 or TRIGGER4 field.

2. The DMAU initiates a read operation from the source

block using the address in the channel’s source

addres s register, SADD〈4—5〉 (see Table 37 on

page 77). If the corresponding XSIZE5 or XSIZE4

field (DMCON0[13,12]) is cleared, the read opera-

tion is 16 bits. If the corresponding XSI ZE5 or

XSIZE 4 field is set, the read operation is 32 bit s.

3. I f the read operation is 16 bits, the DMAU incre-

ment s SADD〈4—5〉 by one. If the read operation is

32 bits, the DMAU increments SADD〈4—5〉 by two.

The DMAU updat es the source counte r register

(SCNT〈4—5〉—Table 39 on page 78) by increment-

ing its SROW[ 12:0] field by one.

4. When the read data from step 2 becomes availabl e,

the DMAU pla ces it into the sou rce look-ah ead

buffer.

5. The DMAU writes the data in the source look-ahead

buffer to the destination block using the address in

the channel ’s destination address register,

DADD〈4—5〉. If the correspondi ng XSIZE5 or

XSIZE4 field (DMCON0[13,12]) is cleared, the write

operati on is 16 bits. If the c orrespondi ng XSIZE 5 or

XSIZE4 field is set, the write operation is 32 bits.

6. I f the write operation is 16 bits, the DMAU incre-

ment s DADD〈4—5〉 by one. If the write operation is

32 bi ts, the DMAU increm ents DADD〈4—5〉 by

two. The DMAU upda tes the destination counter

DROW[ 12:0] field by one.

7. Depending on the SIGCON[2:0] field

(CTL〈4—5〉[3:1]), the DMAU can generate an inter-

rupt.

8. I f this is the last location of t he block

(DCNT〈4—5〉=LIM〈4—5〉) , the DMA U stops pro-

cessing for the channel. If this is not the l ast location

of the block, the DMAU returns to st ep 2.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.6 Memory-to-Memory Transfer Channels (MMT) (continued)

If s ou rce look-ahe ad is enabled, the DMAU performs the same steps as above exce pt that it ini tially repeats steps

2—4 multiple times in a pipelined manner. It then performs reads and writes to the source and destination blocks

as access cycles become available. It is strongl y recomme nded that the user enable sou rce look-ahead. See

Section 4.14.7.4 on page 133 for a performance comp arison.

The DMAU’s control and address registers determine the data size and location supported by a particular channel

and reflect the status of the request. These MMT channel registers are described in Table 49 on page 91 with

additional detail provided in Section 4.13.2, beginning on page 67.

Table 49. MMT-Speci fic Memo ry-Ma pped Registers

The two 16-bit DMAU master control registers, DMCON0 and DMCON1, influence the operation of the MMT chan-

nels. The 32-bit DMAU status register, DSTAT, reflects the status of any MM T transfer. The bit field definition of

the DMAU control and status registers is given in Section 4.13.2, beginning on page 67.

SADD〈4—5〉Source

Address 32-bit Prior to each MMT block move, the program must initialize the corresponding

SADD〈4—5〉 regi ster with the starting addres s in memory for the source block (rea d

data). The DMAU updates the register with the address of the next memory location to

be read by the specified MMT channel as the block mov e proceeds. Table 37 on

page 77 describes the bit fields of SADD〈4—5〉.

SCNT〈4—5〉Source

Counter 20-bit This regis ter cont ains the sourc e row and col um n counter for the corresponding

channel . The DMAU updates the regi ster as the block move proc eeds and automaticall y

clears the register upon the completion of the block move. The source row (SROW ) is

encoded in SCNT〈4—5〉[19:7], and the source col um n (SCO L) i s encoded in

SCNT〈4—5〉[6:0].

Note: SCNT〈4—5〉 are not cleared by a reset of the DMAU channel via the DMCON1

re g iste r (Table 32 on page 72). Before an MMT channel can be used, the pro-

gram must clear the corresponding SCNT〈4—5〉 register after a DSP1641 1

device reset . Otherwise, the val ue of thi s register is undefined.

DADD〈4—5〉Destination

Address 32-bit Prior to each MMT block move, the program must initialize the corresponding

DADD〈4—5〉 regi ster with t he start ing add res s in memory f or the desti nation blo ck (wri te

data). The DMAU updates the register with the address of the next memory location to

be writ ten by the specified MMT channel as the bl ock m ove proceeds. Table 37 on

page 77 describes the bit fields of DADD〈4—5〉.

DCNT〈4—5〉Destination

Counter 20-bit This regis ter cont ains the destination row and column counter for the cor responding

channel . The DMAU updates the regi ster as the block move proc eeds and automaticall y

clears the register up on the complet ion of the block move. The destination r ow (DROW )

is encoded in DCNT〈4—5〉[19:7] and the desti nation colum n (DCOL) is enco ded in

DCNT〈4—5〉[6:0].

Note: DCNT〈4—5〉 are not clear ed by a reset of the DMAU channel via the DMCON1

re g iste r (Table 32 on page 72). Before an MMT channel can be used, the user

program must clear the corresponding DCNT〈4—5〉 register after a DSP16411

device reset . Othe rwi se, the val ue of thi s register is und efi ned.

LIM〈4—5〉Limit 20-bit The user progr am s LIM〈4—5〉 with the l ast row co unt and the last column count for both

the source and destination blocks for the corresponding channe l. The last row count is

the number of rows minus one and i s encode d in th e LASTROW field ( LIM〈4—5〉[19:7]).

The last column c ount is the num ber of col umns m inus one and i s encoded in the LAST-

COL field (LIM〈4—5〉[6:0]). Typically, LASTCOL is zero for a block move.

CTL〈4—5〉Control 16-bit CTL〈4—5〉 controls interrupt generation for both the source and destination block

moves.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.7 Interrupts and Priority Resolution

The DMAU provides information to both cores of the DSP16411 in the form of status and interrupts. A core can

determine status by reading the DMAU’s memory-mapped DSTAT register, which reflects the current state of any

DMAU channe l. The field definitions for DSTAT are def ined in Table 30 on page 69.

A core can c on figure the DMAU interrupts by programming the correspondi ng SIGCO N[2:0] field

(CTL〈0—3〉[3:1]—Table 34 on page 74 and CTL〈4—5〉[3:1]—Ta ble 36 on page 76). Several DMAU interrupt sig-

nals are multiplexed to each core, so not all DMAU interrupt requests can be monitored by a core simultaneously.

Refer to Section 4.4.2, beginning on page 28, regarding the interrupt multiplexer, IMUX. Table 50 provides a list of

the DMAU interrupt signals and their descriptions.

Table 50. DMAU Interru pts

DMAU Channel Description†

† The SI GCON[2:0] field of the cha nnel ’s CTL〈0—5〉 registe r det erm i nes t he condition under which th e DM AU asserts the interr upt. Se e Table 34 on

page 74 for a description of CTL〈0—3〉, or Table 36 on page 76 for a de scription of CTL〈4—5〉).

DSP Core Interrupt Name

SWT0 SIU0 source (outp ut) transaction complete DSINT0

SIU0 destination (in put) transacti on complete DDINT0

SWT1 SIU0 source (outp ut) transaction complete DSINT1

SIU0 destination (in put) transacti on complete DDINT1

SWT2 SIU1 source (outp ut) transaction complete DSINT2

SIU1 destination (in put) transacti on complete DDINT2

SWT3 SIU1 source (outp ut) transaction complete DSINT3

SIU1 destination (in put) transacti on complete DDINT3

MMT4 Memory-to-memory transfer complete DMINT4

MMT5 Memory-to-memory transfer complete DMINT5

Advance Data Sheet

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.7 Interrupts and Priority Resolution (continued)

The DMAU provides arbitration for requests from many

sources. I f multiple requests are pending simulta-

neously, the DMAU com pletes its current transaction1

and then provides access to the source that has the

highest priority. The order of priority, from highest to

lowe st, is a s follows:

1. SWT0 source transaction (SIU0 output ) (highest)

2. SWT0 destination t ransac tion (SIU0 input)

3. SWT1 source transact ion (SIU0 output )

4. SWT1 destination t ransac tion (SIU0 input)

5. SWT2 source transact ion (SIU1 output )

6. SWT2 destination t ransac tion (SIU1 input)

7. SWT3 source transact ion (SIU1 output )

8. SWT3 destination t ransac tion (SIU1 input)

9. PIU

10. MMT4 destination write

11. MMT5 destination write

12. MMT4 source fetch

13. MMT5 source fetch (lowest)

MMT chann el block transfers that are in progres s are

paused if any SWT or PIU bypass channel request

occurs. The single SWT or bypass channel transaction

completes , and then the paused MMT channel block

transfer resumes.

MMT channel priority can be changed by the user

softw are. The default priority of th e MM T channel s is

listed above. If both MMT4 and M MT 5 require service

at the same time, an MMT4 request has higher priority

than the correspon ding M MT5 request. The default

operation does not allow a new MMT request to inter-

rupt an MMT block transfer already in progress, i.e., the

DMAU ’s default c on dition is to start and complete an

MM T block transfer before a new MMT block transfer

can begin. A ny MM T block tran sfer can be interrupted

by any SW T or PIU bypass channel transacti on.

The def ault operation of the MMT channels can be

chan ged. T he HPRIM field (DMCON0[15]—Table 31

on page 71) is used to select the relative priority of

MM T4 and MMT 5. If HPRIM is cleared (the default),

MMT4 has higher priority than MMT5. If HPRIM is set,

MMT5 has the higher priority.

A higher-priority MMT chann el can be made to inter-

rupt a lower-priority M M T channel blo ck transfer

already in progress. The MINT field (DMCON0[14])

controls this feature. If MINT is cleared, MMT channels

do not interrupt each other, as stated above, and an

MMT block transfer already in progress completes

before another MMT channel request is taken. If MINT

is set, the higher-priority M M T channel can interrupt

the lower-priority channel as determined by the HPRIM

field setting. In a typical application, the higher-priority

chan nel is assigned to moving small, time-critical dat a

block s, and the lower-priority channel is assigned to

large, less time-critical blocks. This feature alleviates

latency t hat can be incurred due to the transfer of large

data blocks.

1. A request to the DMAU can result in more than one transaction, a transaction bein g the transfer of one single (1 6-bit) or double (32-bit) word.

Advance Data Sheet

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.8 Error Reporting and Recovery

Each of the ERR[5:0] fields of the DSTAT regi st er

(Table 30 on page 69) reflects a DMAU protocol failure

that indicates a loss of data for the corresponding

channel. For t he SWT〈0—3〉 channels, the DMAU sets

the corresponding ERR[3:0] field if:



An SIU〈0—1〉 requests DM AU service for a channel

before the DMAU has accepted the previous request

from that SIU〈0—1〉 for that channel.



An SIU〈0—1〉 requests DMAU service for a channel,

and that channel’s RESET[3:0] field

(DMCON1[3:0]—Table 32 on page 72) is set.



An SIU〈0—1〉 requests DM AU destination/sourc e

service for a channel, and tha t channel’s

DRUN[3:0]/SRUN[3:0] field

(DMCON0[7:0]—Table 31 on page 71) is cleared.



An SIU〈0—1〉 requests DMAU service for a channel,

and that channel’s source/destination transfer is

complete (SCNT〈0—3〉/DCNT〈0—3〉=LIM〈0—3〉),

and that channel’s AUTOLOAD field

(CTL〈0—3〉[0]—Table 34 on page 74) is cleared.

For the MMT〈4—5〉 channe ls, the DMAU sets the cor-

respon ding ERR[5:4] field if:



The user software attempts to set the TRIGGER[5:4]

field by writing 1 to DMCON0[11 :10] and the

TRIGGER[5:4] field is already set.



The user software attempts to set the TRIGGER[5:4]

field by writing 1 to DMCON0[11 :10] and the

RESET[5:4] field (DMCON1[5:4]) is set.

If servicing a DMAU channel interrupt, the user soft-

ware should poll DSTAT to determine whether an error

has occurred. If so, the user software must perform the

following steps:

1. Set the corresponding RESET[5:0] fi eld

(DMCON1[5:0]) to terminate all channel activity.

2. Write a 1 to the correspo nding ERR[5:0] field to

clear the field and the error co ndition.

3. Reinitialize the corresponding channel address and

coun t registers.

4. Clear the corresponding RESET[5:0] field to reallow

chan nel activity.

5. For an MMT channel, re-enable a channel transfer

by setting the appropriate TRIGG ER [5:4] field

(DMCON0[11:10]).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.9 Programming Examples

Thi s se c ti on illus t r ates th re e ty pic a l DMA U ap plic a t ion s .

4.13.9.1 SWT Example 1: A Two-Dimensional Array

This example descr ibes the input and output of four channels of full-duplex TDM speech dat a from SIU0 with the

following assumptions:



The data is double-buffered to avoid latencies and the potential of missing samples.



Input and outp ut data have the same array size and structure and are processed by the SWT0 channel .



There are four

logical channels (time slots) grouped in four contiguous double buffers, corresponding to the num-

ber of columns (

) in a two-dimensional array.



Each single buffer has 160 elements, or rows (

), and each double buffer has a length of 320 (0x140).



CORE 0 begins processing data after 160 samples have been input for all f our logical channels.



SIU0 input (destination) data begins at address 0x01000 in TPRAM0.



SIU0 output (source) data begins at address 0x02000 in TPRAM0.



The auto load feature is used to minimize core intervention.

Figure 23 illustrates this data structure. T his exampl e does not discuss the setup and control of SIU0.

A Two-Dimensional Data Structure for Doub le-Buffering

Channels

Figure 23. Example of a Two-Dimensional Double-Buffered Data Structure

STR0

(SBAS0)

SOURCE DESTINATION

OUTPUT SOURCE ARRAY INPUT DESTINATION ARRAY

SOURCE DESTINATION

BUFFER

COMPLETE

ARRAY

COMPLETE

BUFFER COMPLETE

(SIGCON=0x3)

ARRAY COMPLETE

(SIGCON=0x5)

0x02000

0x02140

0x02280

0x023C0

ROW=0

ROW=1

ROW=319

ROW=159

COL=0

SINGLE

BUFFER

DOUBLE

BUFFER

ROW=0

ROW=1

ROW=319

ROW=159

ROW=0

ROW=1

ROW=319

ROW=159

ROW=0

ROW=1

ROW=319

ROW=159

COL=1COL=2COL=3

(DBAS0)

0x01000

0x01140

0x01280

0x013C0

ROW=0

ROW=1

ROW=319

ROW=159

COL=0

SINGLE

BUFFER

DOUBLE

BUFFER

ROW=0

ROW=1

ROW=319

ROW=159

ROW=0

ROW=1

ROW=319

ROW=159

ROW=0

ROW=1

ROW=319

ROW=159

COL=1COL=2COL=3

RI0 = –959 (0x803BF)

AUTOLOAD

RI0 = –959 (0x803BF)

AUTOLOAD

(0x140)

STR0

(0x140)

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4 Hardware Architecture (continued)

4 .13 Direct Memory Access Unit

(DMAU) (continued)

4.13.9 Programming Examples (continued)

4.13.9. 1 SWT Exam ple 1: A Tw o-Dimensional

Array (continued)

The user software running in CORE0 must perform the

following steps to properly initialize SWT0:

1. The user software sets the source address

(SADD0—Table 37 on page 77) and the source

base address (SBAS0—Table 44 on page 81) to the

top of the output (source) array located in

TPRAM 0. The use r software writes 0x 00 002000 t o

SADD0 and 0x02000 to SBAS0.

2. The user software sets the destination address

(DADD0—Table 37 on page 77) and the destination

base address (DBAS0—Table 45 on page 81) to the

top of the input (destination) array located in

TPRAM 0. The use r software writes 0x 00 001000 t o

DADD0 and 0x01000 to DBAS0.

3. The user software clears the source and destination

counter registers SCNT0 and DCNT0 (Table 38 on

page 78 and Table 40 on page 79).

4. The user software initializes the lim it register

(LIM0—T able 42 on page 80) with the dimensions of

the array. The number of rows (or elements) is 2

(320), so the user software writes 319 (2

–1) into

the LASTROW[12:0] field (LIM0[19:7]). The number

of columns is 4, so t he user software writes 3 (

–1)

into t he LA STCO L[6:0] field (LIM0[6:0]). The us er

software writes 0x09F83 into LIM0.

5. The user software initializes the st ride register

(STR0—Table 46 on page 82) with the distance

between corresponding rows of consecutive col-

umns. B ecaus e the buffers are conti guous in this

example, the stride is the same as the buff er length

and the user software writes 0x0140 into STR0.

6. The user software initializes the re index regist er

(RI0—Table 47 on page 82) with the sign-magnitude

postmodification value to be applied to SADD0 and

DADD0 after each tim e th at the last column has

been accessed. The magnitude of t he reindex value

is ((2r ×(n–1))–1) or (320×3) – 1 = 959 = 0x3BF.

The sign must be negative, so the user software

writes 0x803BF into RI0.

7. The user software writes the control registers to

enable SWT0 and begin I/O processing. First, the

user software writes one into the POSTMOD[1:0]

field (CTL0[5:4]—Table 34 on page 74) to enable

two-dimens io nal array accesses, writes 0x3 to t he

SIGCON[2:0] fie ld (CTL0[3:1]), and writes 1 t o the

AUTOLOAD field (CTL0[0]) s o that no further core

interaction is needed . The user software writes

0x0017 to CTL0.

8. F inally, the user software sets both the SRUN0 a nd

DRUN0 fields (DMCON0[0] and DMCON0[4]—

Table 31 on page 71) to enable SWT0 source and

destina tion transfers. The user software writes

0x0011 to DMCON0.

The DMAU begins processing the SWT0 input and out-

put channel s. For the output channel , the DMAU per-

forms the following steps:

1. I t reads the single word at the TPRAM 0 location

point ed to by SADD0 (0x0000 2000) and transfers

the data to SIU0. This data is the first output sample

for the first logical chan nel (ROW = 0 and COL = 0).

2. I t increment s SADD0 by the contents of STR0, s o

SADD0 contains 0x000021 40 and points to the first

output sa mple for the second logical channel

(ROW = 0 and COL = 1). It updates SCNT0 by

incre men ting the column counte r, so SCNT0 con-

tains 0x00001.

3. I t reads the data at 0x02140 and t ransfe rs it to SIU0.

4. I t increment s SADD0 by the content s of STR0, so

SADD0 contains 0x000022 80 and points to the first

output sample for the third logical channel (ROW = 0

and COL = 2). It updates SCNT0 by incrementing

the colum n counte r, so SCNT0 contains 0x00002.

5. As in steps 3 and 4, the DMAU continues to read

data, transfer the data to SIU0, and update SADD0

and SCNT0 until the column counter equals the last

column (SCNT0[6:0] = LIM0[6:0] = 3). SADD0 con -

tains 0x00002 3C0 and points to the first row of the

last column.

6. The DMAU s ubtracts the m agnitude of the contents

of RI0 from SADD0 (0x000023C0 – 0x3BF) and

places the result into SADD0 (0x00002001 ).

SADD0 points to the second output sample for the

first logical channel (ROW = 1 and COL = 0).

The DMAU co ntinues processing in this m anner unt il it

processes row 159 of column 3. At this point,

ROW = LASTROW/2 and COL = LASTCOL. Because

this condition is met and SIGCO N[2 :0] = 0x3, the

DMAU asserts the DSINT0 interrupt to CORE0.

CORE0’ s I SR changes SIGCON[2:0] to 0x5 so that the

DMAU asserts DSINT0 again after it has processed the

remaining samples in the buff ers. CORE0 can over-

write the already-processed samples while the DMAU

cont inues t o proc ess t he rema ini ng s amp l es.

The steps performed by the DMAU for t he inpu t chan-

nel are similar to those for the output channel.

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.9 Programming Examples (continued)

4.13.9.2 SWT Examp le 2: A One-Dimensional Array

This example describes the in put of four blocks of speech data from SIU1 with the following assumptions:



The data is single-buffered.



Data is processed by the SWT3 channel.



There are four

blocks of data grouped in four contiguous buffers, corresponding to the number of columns (

) in

a one-dime nsional array.



Each single buffer has 160 elements, or rows (

=0xA0).



The DMAU fills four buffers in sequential order, i.e., it receives all 160 samples of one buffer and then all

160 s am ple s of the next buff er, etc.



The DMAU places the data in ascending linear order in m em ory, beginning at TPRAM1 addres s 0x01000.



CORE 1 begins processing data after 160 samples have been input.



The auto load feature is used to minimize core intervention.

Figure 24 illustrates the data structure for this example.

A One-D imensional D at a St ructure for Bufferi ng

Input Channels

Figure 24. Example of One-Dimensional Data Structure

DESTINATION

BUFFER COMPLETE

0x01000

0x010A0

0x01140

0x011E0

(DBAS3)

AUTOLOAD

ROW=0

ROW=1

ROW=159

COL=0COL=1COL=2COL=3

DESTINATION

BUFFER COMPLETE

DESTINATION

BUFFER COMPLETE

DESTINATION

BUFFER COMPLETE

ROW=0

ROW=1

ROW=159

ROW=0

ROW=1

ROW=159

ROW=0

ROW=1

ROW=159

INPUT DESTINATION ARRAY

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.9 Programming Examples (continued)

4.13.9. 2 SWT Exam ple 2: A One-D imens i on al

Array (continued)

The user software running in CORE1 must perform the

following steps to properly initialize SWT3:

1. The user software sets the destination address

(DADD3—Table 37 on page 77) and the destination

base address (DBAS3—Table 45 on page 81) to the

top of the input (destination) array located in

TPRAM 1. The use r software writes 0x 00 101000 t o

DADD3 and 0x01000 to DBAS3.

2. The user software clears the destination counter

(DCNT3—Table 40 on page 79).

3. The user software initializes the lim it register

(LIM3—T able 42 on page 80) with the dimensions of

the array. The number of rows (or elements) is 160,

so the user software writes 159 (

– 1) into the LAS-

TROW[ 12:0 ] field (LIM3[ 19:7] ). Th e numbe r of col-

umns is 4, so the user software writes 3 (

–1) into

the LASTCOL[6:0] field (LIM3[6:0]). The user soft-

ware writes 0x04F83 to LIM3.

4. The user software writes the control registers to

enable SWT3 and begin I/O processing. First, the

user software writ es two into the POSTMO D[1:0]

field (CTL3[5:4]—Table 34 on page 74) to enable

one-dimensi onal array accesses, writes 0x4 to t he

S IGC O N[ 2 :0] fiel d ( CTL3[3:1]), and write s 1 to the

AUTOLOAD field (CTL3[0]) so that no fu rther core

interaction is needed. The user software writes

0x0029 to CTL3.

5. Finally, the user software sets the DRUN3 field

(DMCON0[7]—Table 31 on page 71 ) to enable

SWT3 destinat ion transfers. T he user softw are

writes 0x0080 to DMCON0.

The DMAU begins processing the SWT3 input channel

and performs the following steps:

1. I t receives data from SIU1 and writes it to the single-

word TPRAM 1 location pointed to by DADD3

(0x00101000). This data is the first input sample for

the first buffer (ROW = 0 and COL = 0).

2. I t increment s DADD3 by one, so DADD3 contains

0x00101001 and points to the second input sample

for the first buffer (ROW = 1 and COL = 0). It

update s SCNT3 by incrementing the row counter , so

SCNT3 contains 0x00080.

3. I t receives data from SIU1 and writes it to the single-

word TPRAM 1 location pointed to by DADD3

(0x00101001).

The DMAU co ntinues processing in this m anner unt il it

fills row 159 of colum n 0. At this point, ROW = L AS-

TROW and COL = 0. Because this condition is m et

and SIGCON[2:0] = 0x4, the DMAU asserts the

DDINT3 interrupt to CORE1. CORE1 can begin pro-

cessing the first buffer while the DMAU continues to fill

the second buffer.

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4 Hardware Architecture (continued)

4.13 Direct Memory Access Unit (DMAU) (continued)

4.13.9 Programming Examples (continued)

4.13.9.3 MMT Example

This example illustrates the use of MMT4 to move a source block of 100 rows or elements (

= 100) in TPRAM0 to

a destination block in TPRAM1, as Figure 25 illustrates. For this ex am ple, the source address in TPRAM0 is

0x01000 and the destination address in TPRAM1 is 0x02000.

Me m o ry - t o -M e m or y B l oc k Tr an s f er

Figure 25. Memory-to-Memory Block Transfer

The user software running in one of the cores must perform the following steps to properly initialize MMT4:

1. The user software writes the source address (SADD4—Table 37 on page 77) with the top of the output (source)

block located in T P RAM0. The user software writes 0x00001000 to SADD4.

2. The user software writes the d es tination address (DADD4—Table 37 on page 77 ) with the top of the input (des-

tination) block located in TPRAM1. The user software writes 0x00102000 to DADD4.

3. The user software clears the source and destination counter registers SCNT4 and DCNT4 (Table 39 on page 78

and Table 41 on page 79).

4. The user s oftware initial izes the limit register (LIM4—Table 43 on page 80) with the dimensions of the array. The

number of rows (or elem ent s) is 100, so t he user software writes 99 (

– 1) into t he LAS TROW [1 2:0] field

(LIM4[19:7] = 0x63). The number of columns is one, so the user software writes zero i nto the LASTCOL[6: 0]

field (LIM4[6: 0]). The user software writes 0x03180 to LIM4.

5. The user software writes the control registers to enable MMT4 and begin block processing. First, the user soft-

ware writes two into the P O STM OD[ 1:0] field (CTL4[5:4]—Table 36 on page 76) to enable pointer and counter

update operations, and writes 0x1 to the S IG CON[ 2:0] field (CTL4[3:1]). The user software writes 0x0022 to

CTL4.

6. Fin ally, the user software sets the SLKA4 field (DMCON0[8]—Table 31 on page 71) to enable source look-

ahead, sets the XSIZE4 field (DMCON0[12] ) to transfer 32-bit words, and sets t he TRIGG E R4 field

(DMCON0[10]) to initiate M M T4 block transfers. Th e user software writes 0x1500 to DMCON0.

The DMAU begins proces sing the MMT4 channel. For each read operation from TPRAM0 starting at address

0x01000, the DMAU increments SADD4 by two and increments the SROW[12:0] field of SCNT4 by one. Th e

DMAU performs multiple fetches from TPRAM0 and places the data into the source look-ahead buffer. F or each

write operation to TPRAM1 starting at address 0x02000, the DMAU increments DADD4 by two and increments the

SROW[ 12:0] field of DCNT4 by on e. Bec ause S IG CON[ 2:0] = 0x1, the DMAU interrupts the cores when the trans-

fer is half comple te (DROW[12:0] = LASTRO W/ 2 = LAST ROW[ 12:0]>>1 = 0x31 or DCNT4 = 0x1 880). The ISR

then changes SIGCON[2:0] to 0x4 to cause the DMAU to interrupt the cores again when the transfer is complete

(DROW[12:0] = LASTROW[12:0] or DCNT4 =LIM4 = 0x3180).

DESTINATION ARRAYSOURCE ARRAY TRANSFER 0x01020000x0001000(SADD4) (DADD4)

ROW=0

ROW=1

ROW=99

ROW=49

COL=0

TRANSFER

1/2 COMPL ETE

ROW=0

ROW=1

ROW=99

ROW=49

0x0001002 0x0102002

COL=0

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI)

The system and external memory interface (SEM I) is

the DSP16411 interface to external memory and mem-

ory-mapped off-chip peripherals:



The SEM I supports a maximum tota l external mem-

ory size of 18 Mwords (16-bit words ) through a c om -

binat ion of an address bus, an address bus

extension, and decoded enab les.



The SEM I can configure the external data bus as

eithe r 16 bits or 32 bit s.



The SEM I can support a mix of asynchronous mem-

ory and synch ronous, pipelined

ZBT

(zero bus turn-

around) SRAMs.



The SEM I provides support for bus arbitration logic

for sha red-mem ory systems.



The SEMI provides programmable enable assertion,

setup, and hold times for external asynchronous

memory.

These features are controlled via a combination of

SEM I pins and control registers. Som e addition al fea-

tures of the SEMI are t he following:



The SEMI arbitrates and prioritizes accesses from

both cores and from the DMAU.



The SEMI allows the cores to boot from internal or

external memory controlled by the state of an input

pin.



The SEMI controls the internal system bus, which

allows the cores, the DMAU, and the P I U to access

the shared internal I/O memory component. This

component includes the SLM and the internal mem-

ory-mapped registers within th e DMAU, SIU0, SIU1,

PI U, and SEMI.

Figure 26 depicts the internal and external interfaces to

the SEMI . The SEM I interfaces directly to the X -me m-

ory space buses and Y-memory space buses for both

cores and to the DMAU’s external Z-memory space

buses. T h is al lo ws :



Either core to perf orm external program or data

accesses.



Either core or the DM AU to access the SLM or inter-

nal memory-mapped registers.

SEMI Interface Block Diagram

Figure 2 6. SEMI Interface Block Diagram

YDB

YAB

XDB

XAB XAB0

XDB0

YAB0

CORE0

ZEAB

ZEDBZEDB

ZEAB

DMAU

SDB

SAB

ED[31:0]

EA[18:0]

ERAMN

EROMN

EION

ERWN[1:0]

ECKO

EREQN

EACKN

ERDY

EXM

ERTYPE

ESIZE

SEMI

CORE1

YDB0

ZSEG ZSEG

ESEG[3:0]

YDB

YAB

XDB

XAB XAB1

XDB1

YAB1

YDB1

SDB

SAB

ADDRESS

AND

DATA

CONFIGURATION

ENABLES

AND

STROBES

BUS

ARBITRATION

CLOCK

DSP16411 EXTERNAL SIGNALS

SYSTEM BUS

(TO SLM, PIU,

SIU0, AND SIU1)

EYMODE

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.1 External Interface

Table 51 provides an overview of the SEMI pins. These pins are described in detail in the remainder of this section.

Tab le 51. Overv iew of SEMI Pins

Function Pin Type Description

Confi guration ESIZE I Size of exter nal SEMI data bus:

ESIZE = 0 selects 16-bit data bus.

ESIZE = 1 selects 32-bit data bus.

ERTYPE I EROM type:

ERTYPE = 0 selects asynchronous memory for the EROM component .

ERTYPE = 1 selects synchronous pipelined

ZBT

SRAM for the EROM component.

EXM I Boot sour ce:

EXM = 0 selects IROM.

EXM = 1 selects EROM.

Bus Arbit ration

for Asynchronous

Memory

EREQN I External request for SEMI bus (negative assertion).

EACKN O SEMI acknowl edge for external reque st (negative assertion).

ERDY I External device ready for asynchronous access.

Enables

and Strobes ERAMN O/Z ERAM component enable (negat ive asser tion).

EROMN O/Z EROM component enable (negative assertion).

EION O/Z EIO component enable (negative assertion).

ERWN[1:0] O/ Z External read/write not :

If ESIZE = 0 (16- bit external bus):

ERWN1: Inactive (logi c high).

ERWN0: Write enable (negative assertion).

If ESIZE = 1 (32- bit external bus):

ERWN1: Odd word (least significant 16 bits) writ e enable (negative assertion).

ERWN0: Even word (most signifi cant 16 bits) wri te enable (nega tive assertion).

External Clock ECKO O External clock. Can be programme d as CKI, CLK, CLK/2, CL K/3, or CLK/4.

Address

and Data ED[31:0]†

† These address and data bus pins contain internal bus hold circuits. If BHEDIS (ECON1[12]—Table 61 on page 1 12) = 0, t hes e b us h ol d c i rcui t s ar e acti -

vated. If BHEDIS = 0 and neither the SEMI nor an external device is driving these pins, the bus hold circuits hold them at their previous valid logic level.

This el imi nate s t he need f or ex ternal pu ll- up or pull -down res i sto rs o n thes e pi n s . See S ecti on 10. 1 on page 268 for details.

I/O/Z Bidi rectional 32-bit external data bus.

EA[18:1]†O/Z External address bus bits 18— 1.

EA0†O/Z If ESI ZE = 0:

External address bus bit 0.

If ESIZ E = 1 and the exte rnal component is synchronous‡:

Write str obe (negative assertion ).

‡ The EROM component is synchronous if the ERTYPE pin is lo gic 1. The ERAM component is synchronous if the YTYPE field (ECON1[9]) is set and

the EIO compon ent i s syn ch r ono us if the ITYPE fi e ld (ECON1[10]) is set. ECON1 is desc ri bed i n Table 61 on page 11 2.

ESEG[3:0]†O/Z External segment address.

EYMODE I This pin determines the mode of the external data bus. It must be static and tied to

VSS (if the SEMI is used ) or VDD2 (if the SEM I is not used). If EYMO DE = 0, the exter-

nal data bus ED[31 :0] oper ates normally as described above. If EYMODE = 1,

ED[31:0] are statically configured as out puts (regardless of the state of RSTN) and

must not be connected ext ernally. See Se cti on 10.1 on page 268 for details.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.1 External Interface (continued)

4.14.1.1 Configu r a t i o n

The SEMI configuration pins are in puts that are indivi duall y tied high or low based on system requirements. The

ESIZE and ERTYPE pins reflect the confi guration of th e external memory system. The EXM pin specifies the

memory boot area for the DSP16000 cores. Table 52 details the SEMI configuration pins.

Table 52. Configu ration Pins for the S EMI Extern al Interface

FPin Value Description

ESIZE

(input) 0 Configures external data bus as 16 bits:



ED[31:16] is activ e and ED[15: 0] is 3- state.



EA[18:0] provides the address.



For a single-word (16- bit) acces s, t he SEMI places the address onto EA[18:0]:

— For a read, the SEMI transfers the word fr om ED[31: 16].

— For a write, th e SEMI dri ves the word onto ED[3 1:16] and asserts ERWN0.



For a double-word (32-bit) access, the SEMI performs t wo single-word (16-bit) accesses:

— First , t he SEM I accesses the most s ignificant half of t he double word a t the original address (see sing le-

word (16-b it) access des cri bed ab ove).

— Second, the SEMI incr ements the addre ss and accesses the l east significant half of the double word

(see single-word (16-bit) access described above).

1 Configures external data bus as 32 bits:



EA[18:1] provides the even addres s.



For a single-word (16-bit) access to an even location:

— For a read, the SEMI transfers the word fr om ED[31: 16] and ignores ED[15:0].

— For a write, th e SEMI dri ves the word onto ED[3 1:16] and asserts ERWN0†.



For a single-word (16-bit) access to an odd location:

— For a read, the SEMI transfers the word fr om ED[15: 0] and ignor es ED[31:16].

— For a write, th e SEMI dri ves the word onto ED[1 5:0] asserts ERW N1†.



For a double-word (32-bit) aligned access, i.e., an access to an even address:

— For a read, the SEMI transfers the double word from ED[31:0].

— For a write, th e SEMI dri ves the doubl e word onto ED[31:0] and asserts ERWN0 and ERWN1†.



For a double-word (32-bi t) misaligned access, the SEMI perfor m s two single-word (16-bit) accesses:

— First , t he SEM I accesses the most s ignificant half of t he double word a t the original address (see sing le-

word (16-b it) access to an odd location descri bed ab ove).

— Second, the SEMI incr ements the addre ss and accesses the l east significant half of the double word

(see single-word (16-bit) access to an even location described above).

† For a synch ronous write , the SEMI also asserts EA0 as a write strobe. The EROM compone nt is synchronous if the ERTYPE pin is logic high. The

ERAM compone nt is sy nchr onous if the YTYPE fie l d ( ECON1[9]) is se t. The EI O component i s s ynchr onous if the ITYPE fie l d ( ECON1[10]) is

set. ECON1 i s describ ed i n Table 6 1 on page 112.

ERTYPE

(input) 0 The EROM component is populat ed with ROM or asynchronous SRAM, and t he SE MI perf orms asynchro-

nous accesses to the EROM component.

1 The EROM compon ent is popul ated with synchronous

ZBT

SRAM, and the SEMI performs sync hronous

accesses to the EROM comp onent.

EXM

(input) 0 If EXM is logi c low when the RSTN pin makes a low-to-high tr ansition, bot h cores begin pro gram exe cution

from their internal ROM (IROM) memory at loc ation 0x3 0000.

1 If EXM i s logic high when the RSTN pin makes a low-to-high transition, both cores begi n program execution

from exter nal ROM (EROM) memory at l ocation 0x8000 0. The SEMI arb itrates the accesses from the two

cores.

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 103

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.1 External Interface (continued)

4.14.1.2 Asynchronous Memory Bus Arbitration

The SEMI allows an external device to request direct access to an asynchronous external memory by asserting the

EREQN pin. The SEM I acknowledges the external request by asserting its EA CKN pin. The SEMI allows an

external device to extend the duration of an external asynchronous access by deas serting the ERD Y pin.

Table 53. Asynch ro nous Memory Bus Arbitration Pins

Pin Description

EREQN

(negative-

assertion input)

An external device asserts EREQN (low) to request direct access to an async hronous exter nal memory. If

the NOSHARE fi eld (ECON1[8]—see Table 61 on page 112) is set, the DSP16411 ignor es the request . If

NOSHARE is cleared, a m inimum of f our cycles lat er the SEMI gr ants the r equest by per forming the fol low-

ing:



First, the SEMI completes any ext ernal acces s that is alr eady in progr ess.



The SEMI 3-st ates the addr ess bus and segment address ( EA[18:0] and ESEG[3:0]), the data bus

(ED[31: 0]), and all the external enables and strobes (ERAMN, EROMN, EIO N, and ERWN[1:0]) unti l the

external device deasserts EREQN. The SEMI continues to dri ve ECKO.



The SEMI acknowledges the request by asserting EACKN.

The cores and the DMAU contin ue processing. If a core or t he DMAU attempts to perform an external

memory access, it stalls until the external device relinquishes the bus. If the ext ernal devi ce deasserts

EREQN (c hanges EREQN from 0 to 1), four cycles lat er the SEMI deasserts EACKN (changes EACKN

from 0 to 1). To avoid exter nal bus content ion, the external device must wait for at least

ATIME

MAX

cycles†

after it deasserts EREQN (changes EREQN from 0 to 1) before reasserting EREQN (changi ng EREQ N

from 1 to 0). The soft ware can read th e stat e of the EREQN pin in the EREQN fie ld (ECON1[4]—s ee

Table 61 on page 112).

Note: If EREQN is not in use by the application, it must be tied high.

†

ATIME

MAX

is the great est o f IATI M E ( ECON0[ 11: 8]), YATI M E (ECON0[7:4]), and XATIME (ECON0[3:0]).

EACKN

(negative-

assertion output)

T he SE MI acknowledges the request of an external device for di rect access t o an asynchronous external

memor y by asserting E ACK N. See the descriptio n of the EREQN pin above fo r details. The sof twar e can

read the state of the EACKN pin in the EACKN field (ECON1[5]—see Table 61 on page 112).

ERDY

(positive-

assertion input)

An external de vice instructs the SEMI to extend th e duration of the current asynchronous external memory

acces s by driv ing ERDY l ow . See Secti on 4.14.5.2 on page 120 for details. The software can read the state

of the ERDY pin in the EREADY fie ld (ECON1[6]—see Table 61 on page 112 ).

Note: If thi s pin is not in use by the appl ication or if all external memory is syn chronous, ERDY must be

tied hi gh.

Advance Data Sheet

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104 A gere System s— P rop rietary Agere Systems In c.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.1 External Interface (continued)

4.14.1.3 Enables and Strobes

The SEMI provides a negative-assertion external memory enable output pin for each of the three external memory

components: ERAM, EIO, and EROM. These pins are the active-low enables for the external memory components

ERAM (external RAM), EROM (external ROM), and EIO (external I/O). Refer to the memory maps described in

Section 4. 5 on page 38 and shown in Figures 6, 7, 8, and 9 for details about these memory component s. T he

SEMI provides two negative-assertion write strobe output pins, ERWN[1:0]. Table 54 details the SEMI enables and

strobe pins. The SEMI 3-states the enables and strobes if it grants a request by an external device to access the

external memory (see description of the EREQN pin in Table 53 on page 103).

Table 54. E n able and Stro be Pins for the SEMI Externa l Interface

Pin Value Description

ERAMN

(negative-

assertion output)

0 The SEMI is sel ecting th e ERAM memory component f or an access. The SEMI ass erts this enable

for a duration based on whether the ERAM memory component is configur ed as asynchronous or

synchronous:



If th e ERAM memory component is configured as asynchronous (the YTYPE field

(ECON1[9]—see Table 61 on page 112) is cleared), the SEM I asserts ERAMN for the num ber of

instruction cycles spec if ied by the YATIME[3:0 ] field (ECON0[7:4]—see Table 60 on page 111).



If t he ERAM memory compon ent is con figur ed as synchr onous (the YTYPE fiel d is set), t he SEMI

asserts ERAMN for one ECKO cycle† for a read or write operation.

1 The SEMI is not sel ecting the ERAM memory component for an access.

Z The SEMI 3-states ERAMN if it grants a request by an external device to access the external mem-

ory (see des cription of the EREQN pin in Table 53 on page 103).

EION

(negative-

assertion output)

0 The SEMI is sel ecting t he EIO memo ry component for an access. The SEMI asserts this enable f or

a duration based on whether the EIO memory component is configured as asynchronous or syn-

chronous:



If t he EIO memory component is c onfigured as asynchron ous (the ITYPE field (ECON1[10]—see

Table 61 on page 112) is cleared), the SEMI asserts EION for the number of instr uction cycles

specified by the IATIME[3:0] field (ECON0[11:8] —se e Table 60 on page 111).



If th e EIO memory compon ent is configured as sync hronous (the ITYPE field is set), the SEMI

asserts EION for one ECKO cycl e† for a read or write operation.

1 The SEMI is not sel ecting the EIO memor y component for an acce ss.

Z The SEMI 3-st ates EION if it gra nts a request by an external device to access the external memory

(see description of the EREQN pin in Table 53 on page 103).

EROMN

(negative-

assertion output)

0 The SEMI is select in g the EROM memor y comp onent fo r an acces s †. Th e SEMI as serts this en able

for a duration based on whether the EROM memory component is configured as asynchronous or

synchronous:



If th e EROM memory component is configured as asynchronous (the ERTYPE pin is low), the

SEMI asserts EROMN for the number of instruction cycles speci fied by the XATIM E [3:0] field

(ECON0[3:0]—see Table 60 on page 111).



If th e EROM memory component is configured as synchronous (the ER TYPE pin is high), the

SEMI asser ts EROMN for one ECKO cycle† for a read or write operation‡.

1 The SEMI is not selecting the EROM memory component for a read access.

Z The SEMI 3-stat es EROMN if it grants a r equest by an external device to access the ext ernal mem-

ory (see des cription of the EREQN pin in Table 53 on page 103).

† If any memory component is configured as synchronous, ECKO must be programmed as CLK/2, CLK/3, or CLK/4 (see the ECKOB[1:0] and

ECKO A[1 :0 ] fields of ECON1—Table 61 on page 112).

‡ T he SEMI can writ e the EROM com ponent onl y if the WER O M field (ECON1[11 ]—see Table 61 on page 112) is set.

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 105

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

Table 54. Enable and Strobe Pin s for the S E M I Externa l Interface (continued)

4.14.1 External Interface (continued)

4.14.1.3 Enables and Strobes (continued)

4.14.1.4 Ex t e r n al Cloc k

The ECKO output pin provides an external clock for i nterfacing the SEM I to external synchronous memory. The

ECKOB[1:0] and ECKOA[1:0] fields (ECON1[3:0]—Table 61 on page 112) sel ect one of several configurations for

ECKO, as specified in Table 55. See Se ction 4. 19 on page 204 for additional detail.

Table 55. ECKO Output Clock Pin Configuration

ERWN1

(negative-

assertion output)

0 The external memory is configured for 32-bit data (th e ESIZE pi n is hi gh), and the SEMI is perf orm-

ing an external writ e access over the least signifi cant half of the external data bus (ED[15:0]).

1 The external memory is configured for 16-bit data (th e ESIZE pi n is l ow) or the external memory is

configured for 32-bit data (the ESIZE pin is high), and the SEMI is not performing an external wri te

access over the l east significant half of the extern al data bus (ED[15:0]).

Z The SEMI 3-states ERWN1 if it grants a request by an external device to access the external mem-

ory (see des cription of the EREQN pin in Table 53 on page 103).

ERWN0

(negative-

assertion output)

0 The SEMI is perf orming an exter nal write access over the most significant half of the external data

bus (ED[31: 16]).

1 The SEMI is not perf orming an ext ernal write access over the most significant half of the external

data bus (ED[31:16]).

Z The SEMI 3-states ERWN0 if it grants a request by an external device to access the external mem-

ory (see des cription of the EREQN pin in Table 53 on page 103).

ECKOB[1:0] ECKOA[1:0] ECKO Pin

ECON1[3] ECON1[2] ECON1[1] ECON1[0] State Description

0000CLK/2†

† Default after reset. After reset, CLK = CKI, so ECKO = CKI/2.

Frequency of CLK‡ di vided by two.

‡ CLK is the internal (core) clock. See Sec tion 4. 17 on page 200 fo r det ails.

0001CLK Frequency of CLK‡.

0010CKI Input clock pin.

00110 Logic zero.

0 1 X X Reserved —

1 0 X X CLK/3 Frequency of CLK‡ di vided by three .

1 1 X X CLK/4 Frequency of CLK‡ div ided by four .

Pin Value Description

† If any memory component is configured as synchronous, ECKO must be programmed as CLK/2, CLK/3, or CLK/4 (see the ECKOB[1:0] and

ECKO A[1 :0 ] fields of ECON1—Table 61 on page 112).

‡ T he SEMI can writ e the EROM com ponent onl y if the WER O M field ( ECON1[11 ]—see Table 61 on page 112) is set.

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

106 A gere System s— P rop rietary Agere Systems In c.

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ursuant to Com

any instructions

4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.1 External Interface (continued)

4.14.1.5 Address and Data

Table 56 details the address and data buses (ED[31:0]), EA[18:0], and ESEG[3 :0]) and the EYMODE signal.

Table 56. Address and Data Bus Pins for the SEMI E xter nal Interface

Pins Description

ED[31:16]†

(input/output)



If t he exter nal memory i s confi gured f or 16-bit data (t he ESIZE pin is low), t he SEMI uses ED[ 31:16] f or all

external accesses.



If th e exte rnal memory is confi gured for 32-bi t data (the ESIZE pin is hig h), the SEMI uses ED[31:16] if:

— The SEMI is accessing a single wor d (16 bi ts) at an even address.

— The SEMI is accessing a double word at an eve n (aligned) address.

— The SEMI is accessing the least significant half of a double word at an odd (misal igned) double-word

address.



If the SEMI is not currently performing one of the above types of accesses, it 3-states ED[31:16]. The

SEMI 3-states ED[31:16] if it grants a request by an external device to access the external memory (see

description of t he E REQN pin in Table 53 on page 103).

ED[15:0]†

(input/output)



If the external memor y is configured for 32-bit data (the ESIZE pin is high), the SEMI uses ED[15:0] if:

— The SEMI is accessing a single wor d (16 bi ts) at an odd address.

— The SEMI is accessing a double word at an eve n (aligned) address.

— The SEMI is accessing the most significant half of a doubl e word at an odd (mi saligned) double-word

address.



If t he SEMI is not cur re ntly pe rformi ng one of th e above ty pes o f access es, it 3-st ate s ED[15:0 ]. The SEMI

3-states ED[15:0] if it grants a request by an external device to access th e external memor y (see descr ip-

ti on o f the E R EQ N pin in Table 53 on page 103).

EA[18:1]†

(output)



If th e exte rnal memory is confi gured for 16-bi t data (the ESIZE pin is low), the SEMI places the 18 most

significant bits of the 19-bit external address onto EA[18:1].



If the ext ernal memory is configured for 32-bit data (the ESIZE pin is high), the SEMI places the 18-bit

external address onto EA[18:1].



After an access is complet e and before the start of a new access, the SEMI continues to drive EA[18:1]

with its current state.



The SEMI 3-states EA[18:1] if it grants a request by an external device to access the external memory

(see descriptio n of the EREQN pin in Table 53 on page 103).

EA0†

(output)



If th e external memory is conf igured for 16-bit data (the ESI ZE pin i s low) , the SEMI pl aces the least sig-

nificant bit of the 19-bit exter nal address onto EA0.



If t he exter nal m emory is c onfigu red for 32-bit data (t he ESIZE pi n is hi gh), t he SEMI does not use EA0 as

an address bit :

— If the selected memory component is configured as asynchr onous‡, the SEMI drives EA0 with its pre-

vious value.

— If the selected memory component is configured as synchr onous‡, the SEM I dr ives a negative-asser-

tion write strobe onto EA0 (the SEMI dri ves EA0 with the logical AND of ERWN1 and ERWN0) .



The SEMI 3-states EA0 if it grants a request by an external device to access the external memory (see

description of t he E REQN pin in Table 53 on page 103).

† T hese addr ess an d data bus pi ns con tain in tern al bus hold circuits. If BHEDI S (ECON1[12]—Table 61 on page 112 ) = 0, thes e bus hold circuit s are

act iv at ed. If BH ED I S = 0 an d neither t he SEMI nor an ext ernal device is driving thes e pi ns, the bus hol d circuits ho l d th em at their previous valid logic

level. This eliminates the need for external pull-up or pull-down resistors on these pins. See Section 10.1 on page 268 for d etails.

‡ The EROM compo nent is synchr onou s if the ERT YPE pin is logic 1. The ERAM compon ent is syn chron ous if YTYPE fie ld (ECON1[9]) is se t. The E IO

com ponent is synch ronous if the ITYPE f i el d (ECON1[10]) is set. ECON1 is de scribed i n Table 61 on page 112.

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 107

Use

ursuant to Com

any instructions

4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

Table 56. Address and Data Bus Pins for the SEMI E xter nal Interface (continued)

4.14.1 External Interface (continued)

4.14.1.5 Address and Data (continued)

The SEMI provides a 32-bit external data bus, ED[31:0]. If the external memory is configured for 16-bit data (the

ESIZE input pin is low), the SEMI uses only the upper half of the data bus (ED[31:16]). The SEMI provides a 19-bit

external address bus, EA[18:0], to select a locat ion within the selected external memory component (ERAM, EIO,

or EROM). If the external memory is configured for 16-bit data, the SEMI uses EA[18:0] to address single (16-bit )

words within t he selected mem ory compon ent . If the external memory is configured for 32-bit d ata (the ESIZE

input pin is high), the SEMI uses EA[18:1] to address double (32-bit) words within the selected memory component

and does not use EA0 as an address bit. For more detail, see Section 4.14.2 and Section 4.14.3 on page 109.

Note: The data and address bus pins (ED[31:0], EA[18:0], and ESEG[3:0]) contain internal bus hold circuit s. If

BHEDIS (ECON1[12]—Ta ble 61 on page 112) = 0, these bus hold circuits are activated. If BHED IS = 0 and

neither the SEMI nor an external device is driving these pins, the bus hold circuits hold them at their previous

valid logic level. This eliminates the need for external pull-up or pull-down resistors on these pins. See

Section 10. 1 on page 268 for details.

ESEG[3:0]†

(output)



If CORE0 acces ses EROM, the SEMI drives ESEG[3:0] with the conte nts of the XSEG0[3: 0] f iel d

(EXSEG0[3:0]—see Table 63 on page 114 ).



If CORE1 acces ses EROM, the SEMI drives ESEG[3:0] with the conte nts of the XSEG1[3: 0] f iel d

(EXSEG1[3:0]—see Table 64 on page 114 ).



If CORE0 accesses ERAM, the SEMI dr ives ESEG[3:0] with the contents of the YSEG0[3:0] field

(EYSEG0[3:0]—see Table 65 on page 115 ).



If CORE1 accesses ERAM, the SEMI dr ives ESEG[3:0] with the contents of the YSEG1[3:0] field

(EYSEG1[3:0]—see Table 66 on page 115 ).



If CORE0 acces ses EIO, the SEMI drives ESEG[3:0] with the con tents of the I SEG0 [3: 0] fi eld

(EYSEG0[7:4]—see Table 65 on page 115 ).



If CORE1 acces ses EIO, the SEMI drives ESEG[3:0] with the con tents of the I SEG1 [3: 0] fi eld

(EYSEG1[7:4]—see Table 66 on page 115 ).



If one of the DMAU SWT〈0—3〉 or M M T 〈4—5〉 channel s accesses EROM, ERAM, or EIO, the SEMI

places the contents of the ESEG[3:0] field (SADD〈0—5〉[26:23] for read operations and

DADD〈0—5〉[26:23] for write operations—see Tabl e 37 on page 77) onto its ESEG[3:0] pins.



If the PIU accesses EROM, ERAM, or EIO via the DMAU bypass channel, the SEMI pl aces the contents

of the ESEG[3 :0] fi eld (PA[26:23]—see Tab le 80 on page 138) onto its ESEG[3:0] pins.



After an access is compl ete and bef ore the start of a new acc ess, the SEMI continues to dri ve ESEG[3:0]

with its current state.



The SEMI 3-st ates ESEG[3:0] if it grants a request by an external device to access the external memory

(see descriptio n of the EREQN pin in Table 53 on page 103).

EYMODE

(input) This pin determines the mode of t he external data bus. I t must be static and tied to VSS (if the SEMI is used)

or VDD2 (i f the SEMI is not used) . If EYMODE = 0, the ext ernal data bus ED[31:0] operates normally as

described above. If EYMODE = 1, ED[31:0] are statically conf igured as outputs (regardless of the state of

RSTN) and must not be connected externally. See Section 10.1 on page 268 for details.

Pins Description

† T hese addr ess an d data bus pi ns con tain in tern al bus hold circuits. If BHEDI S (ECON1[12]—Table 61 on page 112 ) = 0, thes e bus hold circuit s are

act i vat ed. If BH ED I S = 0 an d nei ther the SEMI nor an ext ernal device is driving thes e pi ns, the bus hol d circuits ho l d th em at their previous valid logic

level. This eliminates the need for external pull-up or pull-down resistors on these pins. See Section 10.1 on page 268 for d etails.

‡ The EROM compo nent is synchr onou s if the ERT YPE pin is logic 1. The ERAM compon ent is syn chron ous if YTYPE fie ld (ECON1[9]) i s se t. The E IO

com ponent is synch ronous if the ITYPE f i el d (ECON1[10]) is set. ECON1 is descri bed i n Tabl e 61 on page 112 .

Advance Data Sheet

DSP16411 Digital Signal Processor April 2002

108 A gere System s— P rop rietary Agere Systems In c.

Use

ursuant to Com

any instructions

4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.1 External Interface (continued)

4.14.1.6 Address and Data

The SEMI 3-states ED[31:0], EA[18: 0], and ESEG[3:0]

if it grants a request by an external device to access

the external memory (see description of the EREQN

pin in Table 53 on page 103 ).

The SEMI provides the ESEG[3:0] pins to expand the

size of each of the external memory components, using

one of the following methods:

1. E SEG[3: 0] can be interpreted by the external mem-

ory system as four separa te decoded address

enable signals. Each ESEG[3:0] pin individually

selects one of four segme nts for each memory

component. This results in four glueless 512 Kword

(1 Mbyte) ERAM segments, four glueless 512 Kword

(1 Mbyte) EROM segments, and four glueless

128 Kword (256 Kbytes) EIO segments.

2. E SEG[3: 0] can be interpreted by the external mem-

ory system as an extension of the address bus, i.e.,

th e ESEG[3 :0] pins c an be con ca tenated with the

EAB[18:0] pins to form a 23-bit address. This results

in one glueless 8 Mword (16 M by tes) ERAM seg-

ment, one glueless 8 Mwo rd (16 M by tes) EROM

segment, and one glueless 2 Mword (4 Mbytes) EIO

segment.

For external accesses by either core, the SEMI places

the conte nts of a fi eld in one of four segment address

exten s i o n re g isters onto the ESEG [3 :0] pins. The four

segment address extension registers are described in

Sect ion 4.14.4.3 on page 114. For external accesses

by the DMAU or PIU, the contents of address registers

within those units determine the state of the ESEG[3:0]

pins. See Table 56, beginning on page 106, for more

detail.

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

Agere Systems In c. Agere Systems—P ropri etary 109

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.2 16-Bit External Bus Accesses

Regardless of the configuration of the external data bus via the ESIZE pin, each access by a core or the DMAU

can be a 16-bit (single-word) or 32-bit (double-word) access. Table 57 summarizes each type of access for a 16-bit

external bus configuration (ESIZE = 0).

Table 57. 16-Bit External Bus Configuration

4.14.3 32-Bit External Bus Accesses

Regardless of the configuration of the external data bus via the ESIZE pin, each access by a core or the DMAU

can be a 16-bit (single-word) or 32-bit (double-word) access. Table 58 summarizes each type of access for a 32-bit

external bus configuration (ESIZE = 1).

Table 58. 32-Bit External Bus Configuration

Internal Address Type of Access External Address External Data ERWN1 ERW N0

Even or O d d Single- Word Re ad E v en or Od d E A [18:0 ] ED [31 :16] 1 1

Single-Word Write EA[18:0] ED[31:16] 1 0

Even (aligned†)

† The SE M I perf orms t wo separa te bac k-to -back 16-bi t a cc ess es, even addres s (most signi ficant data) f i rst and odd addres s (least signi ficant dat a) sec -

ond.

Double-Word Read Even EA[18:0] ED[31:16] 1 1

Odd EA[18:0] ED[31:16] 1 1

Double-Word Wri te Even EA[18:0] ED[31:16] 1 0

Odd EA[18:0] ED[31:16] 1 0

Odd (misaligned‡)

‡ The SEMI perform s t wo separate 1 6-bit acc esse s, odd address (most si gnificant d ata) f i rst an d even addr ess (least signi ficant dat a) sec ond. The tw o

acces ses are not neces saril y back-to- back , i.e., t hey ca n be separa ted by other ac ces ses.

Double-Word Read Odd EA[18:0] ED[31:16] 1 1

Even EA[18:0] ED[31:16] 1 1

Double-Word Wri te Odd EA[18:0] ED[31:16] 1 0

Even EA[18:0] ED[31:16] 1 0

Internal Address Type of Access Exte rnal Address External Data ERWN1 ERWN0

Even Single-Word Read EA[18:1] ED[31:16] 1 1

Single- Word Write EA[18:1] ED[31:16] 1 0†

† For a wr i te operati on to a syn chronou s m em o ry c om ponent, the SEM I also drives the EA0 pi n lo w for us e as a write enable. Th e E ROM co m ponent is

synchronous if the ERTYPE pin is logic 1. The ERAM componen t is synchro nous if the YTYPE field (ECON1[9]) is set. The EIO component is syn-

chronous i f t he ITY PE f i el d (ECON1[10]) is set. ECON1 i s des cr i bed in Tab l e 61 on page 112.

Odd Single-Word Read EA[ 18:1] ED[15:0] 1 1

Single- Word Write EA[18:1] ED[15:0] 0†1

Even (ali gned) Double- W ord Read EA[18: 1] ED[31:0] 1 1

Double- Word Write EA[18:1] ED[31: 0] 0†0†

Odd (misaligned‡)

‡ The SE M I perf orms t wo separa te 16-bit ac ces ses. I t access es the mo st signi ficant data in the odd a ddres s f i rst, and th en the least signi ficant data in

the ev en address seco nd. The two access es are no t nece ss ari l y back-to- back , i.e. , they ca n be separated by ot her acc ess es.

Double-Word Read EA[ 18:1] ED[15:0] 1 1

EA[18:1] ED[31:16] 1 1

Double- W ord W ri te EA[18:1] ED[15:0] 0†1

EA[18:1] ED[31:16] 1 0†

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.4 Re g ister s

There are six 16-bit memory-mappe d control registers that configure the operation of the SEMI, as shown in

Table 59.

Table 59. S E M I Memory -Map ped Registers

(Bits) R/W Type Reset Value

ECON0 0x40000 SEMI Contro l 16 R/W Contr ol 0x0FFF

ECON1 0x40002 SEMI Status and Control 16 R/W†Control 0‡

EXSEG0 0x40004 External X Segment Regist er f or CORE0 16 R/W Address 0

EYSEG0 0x40006 External Y Segment Regist er f or CORE0

EXSEG1 0x40008 External X Segment Regist er f or CORE1

EYSEG1 0x4000A Exter nal Y Segment Register for CORE1

† Some bi ts in t hi s regis ter ar e read-only or writ e-onl y.

‡ With the fol l owin g exce pt i ons: ECON1[6,4 ] ar e a reflect i on of the sta te o f ex t ernal pi ns and are unaff ected by reset, and ECON1[5] i s se t.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.4 Re g ister s (continued)

4.14.4.1 ECON0 Reg ister

ECON0 determi nes the setup, hold, and assertion times for the t hree external memory componen t enables. Th e

programmer needs to use the ECON0 register only if one or more of the external mem ory components (ERAM,

EROM , or EIO) is c onfigu re d as asynchronous (se e Section 4.14.4.2 on page 112 and Secti on 4.14.1.1 on

page 102).

Table 60. ECON 0 (External Contro l 0) Register

The memory address for this register is 0x40000.

15 14 13 12 11—8 7—4 3—0

WHOLD RHOLD WSETUP RSETUP IATIME[3:0] YATIME[3:0] XATIME[3:0]

Bit Field Value Description R/W Reset

Value

15 WHOLD 0 The SEMI does not extend t he wri te cycle. R/W 0

1 The SEMI extends the wri te cycle for one CLK cycle, appl ies the ta rget address,

deasserts all enables, deasserts all write strobes, and 3-states ED[31:0].

14 RHOLD 0 The SEMI doe s not ext end the read cycle. R/W 0

1 The SEMI extends the read cycle for one CLK cycle, applie s the target address,

and deasserts all enables.

13 WSETUP 0 The SEMI does not delay the assert ion of the writ e strobe, the memor y enable,

and the assertion of ED[31: 0] for writ e operations. R/W 0

1 The SEMI delays the assertion of th e wri te strobe, the memo ry enable, and

ED[31:0] during a write cycl e for one CLK cycle. During the setup time, the SEMI

applies the target address to EA[18:0], deasserts all enables and ERWN signal s,

and 3-states ED[31:0].

12 RSETUP 0 The SEMI does not delay the assertion of the memory enable for read oper ations. R/W 0

1 The SEMI delays the assertion of th e memor y enable during a read cycle for one

CLK cycle. During the setup time, the SEMI applies t he target addre ss to

EA[18:0], deasserts all enables and ERWN signals, and 3-stat es ED[31:0].

11—8 IATIME[3:0] 0— 15 The duration in CLK cycles (1—15) that the SEMI asserts EION for an asynchro-

nous access to the EIO component. A value of 0 or 1 corresponds to a 1 CLK

cycle assertion time.

R/W 0xF

7—4 YATIME[3: 0] 0—15 The duration in CLK cycles (1— 15) that the SEMI asserts ERAMN f or an asyn-

chronous access to the ERAM component. A value of 0 or 1 corresponds to a 1

CLK cycle assertion time.

R/W 0xF

3—0 XATIME[3: 0] 0—15 The duration in CLK cycles (1— 15) that the SEMI asserts EROMN for an asyn-

chronous access to the EROM component. A val ue of 0 or 1 corresponds to a 1

CLK cycle assertion time.

R/W 0xF

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.4 Re g ister s (continued)

4.14.4.2 ECON1 Reg ister

The ECON1 register (Table 61) reports status information and controls additional features of the SEMI.

Table 61. EC O N1 (External Control 1) Register

The memory address for this register is 0x40002.

15—14 13121110 9 8

Reserved BHPDIS BHEDIS WEROM ITYPE YTYPE NOSHARE

7654 3—2 1—0

Reserved EREADY EACKN EREQN ECKOB[1:0] ECKOA[1:0]‡

Bit Field Value Description R/W Reset

Value

15—13 Reser ved 0 Reserved—writ e wit h zero. R/W 0

13 BHPDIS 0 E nable the bus hold circuits on the PD[ 15:0] and PADD[3:0] pins (see Section 10 .1

on page 268 for details). R/W 0

1 Disable the bus hold ci rcuits on the PD[15 :0] and PADD[3: 0] pi ns.

12 BHEDIS 0 E nable the bus hold circuits on the ED[31:0], EA[18:0], and ESEG[3:0] pins (see

Section 10.1 on page 268 for details). R/W 0

1 Dis able the bus hold cir cui ts on the ED[31 :0] , EA[18: 0], and ESEG[3: 0] pins .

11 WEROM 0 The exter nal port ion of Y-memo ry and Z-memory space is ERAM (see

Section 4.5.3 on page 39). R/W 0

1 The external port ion of Y-me mo ry and Z-memory space is EROM (see

Section 4.5.3 on page 39).

10 IT YPE 0 EION i s asynchronous SRAM. R/W 0

1 EION is pipelined, synchronous SRAM .

9 YTYPE 0 ERAMN is asynchronous SRAM. R/W 0

1 ERAMN is pi pelined, synchr onous SRAM.

8 NOSHARE 0 SEMI works as a bus-shared interface and asserts EACKN in re sponse to EREQN. R/W 0

1 SEMI ig nores request s for the external bus and does not assert EACKN.

7 Reserved 0 Reserved—write with zero. R/W 0

6 EREADY 0 The ERDY pin indicates an external device is requesting the SEMI to ext end the

current asynchr onous ex ternal memory access (see Table 53 on page 103). RP

†

1 The ERDY pin indicates an ext ernal device is not requesting the SEMI to exten d

the current async hronous external memory access (see Table 53 on page 103).

5 EACKN 0 The EACKN pin indicates the SEM I acknowledges a re quest by an external device

for access to external memory ( see Table 53 on page 103). R1

1 The EACKN pin indicates th e SEMI does not acknowl edge a request by an ext er-

nal device for access to external memory (see Table 53 on page 103).

4 EREQN 0 The EREQN pin i ndicates an external device is re questing acce ss to external

memory (see Table 53 on page 103). RP

†

1 The EREQN pin i ndicates an external device is not requ esting access to external

memory (see Table 53 on page 103).

† The state (P) is a reflection of the state of the external pins and is unaffected by reset.

‡ T he st ate of this field i s ignored unless ECKOB[ 1: 0] = 00.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

Table 61. ECON1 Register (continued)

4.14.4 Re g ister s (continued)

4.14.4.2 ECON1 Reg ister (continued)

The ECKOB [1:0] and ECKO A[1: 0] fields (ECON1[3:0 ]) determin e the state of the E CK O output clock pin as sum-

marized in Table 62. If any of the external memory components (ERAM, EROM, or EIO) are configured as synchro-

nous1, the ECKO pin must be configured as CLK/2, CLK/3, or CLK / 4.

Table 62. ECKO Output Clock Pin Configuration

3—2 ECKOB[1: 0] 00 The ECKOA[1:0] fi eld determ ines the configu ration of the ECKO pin. R/W 00

01 Reserved.

10 The ECKO pin is CLK/3 for syn chronous operation of the SEMI.

11 The ECKO pin is CLK/4 for syn chronous operation of the SEMI.

1—0 ECKOA[1:0]‡00 The ECKO pin is CLK/2 f or synchronous operat ion of the SEMI. R/W 00

01 The ECKO pin is the inte rnal clock CLK.

10 The ECKO pin is the buffered i nput cloc k pin CKI.

11 The ECKO pin is held low.

1. The EROM c ompo nen t i s sy nc hron o us i f th e ER T YPE p in is logic 1. The ERAM co mpon en t is synch ronou s if the YTYPE field (ECON1[9]) is se t. The

EIO compo n ent is synch ron ou s if the ITYPE fi e ld (ECON1[10]) is se t. ECON1 is desc ri bed i n Table 61 on page 11 2.

ECKOB[1:0] ECKOA[1:0] ECKO Pin

ECON1[3] ECON1[2] ECON1[1] ECON1[0] State Description

0000CLK/2†

† Default after reset. After reset, CLK = CKI, so ECKO = CKI/2.

Frequency of CLK‡ di vided by two.

‡ CLK is the internal (core) clock. See Sec tion 4. 17 on page 200 fo r det ails.

0001CLK Frequency of CLK‡.

0010CKI Input clock pin.

00110 Logic zero.

0 1 X X Reserved —

1 0 X X CLK/3 Frequency of CLK‡ di vided by three .

1 1 X X CLK/4 Frequency of CLK‡ div ided by four .

Bit Field Value Description R/W Reset

Value

† The state (P) is a reflection of the state of the external pins and is unaffected by reset.

‡ T he st ate of this field i s ignored unless ECKOB[ 1: 0] = 00.

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4 4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.4 Re g ister s (continued)

4.14.4.3 Segment Registers

The external program and data memory components

(EROM, ERAM, and EIO) can each be expanded for

each core through a combination of registers and pins.

The ESEG[3:0] pins (see Sec tion 4 .14.1 on page 101)

reflect the value of the EXSEG0, EXSEG1, EYSEG0,

or EYSEG1 external segment re gisters for a given

external access. A user’s program executing in either

core can write to these registers to expand the external

ERAM and EROM data components. The value written

to any one of these registe rs is driven onto the

ESEG[3:0] pins for a corresponding memory compo-

nent as described below, and can be interpreted by the

system as an address extension (EA[22:19], for exam-

ple) or as decoded enables.

The SEMI drives bits 3:0 of the 16-bit EXSEG0 register

onto the ESEG[3:0 ] pins at the same time as it drives

the address onto EA[18:0] for an external ROM

(EROM) access from CORE0.

The SEM I drives bits 3:0 (f or ERAM ) or bits 7: 4 (for

EIO) of the 16-bit EYSEG0 register ont o the ESEG[3:0]

pins at the same time as it drives the address onto

EA[18:0] for an external RAM (ERAM or EIO) access

from CORE0.

The SEMI drives bits 3:0 of the 16-bit EXSEG1 register

onto the ESEG[3:0 ] pins at the same time as it drives

the address onto EA[18:0] for an external ROM

(EROM) access from CORE1.

The SEM I drives bits 3:0 (f or ERAM ) or bits 7: 4 (for

EIO) of the 16-bit EYSEG1 register ont o the ESEG[3:0]

pins at the same time as it drives the address onto

EA[18:0] for an external RAM (ERAM or EIO) access

from CORE1.

Table 63. EXSEG0 (CORE0 External X Segment Address Extension ) Register

Table 64. EXSEG1 (CORE1 External X Segment Address Extension ) Register

The memory address for this register is 0x40004.

15—4 3—0

Reserved XSEG0[3:0]

Bit Field Description R/W Reset Value

15—4 Reserved Reserved—write wit h zero. R/W 0

3—0 XSEG0[3:0] Exter nal segment addr ess extension for X-me mory accesses to EROM by

CORE0. R/W 0

The memory address for this register is 0x40008.

15—4 3—0

Reserved XSEG1[3:0]

Bit Field Description R/W Reset Value

15—4 Reserved Reserved—write wit h zero. R/W 0

3—0 XSEG1[3:0] External segment addr ess extension for X-me mo ry acc esses to EROM by

CORE1. R/W 0

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.4 Re g ister s (continued)

4.14.4. 3 Segm ent Register s (continued)

Table 65. EYSEG0 (CORE0 External Y Segment Address Extension ) Register

Table 66. EYSEG1 (CORE1 External Y Segment Address Extension ) Register

The memory address for this register is 0x40006.

15—8 7—4 3—0

Reserved ISEG0[3:0] YSEG0[3:0]

Bit Field Description R/W Reset Value

15—8 Reserved Reserved—write wit h zero. R/W 0

7—4 ISEG0[3:0] External segment addr ess extension for Y-memory accesses to EIO by

CORE0. R/W 0

3—0 YSEG0[3:0] External segment addr ess extension for Y-memory accesses to ERAM by

CORE0. R/W 0

The memory address for this register is 0x4000A .

15—8 7—4 3—0

Reserved ISEG1[3:0] YSEG1[3:0]

Bit Field Description R/W Reset Value

15—8 Reserved Reserved—write wit h zero. R/W 0

7—4 ISEG1[3:0] External segment addr ess extension for Y-memory accesses to EIO by

CORE1. R/W 0

3—0 YSEG1[3:0] External segment addr ess extension for Y-memory accesses to ERAM by

CORE1. R/W 0

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.5 Asynchronous Memory

This section describes the functional timing and inter-

facing for external m em ory components that are con-

figured as asynchronous. The EROM component is

asynchronous if the ERTYPE pi n is l ogic 0 . The ERAM

component is asynchronous if the YTYPE field

(ECON1[9]) is c l eared, and the EIO com ponent is

asynchronous if the ITYPE fi eld (ECON1[10 ]) is

cleared. ECON1 is described in Table 61 on page 112.

In this section:



The designat ion

ENABLE

refers to the EROMN,

ERAMN, or EION pin.



The designat ion

ERWN

refers to:

— The ERWN0 pin if the external data bus is config-

ured as 16 bits, i.e., if the ESIZE pin is logic low.

— The ERWN1 and ERWN0 pins if the external data

bus is configured as 32 bits, i.e., if the E S IZE pin

is logic high.



The designat ion

refers to:

— The external address pins EA[18:0] and the exter-

nal segment address pins ESEG [3:0] if the exter-

nal data bus is configured as 16 bits, i.e., if the

ESIZE pin is logic low.

— The external address pins EA[18:1] and the exter-

nal segment address pins ESEG [3:0] if the exter-

nal data bus is configured as 32 bits, i.e., if the

ESIZE pin is logic high.



The designat ion

re fe r s to :

— The external data pins ED[31:16] if the external

data bus is configured as 16 bits, i.e., if t he ESIZE

pin is logic low.

— The external data pins ED[31:0] if the external

data bus is configured as 32 bits, i.e., if t he ESIZE

pin is logic high.



The designat ion

ATIME

refers to IATIME

(ECON0[11:8]) for accesses to the EIO space,

YATIME (ECON0[7:4]) for accesses to the ERAM

space, or XATIME (ECON0[3:0]) for acce sses to the

ERO M spac e.



RSETUP refers to the RSE T UP field

(ECON0[12]—s ee Table 60 on page 1 11 ).



RHOLD refers to the RHOLD field (ECON0[14]).



WSETUP refers to the WSETUP fie ld ( ECON0[13]).



WHOLD refers to the WHOLD field (ECON0[15]).

4.14.5. 1 Functional Timing

The following describes the functional timing for an

asynchronous read operation:

1. On a r ising edge of t he i nte rnal clock (CLK) , the

SEMI asserts

ENABLE

and drives the read address

onto

. If RSETUP is set, the SEMI asserts

ENABLE

one CLK cycle later.

2. T he SEM I asserts

ENABLE

for

ATIME

CLK cycles.

3. The SEM I deasserts

ENABLE

on a rising edge of

CLK and latches the data from

4. The SEM I continues to drive the read address onto

for a minimum of one CLK cycle to guarantee an

address hold time of at l east one cycle. If RHOLD i s

set, the SEMI continues to drive the read address for

an additional CLK cycle.

The SEM I continues to drive the address until another

external memory access is initiated. Another read or a

write to the same memory component can immediately

follow the read cycle described above.

The following describes the functional timing for an

asynchronous write operation:

1. On a r ising edge of t he i nte rnal clock (CLK) , the

SEMI asserts

ERWN

and drives the write addres s

onto

. If WSETUP is set, the SEMI asserts

ERWN

one C LK cycle la ter.

2. One CLK cycle after the SEMI asserts

ERWN

, th e

SEMI asserts

ENABLE

and drives valid data onto

guarantee one CLK cycle of setup time.

3. T he SEM I asserts

ENABLE

for

ATIME

CLK cycles.

4. The SEM I deasserts

ENABLE

on a rising edge of

CLK.

5. The SEM I continues to drive

with the write data,

drive

with the write address, and assert

ERWN

for one additional CLK cycle to guarantee one cycle

of hold time. If WHOLD is set, the SEMI continues

to drive the write address for an additional CLK

cycle.

The SEM I continues to drive the addres s until another

external mem ory access is initiated. Anoth er write to

the same memory component can immediately follow

the write cycle described above. If a read to t he same

mem ory compone nt follows the write cyc le described

above, the SEMI inserts an idle bus cycle (one CLK

cycle).

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.5 Asynchronous Memory (continued)

4.1 4.5 .1 Fu nct i on a l Timing (continued)

Fig ur e s 27 through 30 provide examples of asynchronous me mory accesse s for various SEMI configurations.

These examples ass ume that the DMAU is perform ing the external memory accesses. The access rate shown is

not achievable if the accesses are performed by one or both cores. For det ails on SEMI performanc e for an asyn-

chronous interface, see Section 4.14.7.2 on page 129. For a summary of SEMI performance, see Section 4.14.7.4

on page 133.

Asynchrono us Ti mi ng

Notes:

It is ass ume d th at EC KO is pr og ramme d a s CL K, i .e . , th e E CKO B[1 :0 ] fi el d (ECON1[3:2]—Table 61 on page 1 12) is pr og ra m med to 0x 0 a nd th e

ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.

It is assumed that the YATIME[3:0] field (ECON0[7:4]—Tabl e 60 on page 111 ) is programmed to 0x2 and the IATIME[3: 0] field (ECON0[11:8 ]) is

progra mmed to 0x3.

It is assumed that the DMAU is performing the external memory accesses. The access rate sho wn is not achievable if the accesses are per-

formed by one or both cores.

Figure 27. Async hro no us Me m ory Cycles

EION

ERWN

ECKO

ERAMN

DON’T CARE

HIGH-IMPEDANCE OUTPUT

ERAM ERAM ERAMERAM ERAM EIO EIO

READ READ WRITEWRITE WRITE READ READ

IATIME

A5A4

A3A2A1A0

IDLE CYCLE: WRITE FOLLOWED IMMEDIATELY BY READ

D1 D2 D6Q3 Q4 Q5

YATIME YATIME YATIME YATIME YATIME

IATIME

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.5 Asynchronous Memory (continued)

4.1 4.5 .1 Fu nct i on a l Timing (continued)

Asynchronous Memory Cycles (RSETUP = 1, WSETUP = 1)

Notes:

It is ass ume d th at EC KO is pr og ramme d a s CL K, i .e . , th e E CKO B[1 :0 ] fi el d (ECON1[3:2]—Table 61 on page 1 12) is pr og ra m med to 0x 0 a nd th e

ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.

It is assumed that the YATIME[3:0] field (ECON0[7:4]—Tabl e 60 on page 111 ) is programmed to 0x2 and the IATIME[3: 0] field (ECON0[11:8 ]) is

progra mmed to 0x3.

It is assumed that the DMAU is perfo rming t he external memory accesses. The access rate sho wn is not achievable if the accesses are per-

formed by one or both cores.

Figure 28. Asynch ronou s Memo ry Cycl es (RSETUP = 1, WSE TUP = 1)

EIO

ERWN

ERAM

D1 D2

IDLE CYCLE: WRITE FOLLOWED IMMEDIATELY BY READ

EIO

ECKO

Q0 D1 D2

HIGH-IMPEDANCE OUTPUT

ERAM ERAMERAM EIO

ERAM

A1 A2 A3 A4 A5

READ WRITE WRITE READ READ WRITE

RSETUP

YATIME

IATIME

WSETUP WSETUP WSETUP

RSETUP

Q3 Q4

YATIME YATIME YATIME

IATIME

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.5 Asynchronous Memory (continued)

4.1 4.5 .1 Fu nct i on a l Timing (continued)

Asynchronous Memory Cycles (RHOLD = 1, WHOLD = 1)

Notes:

It is ass ume d th at EC KO is p r ogra mme d as CL K, i .e. , t h e ECKO B[ 1:0 ] fi el d (ECON1[3:2]—Table 61 on page 1 12) is pr og r am med to 0x 0 a nd th e

ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.

It is assumed that the YATIME[3:0] field (ECON0[7:4]—Tabl e 60 on page 111 ) is programmed to 0x2 and the IATIME[3: 0] field (ECON0[11:8 ]) is

progra mmed to 0x3.

It is assumed that the DMAU is performing the external memory accesses. The access rate sho wn is not achievable if the accesses are per-

formed by one or both cores.

Figure 29. Asynchronous Memory Cycles (RHOLD = 1, WHOLD = 1)

ECKO

EIO

ERWN

ERAM

D1 D2 D5

A0 A1

RHOLD

YATIME

IATIME

WHOLD WHOLD WHOLDRHOLD RHOLD

IDLE CYCLE: WRITE FOLLOWED IMMEDIATELY BY READ

HIGH-IMPEDANCE OUTPUT

EIOERAM ERAMERAM EIOERAM

READ WRITE WRITE READ READ WRITE

Q3 Q4Q0

IATIME

YATIME YATIME YATIME

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.5 Asynchronous Memory (continued)

4.14.5.2 Extending Access Tim e Via th e ERDY Pin

An external device can delay the completion of an external memory access to an asynchronous memory compo-

nent by control of the ERDY pin (see Figure 30). If driven low by the ext ernal device, t he SEMI extends the current

external memory access that is already in progress. To guarantee proper operation, ERDY must be driven low at

least 4 CLK cycles before the end of t he acc ess and the enable mus t be programm ed for at least 5 CLK cycles of

assertion (via the YA TIME, XATIME, or IATIME field of ECON0—see Table 60 on page 111). The SEMI ignores the

state of ERDY prior to 4 CLK cycle s before the end of t he acc ess. The access is extended by 4 CLK cycles after

ERDY is driven high. The state of ERDY is readable in the EREADY field (ECON1[6]—see Table 61 on page 112).

This feature of the SEMI provides a convenient interface to peripherals that have a variable access time or require

an access time greater than 15 CLK cyc le s in duration.

Use of ERDY Pin to Extend Asynchronous Accesses

Figure 30. Use of ERDY Pin to Extend Asynchronous Accesses

ENABLE

††

ERDY

4T‡

× T‡

SEMI

SAMPLES

ERDY PIN

ECKO§

ATIME

†

END OF

ACCESS

(UNSTALLED)

× T‡

4T‡

END OF

ACCESS

(STALLED)

†

ATIME

mus t be programmed as greater th an or equal to five CLK cycles. Otherwise, the SEMI ignores the state of ER DY.

‡ T = internal clock period (CLK).

must be greater than or equal to one, i.e., ERDY must be held low for at least one CLK cycle af ter t he

SEMI samples ERDY.

§ ECKO reflects CLK, i.e., ECON1[1:0] = 1.

†† The designation

ENABLE

refers to one of the following pins: EROMN, ERAMN, or EION.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.5 Asynchronous Memory (continued)

4.14.5.2 Extending Access Time Via the ERDY Pin (continued)

Figure 31 illustrates an examp le read and write operation using the ERDY pin to extend the accesses.

Use of ERDY Pin to Extend Asynchronous Accesses

Notes:

It is ass ume d th at EC KO is pr og ramme d a s CL K, i .e . , th e E CKO B[1 :0 ] fi el d (ECON1[3:2]—Table 61 on page 1 12) is pr og ra m med to 0x 0 a nd th e

ECKOA[1:0] field (ECON1[1:2]) is programmed to 0x1.

It is assumed that the YATIME[3:0] field (ECON0[7:4]—Table 60 on page 1 11) is program m ed to 0x 7.

Figure 31. Example of Using the ERDY Pin

HIGH-IMPEDANCE OUTPUT

ECKO

ERAMN

ERDY

YATIME STALL YATIME STALL

ERWN

A0 A1

DON’T CARE

ERAM ERAM

READ WRITE

4T 4T

SAMPLE

POINT SAMPLE

POINT

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.5 Asynchronous Memory (continued)

4.14.5.3 Interfacing Examples

Figures 32 and 33 illustrate two exam ples of interfacing 16-bit asynchronous SRAM s to the SEMI. Th e use r can

individually configure the EROMN, ERAM N, and EION enables to suppo rt asynchronous dev ices. Th e ERTYPE

pin must be at logic low for the EROM component to be configured for asynchronous accesses. Clearing the

YTYPE field (ECON1[ 9]) and ITYPE field (ECON1[10]) configures the ERAM and EIO components for asynchro-

nous accesses.

The programmer can individually configure the access time (defined as the number of CLK cycles that the enable

is asserted) for each enable. The YATIME field (ECON0[7:4]) specifies the number of CLK cycles that the ERAMN

enable is asserted. The XATIME field ( ECON0[3:0]) specifies t he number of CLK cycles that the EROMN enable is

asserted. The IATIME field (ECON0[11:8]) specifies the number of CLK cycles that the EION enable is asserted.

The range of val ues for these fields is from 0 to 15 (corresponding to a ra nge of 1 to 15 CLK cycles). A value of 0

or 1 programs a 1 CLK assertion time for the corresponding enable.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.5 Asynchronous Memory (continued)

4.14.5.3 Interfacing Examples (continued)

32-Bit E xternal Interface with 16-Bit Asynchronous SRAMs

Figure 32. 32-Bit External Interface wi th 16-Bit Asynchro no us SRAMs

16-Bit E xternal Interface with 16-Bit Asynchronous SRAMs

Figure 33. 16-Bit External Interface wi th 16-Bit Asynchro no us SRAMs

SRAM

A[15:0]

DB[15:0]

SRAM

A[15:0]

DB[15:0]

DSP16411

SEMI

ESIZE VDD

EA[16:1]

ERWN0

ERAMN

ED[31:16]

ERWN1

ED[15:0]

EVEN ADDRESS

ODD ADDRESS

ERTYPE VSS

SRAM

A[16:0]

DB[15:0]

DSP16411 SEMI

ESIZE VSS

EA[16:0]

ERWN0

ERAMN

ED[31:16]

ERTYPE VSS

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.6 Synchronous Memory

This section describes the functional timing and inter-

facing for external m em ory components that are con-

figured as synchronous. The EROM compo nent is

synchronous if the ERT Y PE pin is logic 1. The ERAM

component is synchronous if the YTYPE field

(ECON1[9]) is s et, and the EIO component is synchro-

nous if the ITYPE field (ECON1[10]) is set. ECON1 is

described in Table 61 on page 112.

If any of the external memory component s (EROM,

ERAM, or EIO) are configured as synchronous, the

SEMI external output clock (ECKO) must be pro-

grammed as CLK/2, CLK/3, or CLK/4 (see t he

ECKOB[1:0] and ECKOA[1:0] fields of ECON1[1:0]).

After reset, the d efault state of ECKO is CLK/2.

In this section:



The designat ion

ENABLE

refers to the EROMN,

ERAMN, or EION pin.



The designat ion

ERWN

refers to:

— The ERWN0 pin if the external data bus is config-

ured as 16 bits, i.e., if the ESIZE pin is logic low.

— The ERWN1, ERWN0, and EA 01 pins if the exter-

nal data bus is configured as 32 bits, i.e., if the

ESIZE pin is logic high.



The designat ion

refers to:

— The external address pins EA[18:0] and the exter-

nal segment address pins ESEG [3:0] if the exter-

nal data bus is configured as 16 bits, i.e., if the

ESIZE pin is logic low.

— The external address pins EA[18:1] and the exter-

nal segment address pins ESEG [3:0] if the exter-

nal data bus is configured as 32 bits, i.e., if the

ESIZE pin is logic high.



The designat ion

re fe r s to :

— The external data pins ED[31:16] if the external

data bus is configured as 16 bits, i.e., if t he ESIZE

pin is logic low.

— The external data pins ED[31:0] if the external

data bus is configured as 32 bits, i.e., if t he ESIZE

pin is logic high.

4.14.6. 1 Functional Timing

The following describes the functional timing for a syn-

chronous read operation (see Figure 34 on page 125):

1. On a rising edge of the external output clock

(ECKO), the SEMI drives the read address onto

and asserts

ENABLE

for one ECKO cycle.

2. On the rising edge of the second ECKO cycle, the

SEMI deasserts

ENABLE

3. On the rising edge of the third ECKO cycle, a new

access can begin because synchronous accesses

are pipelined.

4. On the rising edge of the fourth ECKO cycle, the

SEM I latches the data from

The following describes the functional timing for a syn-

chrono us write operation (see Figure 34 on page 125):

1. On a rising edge of the external output clock

(ECKO), the SEMI drives the write address onto

and asserts

ERWN

and

ENABLE

for one ECKO

cycle.

2. On the rising edge of the second ECKO cycle, the

SEMI deasserts

ENABLE

and

ERWN

3. On the rising edge of the third ECKO cycle, a new

access can begin because synchronous accesses

are pipeline d. O n this edge, the SEMI drives

with the write data for one EC KO cycle.

4. On the rising edge of the fourth cycle, the external

memory latches the data from

1. The EA0 pin is a strobe only if the bus is configured for 32 bits and the memor y is configured a s synchronous.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.6 Synchronous Memory (continued)

4.1 4.6 .1 Fu nct i on a l Timing (continued)

Figure 34 illustrates an example of synchronous memory accesses. This example assumes that the DMAU is per-

forming the external memory accesses. The access rate shown is not achievable if the accesses are performed by

one or both cores. For details on SEMI performance for a synchronous interface, see Section 4.14.7.3 on

page 131. For a summary of SEMI performance, see Sec tion 4.14.7.4 on page 133.

Synchronous Timing

Figure 34. Synchronous Memory Cycles

CLK

EION

ERWN

ERAMN

HIGH-IMPEDANCE OUTPUT

ECKO

ERAM READ

ERAM

WRITE

ERAM READ

EIO READ

A0 A1 A2 A6A3 A4 A5

Q0 D2 Q3 Q4 Q5 D6

ERAM

WRITE

EIO

WRITE

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.6 Synchronous Memory (continued)

4.14.6.2 Interfacing Examples

If any of the external memory component s (EROM,

ERAM, or EIO) are configured as synchronous, the

SEMI external output clock (ECKO) must be pro-

grammed as CLK/2, CLK/3, or CLK/4 (see t he

ECKOB[1:0] and ECKOA[1:0] fields of

ECON1—Table 61 on page 112 ). After reset, the

default state of ECKO is CLK/2.

Fig u r e s 35 and 36 illustrate examp les of interfacing

16-bit and 32-bit pipelined synchronous

ZBT

SRAMs t o

the SEMI. The program m er can individually configure

EROMN, ERAMN, and EION enables to support this

type of synchronous device. The ERTYPE pin must be

at logic high for the EROM component to be configured

for synchronous accesses. Setting the YTYPE field

(ECON1[9]) and ITYPE field (ECON1[10]) configures

the ER AM and EIO com ponent s for synchron ous

accesses.

Figure 35 illustrates interfacing the SEMI to a 16-bit

synchronous, pipelined

ZBT

SRA M. In this exampl e:

1. The SEM I address bus (EA[1 7:0]) is connected to

the SRAM’s address bus (A[17:0]). One of the SEMI

ESEG[3:0] pins ca n be option ally connected to the

SRAM ’s active-high chip s el ect input (CE2).

2. T he upper 16 bit s of the SEMI data bus (E D[ 31:16] )

are connected to the SRAM’s bidirectional data bus

(DQ[15:0]).

3. The SEMI external clock (ECKO) is programmed for

operation at CLK/2, CLK/3, or CLK/4, and is con-

nected to the SRAM’s CLK input.

4. T he SEM I external dat a compone nt enab le

(ERAMN ) and external read/write stro be (ERWN0)

are connected to the SRAM’s active-low chip enable

and write enable inputs, respectively.

5. T he SRA M ’s active-low ADV/LD must be tied low.

6. The SEMI’s ESIZE pin is tied low to configure the

data bus for 16-bit accesses.

16-Bit External I nterface with 16-Bit

ZBT

Pipelined Synchronous SRAMs

Figure 35. 16-Bit External Interface with 16-Bit Pipelined, Synchrono us

ZBT

SRAMs

A[17:0]

CLK

CE1

DQ[15:0]

VSS

EA[17:0]

ECKO

ERAMN

ED[31:16]

DSP16411 16-bit SYNCHRONOUS

ERWN0 WE

ADV/LD

ESIZE

VSS

SRAM

BWa

BWb

VSS OE

CE2

ESEG[3:0]

VDDERTYPE

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.6 Synchronous Memory (continued)

4.14.6.2 Interfacing Examples (continued)

32-Bit External I nterface with 32-Bit

ZBT

Pipelined Synchronous SRAMs

† SEMI is configured for a 32-bit data bus. In this configuration, EA0 is RWN for 32-bit acces s es (logical AND of ERW N0 and ERWN1).

Figure 36. 32-Bit External Interface with 32-Bit Pipelined, Synchrono us

ZBT

SRAMs

A[16:0]

CLK

DQa[7:0]

VDD

EA[17:1]

ECKO

ERAMN

ED[31:24]

32-bit SYNCHRONOUS

ERWN1

ESIZE

SRAM

BWa

BWb

VSS OE

ERWN0 BWc

BWd

ED[23:16]

ED[15:8]

ED[7:0]

EA0†

DQb[7:0]

DQc[7:0]

DQd[7:0]

DSP16411

VDDERTYPE

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.7 Performance

The following terms are used in this section:



A requester, a core or the DMAU, requests the SEMI

to access external memory or the system bus.



Conten tion refers to mul tiple requests for the same

resource at the same time.



The designat ion

ATIME

refers to IATIME

(ECON0[11:8]—see Table 60 on page 111) for

accesses to the EIO space, YAT IME (ECON0[7:4])

for accesses to the ERAM space, or XATIME

(ECON0[3:0]) for accesses to the EROM space.



RSETUP refers to the RSE T UP field (ECON0[12]).



RHOLD refers to the RHOLD field (ECON0[14]).



WSETUP refers to the WSETUP fie ld ( ECON0[13]).



WHOLD refers to the WHOLD field (ECON0[15]).



Misali gned refers to 32-bit accesses to odd

addresses.



SLKA

refe rs to th e SLKA〈5—4〉 fields

(DMCON0[9:8]—see Table 31 on page 71).



TCLK refers to one period of th e internal clock CLK.

The SEMI controls and arbitrates two types of memory

accesses. The first is to external memory. The second

is to th e int ern a l I/ O segme nt accessed via the system

bus. Section 4.14.7.1 descr ibes the SEMI perfor-

mance fo r system bus acces se s. Section 4.14.7.2 on

page 129 des cribes th e SEMI performance for asyn-

chronous external memory accesses and

Section 4.14.7.3 on page 131 describes the SEMI per-

formance for synchronous external memory accesses.

The performance for all of these types of accesses are

summarized in Section 4.14.7.4 on page 133.

For the remainder of this section, unless otherwise oth-

erwise stated, the fol lowin g assumptions apply:



There is only a single requester, i.e., no contention.



SEM I requests by the DMAU are from a memory-to-

memory (MMT) channel and the user program has

enabled the source look-ahead feature by setting the

appropriate

SLKA

field (Section 4.13.6, beginning on

page 90).

The source of the request (core vs. DMAU), the config-

uration of the S E M I data bus size (16-bit v s. 32-bit),

and the type of access (read vs. write) determine the

throughput of any external memory access.

Section 4.14.7.2, beginning on page 129, and

Section 4.14.7.3, beginning on page 131, describe the

performanc e for all combinations.

The DMAU source look-ahead feature takes advantage

of the DMAU pipeline and allows the DMAU to read

source data before completing the previous write to the

destination. Section 4.14.7.4 on page 133 shows per-

formanc e figures with this feature both enabled and

disabled.

For an MMT channel, each DMAU access consists of a

read of the source location and write to t he dest ination

location. Therefore, the DMAU performance values

state d in this section assume two operation s per trans-

fer.

4.14.7.1 System Bus

The SEM I controls and arbitrates acce sses to internal

I/O segmen t a cce ssed via the system bus. Only 16-bi t

and aligned 32-bit transfers are permitted via the sys-

tem bus. Th e syste m bus is used to access a ll th e

mem ory-mapped registers in the DMAU, SIU0, SIU1,

PIU, and SEMI. S ee Section 6.2.2 on page 231 for

details on the memory-mapped registers. Misaligned

32-bit accesses to internal I/O space cause undefined

results.

Table 67 specifies the minim um system bus access

time for either a single-word (16-bit) or double-word

(32-bit) acces s by a single requeste r. The SEMI pro-

cesses syste m bus accesses by multi ple requesters at

a maximum rate of one access per CLK cycle.

For example, if a program executing in CORE0 per-

forms a read of the 16-bit DMCON0 register , the read

requires a minimum of five CLK cycles. The access

could take longer if the SEMI is busy processing a prior

reques t, i.e., if there is co ntention. A s a second exam -

ple of an S-bus transfer, assume the DMAU is moving

data between TPRAM0 and the SLM. The SLM is a

memory block accessed via the S-bus. Assuming no

contention, the DMA U can read a word from TPRAM0

and write a word t o the SLM at an effect ive rate of two

16-bit words per two CLK cycles.

Table 67. System Bus Minimum Access Times

Access Minimum Acces s Time

Read 5×TCLK

Write 2×TCLK

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.7 Performance (continued)

4.14.7.2 External Memory, Asynchronous Interface

External Accesses by Either Core, 32-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by either core to asynchronous

memory with the external data bus configured as 32-bit

(the ESIZE pin is logic high):

READS—For the cores, 16-bit and 32-bit aligned

external asynchronous memory reads occur with a

minimum period of the enable assertion time (as pro-

grammed in

ATIME

), plus a one CLK cy cle enforc ed

hold time, plus three CLK cycles for the SEMI pipeline

to complete the core access. This assumes that

RSETUP and RHOLD are cleared. The core treats

misaligned 32-bit reads as two separate 16-bit reads

requiring two complete SEMI accesses.

The core read access time for a 32-bit dat a bus is the

following:

[

ATIME

+ 4 + RSETUP + RHOLD] ×

misaligned

× TCLK

where:



misaligned

= 1 for 16-bit a nd aligne d 32-bit

accesses.



misaligned

= 2 for misaligned 32-bit accesses.

WRITES—F or the cores, 16-bit and 32-bit aligned

asynchronous mem ory writes can occur with a m ini -

mum period of the enable assertion time (as pro-

grammed in

ATIME

), plus a one CLK cy cle enforc ed

setup time, plu s a one CLK cycle enforced h old time.

This assumes that WSETUP and WHOLD are cleared.

Unlike read cycles, t he core does not wait for the SEMI

pipeline to complete the access, so t he three CLK

cycle pipeline delay is not incurred on core writes. The

core treats misaligned 32-bit writes as tw o separat e

16-bit writes requiring two complete SEMI accesses.

The core write access time for a 3 2-bit data bus is the

following:

[

ATIME

+ 2 + WSETUP + WHOLD] ×

misaligned

× TCLK

where

misaligned

has the sam e def inition as for reads.

External Accesses by the DMAU, 32-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by a DMAU MMT channel to

asynchrono us memory with the external data bus con-

figured as 32-bit (the ESIZE pin is logic high):

READS—For the DM A U MMT channel s with

SLKA

= 1, 16-bit and 32-bit aligned external asynchro-

nous memory reads (with corresponding writes to inter-

nal TPRAM) occur wi th a minimum period of t he enable

assertion time (as programmed in

ATIME

), plus a one

CLK cycle enforced hold time. This assumes that

RSETUP and RHOLD are cleared. Misaligned 32-bit

reads are not permitted.

The DMAU read ac cess time for a 32-bit data b us with

SLKA

= 1 is the following:

[

ATIME

+ 1 + RSETUP + RHOLD] × TCLK

WRITES—For the DM A U MMT channe ls with

SLKA

= 1, 16-bit and 32-bit aligned asynchronous

memory writes (with corresponding reads from internal

TPRAM) can occur with a m inimum period of the

enable assertion time (as programmed in

ATIME

), plus

a one CLK cycle enforced setup time, plus a one CLK

cycle enf orce d hold time. This a ssumes that WSETUP

and WH OLD are cleared. Misaligned 32-bit writes are

not perm itted.

The DMAU write access time for a 32-bit data bus with

SLKA

= 1 is the following:

[

ATIME

+ 2 + WSETUP + WHOLD] × TCLK

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.7 Performance (continued)

4.14.7.2 External Memory, Asynchronous

Interface (continued)

External Accesses by Either Core, 16-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by either core to asynchronous

memory with the external data bus configured as 16-bit

(the ESIZE pin is logic low):

READS—For the cores, 16-bit external asynchronous

memory reads occur with a minimum period of the

enable assertion time (as programmed in

ATIME

), plus

a one CLK cycle enf or ce d hold ti me, p lus th re e CLK

cycles for the SEMI pipeline to complete the core

access. Thi s assumes that RSETUP and RHOLD are

cleared. The SEMI coordinates two separate accesses

for ali gned 32-bit reads, adding two CLK cycles to the

above descript ion. The core treats misaligned 32-bit

reads as two s ep arate 16-bit reads requiring two com-

plete SEMI accesses.

The core read access time for a 16-bit dat a bus is the

following:

[

ATIME

aligned

+ RSETUP + RHOLD] ×

misaligned

× TCLK

where:



aligned

= 4 and

misaligned

= 1 for 16-bit accesses.



aligned

= 6 and

misaligned

= 1 for 32-bit aligned

accesses.



aligned

= 4 and

misaligned

= 2 for 32-bit misaligned

accesses.

WRITES—For the cores, 16-bit asynchronous memory

writes can occur wit h a minimum perio d of the enable

assertion time (as programmed in

ATIME

), plus a o ne

CLK cycle enforced setup time, plus a o ne CLK cycle

enforced hold time. This assumes that WSETUP and

WHOLD are cleared. Unlike re ad cycles, the core

does not wait for th e SEMI pipeline to complete the

access, so the three CLK cycle pipeline delay is not

incurred on core writ es. T he SEM I coordinates and

treats aligned 32-bit writes as two separate

accesses. The core treats misal igned 32-bit writes as

two separate 16-bit writes requiring two complete SEMI

accesses.

The core write access time for a 16-bit data bus is the

following:

[

ATIME

+ 2 + WSETUP + WHOLD] ×

longword

× TCLK

where:



longword

= 1 for 16-bit accesses.



longword

= 2 f or 32-bit accesses.

External Accesses by the DMAU, 16-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by a DMAU MMT channel to

asynchronous memory with the external data bus con-

figured as 16-bit (the ESIZE pin is logic low):

READS— For the DMAU MMT channels with

SLKA

= 1, 16-bit external asynchronous memory reads

(with corresponding writes to internal TPRAM ) occur

with a minimum period of the enable assertion time (as

programm ed into

ATIME

) plus a one CLK cycle

enforced hold time. This assumes that RSETUP and

RHOLD are cleared. The SEMI coordinates and treats

aligned 32-bit reads as two separate accesses. M is-

aligned 32-bit reads are not perm itted.

The DMAU read ac cess time for a 16-bit data b us with

SLKA

= 1 is the following:

[

ATIME

+ 1 + RSETUP + RHOLD] ×

longword

× TCLK

where:



longword

= 1 for 16-bit accesses.



longword

= 2 f or 32-bit aligned accesses.

WRITES—Fo r the DMAU MMT channe ls with

SLKA

= 1, 16-bit asynchronous memory writes (with

corresponding reads from internal TPRAM) can occur

with a minimum period of the enable assertion time (as

programmed in

ATIME

), plus a one CLK cycle enforced

setup time, plus a one CLK cycle enforced hold

time. This as sumes that WSETUP and WHOL D are

cleared. T he SEM I coordin ates and treats aligned

32-bit writes as two separate accesses. Misaligned

32 -b it w rites are not permitted.

The DMAU write access time for a 16-bit data bus with

SLKA

= 1 is the following:

[

ATIME

+ 2 + WSETUP + WHOLD] ×

longword

× TCLK

where

longword

has the same meaning as for DMAU

reads.

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.7 Performance (continued)

4.1 4.7 .3 E x te rnal Me m ory, Synchronous Interf ace

The primary advantage of synchronous memory is

bandwidth, not latency. The cores’ unpipelined inter-

face to the SEMI cannot take advantage of this band-

width. However, the DMAU has a pipelined interface to

the SEMI and takes advantage of the synchronous

bandwidth . The following sections specify the SEMI

performance for accesses by a core or by the DMAU to

external synchronous memory.

For synchronous operation, the SEMI external output

clock (ECKO) must be programmed as CLK/2, CLK/3,

or CLK/4 (see the ECKOB[1:0] and ECKOA[1:0] fi elds

of ECON1—Table 61 on page 112).

External Accesses by Either Core, 32-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by either core to synchronous

memory with the external data bus configured as 32-bit

(the ESIZE pin is logic high):

READS—For the cores, 16-bit and 32-bit aligned

external synchronous memory reads occur with a mini-

mum period of eight CLK cycles (four ECKO cycles if

ECKO = CLK/2), plus three CLK cycles for SEMI to

arbitrate the co re access, plus one CLK cycle to syn-

chronize ECKO with a rising edge of CLK . The core

treats misaligned 32-bit reads as two separate 16-bit

reads requiring two complete SEMI accesses.

The core read access time for a 32-bit dat a bus is the

following:

12 ×

misaligned

× TCLK if ECKO = CLK/2

16 ×

misaligned

× TCLK if ECKO = CLK/3

20 ×

misaligned

× TCLK if ECKO = CLK/4

where:



misaligned

= 1 for 16-bit a nd aligne d 32-bit

accesses.



misali gned = 2 for misaligned 32-bit access es.

WRITES—For the cores, 16-bit and 32-bit aligned syn-

chronous memory writes can occur with a minimum

period of four CLK cycles (two E CK O cycles if

ECKO = CLK/2) per transfer. The core treats mis-

aligned 32-bit writes as two separate 16-bit writes

requiring two complete SEMI accesses.

The core write access time for a 32-bit data bus is the

following:

4 ×

misaligned

× TCLK if ECKO = CLK/2

6 ×

misaligned

× TCLK if ECKO = CLK/3

8 ×

misaligned

× TCLK if ECKO = CLK/4

where

misaligned

has the same definition as for rea ds .

External Accesses by the DMAU, 32-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by a DMAU MMT channel to syn-

chrono us memory with the external data bus config-

ured as 32-bit (the ESIZE pin is logic high):

READS—For the DM A U MMT channel s with

SLKA

= 1, 16-bit and 32-bit aligned external synchro-

nous memory reads (with corresponding writes to inter-

nal TPRA M) occur with a m ini mu m period of four CLK

cycles (two ECKO cycles if ECKO = CLK/2). Mis-

aligned 32-bit reads are not permitted.

The DMAU read ac cess time for a 32-bit data b us with

SLKA

= 1 is four CLK cycles.

4 × TCLK if ECKO = CLK/2

6 × TCLK if ECKO = CLK/3

8 × TCLK if ECKO = CLK/4

WRITES—For the DM A U MMT channe ls with

SLKA

= 1, 16-bit and 32-bit aligned synch ronous mem -

ory writes (with corresponding reads from internal

TPRAM) can occur with a minimum period of four CLK

cycles (two ECKO cycles if ECKO = CLK/2). Mis-

aligned 32-bit writes are not permitted.

The DMAU write access time for a 32-bit data bus and

SLKA

= 1 is four CLK cycles.

4 × TCLK if ECKO = CLK/2

6 × TCLK if ECKO = CLK/3

8 × TCLK if ECKO = CLK/4

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface

(SEMI) (continued)

4.14.7 Performance (continued)

4.14.7.3 External Memory, Synchronous

Interface (continued)

External Accesses by Either Core, 16-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by either core to synchronous

memory with the external data bus configured as 16-bit

(the ESIZE pin is logic low):

READS—For the cores, 16-bit external synchronous

memory reads occur with a minimum period of eight

CLK cycles (four ECKO cycles if ECKO = CLK/2), plus

th ree CLK cycles fo r SEMI to a rbitr ate the cor e access ,

plus one CLK cycle to synchronize ECKO with a rising

edge of CLK. The SEMI coordinates and treats aligned

32-bit reads as two separate accesses. The core

treats misaligned 32-bit reads as two separate 16-bit

reads requiring two complete SEMI accesses.

The core read access time for a 16-bit dat a bus is the

following:

(12 +

aligned

) ×

misaligned

× TCLK if ECKO = CLK/2

(16 +

aligned

) ×

misaligned

× TCLK if ECKO = CLK/3

(20 +

aligned

) ×

misaligned

× TCLK if ECKO = CLK/4

where:



aligned

= 0 and

misaligned

= 1 for 16-bit accesses.



aligned

= 4 and

misaligned

= 1 for 32-bit aligned

accesses.



aligned

= 0 and

misaligned

= 2 for 32-bit misaligned

accesses.

WRITES—F or the cores, 16-bit synchronous memory

writes can occur wit h a minimum perio d of four CLK

cycle s (tw o ECKO cycles if ECKO = CLK/2) pe r trans-

fer. The SEM I coordinates and treats align ed 32-bit

writes as tw o separat e accesses. The core treats mis-

aligned 32-bit writes as t wo separate 16-bit writes

requiring two complete SEMI accesses.

The core write access time for a 1 6-bit data bus is the

following:

4 ×

longword

× TCLK if ECKO = CLK/2

6 ×

longword

× TCLK if ECKO = CLK/3

8 ×

longword

× TCLK if ECKO = CLK/4

where:



longword

= 1 for 16-bit accesses.



longword

= 2 f or any 32-bit accesses.

External Accesses by the DMAU, 16-Bit SEMI Data

Bus

The following describes the SEMI performance for read

and write operations by a DMAU MMT channel to syn-

chrono us memory with the external data bus config-

ured as 16-bit (the ESIZE pin is logic low):

READS— For the DMAU MMT channels with

SLKA

= 1, 16-bit external synchronous me mory reads

(with corresponding writes to internal TPRAM ) occur

with a minimum period of fou r CLK cycles (two ECKO

cycles if ECK O = CLK/2). The SEMI coordinates and

treats aligned 32-bit reads as two separate accesse s.

Misali gned 32-bit reads are not permitted.

The DMAU read ac cess time for a 16-bit data b us with

SLKA

= 1 is the following:

4 ×

longword

× TCLK if ECKO = CLK/ 2

6 ×

longword

× TCLK if ECKO = CLK/ 3

8 ×

longword

× TCLK if ECKO = CLK/ 4

where:



longword

= 1 for 16-bit accesses.



longword

= 2 f or any 32-bit aligned accesses.

WRITES—Fo r the DMAU MMT channe ls with

SLKA

= 1, 16-bit synchronous memory writes (with cor-

responding reads from internal TPRAM) can occur with

a minimum period of four CLK cycles (two ECKO

cycles if ECK O = CLK/2). The SEMI coordinates and

treats aligned 32-bit writes as two separate

accesses . Misali gned 32-bit writes are not perm it ted.

The DMAU write access time for a 16-bit data bus with

SLKA

= 1 is the following:

4 ×

longword

× TCLK if ECKO = CLK/ 2

6 ×

longword

× TCLK if ECKO = CLK/ 3

8 ×

longword

× TCLK if ECKO = CLK/ 4

where

longword

has the same meaning as for DMAU

reads.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.7 Performance (continued)

4.14.7.4 Summary of Access T imes

Tables 68 through 71 summarize the information in Section 4.14.7.2, beginning on page 129, and Section 4.14.7.3,

beginning on page 131.

Table 68. Access Time Per SEMI Transaction, Asyn chrono us Interface, 32-Bit Data Bus

Table 69. Access Time Per SEMI Transaction, Asyn chrono us Interface, 16-Bit Data Bus

Table 70. Access Time Per SEMI Transaction, Sync hronou s Interface, 32-Bit Data Bus

Table 71. Access Time Per SEMI Transaction, Sync hronou s Interface, 16-Bit Data Bus

Requester Access Type Reads Writes

Core 16-bit [

ATIME

+ 4 + RSETUP + RHOLD] × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × TCLK

32-bit ali gned

32-bit misaligne d [

ATIME

+ 4 + RSETUP + RHOLD] × 2 × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × 2 × TCLK

DMAU,

SLKA

= 1 16-bit [

ATIME

+ 1 + RSETUP + RHOLD] × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × TCLK

32-bit ali gned

Requester Access Type Reads Writes

Core 16-bit [

ATIME

+ 4 + RSETUP + RHOLD] × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × TCLK

32-bit ali gned [

ATIME

+ 6 + RSETUP + RHOLD] × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × 2 × TCLK

32-bit misaligne d [

ATIME

+ 4 + RSETUP + RHOLD] × 2 × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × 2 × TCLK

DMAU,

SLKA

= 1 16-bit [

ATIME

+ 1 + RSETUP + RHOLD] × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × TCLK

32-bit ali gned [

ATIME

+ 1 + RSETUP + RHOLD] × 2 × TCLK [

ATIME

+ 2 + WSETUP + WHOLD] × 2 × TCLK

Requester Access Type Reads W rites

CLK/2†

† Val ue of ECKO , dependi ng on t he program m i ng of the ECKOB[1: 0] and ECKOA[ 1: 0] fields of ECON1—Tabl e 61 on page 112 .

CLK/3†CLK/4†CLK/2†CLK/3†CLK/4†

Core 16-bit 12 × TCLK 16 × TCLK 20 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK

32-bit ali gned

32-bit misaligne d 24 × TCLK 32 × TCLK 40 × TCLK 8 × TCLK 16 × TCLK 32 × TCLK

DMAU,

SLKA

= 1 16-bit 4 × TCLK 6 × TCLK 8 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK

32-bit ali gned

Requester Access Type Reads W rites

CLK/2†

† Val ue of ECKO , dependi ng on t he program m i ng of the ECKOB[1: 0] and ECKOA[ 1: 0] fields of ECON1—Tabl e 61 on page 112 .

CLK/3†CLK/4†CLK/2†CLK/3†CLK/4†

Core 16-bit 12 × TCLK 16 × TCLK 20 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK

32-bit ali gned 16 × TCLK 20 × TCLK 24 × TCLK 8 × TCLK 12 × TCLK 16 × TCLK

32-bit misaligne d 24 × TCLK 32 × TCLK 40 × TCLK 8 × TCLK 12 × TCLK 16 × TCLK

DMAU,

SLKA

= 1 16-bit 4 × TCLK 6 × TCLK 8 × TCLK 4 × TCLK 6 × TCLK 8 × TCLK

32-bit ali gned 8 × TCLK 12 × TCLK 16 × TCLK 8 × TCLK 12 × TCLK 16 × TCLK

Advance Data Sheet

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4 Hardware Architecture (continued)

4.14 System and External Memory Interface (SEMI) (continued)

4.14.7 Performance (continued)

4.14.7.4 Summary of Access Times (continued)

Tables 72 and 73 show example access times under various conditions, including DMAU accesses with SLKA = 0.

These access times are derived from actual measureme nts. For the asynchronous acc ess times , it is assume d

that the programmed enab le assertion time is one (

ATIME

= 1) and t hat RSETUP = RHOLD = WSE TUP =

WHOLD = 0. The actual value of these fields is appl ication-depen dent . For the s ynchronous access times, it is

assumed that ECKO is programmed as CLK/2.

Table 72. Example Average Access Time Per SEMI Transaction, 32-Bit Data Bus

Table 73. Example Average Access Time Per SEMI Transaction, 16-Bit Data Bus

4.14.8 Priority

SEMI prioritizes the requests from both cores and the DMAU in the following order:

1. CORE0 program (X) and data (Y) requests have the highest priority. If CORE0 requires a simultaneous X and Y

access, X is performed fi rst, then Y.

2. CORE1 program (X) and data (Y) r equests have the second-highest priority. If CORE1 requires a simultaneous

X and Y access, X is performed first, then Y.

3. DM AU data reques ts have the lowest priority.

Requester Access Type Asynchronous Synchronous (ECKO = CLK/2)

Reads Writes Reads Writes

Core 16-bit 5 × TCLK 3 × TCLK 12 × TCLK 4 × TCLK

32-bi t ali g ned

32-bit misaligned 10 × TCLK 6 × TCLK 24 × TCLK 8 × TCLK

DMAU,

SLKA

= 1 16-bit 2 × TCLK 3 × TCLK 4 × TCLK 4 × TCLK

32-bi t ali g ned

DMAU,

SLKA

= 0 16-bit 9 × TCLK 5 × TCLK 14 × TCLK 5 × TCLK

32-bi t ali g ned

Requester Access Type Asynchronous Synchronous (ECKO = CLK/2)

Reads Writes Reads Writes

Core 16-bit 5 × TCLK 3 × TCLK 12 × TCLK 4 × TCLK

32-bi t ali g ned 7 × TCLK 6 × TCLK 16 × TCLK 8 × TCLK

32-bit misaligned 10 × TCLK 6 × TCLK 24 × TCLK 8 × TCLK

DMAU,

SLKA

= 1 16-bit 2 × TCLK 3 × TCLK 4 × TCLK 4 × TCLK

32-bi t ali g ned 4 × TCLK 6 × TCLK 8 × TCLK 8 × TCLK

DMAU,

SLKA

= 0 16-bit 9 × TCLK 5 × TCLK 14 × TCLK 5 × TCLK

32-bit al igned 11 × TCLK 6 × TCLK 18 × TCLK 8 × TCLK

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU)

The parallel interface unit (PIU) is t he DSP1 6411 inter-

face to a host microprocessor or microcontroller. This

interface is a 1 6-bit parallel port that i s passive only,

i.e., t he DS P16411 is t he slave to the hos t for all t rans-

actions. The PIU is both

Intel

and

Motorola

® memo ry

bus compatible and provides select logic for a shared-

bus interface. As an additiona l feature, the host can

access the entire DSP16411 m em ory (internal and

external) through the PIU.

The PIU control and data registers are memory-

mapped into the DSP16411 shared internal I/O mem -

ory component (Section 4.5.7 on page 43). The host

can access all of the PIU data and control registers via

external pins. Both cores and the DMAU can access

these registers directly via the system bus. The DMAU

can directly access the PIU data registers PDI and

PDO.

The DMAU supports the PIU via a dedicated bypass

channel. Unli ke the DMAU SWT and M MT channels,

the PIU bypass channel must be configured by the host

via commands over the PIU address pins, PADD[3:0] .

The PIU provides three interrupt signals to the cores.

These interrupts indicate a host-generat ed request or

the completion of an input or output transaction.

The PIU provides the following features:



A high-speed, 16-bit parallel host interface



Compatibility with industry-standard microproce ssor

buses



Chip select logic for sh ar ed bus system archite ctu res



Interrupt output pin for DSP16411-to-host interrupt

generation



Dedicated host and core scratch registers for conve-

nient messaging



Supported by DMAU to access all memory

4.15.1 Registers

As su mma r ized in Table 74, t he P IU contains seven

mem ory-map ped registers that are accessible by the

host and the cores. The host accesses these registers

by issuing commands through the PIU. Please refer to

Section 4.15.5 on page 147. A ll PIU registers are

accessed by the host as 16-bit quantities. The cores

access the PIU registers as 32-bit m em ory -ma pped

locations residing in the shared int ernal I/O mem ory

component (Section 4.5.7 on page 43). The PIU regis-

ters are aligned to even addresses and occ upy

addresses 0x41000 to 0x4100A, as noted in Table 74.

Sect ion 6.2.2 on page 231 provides an overview of

mem ory-map ped registers.

Table 74. PIU Registers

Name Address Size

(Host) Size

(Cores) R/W

(Host) R/W

(Cores) Type†Description

PCON 0x41000 16 32 R/W‡R/W‡c & s PIU contro l and status . The appl icati on must choose

one of the cor es to write PCON.

PDI§0x41008 16 32 W R data PIU data in from host.

PDO 0x4100A 16 32 R R/W dat a PIU data out to host . For a typical applica tion, the

DMAU writes PDO, but either core can also write

PDO. The appl icati on must choo se one of these enti -

ties to write PDO.

PAH 0x41004

(PA)16 32 R/W R/W data PIU address for host acc ess to DSP16411 memory.

The appli cati on must choose ei ther t he h ost or on e of

th e c or e s to write th is re g is te r.

PAL 16 R/W

DSCRATCH 0x41002 16 32 R R/W data DSP scratch. The applicat ion must choose one of

t h e cores to wri t e DSCRATCH.

HSCRATCH 0x41006 16 32 W R data Host scratch.

† c & s means co ntrol and status.

‡ All bits of PCON are readable by both the host and the cores. Not all bits are writable—see Tab le 75 on pa ge 136 for details.

§PDI is double-buffered (unlike the DSP16XX PHIF PDX register). Therefore, a host write to PDI can be issued (but not comp leted) before a

previous h ost wr ite to PDI is completed.

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.1 Re g ister s (continued)

The PCON register is the PIU status and control register . This register reflects the state of the PIU flags (PIBF and

POBE) and provides a mechanism for the host and a core to interrupt each other or reset the PIU. The bit fields of

PCON are detailed in Table 75. For each bit field, the table defines what actions can be performed by the host or a

core: read, write, clear to zero, or set to one. All the bit fields of PCON can be read by the host and by the cores. If

the PCON register is read, only the lower 7 bits contain valid information. The upper bits are undefined. If the host

or a core writes PCON, it must write the upper 25 bits with ze ro.

Table 75. PC O N (P I U Control) Register

The memory address for this register is 0x41000. The application must ensure that both cores do not write PCON

at the same time.

31—7 6 5 4 3 2 1 0

Reserved DRESET HRESET HINT§PINT§PREADY PIBF POBE

Bit Field Name Value Description R/W

(Cores) R/W

(Host) Reset

Value†

† Dev ic e res et or PIU res et .

31—7 Reserved — — Reserved—write with zero; undefined on read. — — —

6 DRESET DSP

Reset 0 Always read as zero. Write wi th zero—no effect. Set/

Read —0

1 The program runni ng in a core resets‡ the PIU by writing a 1

to thi s field. The PIU reset cl ears thi s fi eld automatically.

‡ The purpose of the PIU reset is to reinitialize all PIU sequencers and flags to their reset state.

5 HRESET Host

Reset 0Always read as zero. Write wi th zero—no effect. — Set/

1 The ho st re sets‡ the PIU by writing a one to this fiel d. The

PIU reset clears thi s fi eld automatically.

4HINT

§ If the host an d a core attempt to set/clear this bit simulta neously, the PIU c lears the bit.

Interrupt

from Host 0Read as zero— no outstanding interrupt from host.

Write wit h zero—no effect. Clear/

Read Set/

1 If this field is initially cleared and the host sets it, the PIU

asserts the PHINT interrupt. The interrupted core’s servi ce

rout ine m ust cl ear th is fi eld af ter s ervic ing the PHINT r equest

to allow the host to request a subsequent interrupt. The ser-

vice rout ine cle ars the field by writing one to it.

3PINT

§PIU

Interrupt

to Host

0Read as zero—no outstanding interrupt to host.

Write wit h zero—no effect. Set/

Read Clear/

1 If this field is initially cleared and a program runni ng in either

core sets i t, the PIU asserts the PINT pin to interrupt the

host. The host mus t cl ear thi s fi eld aft er servicing the PINT

request to allow a core to request a subseque nt i nterrupt. It

clears the fiel d by wri ting 1 to it.

2PREADY PIU

Ready — Th is bit is th e logi cal OR of the PIBF and POBE flags. (It is

not the same as the PRDY pin.) If set, the PIU is not r eady. Read Read 1

1 PIB F P IU In p ut

Buffer

Full

0PDI contains data that has already been re ad by one of t he

cores. The host may write PDI with new dat a. Read Read 0

1PDI contains data fro m a pr ior host write request. To avoid

loss of dat a, the host must not wri te PDI.

0 POBE PIU Output

Buffer

Empty

0PDO contains new data. To avoid loss of data, the cores

mus t not write PDO.Read Read 1

1PDO contains data that has already been read by the host.

The co res m ay w rite PDO with new data.

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.1 Re g ister s (continued)

The PDI and PDO registers (Table 76 and Table 77) are the 16-bit PIU input and output data registers. PDI con-

tains data written by the host at the conclusion of a valid host write cycle. PDO contains data written by a core or

the DMAU that is driven ont o the PIU data bus during a valid host read c ycle.

Table 76. PDI (PIU Data I n) Register

Table 77. PDO (PIU Data Out) Reg is ter

The DSCRATCH and HSCRATCH registers (Table 79 and Table 78) are the DSP and host scratch registers t hat

can be used to pass messaging data between a core and the host. After a core writes 16-bit data to DSCRATCH,

the host can read this data by issuing a read_dscratch com man d. Conversel y, the host can write 16-bit data to

HSCRATCH by issuing a write_hscratch c om man d. See S ection 4.15.5 on page 147 for details on host com -

mands.

Table 78. HSCRATCH (Host Scratch) Register

Table 79. DSCRAT CH (DSP Scratch) Register

The memory address for this register is 0x41008.

31—16 15—0

Reserved PIU Input Data

Bit Field Descri ption R/W (Cores) R/W (Host) Reset Value

31—16 Reserved Reserved—read as zero. R W 0

15—0 PIU Input Dat a PIU data in from host. R W 0

The memory address for this register is 0x4100A . F or a typical application, the DMAU writes PDO, but the cores

can also write PDO. The application must ensure that these entities do not write PDO at the same time.

31—16 15—0

Reserved PIU Output Data

Bit Field Descri ption R/W (Cores) R/W (Host) Reset Value

31—16 Reserved Reserved—wr ite with zero. R/W R 0

15—0 PIU Output Data PIU data out to host. R/W R 0

The memory address for this register is 0x41006.

31—16 15—0

Reserved Host Scr atch

Bit Field Descri ption R/W (Cores) R/W (Host) Reset Value

31—16 Reserved Reserved—read as zero. R W 0

15—0 Host Scrat ch Host scratch data to DSP16411. R W 0

The memory address for this register is 0x41002. The applicat ion must choose one of the cores to write

DSCRATCH.31—16 15—0

Reserved DSP Scrat ch

Bit Field Descri ption R/W (Cores) R/W (Host) Reset Value

31—16 Reserved Reserved—wr ite with zero. R/W R 0

15—0 DSP Scr atch DSP scratch data to host. R/W R 0

Advance Data Sheet

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.1 Re g ister s (continued)

The PA register (Table 80) provides the DSP16411 memory address for any host accesses to DSP16411 memory.

The host m ust access this register as two 16-bit quantities: the high half (PAH) and t he low half (PAL). A core

accesses PA as a double-word (32-bit) loc ation at address 0x41004 . S ee Figure 37 for details. As shown in

Table 80, the ADD[19:0] field (PA[19:0]) contains the memory address to be accessed within the selected memory

component determined by the CMP[2:0] field (PA[22:2 0]) . The ESEG[ 3:0 ] fi eld ( PA[26:23]) determines the external

segment extension for external memory accesses through the SEMI. The SEMI drives the value in the ESEG[3:0]

field onto the ESEG[3:0] pins at t he sam e time that it asserts the appropriate enable pin (ERAMN, EION, or

EROM N) and drives the external mem ory address onto EA[18:0].

Table 80. PA (Paral lel Address) Register

32-Bit PA Re gister Host and DSP Ac cess

Figure 37. 32-Bit PA Register Host and Core Access

The memory address for this register is 0x41004. The application must choose either the host or one of the cores

to write this register .

31—27 26—23 22—20 19—0

Reserved ESEG[3:0] CMP[2:0] ADD[19:0]

Bit DSP

Access Host

Access Field Value Definition R/W Reset

Value

31—27 PA†PAH[15:0]‡Reserved 0 Reserved—write with zero. R/W 0

26—23 ESEG[3:0] 0x0

0xF

External memory addr ess extension . The val ue

of this field is placed directly on the ESEG[3:0]

pins for PIU accesses to external memor y§.

R/W 0x0

22—20 CMP[2: 0] 000 The selected memory component is TPRAM0. R/W 000

001 The selec ted mem ory component is TPRAM1.

01X Reserved.

100 The selected mem ory component is ERAM††,

EIO, or inter nal I/O.

101 Reserved.

11X Reserved.

19—16 ADD[19:0] 0x00000

0xFFFFF

The address wit hin the sel ected memory space. R/W 0x00000

15—0 PAL[15:0]‡‡

† Mem ory- m apped to do ubl e word at addres s 0x4 1004.

‡ Write with write_pah comma nd; read with read_pah command.

§ This field is valid o nly for external memory accesses (CMP[2:0] = 100 ) and is ignored for in ternal memory accesses.

†† If the WEROM fiel d (ECON1[11]—Table 61 on page 112) is set, EROM is selected in place of ERAM.

‡‡ Wri t e wi th write_pal command; r ead with read_pal co m m and.

ADD[15:0]ADD[19:16]MEM[2:0]ESEG[3:0]Reserved 19—022—2026—2331—27

HOST ACCESS ES PA[15:0] AS PAL[15:0] VIAHOST ACCESSES PA[31:16] AS PAH[15:0] VIA

CORES ACCESS PA[31:0] AS DOUBLE-WORD MEMORY-MAPPED REGISTER AT LOCATION 0x41004

15 015 0

THE read_pah AND write_pah COMMANDS T HE read_pal AND write_pal COMMANDS

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.1 Re g ister s (continued)

The host ac ce sse s PAH and PAL by executing the read_pah, read_pal, write_pah, and write_pal comma nds .

After certain host commands, the PIU autoincrements the value in PA. See Section 4.15.5 on page 147 for details

on host commands . Unlik e the DSP1620 and DSP16 210 MIOU, the PIU increments the value in the PA register

linearly and does not wrap it.

4.15.2 Hardware Interface

The host interface to the PI U consists of 29 pins, as summarized in Table 81. The remainder of this section

describes these pin s in detail.

Table 81. PIU External Interface

.Function Pin Type Description

Address and

Data PD[ 15:0] I/O/Z 16-bit bidirectional, paral lel data bus. 3-st ated if PCSN = 1.

Note: If BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits con-

nected to PD[15:0] are act ivated. If BHPDIS = 0 and neithe r the PIU nor an

external device is driving PD[15: 0], the bus hold cir cui ts hold PD[15:0] at the ir

previous valid logic level. This eliminates the need for external pull-up or pull-

down resistors on PD[15:0]. See Section 10.1 on page 268 for detai ls.

PADD[3:0]†I PIU 4-bit address and contr ol inpu t.

Note: If BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits con-

nected to PADD[3:0] are activated. If BHPDIS = 0 and an external device is not

driving PADD[3:0], the bus hold ci rcuits hold PADD[3:0] at their previ ous vali d

logi c leve l. Th is elimi nates the nee d f or ext er nal pul l-u p or pu ll- down r esist ors o n

PADD[3:0]. See Section 10.1 on page 268 for detail s.

Enables and

Strobes PODS‡I PIU output data strobe.

Intel

host: Connect to the host active-l ow read data str obe.

Motorola

host: Connect to the host data strobe.

PIDS‡I PIU input data strobe.

Intel

host: Connect to the host active-l ow write data strobe.

Motorola

host: Connect to logic 0 to program an acti ve-high dat a strobe. Connect to

logic 1 to program an active-low data str obe.

PRWN‡I PIU read/wri te not .

Intel

host: Connect to the host active-l ow host write strobe.

Motorola

host: Connect to host RWN strobe.

PCSN‡IPIU chi p select—active-l ow.

Flags, Interrupt,

and Ready POBE O PIU output buffer empty flag.

PIBF O PIU input buffer full fl ag.

PINT O PIU interr upt (interrup t signal to host) .

PRDY O PIU ready.

Indicates the status of the curr ent host r ead operation or previous host write operation.

The PRDYMD pin determines the logic level of thi s pin.

PRDYMD†I PIU ready pin mode.

0: PRDY pin is activ e-l ow (PRDY = 0 indicates the PIU is read y).

1: PRDY pin is activ e-high (PRDY = 1 indi cates the PIU is ready).

† If the system application does not use these pins, they must be ti ed low.

‡ If the system application does not use these pins, they must be ti ed high.

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.2 Hardware Interface (continued)

4.15.2.1 Enables and Strobes

The PIU provides a chip select input pin (PCSN) that allows the host to connect to multiple DSP16411 or other

devices. The function of the enable and strobe pins (PODS, PIDS, and PRWN) is based on whether the host type

Intel

Motorola

. In order to support both types of hosts, the PIU generates a negative-assertion internal strobe

PSTRN that is a logi c al combination of PCSN , PODS, and PIDS as follows:

PSTRN = PCSN |(PIDS ^ PODS)

The PIU initiates all transactions on the falling edge of PSTRN and completes all transactions on the rising edge of

PSTRN.

Tab le 82. En abl e and Stro be Pins

Pin Name Value Description

PCSN

(input) PIU Chip

Select 0 The host is sel ecting this devi ce for PIU transfers.

1 The host is not sel ecting this devic e for PIU transfers and the PIU 3-st ates PD[15:0] and

ignores any activi ty on PIDS, PODS, and PRWN.

PODS

(input) PIU Output

Data Strobe —



For an

Intel

host, PODS functions as an output data strobe and m ust be connected to the

host active-low read data strobe. The host initiates a read transaction by asserting (low)

both PCSN and PODS. The host concl udes a read transaction by deasserting (hi gh)

either PCSN or PODS.



For a

Motorola

host, PODS functions as a data strobe and must be connected to the host

data str obe. The state of the PIDS pin determines the active level of PODS. If PIDS = 0,

PODS is an active-high data strobe. If PIDS = 1, PODS i s an active-low data strobe. The

host initiat es a read tr ansaction by asserting both PCSN and PODS. The host concludes

a read transaction by deasserting either PCSN or PODS.

PIDS

(input) PIU Input Data

Strobe —



For an

Intel

host, PIDS functions as an input data str obe and m ust be connected to the

host acti ve-low write data strobe. The host init iates a write t ransaction by asserting (low)

both PCSN and PIDS. The host concludes a write tr ansaction by dea sserting (high)

either PCSN or PIDS.



For a

Motorola

host, th e state of PIDS determines the active level of the host data stro be,

PODS.

PRWN

(input) PIU

Read/Write

Not Strobe

— The host dr ives PRWN high duri ng host reads and low during host writes . PRWN must be

stable for the entire access (while PCSN and the appropriate data strobes are assert ed).



For an

Intel

host, PRWN and PIDS are c onnected to the host acti ve-low write data strobe.



For a

Motorola

host, PRWN functions as an act ive read/ write strobe and must be con-

nected to t he host RW N output.

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.2 Hardware Interface (continued)

4.15.2.2 Address and Data Pins

The PIU provides a 16-bit ext ernal data bus (PD[15:0]). It provides a 4-bit input address bus (PADD[3:0] ) that the

host uses to select betwee n PIU registers and to issue PIU commands.

Table 83. Address and Data Pins

Pin Name Description

PD[15:0]

(input/

output)

Data Bus



If t he host iss ues a read command, the PIU drives the data contained in PDO onto PD[15: 0].



If t he h ost issu es a writ e command, it drives th e data onto PD[15:0] and t he PIU latc hes the data

into PDI.



If t he PIU is not sel ected by the host (PCSN is high), the PIU 3-s tates PD[15:0].

Note: I f BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits connected to

PD[15:0] are activated. If BHPDIS = 0 and neither the PIU nor an ext ernal device is driving

PD[15:0], the bus hold ci rcuits hold PD[15:0] at their previous valid log ic l evel. This eli mi-

nates the need fo r external pull -up or pul l-down resistors on PD[15:0]. See Section 10.1 on

page 268 for details.

PADD[3:0]

(input) Ad dress Bus A 4-bit address input driven by the host to select between various PIU registers and to issue PIU

commands. See Section 4.15.5 on page 147 for details .

Note: I f BHPDIS (ECON1[13]—Table 61 on page 112) = 0, bus hold circuits connected to

PADD[3:0] are activa ted. I f BHPDIS = 0 and an ext ernal dev ice is not d rivi ng PADD[3:0], t he

bus hold ci rcuits hold PADD[3:0] at the ir prev ious val id l ogic level. This eliminat es the need

for ext ernal pull-up or pull-down resistors on PADD[3 :0]. See Section 10.1 on page 268 for

details.

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.2 Hardware Interface (continued)

4.15.2.3 Flags, Interrupt, and Ready Pins

The PIU provides buffer s tatu s flag pins, an interrupt to th e host, and a host ready and mode pin pair.

Table 84. F lags, Interrupt, and Ready Pins

Pin Name Value Description

POBE†

(output) PIU Output

Buffer Empty 0PDO contains data ready for the host to read.

1PDO i s empty, i.e., there is no data for the host to read.

PIBF‡

(output) PIU Input

Buffer Full 0PDI is empty, so the host can saf ely write another word into PDI.

1PDI is full wit h the previous word tha t was wri tten by the host. If the host

writes PDI, t he previous data is overwritten.

PINT

(output) PIU Interrupt

Host 0 A core has not requested an int errupt to the host.

1 A core has re quested an interrupt to the host by set ting the PINT field

(PCON[3]—Table 75 on page 136) . The host acknowledges the interrupt

by writing a 1 to the PINT fi eld, clearin g it .

PRDYMD

(input) PIU Ready

Mode 0 PRDY i s active-low.

1 PRDY is active-high.

PRDY§

(output) PIU Ready If

PRDYMD = 0 0



For a host data read operation, the rea d data i n PDO and on PD[15:0] is

vali d and the host can latch the dat a and conclude the read cycle††.



For a host write operation, the previous write operation has been pro-

cessed by the DSP16411 (PDI is empty) and t he host can concl ude the

current write cycle††, i.e. , can write PDI with new data.



For a host data read operation , t he DSP16411 is processing the current

read operation (PDO is stil l empty) and t he host mus t extend t he curr ent

access until the PIU drives PRDY low bef ore concluding the read

cycle††.



For a host write operat ion, the DSP16411 is processing the pre vious

write operation (PDI is still full) and the host must extend the curr ent

access until the PIU drives PRDY low before concl uding the write

cycle††.

PRDYMD = 1 0



For a host data read operation , t he DSP16411 is processing the current

read operation (PDO is stil l empty) and t he host mus t extend t he curr ent

access until the PIU drives PRDY high before concluding the r ead

cycle††.



For a host write operat ion, the DSP16411 is processing the pre vious

write operation (PDI is still full) and the host must extend the curr ent

access until the PIU drives PRDY high before concluding the writ e

cycle††.



For a host data read operation, the rea d data i n PDO and on PD[15:0] is

vali d and the host can latch the dat a and conclude the read cycle††.



For a host write operation, the previous write operation has been pro-

cessed by the DSP16411 (PDI is empty) and t he host can concl ude the

current write cycle††, i.e. , can write PDI with new data.

† The state of this pin i s also readable by the cores in t he P O B E field (PCON[0]—see Tabl e 75 on page 13 6).

‡ The state of this pin i s also readable by the cores in t he P IB F field (PCON[1]—see Tab l e 75 on page 136).

§ For the descriptions in this table to be valid, the PIU must be activated, i.e., PSTRN must be asserted. See Section 4.15.2.1 on page 140 fo r a d efini-

tion of PSTRN.

†† S ee desc ri ption of PIDS and PODS i n Table 82 on page 14 0 .

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.3 Host Data Read and Write Cycles

This section describes typical host read and write

cycles of data for both

Intel

and

Motorola

hosts.

Figure 38 on page 144 is a functional timing diagram of

a data read and a data write cycle for both an

Intel

and

Motorola

host. T he address that the host applies to

PADD[3:0] during the cycle determines the transaction

type, i.e., determines th e host command. S ee

Section 4. 15. 5 on page 147 for details on host com-

mands.

The following sequence c orresponds to the

Intel

data

read cycle shown in Figure 38:

1. The host drives a valid address onto PADD[3:0].

The host must hold PIDS high for the entire duration

of the access.

2. The host ini ti a tes th e cycl e by assert i n g (low) PCSN

and PODS.

3. When data becomes available in PDO, the PIU

drives the data onto PD[15:0].

4. To notify the host that the data in PDO and on

PD[15:0] is valid, the PIU asserts PRDY and deas-

serts POBE. If the data in PDO is not yet valid, the

PIU continues deasserting PRDY and the host must

wait unt il th e PIU assert s PRDY.

5. The host concludes the cycle by deasserting PCSN

or PODS and latching the data from PD[15:0].

6. The PIU 3-states PD[15:0].

The following sequence c orresponds to the

Intel

data

write cycle shown in Figure 38:

1. The host drives a valid address onto PADD[3:0].

The host must hold PODS high for the entire dura-

tion of the access.

2. The host i nitiat es the cycl e by assert ing (low ) PCSN,

PI DS, a n d PRWN.

3. The host drives data onto PD[15:0].

4. If PDI is empty, the PIU noti fies the host by asserting

PRDY and deasserting PIBF. If PDI is still full from a

previous host write, the host must wait until the PIU

asserts PRDY.

5. The host concludes the cycle by deasserting PCSN

or PIDS, causing the P I U to latch the data from

PD[15:0] into PDI.

6. The host 3-states PD[15:0].

The following sequence corresponds to the

Motorola

data read cycl e shown in Figure 38. In the figure and i n

the timing sequences described below, it is assumed

that PIDS is tied high, selecting an active-low data

strobe (POD S).

1. T he hos t drives a valid address onto PADD[3:0].

The host m ust hold PRWN high for the duration of

the access.

2. T he host initiates the cycle by asserting PCSN and

POD S (low).

3. When dat a becomes av ailable in PDO, the PIU

drives the data onto PD [15:0].

4. To notify the host that the data in PDO and on

PD[15: 0] is valid, t he P IU asserts PRDY and deas-

serts PO BE. If the dat a in PDO is not yet valid, the

PIU continues deasserting PRDY and the host must

wait until the PIU asserts PRDY.

5. The host concludes the cycle by deasserting PCSN

or PODS and latching the data from PD[15:0].

6. T he PIU 3-states PD[15: 0].

The following sequence corresponds to the

Motorola

data write cycle shown in Figure 38. In the figure and

in the timing sequences described below , it is assumed

that PIDS is tied high, selecting an active-low data

strobe (POD S).

1. The host drives a valid address onto PADD[3:0] and

drives PRWN low.

2. T he host initiates the cycle by asserting PCSN and

POD S (low).

3. The host drives data onto PD[15:0].

4. If PDI is empty , the PIU notifies the host by asserting

PRDY and deasserting PIBF. If PDI is still f ull from a

previous host write, the host must wait until the PIU

asserts PRDY.

5. The host concludes the cycle by deasserting PCSN

or PODS, causing the PIU to latc h the data from

PD[ 15:0] into PDI.

6. The host 3-states PD[15:0] .

Note: Once the host initiates a d ata read or data write

transaction, it must complete it properly as

described above. I f the host concludes the

transaction before the PIU asserts PRDY, the

results are undefined and the PIU must be

reset. In th is cas e, the ho st can re set the PIU by

setting the HRESET field (PCON[5]—Tab le 75

on page 136), or a cor e can reset the P IU by set-

ting the DRESET field (PCON[6]).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.3 Host Data Read and Write Cycles (continued)

PIU Functional Timing for a Data Read and Write Operation

Figure 38. PIU Functional Timing for a Data Read and Wri te Ope ration

PRDY§

12 3456 123

PIBF

456

DATA READ DATA WRITE

† For the

Motorola

interface, it is assumed that P IDS is tied high, selecting an active-low data strobe (PODS).

‡ PSTRN is an internal signal th at is a logical combination of PCS N, PIDS, and PODS as foll ows: P STRN = PCS N |(PIDS ^ PODS).

§ It is assumed that t he PRDYMD input pin is logic low , causing PRDY to be ac tive-low.

POBE

PADD[3:0]

PD[15:0] DSP

DATA HOST

DATA

PSTRN‡

PODS

PIDS/

PCSN

ADDRESS ADDRESS

PRWN

PODS†

PRWN

INTEL

INTERFACE

MOTOROLA

INTERFACE

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.4 Host Register Read and Write Cycles

This section describes typical host read and write

cycles of PIU registers for both

Intel

and

Motorola

hosts. Figure 39 on page 146 is a functional timing dia-

gram of a regi ster read and a register writ e cycle for

both an

Intel

and a

Motorola

host. Th e address that

the host applies to PADD[3:0] during the cycle deter-

mines how the host accesses the register, i.e., deter-

mines the host command. See Section 4.15.5 on

page 147 for details on host commands.

The following sequence c orresponds to the

Intel

host

read of the PAH, PAL, PCON, o r DSCRATCH register

shown in Figure 39:

1. The host drives a valid address onto PADD[3:0].

The host must hold PIDS high for the entire duration

of the access.

2. The host ini ti a tes th e cycl e by assert i n g (low) PCSN

and PODS.

3. The PIU drives the contents of the register onto

PD[15:0].

4. The host concludes the cycle by deasserting PCSN

or PODS and latching the data from PD[15:0].

5. The PIU 3-states PD[15:0].

The following sequence c orresponds to the

Intel

host

write of the PAH, PAL, PCON, o r HSCRATCH reg i ster

shown in Figure 39. The PIU uses the PDI register to

temporarily hold the write data.

1. The host drives a valid address onto PADD[3:0].

The host must hold PODS high for the entire dura-

tion of the access.

2. The host i nitiat es the cycl e by assert ing (low ) PCSN,

PI DS, a n d PRWN.

3. The host drives data onto PD[15:0].

4. If PDI is empty, the PIU noti fies the host by asserting

PRDY and deasserting PIBF. If PDI is still full from a

previous host write, the host must wait until the PIU

asserts PRDY.

5. The host concludes the cycle by deasserting PCSN

or PIDS, causing the P I U to latch the data from

PD[15:0] into PDI. The PIU transfers the data in PDI

into PAH, PAL, PCON, or HSCRATCH.

6. The host 3-states PD[15:0].

The following sequence corresponds to the

Motorola

read of the PAH, PAL, PCON, or DSCRATCH reg i ster

shown in Figure 39. In the figure and in the tim ing

sequences described below, it is assumed that PIDS is

tied high, selecting an active-low data strobe (PODS).

1. T he hos t drives a valid address onto PADD[3:0].

The host m ust hold PRWN high for the duration of

the access.

2. The host initiates the cycle by asserting (low) PCSN

and PODS.

3. The PIU drives the data in the register onto

PD[15:0].

4. The host concludes the cycle by deasserting PCSN

or PODS and latching the data from PD[15:0].

5. T he PIU 3-states PD[15: 0].

The following sequence corresponds to the

Motorola

write of the PAH, PAL, PCON, or DSCRATCH register

shown in Figure 39. In the figure and in the tim ing

sequences described below, it is assumed that PIDS is

tied high, selecting an active-low data strobe (PODS).

1. The host drives a valid address onto PADD[3:0] and

drives PRWN low.

2. The host initiates the cycle by asserting (low) PCSN

and PODS.

3. The host drives data onto PD[15:0].

4. If PDI is empty , the PIU notifies the host by asserting

PRDY and deasserting PIBF. If PDI is still f ull from a

previous host write, the host must wait until the PIU

asserts PRDY.

5. The host concludes the cycle by deasserting PCSN

or PODS, causing the PIU to latc h the data from

PD[15:0] into PDI. The PIU transfers the data in PDI

into PAH, PAL, PCON, o r HSCRATCH.

6. The host 3-states PD[15:0] .

Note: Once the host initiates a reg ister write transac-

tion, it must complete it properly as described

above . If the host concludes the transac tion

before the PIU asserts PRDY, the results are

undefi ned and the PIU must be reset. In this

case, the host can reset the PIU by setting the

HRESET field (PCON[5]—Table 75 on

page 136) or a c ore can reset the PI U by setting

the DRESET field (PCON[6]).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.4 Host Register Read and Write Cycles (continued)

PIU Functional Timing for a Register Read and Write Operation

Figure 39. PIU Functional Timing for a Register Read and Write Operation

PRDY§

12 3 45 123

PIBF

456

† For the

Motorola

interface, it is assumed that P IDS is tied high, selecting an active-low data strobe (PODS).

‡ PSTRN is an internal signal th at is a logical combination of PCS N, PIDS, and PODS as foll ows: P STRN = PCS N |(PIDS ^ PODS).

§ It is assumed that t he PRDYMD input pin is logic low , causing PRDY to be ac tive-low.

PADD[3:0]

PD[15:0] DSP

DATA HOST

DATA

PSTRN‡

PODS

PIDS/

PCSN

ADDRESS ADDRESS

PRWN

PODS†

PRWN

INTEL

INTERFACE

MOTOROLA

INTERFACE

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.5 Host Commands

The host comma nds ar e su mmarized in Table 85. A host command is a host read or write cycle with t he PADD[3:0]

pins configured to select one of several commands. Each command has a corresponding mnemonic as defined in

the table. These mnemonics are defined to simplify the explanations that follow and are also used by the

DSP16411 model in the

LUxWORKS

™ debugger. These com ma nds are detailed in the remainder of this section.

Table 85. Summ ary of Host Comma nds

Command

Type Pins Command

Mnemonic Description

(PIU/DMAU Response) Flow

Control

PRWN PADD[3:0]

Memory Write 0 000 0 write_pdi W rite DSP16411 memo ry location pointed to by PA with

data on PD[15:0]. Yes

0 0001 write_pdi++ 1. Write DSP16411 memory location pointed to by PA

with data on PD[15:0] .

2. Increment PA by one.

PIU Register W rite 0 100X write_pah Write high hal f of PA via PDI with dat a fr om PD[15: 0]. Yes

0 101X write_pal Write low half of PA via PDI with data from PD[15:0].

0 110X write_pcon Write PCON via PDI with data from PD[15:0].

0 111X write_hscratch Write HSCRATCH via PDI with data from PD[15:0].

Memory Read 1 0000 read_pdo Re ad DSP164 11 memory l ocation poi nted t o by PA, and

place the contents onto PD[15:0]. Yes

1 0001 read_pdo++ 1. Read DSP16411 memory location pointed to by PA,

and place the cont ents onto PD[ 15:0] .

2. Increment PA by one.

1 0010 — Reserved. —

1 0011 rdpf_pdo++ Perform a memory read operation with prefetch . This is

the highest-performance com mand for host reads of

contiguous bl ocks of me mo ry.

See Section 4.15.5.3 on page 149 for details.

Yes

1 0100 load_pdo 1. Read DSP16411 memory location pointed to by PA,

and place t h e c ontents i n PDO.

2. Follow with unld_pdo.

1 0101 load_pdo++ 1. Read DSP16411 memory locat ion pointed to by PA,

and place t h e c ontents i n PDO.

2. Increment PA by one.

3. Follow with unld_pdo.

1 0110 unld_pdo Place the contents of PDO onto PD[15:0]. Yes

PIU Register Read 1 100X read_pah Place the contents of the high hal f of PA onto PD[15:0]. No

1 101X read_pal Place the contents of the low half of PA onto PD[15:0].

1 110X read_pcon Place the cont ents of PCON onto PD[15:0] .

1 111X read_dscratch Plac e the contents of DSCRATCH onto PD[15:0] .

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.5 Host Commands (continued)

The host issues commands to the PIU t hrough the PIU’s external i nterface. Ho st comm ands allow the host to

access all DSP16411 internal and external memory locations. Host commands ca n also read or write PIU scratch

and control/status registers. All commands are executed by a combination of actions performed by the PIU and by

the DMAU bypass channel.

A host command consists of four parts:

1. Read v s. write operation is det erm ined by the state of the PRWN pin.

2. The selection of a PIU int ernal register (PDI, PDO, PA, PCON, HSCRATCH, or DSCRATCH) is ma de by

PADD[3:1].

3. The command can be qualified by the state of the PADD[0] pin. This pin determines if a read or write command

requires a postincrement of the PA register.

4. Dat a is read or d riv en onto PD[15:0 ] by the host.

4.15.5.1 Status/Control/Address Register Read Commands

The host can read the PA, PCON, and DSCRATCH registers by issuing the appropriate command as part of a host

read cycle. These commands do not affect t he state of the PA, PCON, or PDO registers or the state of the PIBF,

POBE, or PRDY pins. No flow control is required for these commands.

Table 86. St atu s/Contro l/Address Register Read Commands

4.15.5.2 Status/C ontrol /Addre ss Regi ster Write Comman ds

The host can write the PA, PCON, and HSCRATCH re giste rs by executing the appropria te comman d as part of a

host writ e cy cle. Flow control is required for these commands, i.e., the host must check the status of the PRDY pin

to ensure that any previous data writ e has compl eted before writing to PA, PCON, or HSCRATCH. For a descrip-

tion of flow control, see the flow control description in Section 4.15.5.5 on page 151.

Table 87. St atu s/Contro l/Address Register Write Co m mand s

Command

Mnemonic Description

read_pah This comman d causes the PIU to place the upper 16-bit contents of the PA register (PAH) onto PD[15:0].

read_pal This command causes the PIU to place the lower 16- bit contents of the PA register (PAL) onto PD[15:0] .

read_pcon This command causes the PIU to place the 16-bit cont ents of the PCON register onto PD[15:0].

read_dscratch This comm and causes the PIU to place the 16-bit contents of the DSCRATCH register onto PD[15: 0].

Command

Mnemonic Description

write_pah This comm and causes the PIU to move the contents of the PDI register into the upper 16 bits of the PA reg-

iste r (PAH). The data move begins at the termi nation of a PIU host write cycle.

write_pal This command causes the PIU to move the contents of the PDI register into the lowe r 16 bits of the PA reg-

iste r (PAL) . The data move begi ns at the termination of a PIU host write cycle.

write_pcon This command causes the PIU to move the contents of the PDI register i nto the PCON register. The data

mov e begins at the ter m ination of a PIU host w rite cycle.

write_hscratch This comm and causes the PIU to move the contents of the PDI regist er into the HSCRATCH re gister. The

data move begins at the termination of a PIU host write cycle.

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.5 Host Commands (continued)

4.15.5.3 Memory Read Commands

The DMAU1 coordinates and executes host data read comm ands via its PIU bypass channel (Section 4.13.4 on

page 86). Prior to issuing a data read command, the host must initialize the PA register with the starting address in

memory by executing the write_pah and write_pal commands. Table 88 describes each host read command in

detail.

Table 88. Memo ry Read Command s

1. A core can coordinate host data read commands by program control, but this is very inefficient compar ed to using the DMAU fo r this pur-

pose.

Command

Mnemonic Description

load_pdo This com mand causes the PIU to:



Request the DMAU to fet ch the sing le word (16 bits) poi nted to by th e contents of PA.



Place the word into PDO.

The host does not wait for the data after issuing this comm and (flow co ntr ol can be igno red), but mus t issue

a subsequent unld_pdo command.

load_pdo++ This com mand causes the PIU to:



Request the DMAU to fet ch the sing le word (16 bits) poi nted to by th e contents of PA.



Place the word into PDO.



Postincrement the addr ess in PA by one to point to the next single-word location.

The host does not wait for the data after issuing this comm and (flow co ntr ol can be igno red), but mus t issue

a subsequent unld_pdo command.

unld_pdo This com mand causes the PIU to drive the current contents of PDO onto PD[15:0]. The host must use

proper flow contr ol wi th t his command (see Section 4.15.5.4 on page 150).

read_pdo This com mand causes the PIU to:



Request the DMAU to fet ch the sing le word (16 bits) poi nted to by th e contents of PA.



Place the word into PDO.



Drive the contents of PDO onto PD[15:0].

The host must use proper flow control with this command (see Section 4.15.5. 4 on page 150).

read_pdo++ This com mand causes the PIU to:



Request the DMAU to fet ch the sing le word (16 bits) fr om the addr ess in PA.



Place the word into PDO.



Drive the contents of PDO onto PD[15:0].



Postincrement the addr ess in PA by one to point to the next single-word location.

The host must use proper flow control with this command (see Secti on 4.15.5. 4 on page 150).

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

Table 88. M emo ry Read Comm ands (continued)

4.15.5 Host Commands (con tinued)

4.15.5.3 Memory Read Commands (continued)

4.15.5.4 Flow Control for Memory Read Commands

The host performs flow control for memory read commands by one of two methods:

1. The host can monitor the PRDY pin to extend an access that has been initiated and wait for PRDY to be

asserted. This method must be used for the read_pdo, read_pdo+ +, and rdpf_pdo++ commands and can be

used for the unld_pdo command.

2. If the host is unable to use the PRDY pin for flow control, it cannot use the read_pdo, rea d_p do ++, or

rdpf_pdo++ comm and to read mem ory and must instead use the com bination of the load_pdo and unld_pdo

commands. The host monitors the POBE field (PCON[0]—see Table 75 on page 136) to determine if PDO is f u ll

and can be read with the unld_pdo command, as shown in the following pseudocod e:

Issue the load_pdo command to the core // Fetch a word from DSP16411 memory

Do: // and place into PDO register.

Issue a read_pcon command to the core // Host read of PCON.

Repeat until POBE is 0 // Wait for POBE = 0.

Issue the unld_pdo command // Data in PDO now on PD[15:0].

rdpf_pdo++ This com mand is a host re ad wit h prefetch. It is t he highest-performance command for hos t reads of con ti g-

uous blocks of memory because it causes the DMAU to fetc h the bl ock of data as doubl e words (32 bits).

Becaus e the host read s the data as singl e wor ds (16 b its) , the PI U stores t he other half of the doubl e word i n

a prefetch buffer. As a result, the host must adhere to the following ru les to use th is comman d:



Before the host issues its first rdpf_pdo++ command with a new memory address, it must first issue a

read_pdo++ command. Thi s fl ushes the pref etch buffer from any previously issue d rdpf_pdo++ com-

mand.



The host m ust not issue a com m and that reads or wr ites PA, PCON, HSCRATCH, or DSCRATCH within

a s e ries of rdpf_pdo++ comm ands.



The host must use proper flow control with this comm and (see Section 4.15.5.4).

F or every two rdpf_pdo++ commands issued by the host, the DMAU and PIU per for m the fo ll owing:



The PIU requests the DM AU to fetch the double word† pointed to by the contents of PA.



The PIU postincrements PA by two to point to the next double-word location.



The PIU places the first word (the single word at the address in PA) into PDO, places the second word

(the si ngle word at the address in PA + 1) into the prefetch buffer, and drives the word in PDO onto

PD[15:0].



In re spons e to th e second rdpf_pdo++ c omm and issu ed by the host , th e PIU pla ces the secon d wor d (the

contents of the prefetch buffer) into PDO and drives the word in PDO onto PD[15:0].

This command achieves an average throughput of one word per seven CLK cycles.

† If PA contains an odd address, the PIU requests a single-word access for the first rdpf_pdo++ command in the sequence because the DMAU

requires all double-word accesses to have even addresses. All subsequent rdpf_pdo++ commands in the sequence have even addresses

and the PIU requests double-word accesses.

Command

Mnemonic Description

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.5 Host Commands (continued)

4.15.5.5 Memory Write Commands

The DMAU1 coordinates and executes host data write commands via its PIU bypass channel (Sec tion 4.13.4 on

page 86). Prior to issuing a data write command, the host must initialize the PA register with the starting address in

memory by executing the write_pah and write_pal commands. Table 89 describes each host write comm and in

detail.

Table 89. Memo ry Write Commands

4.15.5.6 Flow Control for Control/Status/A ddress Register and Memo ry Write Comman ds

The host must use proper flow control for write commands (write_pdi, write_pdi++, write_pah, write_pal,

write_pcon, o r write_hscratch) using one of t wo methods :

1. After the host initiates a write cycle, it can monitor the PRDY pin to determine if PDI is already full. If so, the host

can extend the access and wait for the P IU to assert PRDY.

2. If the host is unable to use the PRDY pin for flow control, it can monitor the PIBF field (PCON[1]—see Table 75

on page 136) before initiating the transaction. For example, the host can execute the following pseudocode:

Do:

Issue a read_pcon command to the core // Host read of PCON.

Repeat until PIBF = = 0 // Wait for PIBF = 0.

Issue the write_pdi command // Write word into PDI.

1. A core can coordinate host data read commands by program control, but this is very inefficient compar ed to using the DMAU fo r this pur-

pose.

Command

Mnemonic Description

write_pdi This command causes the PIU to:



Latch the data from PD[15:0] into PDI.



Request the DMAU to write th e contents of PDI to the singl e wo rd poi nted to by the contents of PA.

The host must use proper flow control with this command (see Section 4.15.5.6).

write_pdi++ This command causes the PIU to:



Latch the data from PD[15:0] into PDI.



Request the DMAU to write th e contents of PDI to the singl e wo rd poi nted to by the contents of PA.



Postincrement the addr ess in PA to point to the next single-word loc ation.

The host must use proper flow control with this command (see Section 4.15.5.6).

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.6 Host Command Examples

4.15.6.1 Download of Program or Data

This example illustrates a host downloa d to DSP16411 T P RAM1 (CORE1) me mory. D o wnload will begin at

address 0x0 in TPRAM1 and proceed for 1000 16-bit words. For all the followi ng steps, the host must observe

proper flow control.

1. First , the host must write the starting address into the PA register. The sta rting address is location 0x0 in

TPRAM 1, so the host iss ues the following two host write comman ds:

write_pah 0x0010 // Host sets PADD[3:0] to 0x8 and writes 0x0010 to PD[15:0]

write_pal 0x0 // Host sets PADD[3:0] to 0xA and writes 0x0 to PD[15:0]

2. Nex t, the host begins to write the dat a to TPRAM1. T his is done by repeatedly issuing the following command

999 times. Each iteration writes the appropriate data to be loaded to each sequential 16-bit location in TPRAM1.

write_pdi++ data // Host sets PADD[3:0] to 0x1 and writes data to PD[15:0]

3. For the write of the last dat a word (in this example, the 1000th word), th e host issues the following command:

write_pdi data_ // Host sets PADD[3:0] to 0x0 and writes data_ to PD[15:0]

4.15.6.2 Uplo ad o f D a t a

This example illustrates a host upload from DSP16411 TPRAM0 (CORE0) memory. The upload begins at address

0x0200 in TPRAM0 and proceeds for 160 16-bit words. For all the following steps, the host must observe proper

flow control.

1. First , the host must write the starting address into the PA regist er. The starting address is location 0x0200 in

TPRAM 0, so the host iss ues the following two host write comman ds:

write_pah 0x0 // Host sets PADD[3:0] to 0x8 and writes 0x0 to PD[15:0].

write_pal 0x0200 // Host sets PADD[3:0] to 0xA and writes 0x0200 to PD[15:0].

2. Next, the host begins to read the data from TP RAM0 , as transferred to the PIU’s PDO regi ster via the DMAU.

This is done by first issuing the following command, which drives PD[15:0] with the data from TPRAM0 address

0x00200:

read_pdo++ // Host sets PADD[3:0]=0x1 and reads data (address 0x00200) on PD[15:0].

// (PIU requests DMAU to fetch single word from address 0x00200.)

3. The host then issues the following commands . Becaus e the address is initially misaligned, the first command

causes the PIU to request the DMAU to fetch a single word. For the remaining commands, the PIU requests the

DMAU to fetch a double word for every other command.

rdpf_pdo++ // Host sets PADD[3:0]=0x3 and reads data (address 0x00201) on PD[15:0].

// (PIU requests DMAU to fetch single word from address 0x00201.)

rdpf_pdo++ // Host sets PADD[3:0]=0x3 and reads data (address 0x00202) on PD[15:0].

// (PIU requests DMAU to fetch double word from address 0x00202.)

rdpf_pdo++ // Host sets PADD[3:0]=0x3 and reads data(address 0x00203)on PD[15:0].

// Repeat rdpf_pdo++ command 156 more times for a total of 159 times.

Note: The host must not issue a command that reads or writes PA, PCON, HSCRATCH, or DSCRATCH within a

series of rdpf_pdo++ commands.

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4 Hardware Architecture (continued)

4.15 Parallel Interface Unit (PIU) (continued)

4.15.7 PIU Interrupts

A core can request an interrupt to the hos t by setting

the PINT field (PCON[3]—see T able 75 on page 136).

If this field is initially cleared and the core sets it, the

PIU asserts (high) the PINT pin. The host must clear

this field after servicing the PINT request to allow a

core to request a subsequent interrupt. It clears t he

field by writing 1 to it.

The host can request an interrupt to the cores b y set-

ting the HINT field (PCON[4]—see Table 75 on

page 136). If this field is initially cleared and the host

sets it, the PIU asserts the PHINT interrupt to the

cores. The interrupted core’s service routine mu st

clear this field after servicing the PHINT request to

allow the host to request a subsequent interrupt. It

clears the field by writing 1 to it. See Section 4.4,

beginning on page 25, for more information on inter-

rupts.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU)

The DSP16411 prov ide s two identical serial interfac e

units (SIU) to i nterface to codecs and various time divi-

sion multiplex (T DM ) bit st ream s. Each SIU is a full-

duplex, double-buffered serial port with independent

input and output frame and bit cl oc k control. The S IU

can generate clocks and frame syn cs internally

(active), or can use c l ocks and frame syn cs generated

externally (passive ). The programmable modes of the

SIU provide for T1/E1 and ST-bus c om patibi lity.

The SIU control registers SCON〈0—12〉, the SIU sta-

tu s registers (STAT and FSTAT), and the SIU input and

output chann el index registers (ICIX〈0—1〉 and

OCIX〈0—1〉) are memory-mapped into the DSP16411

shared I/O memory comp onent (see Sectio n 4 .5.7 on

page 43). Section 4.16.15 on page 184 provides a

detailed description of the encoding of these registers.

The DMAU supports each SIU with two bidirectional

SWT (single-word transfer) channels. S IU0 is directly

connected to DMAU channels SWT0 and SWT1. SIU1

is directly connected to DMAU channels SWT2 and

SWT3. The SWT channels provide transfers between

the SIU input and output data registers and any

DSP1641 1 memory space with minimal core overhead.

Each of the SWT channels can perform two-dime n-

sional memory accesses to support the bufferi ng of

TDM data to or from the SIU. Refer to Section 4.13 on

page 64 for more information on the DMAU.

Each SIU provides two interrupt signals directly to each

DSP core, indicating the completion of an in put or out-

put transaction. Each core can individually enable or

mask these interrupts by programming the core’s inc0

The DSP16 411 SIU provides t he following features:



Two modes of operation: cha nnel mode and frame

mode:

— Both modes support a maximum frame size of

128 logical channels.

— Frame mode selects all channels wit hin a given

frame.

— Channel mode with a maximum of 32 channels in

two subframes allows minimum core intervention

(a core configures the input and output sections

independently only once or on frame bound-

aries).

— Channel mode with a maximum of 128 channels

in eight subframes is achievable if a core config-

ures the input and output sections independently

on subframe boundaries.



Independe nt input and output sections:

— P rogram m able data length (4 bits, 8 bits, 12 bits,

or 16 bits ).

— LSB or MSB first.

— P rogram m able frame sy nc active level, fre-

quency, and position relative to the first data bit in

the frame.

— P rogram m able bit clock active level and fre-

quency.

— Programmable active or passive frame syncs and

bit clocks.



Compatible with T1/E1 and ST-bus framer devices.



Hardware for µ-law and A-law companding.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

Figure 40 is a block diagram of an SIU.

SIU Block Diagram

Figure 40. SIU Block Diagram

SICK

SIFS

SOCK

SOD

SOFS

SCK

CONDITIONING

CLOCK

AND

FRAME SYNC

SELECTION

ACTIVE CLOCK

AND FRAME SYNC

GENERATOR

AGFS AGCKI AGCKO

CLK

SIFSK

ICK

IFS

OCK

OFS

SIOLB

SID

INPUT SHIFT

SIB

OPTIONAL

(µ-LAW OR A-LAW)

SIDR

MUX

SODR

16 DSI

DDO

16 16

SDB

OUTPU T SHIFT

OPTIONAL

(µ-LAW OR A-LAW)

ICK

OCK

CONTROL AND

STATUS REGISTERS

SCON〈0—12〉

STAT

FSTAT

INPUT

CHANNEL

ICIX〈0—1〉

INDEX REGISTERS

OUTPUT

CHANNEL

OCIX〈0—1〉

INDEX REGISTERS

MUX MUX

SOCIX

SICIX

16 16 16

16 16

DMAU

INTERNAL

BIT CLOCKS

AND

FRAME SYNCS

INPUT

SIGNALING OUTPUT

SIGNALING

SOINT

(TO

CORES)

SIINT

(TO

CORES)

IFIX[4] OFIX[4]

IFIX[3:0] OFIX[3:0]

Note: The signals within ovals are control/status register bits. SIOLB is SCON10[8] . IFIX[6:0] is FSTAT[6:0]. OFIX[6:0] is

FSTAT[14:8].

COMPRESSIONEXPANSION

OINTSEL[1:0]

OUTPUT

REQUEST

INPUT

REQUEST

(TO DMAU )

IINTSEL[1:0]

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.1 Hardware Interface

The system interface to the SIU consists of seven pins, describe d in Table 90.

Table 90. SI U External Interface

Pin†Type Name Description

SID I SI U Inp ut

Data The SIU latches data from SID into its input shift register. By default, the SIU latches data from

SID on each falling edge of the input bit clock.

SICK I/O/Z SI U In put

Bit Clock By default, SICK i s configured as an input (pass ive) that provides the serial input bit clock. Alter-

nati vely, the SIU can gener ate the in put bit clock interna lly and can dr ive this clo ck onto the SICK

output (active) .

SIFS I/O/Z SIU In put

Frame Sync SIFS specifies the beginning of a new input frame. By default, SIFS is active-high and is config-

ured as an input (passive). Alternatively, the SIU can gene rate the input fr am e sync int ernally

and can dri ve thi s sync on to the SI FS ou tput ( activ e). To support a 2x ST-bus int erface , SIFS can

be configured as an input that synchronize s the i nternally generated (acti ve) input and output bit

clocks.

SOD O/Z SIU Output

Data The SIU drives data onto SOD from it s output shift regi ster. By default, t he S IU drives data ont o

SOD on each risi ng edge of the outpu t bi t cl ock. The SIU 3-s tat es SO D duri ng inactive or

masked channel periods.

SOCK I/O/Z SIU Output

Bit Clock By default, SOCK is configured as an input (passive) tha t pr ovides the serial output bit clock.

Alt ernati vely, the SIU ca n generate the output bit clo ck inter nall y and can driv e this clock onto the

SOCK output (act ive).

SOFS I /O/Z SIU Output

Frame Sync SOFS specifies the beginning of a new output frame. By default , SOFS is ac tive-high and is con-

fig ured as an i nput ( passive ). Alternat ively, the SIU c an genera te the out put fr ame sy nc int ernal ly

and can drive this sync ont o the SOFS output (act ive).

SCK I SIU External

Clock Source SCK is an inpu t that provides an ext ernal clock source for generating the active mode input and

output bit clocks and frame syncs.

† The name of the pins has a 0 suffix for SIU0 and a 1 suffix for SIU1.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.2 Pin Conditioning Logic, Bit Clock Selection Logic, and Frame Sync Selection Logic

Figure 41 on page 158 diagrams the pin conditioning logic, bit clock s election logic, and f rame sync selection logic.

This logic is controlled by fields in the SCON10, SCON3, SCON2, and SCON1 registers, as detailed in

Table 91. Inpu t functional timing is described in detail in S ection 4.16.3 on page 159. Output functional timing is

described in detail in Section 4.16.4 on page 160. Active clock and frame sync generation is described in detail in

Section 4. 16.5 on page 161. SIU loopba ck is described in detail in Section 4.16.7 on page 168.

Table 91. Control Register Fields for Pin Conditioning, Bit Clock Selection, and Frame Sync Selection

Field Value Description

SIOLB SCON10[8] 0 Di sable SIU loopback mode.

1 Enable SIU loopbac k mo de.

OCKK SCON10[7] 0 The SIU drives output data onto SOD on the rising edge of the output bit clock.

1 The SIU drives output data ont o SOD on the falling edge of t he output bit clock.

OCKA SCON10[6] 0 The output bit clock is provided externally on the SOCK pin (passive).

1 The output bit clock is internally generat ed (active).

OFSK SCON10[5] 0 The output frame sync is active-high.

1 The output fram e sync is active-low.

OFSA SCON10[4] 0 The output frame sync is provi ded externally on the SOFS pi n (passive).

1 The output fra me sync is internally generated (active).

ICKK SCON10[3] 0 The SIU latches i nput data f rom SID on the falling edge of the output bit clock .

1 The SIU latches input data f rom SID on the rising edge of the out put bit clock.

ICKA SCON10[2] 0 The input bit clock is provided ext ernall y on the SICK pin (passive) .

1 The input bit clock is interna ll y generated (ac ti ve).

IFSK SCON10[1] 0 The input frame sync is active- high.

1 The input frame sync is active- low.

IFSA SCON10[0] 0 The input frame sync is provided exter nally on the SIFS pin (passive).

1 The input frame sync is intern all y generated (a cti ve).

OFSE†SCON3[15] 0 Do not drive internally gener ated output frame sync onto SOFS.

1 Drive inte rnal ly generated output frame sy nc onto SOFS.

OCKE†SCON3[14] 0 Do not dr ive int ernally generated output bit clock onto SOCK.

1 Drive internally generated output bit clock onto SOCK.

IFSE†SCON3[7] 0 Do not drive internally gener ated input frame sync onto SIFS.

1 Drive inte rnal ly generated input frame syn c onto SIFS.

ICKE†SCON3[6] 0 Do not driv e int ernally generated input bit clock onto SICK.

1 Drive inte rnal ly generated input bit clock onto SICK.

ORESET SCON2[10] 0 Activate output section and begin output proces sing after next output fr am e sync.

1 Deactivate outp ut section and ini tialize bit and fr am e counters.

OFSDLY[1:0] SCON2[9:8] 00 Do not delay out put frame sync.

01 Delay output frame sync by one cycle of the output bit clock.

10 Delay output frame sy nc by two cycles of th e output bit clock.

IRESET SCON1[10] 0 Activate input section and begin input processing after next input fram e sync.

1 Deactivate input section and initialize bit and frame counters.

IFSDLY[1:0] SCON1[9:8] 00 Do not delay input frame sync.

01 Delay input frame syn c by one cycle of the input bit clock.

10 Delay input frame syn c by two cycles of th e input bit clock.

† Set this field in active mode only, i.e., if the corresponding OCKA/OFSA/ICKA/IFSA field is set.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.2 Pin Conditioning Logic, Bit Clock Selection Logic, and Frame Sync Selection Logic (continued)

Fi gure 4 1. Pin Co nditioni ng Logic, B i t Clock S e l ecti on Logic, and Fra m e S ync Selection Logi c

SIFS

IFSK

IFSA

AGFS

(FRO M AC TIVE

IFS

IFSDLY[1:0]

IFSE IFSK

SOFS

OFSK

OFSE OFSK

OFSA

IRESET

CLOCK GENERATOR)

ICK ICK

SIFSK

(TO ACTIV E

CLOCK GENERATOR) SIOLB

OFS

OFSDLY[1:0]

ORESET

DQ DQ

OCK OCK

SICK

ICKK

ICKA

AGCKI

(FRO M AC TIVE

ICKE ICKK

SOCK

OCKK

OCKE OCKK

OCKA

CLOCK GENERATOR) SIOLB

AGCKO

(FRO M AC TIVE

CLOCK GENERATOR)

ACTIVE/PASSIVE

LOOPBACK

PIN CONDITIONING CLO CK AND FRAME SYNC S ELECTION

DELAY

ICK

OCK

ACTIVE/PASSIVE

LOOPBACK

Not e: The signals within ovals are control register fields. SIO LB is SCON10[8], IFSE is SCON3[7], IFSK is SCON10[1], IFSA is SCON10[0],

IRESET is SCON1[10], IFSDLY[1:0] is SCON1[9:8], OFSE is SCON3[15], OFSK is SCON10[5 ], OFSA is SCON10[4], ORESET is

SCON2[10], OFSDL Y[1:0] is SCON2[9:8], ICKE is SCON3[6], I CK K is SCON10[3], ICKA is SCON10[2], OCKE is SCON3[14], OCKK is

SCON10[7], and OCKA is SCON10[6].

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.3 Basic Input Processing

The SIU begins input processing when the user soft-

ware clears the IRESET field (SCON1[10]). The sys-

tem application must ensure that the input bit clock is

applied before IRESET is cleared. If an input bit clock

is active (internally generated), the user program must

wait at least t wo bit clock cycles between c hangi ng

AGRESET (SCON12[1 5]) and clearing IRESET. I f the

DMAU is used to service the SI U, the user software

must activate the DMAU channel before clearing

IRESET.

Figure 42 illustrates the default functional input

timing. SICK (SIU input bit clock) sy nchronizes all SIU

input transactions. The SIU samples SIFS (SIU input

frame sync) on the risin g edge of SICK. If the SIU

detects a rising edge of SIFS, it ini tiates inpu t process-

ing for a new fram e. The SIU latches data bits f rom

SID (SIU input data) on the falling edge of S I CK for

active channels (i.e., channels selected via software).

Serial Input Functional Timing

Figure 42 . D efault Ser ial Input Functional Timing

To vary the functional input timing from the default

operati on described abov e, either core can program

control register fields as follows:



If either c ore sets the ICKK field (SCON10[3]—see

Table 113 on page 191), the SIU inverts S ICK and:

— De tec t s t he as sertion of SI FS o n the falling ed ge

of SICK.

— Latches data from SID on each rising edge of

SICK.



If the software sets the IFSK field (SCON10[1]), SI FS

is active-low and the start of a new frame is specified

by a high-to-low transition (falling edge) on SIFS,

detected by an activating edge1 of the input bit clock.



By default, the SIU latches the first data bit of an

input frame from SID one phase of SICK aft er the

detection of the input frame sync. Either core can

increase this delay by one or two input bit c lock

cycles by programmi ng the IFSDLY[1:0] field

(SCON1[9:8]—see Ta ble 104 on page 186).

An exte rnally generated input bit clock can drive SICK

(passive mode) or the SIU can generate an internal

input bit clock that c an be appl ied to SICK (active

mode). An externally gene rated input frame sync can

drive SIFS (passive mode) or the SIU can generate an

internal input frame sync that can be applied to SIFS

(active mode). S ee Section 4.16.5 on page 161 for

detai ls on clock and frame sync generation .

Note: T he combi nati on of passive input bit clock and

active input frame sync is not supported.

The SIU clocks the dat a fo r the select e d ch a nnel i n to a

16-bit input shift register (see Figure 40 on

page 155). After the SIU clocks in a complete 4 bits,

8 bits, 12 bits, or 16 bits according to the ISIZE[1:0]

field (SCON0[4 :3]—see Table 103 on page 185), it

tra n s fers the d a ta t o SIB (serial input buffer register)

and sets the SIBV (serial input buffer val id) flag

(STAT[1]—see Table 118 on page 197 ). SIB is not a

user-accessible register . Either core can program the

IMSB fi eld ( SCON0[2]) to select MSB- or LSB-first data

transfer from the input shift register to SIB. For data

lengths that are less than 16 bits, the SIU right justifies

the data (places the data in the lower bit positions) in

SIB and fills the upper bits with ze ros.

SICK

SIFS

SID B0B1

DATA

LATCHED DATA

LATCHED

START OF

FRAME

1. The act ivating edge of the input bit clock is the rising edge of the

clock i f the ICKK f ield (SCON10[3]) is cleared and the falling edge

of the clock if the ICKK field is set.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.3 Basic Input Processing (continued)

If SIDR (serial input data register) i s empty (the SIDV

flag (STAT[0]) is cleared), the following actions occur:

1. The SIU formats the data (µ-law, A-law, or no modifi-

cation) in SIB according to the IFORMAT[1:0] field

(SCON0[1:0]—see Table 103 on page 185).

2. The SIU transfers the formatted data to SIDR.

3. The SIU clears the SIBV (serial input buff er valid)

flag (STAT[1]).

4. The SIU sets the SIDV flag to i ndicate that SIDR is

full.

5. The SIU signals the DMAU that serial input data is

ready for transfer to memory.

6. If the IINTSEL[1:0] field (SCON10[ 12: 11] —see

Table 113 on page 191) equals two, the SIU asserts

the SIINT interrupt to the c ores to reque st service.

Dat a rem ains in SIDR and SIDV remains set until the

data is read by the DMAU or by one of t he cores. After

SIDR has been read, the DSP16411 clears the SIDV

flag.

If new data is completely shifted in before the old data

in SIB is transferred to SIDR (i.e. , wh il e SIBV and SIDV

are both set), an input buffer overfl ow occurs and the

new data overwrites the old data. The SIU sets the

IO F L OW field ( STAT[6]) to reflect this e rror condition.

If the IINTSEL[1:0] field (SCON10[12:1 1]) equals three,

the SIU asserts the SIINT interrupt to the cores to

reflect this condition.

4.16.4 Basic Output Processing

The SIU begins output processing when the user soft-

ware clears the ORESET field ( SCON2[1 0]). The sys-

tem application must ensure that the output bit cl oc k is

applied before ORESE T is cleared. If an output bit

clock is active (internally generated), the user program

must wait at least four bit clock cycles between ch ang-

in g AGR ESET (SCON12[ 15]) and clearing ORESET. If

the DMAU is used to service the SIU, the user software

must activate the DMAU channel before clearing

ORESET.

Figure 43 illustrates the default serial functional output

timing. SOCK (SIU output bit clock) synchronizes all

SIU output transactions. The SIU samples SOFS (SIU

output frame sync) on the rising edge of SOCK. If the

SIU detects a risi ng edge of SOF S, it initiates output

processin g for a new frame. Th e SIU drives data bits

onto SOD (SIU output data) on the rising edge of

SOCK for active channels (i.e., channels selected via

software). The SIU 3-states SOD for inactive channels

and during idle periods . (See Section 4.16.8 on

page 168 for details.)

Figure 43 . Default Serial Output Fu nc ti onal Timi ng

To vary the serial function output timing from the default

operation des cribed above, either core can program

control register fields as follows:



If either core sets the OCKK field (SCON10[7]—see

Table 113 on page 191), the SIU inverts S OCK and:

— Detects the assertion of SOFS on the falling edge

of SOCK.

— Drives data onto SOD on each falling edge of

SOCK.



If either core sets the OFSK field (SCON10[5]),

SOFS is active-low and the start of a new frame is

specified by a high-to-low t rans ition (falling edge) on

SOFS, detected by an activating edge 1 of the output

bit clock.



By default, the SIU drives output data onto SOD

immediately after the detection of the output frame

sync. Either core can program the OFSDL Y[1:0] field

(SCON2[9:8]—see Table 105 on page 187) to cause

the SIU to delay driving data onto SOD by one or two

output b it clock cycl e s.

SOC K can provide an externa lly generated outp ut bit

clock (passive mode ) or the SIU c an generate an inter-

nal output bit clock (active mode) that can be applied to

SOC K. SOFS c an provide an externally generate d

output frame sync (passive mod e) or the S I U can gen-

erate an internal output frame sync (active mode) that

can be applied to SOF S. S ee Section 4.16.5 on

page 161 for details on clock and frame sync genera-

tion.

Note: T he combi nation of passive outp ut bit clock and

active output frame syn c is not supported.

1. The activating edge of the output bit cloc k is the rising edge if the

OCKK field (SCON10[7]) is cleared and the falling edge if the

OCKK field is set.

SOCK

SOFS

SOD B0B1

START OF

FRAME

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.4 Basic Output Processing (continued)

The DMAU or either of the cores writes output data into

SODR (serial output data register). See F igure 40 on

page 155.If SODR is empty, the SIU clears the SODV

flag (serial output data valid, STAT[3]—Table 118 on

page 197). This indicates that a core or the DMAU can

write new data to SODR. The following describes the

sequence of even ts that follow this condition:

1. The SIU signals the DMAU that it i s ready to accept

new data. If the OINTSEL[1:0] field

(SCON10[14:13]) equals two, the SIU generates the

SOINT interrupt signal to both c ores.

2. The DMAU or one of the cores writes SODR with

new data.

3. The SIU sets SODV to indicate that SODR is ful l.

4. At the beginning of the time slot for the next active

channel (on an activating edge of the output bit

clock), the SIU transfers the contents of SODR to the

16-bit output shift regis ter, clears SODV, and drives

the first data bit onto SOD. While transferring the

data from SODR to the output shift register, the SIU

formats the data (µ-law, A-law, or no modification)

according to the value of the OFORM AT [1:0] field

(SCON0[9:8]—see Table 103 on page 185). Based

on the value of the OMSB field (SCON0[10]), the

SIU shifts the dat a out LSB-first or M SB -first. Based

on the value of the OSIZE[1:0] field ( SCON0[12:1 1]),

the SIU drives 4 bits, 8 bits, 12 bits, or 16 bits of the

data in the output shift register onto SOD. If

OSIZE [1:0] is programmed to select a data size of

4 bits, 8 bits, or 12 bits, the data must be right-justi-

fied in (placed in the least significant bits of) the

16-bit SODR register.

Output buffer underflow can occur if the DMAU or core

does not write new data into SODR before the contents

of SODR are to be transferred to the output shift regis-

ter. Specifically, an output buffer underflow occurs if all

three of the f ollowing conditions ex ist:



SODR is em pty (SODV = 0).



The output shift register is empty.



The time slot for an active channel is pending.

If output buffer underflow occurs, the SIU sets the

OUF LOW field (STAT[7]) and continues to output the

old data in SODR (repeats step 4) for any a ctive chan-

nels until the DMAU or core writes new data t o

SODR. If the OINTSEL[1:0] field ( SCON10[14:13])

equals three, the SIU asserts the SOINT interrupt to

notify the cores of the underflow condition.

4.16.5 Clock and Frame S ync Generati on

Generation of the SIU bit clocks (SICK and SOCK) and

frame syncs (SIFS and SOFS) can be active or pas-

sive. In active mode, these signals can be derived

from the DSP clock, CLK, or from an external clock

source appl ied to the SCK pin. In either case, the

active clock source is divided down by a programmable

clock divide r to generate the desired bit clock and

frame sync frequencies. In passive mode, the external

clock source applied to the SICK pin is used directly as

the input bit clock, the signal applied to SIFS is used

directly as the input frame sync, the clock source

applied to the SOCK pin is used directly as the output

bit clock, and the signal applied to SOFS is used as the

output frame sync. All of the bit fields that control bit

clock and frame syn c generatio n are summa rized in

Table 92 on page 164.

The input section and the outp ut section of each SIU

operate independently and require individual clock

sources to be specified.

Note: T he combi nati on of passive input bit clock and

active input frame sync is not supported, and the

combination of passive output bit clock and

active output frame syn c is not supported. If the

combinat ion of an active bit clock and a passive

frame sync is selected, the frame sync must be

derived from the bit clock and must meet the tim-

ing requirem ents specified in Section 11.11,

beginning on page 294.

The def ault operation specifies that the SIU clocks

input data bits from SID on the falling edge of SICK and

drive output data bits onto SOD on the rising edge of

SOC K. The DSP16411 c an invert the polarity (active

level) of the SICK pin by setting the ICKK field

(SCON10[3]—see Table 113 on page 191) and the

polarity (active level) of the SOCK pin by setting the

OC KK field (SCON10[7]). The SIU can generate one

or both bit clocks i ntern ally (active) or externally

(passive). Setting the ICKA field (SCON10[2]) puts

SICK into active mode, and setting the OCKA field

(SCON10[6]) puts SOCK into active mode.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.5 Clock and Frame Sync

Generation (continued)

Active bit clocks are generated by di viding down either

the internal clock (CLK) or a clock source applied to the

SCK pin, depend ing on the AGEXT field

(SCON12[12]—see Table 115 on page 195). The

active clock generator must also be enabled by clearing

the AGRESET field (SCON12[15]) and programming a

divide ratio into the A GCKLI M[7:0] field

(SCON11[7:0]—see Table 1 14 on page 194). I f either

bit clock is internally generated, the corresponding

clock pin (SICK or SOCK) is an output that can be

turned off by clearing the ICKE field (SCON3[6]— see

Table 106 on page 188) or the OCKE field

(SCON3[14]—s ee Table 106 on page 188), placing the

corresponding pin into 3-state.

Passive bit clocks are externally generated and applied

directly to the corresponding SICK or SOCK pins. In

this case, the ICKA or OCKA field (SCON10[2] or

SCON10[6]) is cleared. The program should disabl e

the active clock generator by set ting the AGRESET

field (SCON12[15]) only if both clocks and bot h frame

syncs are externally generated.

The default operation of the SIU specifies the active

level of the input and output frame sync pins to be

active-high, so the rising edge of SIFS or SOFS indi-

cates the beginning of an input or output frame, respec-

tively. The program c an invert the active level (active-

low) by s etting the IFSK and OFSK fields ( SCON10[1]

and SCON10[5]). Th e program can configure one or

both frame syncs as internally generated (active) or

externally generated (pas sive), based on the states of

the IFSA and OFSA fields (SCON10[0] and

SCON10[4]).

The active frame syncs are generated by dividing down

the internally generated active mode bit clock. The

active clock generator must also be enabled by clearing

the AGRESET fi eld (SCON12[15]) and by program-

ming a divide ratio into the AGFSLI M[10: 0] field

(SCON12[10:0]). If either frame sync is internally gen-

erated, the corresponding frame sync pin (SIFS or

SOFS) is an output that can be turned off by clearing

th e IF SE fi e ld (SCON3[7]—see Table 106 on

page 188) or the OF SE field (SCON3[15]—s ee

Table 106 on page 188), placing the corresponding pin

into 3-state.

Passive frame syncs are externally generated and

applied directly to the SIFS or SOFS pins. In this case,

the IFSA field (SCON10[0]—see Table 113 on

page 191) or the OFSA field (SCON10[4]) is cleared.

The program should disable the active clock generator

by setting the AGRESET field (SCON12[15]—see

Table 115 on page 195) only if both frame syncs and

both bit clocks are externally generated.

The active clock generator has the ability to synchro-

nize to an external source (SIFS). If the AGSYNC field

of (SCON12[14] ) is set, t he internal clock generator is

synchroni zed by SIFS. Thi s feature is used only if an

external clock sou rce is applied to the SCK pin and

drives the internal clock gene rator, i.e., if t he program

set the AGEXT fie ld (SCON12[12]). A typical applica-

tion for using external synchronization is an S T-bu s

interface that employs a 2X external clock source. This

feature is discussed in more detail in Section 4.16.6,

beginning on page 166.

The active clock generator also has the ability to pro-

vide addit ional input data setup time if an external

source (the SCK pin, selected by AGEXT = 1) is

selec ted to generate the input and output bit clocks.

If the I2XDLY fiel d (SCON1[11]— s ee Table 104 on

page 186) is set, the high phase of the internally gener-

ated inpu t bit clock, I CK , is stretched by one SCK

phas e, providing extra data capture time. This feature

is illustrated in Figure 53 on page 183.

The relative location of data bit 0 of a new f rame can be

delayed by a maximum of two bit clock periods with

respect to the location of the frame sync. T his feature

is controlled by the IFSDLY[1:0] field (SCON1[9:8]—

see Table 104 on page 186) for input and the

OFSDLY[1:0] field (SCON2[9:8]—see Table 105 on

page 187) for output. The location of the leading edge

of frame sync is approxim ately coincident with bit 0 by

defaul t. However, bit 0 can be delayed by one or two

bit clocks after frame sync as shown in Figure 44.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.5 Clo ck and Frame S ync Ge nera tion (continued)

Frame Sync to Data Delay T iming

Figure 44. Frame Sync to Data Delay Timing

5-7849 (F)

Bn – 2 Bn – 1 B0B1B2B3B4B5B6B7

Bn – 3 Bn – 2 Bn – 1 B0B1B2B3B4B5B6

Bn – 4 Bn – 3 Bn – 2 Bn – 1 B0B1B2B3B4B5

S〈I,O〉CK

S〈I,O〉FS

S〈I,O〉D

(〈I,O〉FSDLY = 0)

S〈I,O〉D

(〈I,O〉FSDLY = 1)

S〈I,O〉D

(〈I,O〉FSDLY = 2)

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.5 Clock and Frame Sync Generation (continued)

Table 92. A Summa ry of Bit Clock and Frame Sync Control Register Fields

Bit Field Register Description

AGRESET SCON12[15] Enables the int ernal active clock divider/generator.

AGSYNC SCON12[14] Enables synchronization of the internal active clock generator to SIFS. If set,

AGEXT must al so be set. This feature is enabl ed for 2x ST-bus operation.

SCKK SCON12[13] Defines the act ive level of the external clock sour ce, SCK.

AGEXT SCON12[12] Defines the cl ock source to the internal clock di vider/ge nerator (eit her the DSP

CLK or external SCK pin).

AGFSLIM[10:0] SCON12[10:0] Defines the clock divider ratio for the internal generation of frame syncs (active

mode).

AGCKLIM[7:0] SCON11[7:0] Defines the clock divider ratio for the internal generation of bit clocks (act ive

mode).

SIOLB SCON10[8] Enables SIU loopback mode. See Section 4.16.7 on page 168.

OCKK SCON10[7] De fines the active leve l of the SOCK pin.

OCKA†SCON10[6] De fi nes SO CK as internally (act ive mode, SOCK is an output) or externally (pas-

sive mode, SOCK is an input) generated.

OFSK SCON10[5] De fines the active leve l of the SOFS pin.

OFSA†SCON10[4] Defines SOFS as inter nally (acti ve m ode, SOFS is an outpu t) or ext ernally (pas-

sive mode, SOFS is an input) generated.

ICKK SCON10[3] Defines the active level of the SICK pin.

ICKA†SCON10[2] Defines SI CK as int ernally (SICK is an output) or externally (SICK is an input)

generated.

IFSK SCON10[1] De fi nes the active level of the SIFS pin.

IFSA†SCON10[0] Defines SIFS as internal ly (active mode, SIFS is an output) or externally (passi ve

mod e, SIFS is an input) generated.

IFSE SCON3[7] Fo r active mode SIFS, this bit determi nes if t he SIFS pi n is dr iven as an output.

ICKE SCON3[6] For active mode SICK, this bit determines if the SICK pin is driven a s an output.

OFSE SCON3[15] For active mode SO FS, t his bit determines if the SOFS pi n is driven as an output .

OCKE SCON3[14] For active mode SO CK, t his bit deter mines if the SOCK pin is driv en as an output .

I2XDLY SCON1[11] If set, the SIU stre tches the high phase of the internal ly generated input bi t clock,

ICK, by one SCK phase to provide additional serial input data setup (capture)

tim e. This feature is valid only if AGEXT = 1 and ICKA = 1.

† The combination of passive output bi t clock (OCKA = 0) and active output frame sy nc (OFSA = 1) is not supported. The combinat ion of pas-

sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.5 Clock and Frame Sync

Generation (continued)

Table 93 off ers t hree ty pical settings for the SI U contr ol

generation. The term as required used in this table

refers to the user’s system requirem ent s.



Example 1 shows the bit field values if both bit clocks

and frame syncs are supplied directly from an exter-

nal serial device (e.g., a co dec).



Exam ple 2 show s the bit fi eld v alues i f bot h bit clocks

and frame syncs are active and generated directly

from the internal clock, CLK. This example assumes

that the S I CK, SOCK, SIFS, and SOFS pins are out-

puts driven by the SIU.



Exam ple 3 show s the bit fi eld v alues i f bot h bit clocks

and the output frame sync are active and generated

directly from the external clock source applied to the

SCK pin. The SIFS pin is driven by an external

source and is used to synchronize the internal frame

bit counter. The SICK, SOCK, and SOFS pins are

not driven by the SIU, and th e high phase of the

internal input bit clock is st retche d. T hese sett ings

are valid for a doubl e-rate clock ST-bus interface.

The eff ect of these SIU control register settings is

illustrated by Figure 53 on page 183.

Table 93. Exam ples of Bit Clock and Frame Sync Control Register Fields

Bit Fie ld Regist er Example 1

All Passi ve Example 2

All Active (CLK) Example 3

All Active (SCK)

Double-Rate ST-Bus

AGRESET SCON12[15] 1 0 0

AGSYNC SCON12[14] 0 0 1

SCKK SCON12[13] 0 0 1

AGEXT SCON12[12] 0 0 1

AGFSLIM[10:0] SCON12[10:0] 0 as required as required

AGCKLIM[7:0] SCON11[7:0] 0 as required 1

SIOLB SCON10[8]000

OCKK SCON10[7 ] as requ ired as required as requ ired

OCKA†SCON10[6]011

OFSK SCON10[5 ] as requ ired as required as requ ired

OFSA†SCON10[4]011

ICKK SCON10[3 ] as requ ired as required as required

ICKA†SCON10[2]011

IFSK SCON10[1] as requ ired as required 1

IFSA†SCON10[0]011

IFSE SCON3[7]010

ICKE SCON3[6]010

OFSE SCON3[15] 0 1 0

OCKE SCON3[14] 0 1 0

I2XDLY SCON1[11] 0 0 1

† The combination of passive output bi t clock (OCKA = 0) and active output frame sy nc (OFSA = 1) is not supported. The combinat ion of pas-

sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.6 ST -Bus Timing Examples

Figures 45 and 46 illustrate SIU timing examples for 2x ST -bus compatibility, which requires active clock generation

with SCK as the cl oc k source and SIFS synchronizat ion enabled (AGEXT = 1, IFSA = 1, and AGSYNC = 1). T he

input frame sync, SIFS, is externally generated.

Figure 45 illustr ates the functional timing of the internally generated bit clocks, ICK and OCK, assuming the bit

clock divide ratio is two (AGCKLIM = 1). This results in bit clocks that have a period that i s twice the period of SCK.

Since the divide ratio is even, the duty cycle of the generated bit clock is 50%. Also shown are the internally gener-

ated frame syncs, IFS and OFS. Refer to F igure 40 on page 155 for a block diagram of the internal clock genera-

tor.

Clock and Frame Sync Generation with External Clock and Synchronization

(AGCKLIM = 1, SCKK = 1, IFSK = 1, SIFS Has No Effect)

Note: The timing reference TACKG is the active clock period determined by the AGCKLIM[7:0] f ield (SCON11[7:0]).

Figure 45. Clock and Frame Sync Generation with External Clock and Synchronization

(AGEXT = AGSYNC = IFSA = IFSK = 1 and Timing Requires No Resynchronization)

SCK

OCK

SIFS

ICK

OFS

IFS

TACKG

SOD B0B1BNBN – 1

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.6 ST -Bus Timing Examples (continued)

Figure 46 illustrates the functional timing of t he internally generated bit clocks and frame syncs, ICK, OCK, IFS,

and OFS, assu ming the bit clock divide ratio is t wo (AG CK LIM = 1, sam e as Figure 45 on page 166) and SIFS is

asserted while the internally generated bit clocks are high. In this case, the internal bit clocks are forced to remain

high a t the falling e dge of SIFS. This effe ctiv e ly s tret c h es the int e rn al b it cl oc ks b y on e SCK cyc le, sync h ro niz in g

th e int ern al bit clocks to th e externa l fra me sync , SIF S. As a result , th e fir st fra me fo llowing synchron i za ti o n is

lost. The SIU 3-states the SOD pin during the lost frame. Subsequent frames are synchronized and function cor-

rectly. The dotted lines in this fig ure show the location of SIFS and the active bit clocks and syncs if S I FS had

occurred one SCK cycle later (i .e., if the int ernal frame bit counter had expired prior t o the assertion of SIFS, the

same as Figure 45).

Clock and Frame Sync Generation with External Clock and Synchronization

(AGCK LIM= 1 , SCKK= 1, IF SK =1, SIFS C aus e s Resy nchronizat ion )

Figure 46. Clock and Frame Sync Generation with External Clock and Synchronization

(AGEXT = A GSY N C = IFSA = IFSK = 1 and Timing Requires Resync hroni zatio n)

SCK

OCK

SIFS

ICK

OFS

IFS

SOD BNBN – 1BN – 2

THIS FRAME IS LOST

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.7 SIU Loopback

Each SIU of the DSP16411 includes an internal diag-

nostic mode to verify functionality of the SIU without

requiring syste m intervention. If the SIOLB field

(SCON10[8]—see Table 113 on page 191) is set, th e

SIU output data pin (SOD) i s internally looped back to

the SIU in put data pin (SID), the output bit clock is

internally connected to the input bit clock, and the out-

put frame sync is internally connected to the input

frame sync. Any input at t he S ID pin is ignored whil e

loopback is enabled.

There are two ways that SIU loopback can be used:

1. The user’s code can define the output bit clock and

output frame sync to be active and the input bit clock

and input frame sync to be passive. Se e

Section 4.16.5, beginning on page 161, for in forma-

tion on configuring the bit clocks and frame syncs as

active or passive. If SIU loopback is enabled, the

act iv e sig nals g enera te th e necessa ry clocks and

frame syncs for the S IU to send and receive data to

itself. Unless enabled by the user, the SICK, SOCK,

SIFS, and SOFS pins are 3-state. To enable these

outputs, set the ICKE, OCKE, IFSE, a nd O FSE

fields (see SCON3 in Table 106 on page 188).

2. The user’s code can define all the SIU clocks and

syncs to be passive. See Section 4.16.5, beginning

on page 161, for information on configuring the bit

clocks and frame syncs as active or passive. The

system must supply a bit clock to the SOCK pin and

a frame sync to the SOFS pin.

4.16.8 Basi c Frame St ructure

The primary data structure processed by the SIU is a

fram e, a sequence of bits that is initiated by a frame

sync. E ach inpu t and output frame is composed of a

numbe r of channels, as determined by the IFLIM[6:0 ]

field (SCON1[6:0]—Table 104 on page 186) for input

and the OF LIM[6:0 ] field (SCON2[6:0]—Ta ble 105 on

page 187) for output. Eac h channel consists of 4 bits,

8 bit s, 12 bits, or 1 6 bi ts, as determined by the

ISIZE[1: 0] and OSIZE[ 1:0 ] fields (SCON0[4:3] and

SCON0[12:11]—see Table 103 on page 185), and has

a programmable data format (µ-law , A-law , or linear) as

determined by the IFORMAT[1:0] and OFORMAT[1:0]

fields (SCON0[ 1:0] and SCON0[9:8]). All channels in a

frame must have the same data length and data format.

Figure 47 illustrates the basic frame structure assum-

ing five channels per frame (〈I,O〉IFLIM[6:0] = 4) and a

chan nel size of 8 bits (〈I,O〉SIZE[1:0] = 0). Figure 48

on page 169 illustrates the same frame structure wit h

idle time. The SIU 3-states the SOD pin during idle

time.

Note: If the output section is configured for a one-chan-

nel frame (OFLIM[6: 0] = 0x0) and a passive

frame sync (OFSA(SCON10[4]) = 0), the SOFS

frame sync interval must be constant and a mul-

tiple of the OCK output bit clock.

Basi c Frame Structure

Figure 47. Basic Frame Structure

CHANNEL

〈I,O〉CK

S〈I,O〉D

〈I,O〉SIZE

〈I,O〉FS

02176534 02176534 02176534 02176534 02176534 02176534

CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 0

FRAME PERIOD

〈I,O〉FLIM + 1 CHANNELS

FRAME

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.8 Basic Frame Structure (continued)

Figure 48 . Basic Frame S tructu re with Idle Time

To assist channel select ion within a frame, a frame is

partitioned into a maximum of eight subframes. Each

subframe has 16 logical chann els, for a total channel

capacity of 128 channels per frame.

4.16.9 Assigning SIU Logical Channels to DMAU

Channels

Regardless of the operating mode, the channel index

registers for t he SIU must be initialized via software if

the DMAU is used to transfer data to and from memory .

There are a t ot al of four 16-bit chan nel index registers:

two for input (ICIX〈0—1〉) and two for output

(OCIX〈0—1〉). Each bit corresponds to one logical

channel within the currently selected even or odd s ub-

frame. These bit fields determine the assignmen t of

logical channels within a s ubfram e to a specific DMAU

SWT channel dedicated to that SIU. Recall that two

bidirectional SWT channels of the DMAU support each

SIU so that logical channels can be routed to two sepa-

rate memory spaces.

In channel mode, ICIX0 co rrespo nds to the currently

selected even input subframe, as determined by the

ISFID_E[1:0] field (SCON3[1:0]—see Table 106 on

page 188). ICIX1 corresponds to the currently

selected odd input subfram e, as determined by the

ISFID_O[1:0] field (SCON3[4:3]). OCIX0 corresponds

to the currently selected even output subframe, as

determined by the OSFID_E[1:0] field

(SCON3[9:8]—see Table 106 on page 188). OCIX1

correspond s to the currently selected odd output sub-

frame, as determined by the OSFID_O[1:0] field

(SCON3[12:11]). In frame mode, ICIX〈0—1〉 and

OCIX〈0—1〉 are circularly mapped to multiple channels

in the frame as illustrated by Ta ble 122 on page 199

and Table 1 21 on page 198.

If a bit f iel d of SIU0’s ICIX〈0—1〉 or OCIX〈0—1〉 regis-

ter is cleared, the corresponding logical channel of

SIU0 is assigned to SWT0. If a bit field of these regis-

ters is set to one, the corresponding logi cal channel of

SIU0 is assigned to SWT1. If a bit field of SIU1’s

ICIX〈0—1〉 or OCIX〈0—1〉 register is cl eared, the cor-

respon ding logical channel of SIU1 is assigned to

SWT2. If a bit field of these same registers is set to

one, the corresponding logical channel of SIU1 is

assig ned to SWT3 . Fo r example, to assign SIU0 inpu t

chan nels 0 to 7 to SWT0 and 8 to 15 to SWT1, the

value written to ICIX0 is 0xFF00 .

CHANNEL

FRAME PERIOD

〈I,O〉FLIM + 1 CHANNELS

〈I,O〉CK

S〈I,O〉D

〈I,O〉SIZE

〈I,O〉FS

02176534 02176534 02176534 02176534 02176534 021534

CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 0

FRAME

000000

IDLE†

† The SIU 3-state s SOD dur ing idle time.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.10 Frame E rror Detectio n and Reporting

The SIU supports back-to-back frame processing.

However, when a frame has completed, the SIU s tops

processing until the beginning of another frame is

detected by sampling a new frame sync. If the new

frame sync is detected before a frame has complet ed,

the following actions are taken by the SIU:

1. A n interrupt request is generated, if

enabled. Spec ifical ly, if the oc currence of SIFS is

detected before the end of the input frame, an input

error has occurred. If enabled via t he IINTSEL[ 1:0]

field (SCON10[12:11]—see Table 1 13 on page 191),

the SIINT interrupt is asserted to the DSP cores. If

the occurrence of SOFS is detected before the end

of the output frame, an output error has occurred. If

enabled via the OINTSE L[1:0] field

(SCON10[14:13]), the SOINT interrupt is asserted to

th e cores.

2. The IFERR flag (in put frame error) or OFERR flag

(output frame error) i s set in the STAT register

(Table 118 on page 197), as appropriate. All sub-

frame, channel, and bit counters are reinitialized and

a new input or output frame transaction is

initiated. The data from the incomplete frame can be

erroneous and the core software should perform

error recovery in response to the setting of IFERR or

OFERR.

3. If the SIU is i n passive mode (clocks and frame syn c

are externally generated) or in acti ve mode with the

AGSYNC fie ld (SCON12[ 14]) cleared, the new

frame transaction begins immediately after the new

frame sync is detected. If the SIU is in active mode

with AGSYNC set and an externally generated clock

is applied to SCK, the new frame transaction begins

after the detection of the f irst frame sync that does

not cause resynchronization of the bit clocks. See

Section 4.16.6 on page 166 for details on resynchro-

nizing bit clocks in active mode.

4.16.11 Frame Mo de

Frame mode allows for a high channel capacity, but

sacrifices channel selectivity. A program selects frame

mode by setting the IFRAME field (SCON1[7]—

Table 104 on page 186) for input and the OFRAM E

field (SCON2[7]—see Table 105 on page 187 ) for

output. In this mode, the SIU processes all channels in

the frame. A maximum of 128 consecutive channels in

the frame can be accessed. T he IFLIM[ 6:0] field

(SCON1[6:0]) and OFLIM[6: 0] field (SCON2[6:0])

define the number of channels in each input and output

frame.

If using frame mode, the user performs the following

steps in software:

1. Configure the number of channe ls in the frame

structure (1 to 128) by programming the IFLIM[6:0]

field with the input frame size, and the OFLIM[6:0]

field with the output frame size. The input and out-

put frame size is the number of channels m inus

one. For simple serial communications (one chan-

nel per frame), these fields should be programmed

to ze ro.

2. Configure the channel size (4 bits, 8 bits, 12 bits, or

16 bits) by writing the ISIZE[1:0] and OSIZE[1:0]

fields (SCON0[4:3] and SCON0[12:11]—Table 103

on page 185). Select LSB-fi rst or MSB-first by pro-

gramm ing the IMS B and OMS B fields (SCON0[2]

and SCON0[10]). Configure the data format by pro-

gramm ing the IFORM AT [1 :0] and OFOR MAT[1:0]

fields (SCON0[1:0] and SCON0[9:8]).

3. P rogram the 16-bit channel index registers,

ICIX〈0—1〉 and OCIX〈0—1〉 (Table 120 on

page 198), to assign specific SIU input and output

chan nels to be routed to one of t wo DMAU SW T

channels (SWT0 or SWT1 for SIU0; SWT2 or SWT3

for SIU1). T he ma ximum num ber of channels that

ICIX〈0—1〉 or OCIX〈0—1〉 can specify is 32 (two

16-bit registers). If the number of channels is

greater than 32, the DMAU routing specified for

chan nels 0—3 1 is applied to channels 32—63,

chan nels 64— 95, etc., as shown in Table 122 on

page 199 and Table 121 on page 198. For the spe-

cial case of simpl e seria l communi cations (one

channel per frame), program channels 0 and 1 t o the

same value, i.e., program ICIX〈0—1〉[1:0 ] to th e

same v alue for input and OCIX〈0—1〉[1:0 ] to th e

same v alue for output.

4. E nable frame mode by setting IFRAME ( SCON1[7])

and OFRAME (SCON2[7]).

5. Di sa ble channel mode by clearing the ISFIDV_E

field (SCON3[2]—see Table 106 on page 188),

ISFIDV _O field (SCON3[ 5]), OSFID V_E field

(SCON3[10]), and OSFIDV_O field (SCON3[13]).

6. S ele ct pass ive vs. active bit clocks and frame syncs

(see Sec tion 4 .16.5 on page 161 for details).

7. P rogram the IINTSEL[1: 0] field (SCON10[12:11])

and OINTSEL[1:0] field (SCON10[14:13]) as

required by the application.

8. Begin input and output processing by clearing the

IRESET fi e ld (SCON1[10]) and the ORESET field

(SCON2[10]).

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.12 Chan nel Mode—32 Cha nne ls or Less in

Tw o Su bf ram es or Le ss

Compared to frame mode, channel mo de provides for

channel selectivity with minimal core overhead at the

expense of chann el density. For input, this mode is

selected if the following conditions are met:



The IFRAME field (SCON1[7]—see Table 104 on

page 186) is cleared.



The ISFIDV_E field (SCON3[2]—see Table 106 on

page 188), the ISFIDV_O field ( SCON3[5]), or both

are set.

For output, channel mode is selected if the following

conditions are met:



The OFRAME field (SCON2[7]—see Table 104 on

page 186) is cleared.



The OSFIDV_E field (SCON3[10]), the OSFIDV_O

field (SCON3[ 13]), or both are set.

In this mode, the SIU processes a maximum of

32 channels within a given frame. The maximum frame

size is 128 channels. The IFLIM[6: 0] field

(SCON1[6:0]—Table 104 on page 186 ) for input and

the OF LIM[ 6:0] field (SCON2[6:0]—Ta ble 105 on

page 187) for output define the number of channels in

the frame structure.

To ass ist with channel selection, both input and output

frames are divided into eight subframes: four even (0,

2, 4, 6) and four odd (1, 3, 5, 7). The SIU can enable

only one even and one odd subframe at any one time.

Each subf rame cont ains 16 channels1 that can be indi-

vidually enabl ed. Figure 49 shows a 128-channel

frame and the relationship between frames, subframes,

and logical channels. Table 94 on page 172 specifies

the assoc iation of channe l numbers to even and odd

subframes.

Channel Mode on a 128-Channel Frame

Figure 49. Channel Mode on a 128-Channe l Frame

1. It is assumed that for channel mo de, the number of channels per frame as determined by the IFLIM[6:0 ] and O FLIM[6:0] fields is evenly divis-

ible by 16. This results in exactly 16 channels per su bframe. If the nu mber of channels per fr ame is not ev enly divis ible by 16, th e last sub-

frame is a par tial subframe of less than 16 cha nnels. If this is the case and if interrupts are program m ed to occur on subf rame boundaries

(see Figure 51 on page 178), then an interrupt is not generated for the partial subframe.

1513

1413

SYNC

DATA

128-CHA NNEL FRAME

〈I,O〉FLIM = 0x 7F

〈I,O〉FRAME = 0x0 ; DEFINE AS 128-CHANNEL FRAME

; TRANSFER ONLY SELECTED CHANNELS

8 SUBFRAMES PER TDM FRAME

16 CHANNELS PER SUBFRAME

[0:15] [16:31] [112:127][96:111][80:95][64:79][48:63][32:47]

SUBFRAME 2 SUBFRA ME 5

01 2 1314

〈I,O〉SFID_E = 1

〈I,O〉SFIDV_E = 1

〈I,O〉SFVEC_E = 0xFFFF

OSF MS K_E = 0x 7FF9

CHANNEL DATA BITS

; SUBFRAME 2 SELECTED

; ALLOW INDIVIDUAL CHANNEL SELECTION

; ALL 16 CHANNELS ACCE SSIBLE

; MASK ALL OUTPUT CHANNELS

; EXCEPT 15, 2, 1

〈I,O〉ISIZE = 1

〈I,O〉MSB = 1 ; 16-B IT CHANNELS

; MSB SHIFTED FIRS T

ACTIVE CHANNE LS

M ASKED C H AN N ELS

CHANNEL DATA BITS

1215

014

EVEN

SUBFRAME ODD

SUBFRAME

EVEN

SUBFRAME EVEN

SUBFRAME ODD

SUBFRAME

〈I,O〉SFID_O = 2

〈I,O〉SFIDV_O = 1

〈I,O〉SFVEC_O = 0xFFFF

OSF M SK_O = 0xBFF D

; SUBFRAME 5 SELECTED

; ALLOW INDIVIDUA L CHANNEL SELECTION

; ALL 16 CHAN N ELS AC C ESSI BLE

; MASK ALL OUTPUT CHA NNELS

; EXC EPT 1 AND 14

16 BITS PER CHANNEL

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.12 Channel Mode— 32 Chan nels or Less in Two Subframes or Less (continued)

Table 94. Subframe Definition

For SIU processing of specific l ogical chann els, the

user enables at least one active even or odd subframe

within the input and output frames and defines the even

(0, 2, 4, or 6) or odd (1, 3, 5, or 7) input and output sub-

frame ID. Within each active subfram e, active input

channels and active outpu t channels are individuall y

selected via the channel activation vectors. These fea-

tures are controlled by the SIU control m em ory -

mapped registers, SCON〈3—9〉.

In channel mode, the SIU drives data onto the SOD pin

only during the time slots for active output

channels. Otherwise, the S IU 3-st ates SOD. Similarly,

in channel mode, the SIU latches input data bits only

during the time slots for active input channels.

If the DMAU is used to transfer SIU input data to mem-

ory, each active input channel (time slot) can be individ-

ually routed to a specific SWT channel. See

Section 4.16.9 on page 169 for details.

Even Subframes Odd Subfram es

Subframe Channels Subframe Channels

00—15 1 16—31

2 32—47 3 48—63

4 64—79 5 80—95

6 96—111 7 112—127

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.12 Chan nel Mode—32 Cha nne ls or Less in

Tw o Su bf ram es or Le ss (continued)

If using channel mode, the user performs the following

steps in software:

1. Configure the number of channels in the frame

structure (1 to 12 8) by programming the IFLIM[6: 0]

field (SCON1[6:0] —see T able 104 on page 186) with

the frame size for input and the OFLIM [6:0] field

(SCON2[6:0]—see Tab le 105 on page 187) with the

frame size for output.

2. Conf igure the channel size (4 bits, 8 bits, 12 bits, or

16 bit s) by writing the IS I ZE[ 1:0] and OSIZE [1:0]

fields (SCON0[4:3] and SCON0[12:11]—see

Table 103 on page 185). Select LSB-first or MSB-

first by programm ing the IMSB and OM S B fields

(SCON0[2] and SCON0[10]). Con figure the data

format by programming the IFORMAT[1:0] and

OFORMAT[1:0] fields (SCON0[1 :0 ] a nd

SCON0[9:8]).

3. Disable frame mode by clearing the IFRAME field

(SCON1[7]—see Table 104 on page 186 ) and t he

OFRAME field (SCON2[7]—see Tab le 105 on

page 187).

4. S elect the num ber of subframes (one or two) to be

enabled. If two subframes are enabled, one must be

even and one must be odd. See s tep 5.

5. S elect the active subframe(s) and channels within

each subframe. Tables 95 to 99 further detail the bit

fields described below:

— To activate an even input subframe, set the

ISFIDV_E field (SCON3[2]—see Tab le 106 on

page 188). Also program the ISFID_E[1:0] field

(SCON3[1:0]) with the address of the active even

subframe (active subframe numbe r is

2×ISFID_E). Within the active subframe, up to

16 logical channels can be individually enabled

via the ISFVEC_ E[15:0] field (SCON4— s ee

Table 107 on page 189). For each enabled chan-

nel, assign one of two DMAU SWT channels by

setting or clearing the c orresponding bit in ICIX0

(Table 122 on page 199).

— To activate an odd input subframe, set the

ISFIDV_O field (SCON3[5]—see Table 106 on

page 188). Als o program the ISFID_O[ 1:0] field

(SCON3[4:3]) with t he address of the active odd

subframe (active subframe numbe r is

(2 ×ISFID_O) + 1). Within the active subframe,

up to 16 logical c ha nnels c an be individually

enabled via th e ISFVEC _O[15: 0] field

(SCON5—see Table 108 on page 189). For each

enabled channel, assign one of two DMAU SWT

channels by setting or clearing the corresponding

bit in ICIX1 (Table 122 on page 199).

— To activate an even output subframe , set the

OSFI DV_E field (SCON3[10]). Also program the

OSFID_E[1:0] field (SCON3[9:8]) with the

address of the active even subframe (active sub-

fram e numbe r is 2 ×OSFID_E). Within the

active subframe, up to 16 logical channels can be

individually enabled via the OSFVEC_E[15:0]

field (SCON6—see Table 109 on page 190). Any

enabled channel can be individually masked via

the OSFM S K_E [15:0] field (SCON8—see

Table 11 1 on page 190). Mask ing an output

channel retains the data structure (the DMAU

coun ters are updated) but does not drive data

onto SOD for that channel period. For each

enabled channel, assign one of two DMAU SWT

channels by setting or clearing the corresponding

bit in OCIX0 (Table 121 on page 198).

— To activate an odd output subfram e, set the

OSFIDV_O field (SCON3[13]). Also program the

OSF ID_O[ 1:0 ] field (SCON3[ 12:11]) with the

address of the active odd subframe (active sub-

fram e number is (2 ×OSFID_O ) + 1). Wi t hin the

active subframe, up to 16 logical channels can be

individually enabled via the OSFVEC_O[15:0]

field (SCON7—s ee Table 110 on page 190). Any

enabled channel can be individually masked via

the OSFM S K _O[ 15:0] field (SCON9—s ee

Table 112 on page 190). M ask ing an output

channel retains the data structure (the DMAU

coun ters are updated) but does not drive data

onto SOD for that channel period. For each

enabled channel, assign one of two DMAU SWT

channels by setting or clearing the corresponding

bit in OCIX1 (Table 121 on page 198).

6. S ele ct pass ive vs. active bit clocks and frame syncs

(see Table 4.16.5 on page 161 for details ).

7. P rogram the IINTSEL[1: 0] field (SCON10[12: 11] )

OINTSEL[1:0] field (SCON10[14:13]) as required by

the applic ation.

8. Begin processing the active channels by clearing the

IRESET fi e ld (SCON1[10]—see Table 104 on

page 186) and the ORESET field (SCON2[10]—see

Table 105 on page 187). Further user software

intervention for SIU configuration is only required to

redefin e the subframe enab le, the subframe ID, or

the active channels within a subframe and their

associated channel index values.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.12 Chan nel Mode— 32 Cha nne ls or Less in Two Subframes or Le ss (continued)

Table 95. L oc ation of Control Fields Used in Channel Mode

Table 96. Description of Control Fields Used in Channel Mode

Even Subframe Control Odd Subfram e Control Description

Input/

Output Field Register Field Register

Input ISFIDV_E SCON3[2] ISFIDV_O SCON3[ 5] Subframe ID valid (enable).

ISFID_E[1:0] SCON3[1:0] ISFID_O[1:0] SCON3[4 :3 ] Su b fra me ID.

ISFVEC_E[15:0] SCON4[15:0] ISFVEC_O[15:0] SCON5[15:0] Channel act ivation vector.

Output OSFIDV_E SCON3[10] OSFIDV_O SCON3[13] Subfram e ID valid (enable).

OSFID_E[1:0] SCON3[9:8] OSFID_O[1:0] SCON3[12:11] Subframe ID.

OSFVEC_E[15:0] SCON6[15:0] OSFVEC_O[15:0] SCON7[15:0] Channel activation vector.

OSFMSK_E[15:0] SCON8[15:0] OSFMSK_O[15:0] SCON9[15:0] Channel maski ng vector.

Even Subframe Control Odd Subframe Control

Input/

Output Field Description Field Description

Input ISFIDV_E Enable ev en input subframes. ISFIDV_ O Enab le odd input subframes.

ISFID_E[ 1:0] Select one of f our even input

subframes 0, 2, 4, or 6

(active subframe = 2 ×ISFID_E).

ISFID_O[1:0] Select one of four odd input sub-

frames 1, 3, 5, or 7

(active subframe =

(2 ×ISFID_O) + 1).

ISFVEC_E[15:0] Bit vector activate s up to

16 logical channel s indepen-

dently within selected even input

subframe.

ISFVEC_O[15:0] Bit vec tor activates up to 16 logical

channels indepen dently within

selected odd input subfram e.

Output OSFIDV_E Enable even output subfram es. OSFIDV_O Enable odd output subframes.

OSFI D_E[1:0] Select one of four even output

subframes 0, 2, 4, or 6

(active subframe =

2×OSFID_E).

OSFI D_O[1:0] Select one of four odd output sub-

frames 1, 3, 5, or 7

(active subframe =

(2 ×OSFID_O) + 1).

OSFVEC_E[15:0] Bit vector activates up to

16 logical channel s indepen-

dently within sel ected even out-

put subframe.

OSFVEC_O[15: 0] Bit vector activates up to 16 logical

channels indepen dently within

selected odd output subframe.

OSFMSK_E[ 15:0] Bi t vect or sele cts up t o 16 logical

channels indepen dently within

selected even output subframe to

be mask ed †.

OSFMSK_O[15: 0] Bit vector select s up to 16 logi cal

channels indepen dently within

selected odd output subframe to be

masked†.

† If an output channel is masked, then the SOD pin is forced to the high-impedance state during that channel’ s time slot.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.12 Chan nel Mode— 32 Cha nne ls or Less in Two Subframes or Le ss (continued)

Table 97. Subfram e Selection

Table 98. Channel Activation Within a S elected Subfram e

Table 99. Channel Mask ing Within a Selected Subfram e

Input/

Output Even/Odd

Subframes To Select

Subframe Set Control Bit Configur e Control Field

Name Location Name Location Value

Input Even 0 ISFIDV_E SCON3[2] ISFID_E[1:0] SCON3[1:0] 0

2 1

4 2

6 3

Odd 1 ISFIDV_O SCON3[5] ISFID_O[1:0] SCON3[4:3] 0

3 1

5 2

7 3

Output Even 0 OSFIDV_E SCON3[10] OSFID_E[1:0] SCON3[9:8] 0

2 1

4 2

6 3

Odd 1 OSFIDV_O SCON3[13] OSFID_O[1:0] SCON3[12:11] 0

3 1

5 2

7 3

Input/

Output Selected

Even/Odd

Subframe

Control Field

Name Location Description

Input Even ISFVEC_E[15:0] SCON4[15:0] See Figure 50 on page 176.

Odd ISFVEC_O[15:0] SCON5[15:0] See Figure 50 on page 176.

Output Even OSFVEC_E[15:0] SCON6[15:0] See Figure 50 on page 176.

Odd OSFVEC_O[15:0] SCON7[15:0] See Figure 50 on page 176.

Input/

Output Selected

Even/Odd

Subframe

Control Field Description

Name Location

Output Even OSFMSK_E[15:0] SCON8[ 15:0] See Figure 50 on page 176 .

Odd OSFMSK_O[15:0] SCON9[15:0] See Figure 50 on page 176 .

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.12 Chan nel Mode— 32 Cha nne ls or Less in Two Subframes or Le ss (continued)

Subframe and Channel Selection in Channel Mode

Fig ure 50 . Su bf ram e a n d C hanne l Sel ect i on in Channel Mo de

SELECT SUBFRAME 6 (〈I,O〉SFID_E = 3)

ISFVEC_E[15:0] (if ISFIDV_E = 1)

OS FVEC_E[15:0] (if OSFIDV_E = 1)

OS FMSK_E[15:0] (if O SFIDV_E = 1)

ISFVEC_O[15:0] (if ISFIDV_O = 1)

OS FVEC_O[15:0] (if OSFID V_O = 1)

OSFMSK_O[15:0] (if OSFIDV_O = 1)

BIT

100

101

102

103

104

105

106

107

108

109

110

111

SELECT SUBFRAME 0 (〈I,O〉SFID_E = 0)

SELECT SUBFRAME 4 (〈I,O〉SFID_E = 2)

SELECT SUBFRAME 2 (〈I,O〉SFID_E = 1)

SELECT SUBFRAME 7 (〈I,O〉SFID_O = 3)

BIT

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

SELECT SUBFRAME 1 (〈I,O〉SFID_O = 0)

SELECT SUBFRAME 5 (〈I,O〉SFID_O = 2)

SELECT SUBFRAME 3 (〈I,O〉SFID_O = 1)

EVEN SUBFRAMES

ODD SUBFRA MES

ACTIVATE/MASK CHANNEL CONTROL:

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.13 Chan nel Mode—Up to 128 Channels in a

Maximum of Eight Subfra mes

The SIU has th e ab ilit y to p ro c es s a maximum of

128 c hannel s in channe l mode if the SIU control is

properly synchronized with core intervention. The

steps required for the additional channel processing

are the same as for the channel mode disc uss ed in

Section 4.16.12, beginning on page 171. However, the

SIU control registers must be reconfigured with greater

frequency, costing additional core overhead. In this

case, subframe activation and channel definition within

a subframe can occur as of ten as every subframe

boundary.

The SIU has the abilit y to interrupt either core at frame

boundaries, subframe boundaries, channel bound-

aries, or if an error is detec ted (ove rflow or underflow).

The interrupt signal trigger is determined by the

IINT S EL [1 :0] fi e ld (SCON10[ 12:11]—see Table 113 on

page 191) fo r input processing and by the

OINTSEL[1:0] field (SCON10[ 14:13]) for output

processing. When servicing subframe boun dary inter-

rupts generated by SIU0 or SIU1, eit her CORE0 or

CORE1 can modify the input and output subframe and

channel control fields without aff ecting the current sub-

frame being processed. Spec ifically, the cores can

modify the OSFID_E [1:0] and OSFI D_O[ 1:0] fields

(SCON3—see Table 106 on page 188), the

ISFID_E[1:0] and ISFID_O[1 :0] fields (SCON3—see

Table 106 on page 188), the ISFVEC_ E[15: 0] field

(SCON4—see Table 107 on page 189), the

ISFVEC_O[15:0] field (SCON5—see Table 108 on

page 189), the OSF VEC_E [ 15:0] field (SCON6—s ee

Table 109 on page 190), the OSFVEC_O[15:0] field

(SCON7—see Table 110 on page 190), the

OSFMSK_E[15:0] field (SCON8—see Table 111 on

page 190), and the OSFMSK_O[15:0] field

(SCON9—see Table 112 on page 190). This is al so

true for the ICIX0, ICIX1, OCIX0, and OCIX1 registers

(see Table 122 on page 199 and Ta ble 121 on

page 198). The SIU latches the val ues in these control

bit fields at the beginning of every subframe.

If one of the cores uses this feature in an SIINT or

SOINT interrupt service routine (ISR), the SIU can be

programmed to individually select channels for input or

outpu t anywhere within the frame. The user can take

advantage of this feature by updating the input and out-

put subframe and channel control fields after each sub-

frame is processed, allowing channels in more than two

subfram es to be processed during each frame. T his

requires the ISR to count the subframe interrupts and

program the neces sary SIU control registers with the

appropriat e values to process the next desired sub-

fram e. Th e user also has the option of programming

the input and output subframe and chan nel control

fields two subframes in advance, because these bit

fields are double-buffered. For example, if the active

subframe is even, the user’s ISR can reprogram the

control bit fields with the appropriate values for the next

even subframe without disturbing the processing of the

currently active subframe.

In channel mode, the SIU drives data onto the SOD pin

only during the time slots for active output channels.

Otherwise, t he S IU 3-states S OD. Similarly, in channel

mode, the SIU latches input data bits only during the

time slots for active input channels.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.13 Chan nel Mode— Up to 128 Channels in a Maximum of Eight Subfra mes (continued)

Figure 51 illustrates the conditions under which the SIINT or SOINT input or output interrupt is asserted if the

IINTSEL[1:0] or OINTSEL[1:0] field (SCON10[12:11] or SCON10[ 14:13]—see Table 113 on page 191 ) is pro-

grammed to cause the SIU to generate interrupts on subframe boundaries. The SIU computes the current channel

number mod ulo 16. It compares this value to 15 and generates SIINT or SOINT if there is a match. This notifies

the cores of the completion of the subframe.

Generating Interrupts on Subframe Boundaries

Figure 51. Generating Interrupts on Subframe Boundaries

100

106

107

108

109

110

111

SELECT SUBFRAME 7 (〈I,O〉SFID_O = 3) 112

113

114

115

116

122

123

124

125

126

127

SELECT SUBFRAME 1 (〈I,O〉SFID_O = 0)

SELECT SUBFRAME 5 (〈I,O〉SFID_O = 2)

SELECT SUBFRAME 3 (〈I,O〉SFID_O = 1)

EVEN SUBF RAMES

ODD SUBF RAMES

SELECT SUBFRAME 6 (〈I,O〉SFID_E = 3)

SELECT SUBFRAME 0 (〈I,O〉SFID_E = 0)

SELECT SUBFRAME 4 (〈I,O〉SFID_E = 2)

SELECT SUBFRAME 2 (〈I,O〉SFID_E = 1)

(CURRENT CHANNEL NUMBER)MODULO 16 = 1 5

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.13 Chan nel Mode—Up to 128 Channels in a

Maximum of Eight Subfra mes (continued)

For example, the following steps are performed by soft-

ware running in CORE0 to use SIU0 to process input

channels 2, 3, 18, 20, 36, 55, 7 8, 100, and 111 as part

of a 128-channel input frame. It is assumed that the

DMAU SWT0 and SWT1 channels are used to transfer

the input data to memory.

1. Initi alize the SWT0 and SW T1 channel s (see

Section 4. 13.5 on page 87).

2. Conf igure the channel size (4 bits, 8 bits, 12 bits, or

16 bit s) by writing the IS I ZE[ 1:0] field

(SCON0[4:3]—Table 103 on page 185). Select

LSB-first or MSB-first by programming the IMSB field

(SCON0[2]). Configure the data format by program-

ming the IFOR MAT[ 1:0] field (SCON0[1:0]).

3. Conf igure SIU0 for a 128-channel input frame struc-

ture by programming the IFLIM[6:0] field

(SCON1[6:0]—Table 104 on page 186) to

127. En able channel mode with two active sub-

frames by clearing the IFRAME field (SCON1[7])

and setting the ISFIDV_E and ISFIDV_O fields

(SCON3[2,5]—Table 106 on page 188). Program

input interrupts to occur at every subframe boundary

by programming the IINTSEL[1:0] field

(SCON10[12:11]—Table 113 on page 191) to 0x1.

4. P rogram SIU0 with the active channels for the first

even (channels 2 and 3) and odd (18 and 20)

subframes. This is a ccom pl ished by writing the firs t

subframe IDs (0 and 1) t o the ISFID_E[1:0] and

ISFID_O[1:0] fields (SCON3—see Table 106 on

page 188) and enabling the channels within these

subframes via the ISFV EC_ E[15:0] field

(SCON4—see Table 107 on page 189) and

ISFVEC_O[15:0] field (SCON5—see Table 108 on

page 189). In summary, ISFID_E[1:0] = 0,

ISFID_O[1:0] = 0, ISVEC_E[15:0] = 0xC, and

ISVEC_O[15:0] = 0x14.

5. Program the input channel index registers to assign

each channel to either SWT0 or SWT1. The SWT

channel chosen determ ines the dest ination of the

data. In this example, channels 2 and 18 are

assigned to SWT0, and channels 3 and 20 are

assigned to SWT1. T heref ore, ICIX0 = 0x8 and

ICIX1 =0x10.

6. E nab le the SIINT interrupt (see Section 4 .4.6 on

page 31) and the SWT0 and SWT1 channels of the

DMAU by settin g the DRUN[1:0 ] fie lds

(DMCON0[5:4]—Table 31 on page 71). Create a

softw are-managed s ubframe count er and initialize

the count er to zero. Clear the IRES ET field

(SCON1[10]—see Tab le 104 on page 186) to begin

input data processing by SIU0. CORE0 can con-

tinue to process the user’s application.

7. When the SIINT interrupt occurs, CORE0’ s ISR

immedia tely reads the software-mana ged subframe

counter to determine the current subframe in

progress and increm ent s the counter by one. The

ISR then reprograms the SIU to process the next

even subframe. I n this example, the next even sub-

fram e is 2, s o ISF ID_E[1: 0] is program med to

0x1. The active channel for this subframe is 36, so

ISVEC_E[15:0] is written with 0x10. ICIX0 also must

be reprogrammed to assign channel 36 to either

SWT 0 or SWT1. I f SWT 1 is selected, then

ICIX0 = 0x10. This active channel setting takes

place at the next s ub frame boundary. This ISR is

now complete and CORE 0 returns to the previous

activity.

8. When the next SIINT interrupt occurs, CORE0’s ISR

again reads the subf rame counter to determine the

current subframe in progress. If the counter value is

7, it is re s et to zer o; oth er w i se, the valu e is incr e -

mented by one. The ISR then reprograms SIU0 to

process the next odd subframe. In this example, the

next odd subframe is 3, so ISFID_O[ 1:0] is pro-

grammed to 0x1. The desired active channel for this

subframe is 55, so ISVEC_O[15:0] is written with

0x80. ICIX1 mu st also be reprogrammed to assign

chan nel 55 to either SWT0 or SWT1. If SWT1 is

selec ted, then ICIX1 = 0x80. T his active channel

setting takes place at the next subframe

boundary. This ISR is now complete, and CORE0

returns to the previous activity.

9. Steps 7 and 8 are repeated indefinitely, processing

all eight subframes and then beginning again with

subfram e 0 of the next frame.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.14 SIU Examples

The following section s illustrate examples of single-chan nel I/O and the ST-bus interface.

4.16.14.1 Single-Channe l I/O

If t he SIU is interfaced directly to a si ngle codec, the program typically configures the SIU as fol lows:

1. E nable frame m ode operation, one channel per frame.

2. Conf igure the data length as required by the external device (4 bi ts, 8 bit s, 12 bits, or 16 bits).

3. E nable passive bit clocks and frame syncs, configured as required by the external device. Se e Table 93 on

page 165.

This configuration assum es that the codec device generates the bit clock and frame sync.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.14 SIU Examples (continued)

4.16.14.2 ST-Bus Interface

The SIU is compati ble with the

MITEL

® S T-bu s. Both single-rate and dou ble-rate clock protocols are supported.

Table 100 describes the SIU control field se ttings and resulting signal s for both protocols.

Tabl e 100. Control Regist er an d Fiel d Co nfiguratio n for ST-B us I nterface

Control Field Description Value

(Single-Rate

Clock)

Value

(Double-Rate

Clock)

OSIZE[1:0] SCON0[12:11] Clear for 8-bi t out put data. 00 00

ISIZE[1:0] SCON0[4:3] Clear for 8-bit inpu t dat a. 00 00

I2XDLY SCON1[11] Set to extend high phase of ICK. 0 1

IFSDLY[1:0] SCON1[9:8] Clear fo r no IFS del ay. 00 00

OFSDLY[1:0] SCON2[9:8] Clear for no OFS delay. 00 00

OFSE SCON3[15] For active O FS, selects whether OFS is driven onto SOFS

pin. 00

OCKE SCON3[14] Clear t o not drive active OCK onto SOCK pin. 0 0

IFSE SCON3[7] For active IFS, select s whether IFS is driv en onto SIFS pi n. 0 0

ICKE SCON3[6] Clear to not drive active ICK onto SICK pin. 0 0

SIOLB SCON10[8] Clear to disable loopback. 0 0

OCKK SCON10[7] Clear to driv e output data on risi ng edge of output bit clock . 0 X

OCKA SCON10[6] Clear to select passive OCK. Set to se lect act ive OCK . 0 1

OFSK SCON10[5] Set to invert OFS (active-low frame sync). 1 X

OFSA SCON10[4] Clear to select passive OFS. Set to select active OFS. 0 1

ICKK SCON10[3] Clear to captur e input data on falling edge of input bit clock. 0 X

ICKA SCON10[2] Clear to se le ct passive IC K . Set to sele ct act ive ICK. 0 1

IFSK SCON10[1] Set to invert IFS. 1 1

IFSA SCON10[0] Clear to select passive IFS. Set to select active IFS. 0 1

AGCKLIM[7:0] SCON11[7:0] Active bit clock divide ratio. X 1

(ICK and OCK

are SCK/ 2)

AGRESET SCON12[15] Clear to activate active clo ck and frame sync generator. 0 0

AGSYNC SCON12[14] Set to synchronize acti ve generated bi t cl ocks to SIFS pin. 0 1

SCKK SCON12[13] Set to invert SCK. Clear if AGEXT is clea red. 0 1

AGEXT SCON12[12] Clear t o select CLK as s ource f or acti ve clo ck and fr ame sync

generator . Set to selec t SCK as source for active clock and

frame sync generator.

AGFSLIM[10:0] SCON12[10:0] Active frame sync divide ratio. X 0x3FF

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.14 SIU Examples (continued)

4.16.14.2 ST-Bus Interface (continued)

Table 101 descri bes the SIU control registers and control register fields that must be configured as required by the

particular system applicat ion using an ST-bus interface.

Table 101. Control Register and Fields That Are Configured as Required for ST-Bus Interface

Contr ol Regist er or

Field Description

OMSB SCON0[10] Selects LSB- or MSB-f irst output data.

OFORMAT[1:0] SCON0[9:8] Selects li near, µ-law, or A-law output format.

IMSB SCON0[2] Sele cts LSB- or MSB-first input data.

IFORMAT[1:0] SCON0[1:0] Selects linear, µ-law, or A-law input format.

IFRAME SCON1[7] Clear to select input channel mode. Set to sel ect input fram e mo de.

IFLIM[6:0] SCON1[6: 0] Program to 127 for 128 channels per input frame.

OFRAME SCON2[7] Clear to sel ect output channel mode. Set to select outp ut frame mode.

OFLIM[6:0] SCON2[6: 0] Program to 127 f or 128 channels per output frame.

OSFIDV_O SCON3[13] Set to enabl e odd output subfram es.

OSFID_O[1:0] SCON3[12:11] Selects odd output subfram e 1, 3, 5, or 7.

OSFIDV_E SCON3[10] Set to enable even output subframes.

OSFID_E[1:0] SCON3[9:8] Select s even output subframe 0, 2, 4, or 6.

ISFIDV_O SCON3[5] Set to enable odd inp ut subframes.

ISFID_O[1:0] SCON3[4:3] S elects odd i n put subfr a m e 1, 3, 5, or 7.

ISFIDV_E SCON3[2] Set to enable even input subframes.

ISFID_E[1:0] SCON3[1:0] Sele cts even in put subfr am e 0, 2, 4, or 6.

ISFVEC_E[15:0] SCON4[15:0] Set to enable corresponding channel of the selected even input subframe.

ISFVEC_O[15:0] SCON5[15:0] Set to enable corresponding channel of the selected odd input subframe.

OSFVEC_E[15:0] SCON6[15:0] Set to enable corresponding channel of the selected even output subframe.

OSFVEC_O[15:0] SCON7[15:0] Set to enable corresponding channel of the selected odd output subframe.

OSFMSK_E[15:0] SCON8[15:0] Set to mas k corresponding channel of the se lected even output subframe.

OSFMSK_O[15:0] SCON9[15:0] Set to mask corresponding channel of the selected odd output subframe.

OINTSEL[1:0] SCON10[14:13] Sel ects one of four conditions for which the SIU output interrupt (SO INT) is asserted.

IINTSEL[1:0] SCON10[12:11] Selects one of four conditions for which the SIU input int errupt (SIINT) is asserted.

ICIX0[15:0] Input channel index for the act ive even i nput subfra me—selec ts one of two DMAU SWT channels (SWT0

or SWT1 for SIU0 ; SWT2 or SWT3 for SIU1) for each logical channel in the acti ve even input subframe.

ICIX1[1 5:0] Input channel in dex for the act ive odd inp ut subfr ame—sel ects one of two DMAU SWT c hannels (SWT0

or SWT1 for SIU0 ; SWT2 or SWT3 for SIU1) for each logical channel in the acti ve odd input subframe.

OCIX0[15:0] Input channel index for the active even output subframe—s elects one of two DMAU SWT channel s

(SWT0 or SWT1 for SIU0; SWT2 or SWT3 for SIU1) for each logical channel in the active even output

subframe.

OCIX1[15:0] Input channel index for the active odd output subframe—se lects one of two DMAU SWT channel s

(SWT0 or SWT1 for SIU0; SWT2 or SWT3 for SIU1) for each logical channel in the acti ve odd output

subframe.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.14 SIU Examples (continued)

4.16.14.2 ST-Bus Interface (continued)

Figure 52 illustrates ST-bus operation with a single-rate clock.

ST-Bus Single Rate Clock

Fi gure 5 2. ST-Bus Sin gle- Rate C lock

Figure 53 illustrates ST-bus operation with a double-rate clock a pplie d to SCK, with an acti ve mode bit clock and

output frame sync generat ion for internal use only. In addition , this figure assumes the use of SIFS for external

clock sy nchr onizati on (AGSYNC = 1) of both the i nput and o utput bi t clocks. ICK, OCK, IFS, and OFS are t he inte r-

nally generated bit clocks and frame sync s. Ref er to Figure 40 on page 155 to rev i ew the block diagram of the

internal clock generator.

ST- Bus Double Rate Clock

Figure 53. ST-Bus Double-Rate Clock

S〈IO〉CK

S〈IO〉FS

SID B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2

SOD B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2

ICK

OCK

SID

IFS

B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2

SOD B0 B1 B2 B3 B4 B5 B6 B7BN – 1BN – 2

SCK

ICK

OCK

OFS

SIFS

CAPTURE

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers

Each SIU contains 21 contro l, status, and data regis-

ters as summarized in Table 102. These can be func-

tionally grouped as:



Thirteen control registers (SCON〈0—12〉)



Two status registers (STAT and FSTAT)



One read-only input data register (SIDR)



One write-only output register (SODR)



Two input channel index registers (ICIX〈0—1〉)



Two output chann el index registers (OCIX〈0—1〉)

All of these 16-bit registers are aligned on even

addres ses in DSP16411 shared I/O memo ry space.

The rema inder of this section provides detail on each

of these registers.

Table 102 summariz e s al l t h e SIU me mory-map ped

registers. Tables 103 through 121 describe each regis-

ter individually.

Table 102. SIU Registers

Name Address Description Size

(Bits)†R/W Type‡Reset

Value

SIU0 SIU1

SCON0 0x43000 0x44000 SIU Input/Output General Control 16 R/ W control 0x0000

SCON1 0x43002 0x44002 SIU Input Frame Contr ol 0x0400

SCON2 0x43004 0x44004 SIU Output Fram e Contr ol 0x0400

SCON3 0x43006 0x44006 SIU Input/Output Subframe Cont rol 0x0000

SCON4 0x43008 0x44008 SIU Input Even Subfr am e Valid Vector Control 0x0000

SCON5 0x4300A 0x4400A SIU In put Odd Subframe Valid Vecto r Control 0x0000

SCON6 0x4300C 0x4400C SIU Output Even Subframe Valid Vector Control 0x0000

SCON7 0x4300E 0x4400E SIU Output Odd Subframe Valid Vector Control 0x0000

SCON8 0x43010 0x44010 SIU Output Even Subframe Mas k Vector Control 0x0000

SCON9 0x43012 0x44012 SIU Output Odd Subframe M ask Vec tor Co ntrol 0x0000

SCON10 0x43014 0x44014 SIU Input/Output Gene ral Control 0x0000

SCON11 0x43016 0x44016 SIU Input/Output Acti ve Clock Control 0x0000

SCON12 0x43018 0x44018 SIU Input/ O utput Active Fra me Sync Contr ol 0x8000

SIDR 0x4301A 0x4401A SIU Input Data 16 R data 0x0000

SODR 0x4301C 0x4401C SIU Output Data W

STAT 0x4301E 0x4401E SIU Input/ O utput General Status 16 R/W §c & s 0x0000

FSTAT 0x43020 0x44020 SIU Input/Output Frame Status 16 R status 0x0000

OCIX0 0x43030 0x44030 SIU Output Chann el I ndex for Even Subfram es 16 R/W control 0x0000

OCIX1 0x43032 0x44032 SIU Output Chann el I ndex for Odd Subframes

ICIX0 0x43040 0x44040 SIU Input Channel Index for Even Subfr am es 16 R/W cont rol 0x000 0

ICIX1 0x43042 0x44042 SIU Input Channel Index for Odd Subframes

† The SI U memory- m apped regist er sizes re prese nt bits used. T he registe rs a re right-justi fied and padded to 32 bi ts (the unused upper bits are zero-

filled).

‡ c & s mean s control and sta tu s.

§ All bits of STAT are readable, and so m e can be writ ten wit h one to clear them .

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 103. SCON0 (SIU In put/Outpu t Ge neral Control) Register

The memory address for this register is 0x43000 fo r SIU0 and 0x44000 for SIU1.

15—13 12—11 10 9—8 7—5 4—3 2 1—0

Reserved OSIZE[1:0] OMSB OFORMAT[1:0] Reserved ISIZE[1:0] IMSB IFORMAT[1:0]

Bit Field Value Descri ption R/W Reset Value

15—13 Reserved 0 Reserved—write with zero. R/W 0

12—11 OSIZE[1:0]†0 The channel size for serial output dat a is 8 bits‡.R/W0

1 The channel size for serial output dat a is 16 bit s.

2 The channel size for serial output dat a is 4 bits ‡.

3 The channel size for serial output dat a is 12 bit s‡.

10 OMSB†0 Shift data out ont o SO D pin least signif icant bit (LSB) fir st. R/W 0

1 Shift data out onto SOD pin most significant bit (MSB) first.

9—8 OFORMAT[1:0]†00 When trans ferring data from the SODR regi ster to the output shi ft regis-

ter, do not for mat (modify) the data. R/W 00

01 Reserved.

10 When transferring 16-bit data fr om the SODR regi ster to the output shift

lin ear PCM format to 8-bit µ-law PCM for m at, place the result int o the

lower half of the outpu t shift register, and clear the upper hal f. Ignore the

least sig n ificant 2 bits of SODR.

11 When transferring 16-bit data fr om the SODR regi ster to the output shift

lin ear PCM format to 8-bit A-law PCM for ma t, place the r esult into the

lower half of the outpu t shift register, and clear the upper hal f. Ignore the

least sig n ificant 3 bits of SODR.

7—5 Reserved 0 Reserved—write with zero. R/W 0

4—3 ISIZE[1:0]§0 The ch annel size for serial input data is 8 bits††.R/W0

1 The channel size for serial input dat a is 16 bit s.

2 The channel size for serial input dat a is 4 bits††.

3 The channel size for serial input dat a is 12 bit s††.

2IMSB

§0 Capture input data from SID pin least sig nif icant bit (LSB) fi rst. R/W 0

1 Capture input data from SID pin most significant bit (MSB) first.

1—0 IFORMAT[1:0]§00 When t ransf erri ng 16-bi t d ata fr om the SIB‡‡ regist er to t he SIDR re gis ter ,

do not for m at (modify) the dat a. R/W 00

01 Reserved.

10 When transferring data from the SIB‡‡ register to the SIDR reg ister, con-

vert the lower 8 bits of SIB (SIB[7:0]) from µ-la w PCM format to 14-bit lin-

ear PCM format, place the result into the 14 most significant bits of SIDR

(SIDR[15:2]), and clea r the least significant 2 bits of SIDR (SIDR[1:0]).

11 When transferring data from the SIB‡‡ register to the SIDR reg ister, con-

vert the lower 8 bi ts of SIB (SIB[7:0]) from A-law PC M form a t to 1 3 -b it lin-

ear PCM format, place the result into the 13 most significant bits of SIDR

(SIDR[15:3]), and clea r the least significant 3 bits of SIDR (SIDR[2:0]).

† If the ORESET field (SCON2[10]) is cleared, do not change the value in this field.

‡ T he SIU shifts data from the low po rtion of the out put sh ift register onto the SOD pin and ignores the high por tion of the reg ister.

§ If the IRESET field (SCON1[10]) is cleared, do not change the value in this field.

†† The SIU right justifies the received serial input data, i.e., it places the data in the least significant bit positions of the 16-bi t serial input buffer

‡‡ The SIB register is an intermediate register that holds the contents of the input shift register and is not user accessible.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 104. SCON 1 (SIU Input Frame Contr ol) Register

The memory address for this register is 0x43002 fo r SIU0 and 0x44002 for SIU1.

15—12 11 10 9—8 7 6—0

Reserved I2XDLY IRESET IFSDLY[1:0] IFRAME IFLIM[6:0]

Bit Field Value Description R/W Reset

Value

15—12 Reserved 0 Reserved—write with zero. R/W 0

11 I2XDLY†0 Do not st retch the active generated input bit clock (ICK) rela tive to the acti ve-

mod e generated outpu t bi t clock (OCK), i.e ., ICK and OCK are identical and i n-

phase.

R/W 0

1 Stretch the high phase of the acti ve generated i nput cloc k (ICK) by one SCK

phase relative to the act ive generated output bit clock (OCK) to provi de addi-

tional input ser ial data capture time .

10 IRESET 0 Activate input section and begin input processing at the start of the firs t act ive

input channel. R/W 1

1 Deactivate input sect ion and ini tialize bi t and frame counters.

9—8 IFSDLY[1:0]†00 No input frame sync del ay—capture in put data from SID pi n star ting with the

sam e intern al bit clock ( ICK) that latches the inp ut frame sync ( SIFS pin for pas-

sive sync or IFS signal for active generated sync).

R/W 00

01 One -cycl e input frame syn c del ay—cap ture i nput dat a from SI D pin sta rtin g one

bit clo ck (ICK) after the bit clock that lat ches the input frame sync (SIFS pin for

passive sync or IF S signal for active generated sync).

10 Two-cycl e input frame sync delay—capture input dat a from SID pin star ting two

bit clocks ( ICK) after t he bit cl ock that latches the in put frame sy nc (SIFS pin for

passive sync or IF S signal for active generated sync).

11 Reserved.

7IFRAME

†0Channel mode—base the input tr ansfer decision on the ISFIDV_E field

(SCON3[2]), the ISFVEC_E[15:0] field (SCON4[15:0]), the ISFIDV_O field

(SCON3[5]), and the ISFVEC_O[15: 0] field (SCON5[15:0]).

R/W 0

1 Frame m ode—capture all IFLIM + 1 channels in the fr am e.

6—0 IFLIM[6:0]†0—127 Input frame chann el count limit—the number of chann els in the input frame is

IFLIM + 1. R/W 0

† If the IR ESET f i el d (SCON1[10]) is cleared , do not chang e the va l ue i n this field.

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 105 . SCON2 (SIU Output Frame Control) Register

The memory address for this register is 0x43004 fo r SIU0 and 0x44004 for SIU1.

15—11 10 9—8 7 6—0

Reserved ORESET OFSDLY[1:0] OFRAME OFLIM[6:0]

Bit Field Value Description R/W Reset

Value

15—11 Reserved 0 Reser ved— wri te with zero. R/W 0

10 ORESET 0 Activ ate outp ut sect ion, reques t output ser vice from t he DMAU, an d drive SOD

pin at the start of the first active output channel . R/W 1

1 Deactivate output section and i nit ialize bit and fram e counters.

9—8 OFSDLY[1:0]†00 No outp ut fr am e sync delay—drive out put data ont o SO D pin st arting with the

same internal bit c lock (OCK) that latches the out put frame sync (SOFS pin for

passive sync or OFS signal for active generated sync).

R/W 00

01 One-cycle output fram e sync delay—dr ive output data onto SOD pi n starting

one bit clock (OCK) after the bit clock that latches the output frame sync

(SOFS pin for passive sync or OFS sig nal for active generated sync).

10 Two-cycle output fram e sync delay—drive output data onto SOD pin starting

two bit clocks (OCK) after the bit clock that lat ches output frame sync (SOFS

pin for passive sync or OFS si gnal for active generated sync).

11 Reserved.

7OFRAME

†0Channel mode—base the output tran sfer decision on the OSFIDV_E field

(SCON3[10]), the OSFVEC_E[15:0] fie ld (SCON6[15:0]), the OSFIDV_O fi eld

(SCON3[13]), and the OSFVEC_O[15:0] field (SCON7[15:0]).

R/W 0

1 Fram e mode—transmit all O FLIM + 1 channels in the frame.

6—0 OFLIM[6:0]†0—127 Output frame channel count limit—the number of channels i n the output frame

is OFLIM + 1. R/W 0

† If th e ORESET field (SCON2[10]) is c le ared, do not c hange the value i n this field.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 106. SCON 3 (SIU Input/Out put Subfram e Control) Register

The memory address for this register is 0x43006 fo r SIU0 and 0x44006 for SIU1.

15 14 13 12—11 10 9—8

OFSE OCKE OSFIDV_O OSFID_O[1:0] OSFIDV_E OSFID_E[1:0]

7 6 5 4—3 2 1—0

IFSE ICKE ISFIDV_O ISFID_O[1:0] ISFIDV_E ISFID_E[1:0]

Bit Field Value Description R/W Reset

Value

15 OFSE

(acti ve mode only) 0 Do not dri ve int ernally generated frame sync onto SOFS pin. R/W 0

1 Drive internally generated frame sync onto SOFS pin.

14 OCKE

(acti ve mode only) 0 Do not dri ve int ernally generated clock onto SO CK pin. R/W 0

1 Drive internally generated clock onto SOCK pin.

13 OSFIDV_O

(channel mode only) 0 Odd output subframe vector valid. Disable odd output subframes. In frame

mode (OFRAME(SCON2[7]) = 1), thi s fi eld must be cleared. R/W 0

1 Odd output subframe vector valid. Enabl e odd output subf rames.

12—11 OSFID_O[1:0]

(channel mode only) 00 For odd sub fr am es, the out put subframe ID of the subframe under

control of the OSFVEC_ O [15: 0] fi eld (SCON7[15:0]) and the

OSFMSK_O[15:0] field ( SCON9[15:0]) is:

2 × OSFID_O + 1

as shown at right.

1R/W00

01 3

10 5

11 7

10 OSFIDV_E

(channel mode only) 0 Even output subframe vector valid. Disable even output subfram es. In

fram e mode (OFRAME(SCON2[7]) = 1), this field must be cl eared. R/W 0

1 Even output subframe vector valid. Enabl e even output subframes.

9—8 OSFID_E[1:0]

(channel mode only) 00 For even subframes, the output subframe ID of the subframe under

control of the OSFVEC_ E[15:0] fiel d (SCON6[15:0]) and the

OSFMSK_E[15:0] field (SCON8[15:0]) is:

2 × OSFID_E

as shown at right.

0R/W00

01 2

10 4

11 6

7IFSE

(acti ve mode only) 0 Do not dri ve int ernally generated frame sync onto SIFS pin. R/W 0

1 Active m ode only. Drive int ernally generated frame sync onto SI FS pin.

6ICKE

(acti ve mode only) 0 Do not dri ve int ernally generated clock onto SICK pi n. R/W 0

1 Active m ode only. Drive int ernally generated clock onto SICK pi n.

5 ISFIDV_O

(channel mode only) 0 Odd input subframe vector valid. Di sable odd input subframes. In frame

mode (OFRAME(SCON2[7]) = 1), thi s fi eld must be cleared. R/W 0

1 Odd input subframe vector valid. Enable odd input subfr am e s.

4—3 ISFID_O[1:0]

(channel mode only) 00 For odd subframes, the input subfram e ID of th e subframe under con-

trol of the ISFVEC_O[15:0] field (SCON5[15:0]) is:

2 × ISFID_O + 1

as shown at right.

1R/W00

01 3

10 5

11 7

2 ISFIDV_E

(channel mode only) 0 Even input subframe vect or vali d. Di sable even input subframes. In frame

mode (OFRAME(SCON2[7]) = 1), thi s fi eld must be cleared. R/W 0

1 Even input subfram e vector valid. Enable even input subfram es.

1—0 ISFID_E[1:0]

(channel mode only) 00 For even subfr am es, the input subframe ID of the subfr am e under

control of the ISFVEC_E[15:0] field (SCON4[15:0]) is:

2 × ISFID_E

as shown at right.

0R/W00

01 2

10 4

11 6

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 107 . SCON4 (SIU Input Even Subfram e Valid Vector Control) Register

Tab le 10 8. SC ON 5 (SI U Input Od d Subfram e Valid Vect or Cont ro l) R egi s ter

The memory address for this register is 0x43008 fo r SIU0 and 0x44008 for SIU1.

15—0

ISFVEC_E[15:0]

Bit Field Value Description R/W Reset

Value

15—0 ISFVEC_E[15:0] 0 The corresponding channel of the selected even input subframe is disabled. R/W 0

1 The corresponding channel of the selected even input subfr ame is enabled.

The memory address for this register is 0x4300A for SIU0 and 0x4400A for SIU1.

15—0

ISFVEC_O[15:0]

Bit Field Value Description R/W Reset

Value

15—0 IS FVEC_O[15:0] 0 The corre sponding channel of t he selected odd input subfr am e is disa bled. R/W 0

1 The corre sponding channel of the selected odd input subframe is enabl ed.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 109. SCO N6 (SIU Outp ut Ev en Subfra me Valid Vector Contro l) Register

Table 110. SCON7 (SIU Output Odd Subframe Valid Vector Control) Register

Table 111. SCON8 (SIU Output Even Subframe Mask Vector Control) Register

Table 112. SCON9 (SIU Output Odd Subframe Mask Vector Control) Register

The memory address for this register is 0x4300C for SIU0 and 0x4400C for SIU1.

15—0

OSFVEC_E[15:0]

Bit Field Value Description R/W Reset

Value

15—0 OSFVEC_E[15:0] 0 The corr esponding channel of the selected even output subframe is disabl ed. R/W 0

1 The corr esponding chann el of the selected even outp ut subframe is ena bled.

The memory address for this register is 0x4300E for SIU0 and 0x4400E for SIU1.

15—0

OSFVEC_O[15:0]

Bit Field Value Description R/W Reset

Value

15—0 OSFVEC_O[15:0] 0 The corresponding channel of the selected odd output subframe is disabled. R/W 0

1 The corresponding channel of the selected odd output subfr ame is enabled.

The memory address for this register is 0x43010 fo r SIU0 and 0x44010 for SIU1.

15—0

OSFMSK_E[15:0]

Bit Field Value Description R/W Reset

Value

15—0 OSFMSK_E[ 15:0] 0 Do not mask th e corr esponding output channel. R/W 0

1 For an acti ve even subframe, mask the corresponding output channel (do

not driv e SOD during the out put ti me slot).

The memory address for this register is 0x43012 fo r SIU0 and 0x44012 for SIU1.

15—0

OSFMSK_O[15:0]

Bit Field Value Description R/W Reset

Value

15—0 OSFMSK_O[15:0] 0 Do not mask the correspondi ng output channel. R/W 0

1 For an active odd subframe, mask the corresponding output channel (do

not dri ve SOD during t he output time slot).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 113. SCO N10 (SIU Input/Ou tput General Contr ol) Register

The memory address for this register is 0x43014 fo r SIU0 and 0x44014 for SIU1.

15 14—13 12—11 10—9 8 7 6 5 4 3 2 1 0

Reserved OINTSEL[1:0] IINTSEL[1:0] Reserved SIOLB OCKK OCKA OFSK OFSA ICKK ICKA IFSK IFSA

Bit Field Value Description R/W Reset

Value

15 Reserved 0 Reserved—write with zero. R/W 0

14—13 OINTSEL[ 1:0] 00 Assert output interr upt (SOINT) aft er out put frame sync detected. R/W 00

01 Assert output interrupt (SOINT) after output subframe transfer complete.

10 Assert outpu t i nterrupt (SOINT) aft er output channe l transfer complete.

11 Assert out put interrupt (SOI NT) after output fram e error or output un derflow error

occurs†.

12—11 IINTSEL[1:0] 00 Assert input interrupt (SIINT) after input frame sync detected. R/W 00

01 Assert input interrupt (SIINT) after input subframe transfer com plete.

10 Assert inpu t in terrupt (SII NT) after input channel transf er complete.

11 Assert input interrupt (SIINT) after input frame error or input overflow error

occurs†.

10—9 Reserved 0 Reserved—write with zero. R/W 0

8SIOLB

‡0 Normal operation. R/W 0

1 Place SIU in loop back mode (SOD int ernally connect ed to SID, OCK internally

connected to ICK, OFS internally connected to IFS).

7OCKK

§0 Drive output data onto the SOD pin on the rising edge of the output bit clock pin

(SOCK).



If OCKA is 0 (passive clock), do not i nvert SOCK to generate the int ernal out-

put bit clock (OCK).



If OCKA is 1 (active clock), do not invert the active generated output bit clock

(OCK) before applyi ng to the SOCK pin.

R/W 0

1 Drive output data onto the SOD pin on the fal ling edge of the output bit clock pin

(SOCK).



If OCKA is 0 (passive clock), invert SOCK to g enerate the inter nal output bit

c lock (OCK).



If OCKA is 1 (act ive cloc k), invert the acti ve generated out put bit clock (OCK)

before applying to the SOCK pin.

6OCKA

§0 Passive mode output clock††—driv e the i nternal output bit clock (OCK) f rom the

external output bi t clock pin (SOCK pin mod if ied according to OCKK). The SIU

configures SOCK as an input.

R/W 0

1 Activ e mo de output clock—dr ive the interna l output bit clo ck (OCK) fro m the

active generated output bit clock derived from CLK or SCK. The SIU configures

SO CK as an ou tput.

† To determine the type of error, the program can read the contents of the STAT register (see Table 118 on page 197).

‡If the IRESET field (SCON1[10]) or ORESET fie l d (SCON2[10]) is cl eared, do not change the v al ue in this field.

§If the ORESET field (SCON2[10]) is cleared, do not c hange t he value in this field.

†† The combination of passive output bit clock (OCKA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-

sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.

§§ If the IRESET field (SCON1[ 10]) is cleared , do not change the value i n this f i el d.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

Table 113. SCON10 (SIU Input/Output General Control) Register (continued)

4.16.15 Registers (continued)

5OFSK

§0 The external output f rame sync pin (SOFS) is active-high.



If OFSA is 0 (passi ve sy nc), do not inver t SOFS to generat e the inte rnal out put

frame sync (OFS).



If OFSA is 1 (act ive sy nc) , do not i nvert the act ive gene rat ed output frame sy nc

(OFS) before applying to the SOFS pin.

R/W 0

1 The external output f rame sync pin (SOFS) is active-low.



If OFSA is 0 (passive sync), invert SOFS to generate th e internal output frame

sync (OFS).



If OFSA is 1 (act ive syn c), inver t the act ive gen erated o utpu t frame s ync (OFS)

before applying to the SOFS pin .

4OFSA

§0Passive mode output f rame sync—drive the internal output frame sync (OFS)

from the exter nal output frame sync pin (SOFS modified according to OFSK and

SCON2[OFSDLY]) . The SIU configures SOFS as an input.

R/W 0

1 Activ e mo de o utput frame syn c ††—dr ive the internal output fram e sync (OFS)

from the active generated fram e sync (AG FS) modified according to

SCON2[OFSDLY]. The SIU config ures SOFS as an output.

3ICKK

§§ 0 Capture input data from the SID pin on the falling edge of the input bit clock pi n

(SICK).



If ICKA is 0 (pass ive clo ck), do not inver t the inp ut bit cloc k pin (SI CK) to gener -

ate ICK.



If ICKA is 1 (active clock), do not invert the active generated input bit clock

(ICK) bef ore applying to the SICK pin.

R/W 0

1 Captur e input data from the SID pin on the ri sing edge of the input bit clock pi n

(SICK).



If ICKA is 0 (passive clock), invert SI CK to generate the int ernal input bit clock

(ICK).



If ICKA is 1 (acti ve clock), invert the acti ve generated in put bi t clock (ICK)

before applying to the SICK pin.

2ICKA

§§ 0 Passive mode input bit clock††—drive the internal input bit clock (I CK) from the

external input bi t cl ock pin (SICK pin modified accor ding to ICKK). The SIU con-

figures SICK as an input.

R/W 0

1 Activ e mode inp ut b it clock —dri ve the i ntern al input b it clock (I CK) fr om the act ive

generated input bit clock derived fr om CLK or SCK. The SIU configures SICK as

an output.

Bit Field Value Description R/W Reset

Value

† To determine the type of error, the program can read the contents of the STAT register (see Table 118 on page 197).

‡If the IRESET field (SCON1[10 ]) or ORESET fie ld (SCON2[ 10]) is cleared, do not c hange t he value in this field.

§If the ORESET field (SCON2[10]) is cleared, do not c hange t he value in this field.

†† The combination of passive output bit clock (OCKA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-

sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.

§§ If the IRESET field (SCON1[10] ) i s cleared , do not change the va lu e i n this f i el d.

Advance Data Sheet

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any instructions

4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

Table 113. SCON10 (SIU Input/Output General Control) Register (continued)

4.16.15 Registers (continued)

1IFSK

§§ 0 The exter nal inpu t fr am e sync pin (SI F S) is active-hig h.



If IFSA is 0 (passive sync) , do not invert SIFS to generat e the int ernal input

frame sync (I FS).



If IFSA is 1 (acti ve sync), do not invert the active generated input frame sync

(IFS) before apply ing to the SIFS pin .

R/W 0

1 The exter nal inpu t fr am e sync pin (SI F S) is active-low.



If IFSA is 0 (passive sync) , in vert the input fr ame sync pin (SIFS) to generate

the internal in put frame sync (IFS).



If IFSA is 1 (acti ve sync), invert th e acti ve generated input frame sync (IFS)

before applying to the SIF S pin.

0IFSA

§§ 0Passive mode input f rame sync—drive the internal input fram e sync (IFS) from

the external input frame sync pin (SIF S) modified according to IFSK and

SCON1[IFSDLY] . The SI U confi gures SIFS as an input.

R/W 0

1 Active mode input frame sync††— drive the internal input frame sync (IFS) from

the active generated frame sync ( AGFS) modified according to

SCON1[IFSDLY]. If SCON12[AGSYNC] is cleared, the SIU configures SIFS as

an output. If SCON12[AGSYNC] is set, the SIU conf igures SIFS as an input for

the purpose of synchronizing the active generated bit clocks.

Bit Field Value Description R/W Reset

Value

† To determine the type of error, the program can read the contents of the STAT register (see Table 118 on page 197).

‡If the IRESET field (SCON1[10]) or ORESET fie l d (SCON2[10]) is cl eared, do not change the v al ue in this field.

§If the ORESET field (SCON2[10]) is cleared, do not c hange t he value in this field.

†† The combination of passive output bit clock (OCKA = 0) and active output frame sync (OFSA = 1) is not supported. The combination of pas-

sive input bit clock (ICKA = 0) and active input frame sync (IFSA = 1) is not supported.

§§ If the IRESET field (SCON1[ 10]) is cleared , do not change the value i n this f i el d.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 114. SCON11 (SIU Input/Output Active Clock Control) Register

The memory address for this register is 0x43016 fo r SIU0 and 0x44016 for SIU1.

15—8 7—0

Reserved AGCKLIM[7:0]

Bit Field Value Description R/W Reset

Value

15—8 Reserved 0 Reserved—write with zero. R/W 0

7—0 AGCKLIM[7:0]†0—255 Active cloc k divide ratio—controls the per iod and duty cycle of the active g ener-

ated input and output bit clo cks (ICK and OCK). R/W 0

The period of ICK and OCK (TAGCK) is the following:

TAGCK = TCKAG × (max(1, AGCKL IM[7:0]) + 1)

where TCKAG is the period of t he clock source‡ fo r ICK an d O C K.

The high and lo w times of ICK and OCK ( TAGCKH and TAGCKL) are as follows:

TAGCKH = T CKAG × int( (max(1, AGCKLIM[7 :0] ) + 2) ÷2)

TAGCKL = TCKAG × i nt( (max(1, AGCKLIM[7:0]) + 1) ÷2)

where T CKAG is the period of t he clock source‡ for ICK and OCK and int( ) is the

integer function (truncation).

The following table illustrates examples:

† If the IR ESET f i el d (SCON1[10]) or ORESET field (SCON2[10] ) i s cleared, do not c hange t he value in this fie l d.

‡ The clock source is selected by SCON12[AGEXT] as either the SCK pin (modified by SCON12[S CKK]) or t he proc esso r cl ock , CLK.

Bit Clock

Period High Time Low Time

AGCKLIM[7:0] TAGCK TAGCKH TAGCKL

0 or 1 2 × TCKAG 1 × TCKAG 1 × TCKAG

23 × TCKAG 2 × TCKAG 1 × TCKAG

34 × TCKAG 2 × TCKAG 2 × TCKAG

45 × TCKAG 3 × TCKAG 2 × TCKAG

56 × TCKAG 3 × TCKAG 3 × TCKAG

67 × TCKAG 4 × TCKAG 3 × TCKAG

254 255 × TCKAG 128 × TCKAG 127 × TCKAG

255 256 × TCKAG 128 × TCKAG 128 × TCKAG

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 115. SCON 12 (SIU Input/Ou tput Active Frame Sync Contro l) Register

The memory address for this register is 0x43018 fo r SIU0 and 0x44018 for SIU1.

15 14 13 12 11 10—0

AGRESET AGSYNC SCKK AGEXT Reserved AGFSLIM[10:0]

Bit Field Value Description R/W Reset

Value

15 AGRESET†0 Act ivate the active clock and frame sync generator. R/W 1

1 Deactivate the active clock and fram e sync gener ator.

14 AGSYNC†0 Do not synchronize the active generated input and out put bit clocks to an

external source. R/W 0

1 Configure the external input fr am e sync (SIFS) pin as an input and synchro-

nize the active generated input and output bit clocks to SIFS.

13 SCKK†0 Do not inver t the SCK pin before appl ying it to the active cl ock generat or, i.e.,

if SCK is selected as the active clo ck source‡, the rising edge of the active

generated input and output bit clo cks is generat ed by the ri sing edge of SCK.

R/W 0

1 Invert the SCK pin before applying it to the active c lock generator, i .e., if SCK

is s el ected a s t he act ive c loc k s ource‡, t he ri sing edge of t he activ e genera ted

input and outp ut bit clocks is generated by the fall ing edge of SCK.

Caution: Set this bi t only if AGEXT is also set .

12 AGEXT†0 The processor clock (CLK) is the clock source for the active clock and frame

sync generator. R/W 0

1 The SCK pin (modified accordi ng to SCKK) is the cl ock source for the active

clock and frame sync generator.

11 Reserved 0 Reserved—write with zero. R/W 0

10—0 AGFSLIM[10:0]†0—2047 Acti ve frame sync di vide ratio— controls the peri od and du ty cycle of the

active generated frame syncs (IFS and OFS) . R/W 0

The period of IFS and OFS (TAGFS) is the following:

TAGFS = T AGCK × (max(1, AGFSLIM[10:0]) + 1)

where TAGCK is the peri od of the clock sou rce § for IFS and OFS.

The high and l ow ti me s of IF S and OFS (TAGFSH and T AGFSL) are as f ollows:

TAGFSH = TAGCK × int((max(1, AGFSLIM[10:0]) + 1) ÷2)

TAGFSL = T AGCK × int((max(1, AGFSL IM[10:0]) + 2) ÷2)

where TAGCK is the peri od of the clock sou rce § for IFS and OFS and int( ) is

the int eger function (truncati on).

The foll owing table il lustrates examples:

† If the IR ESET f i el d (SCON1[10]) or ORESET field (SCON2[10] ) i s cleared, do not change the val ue in this field.

‡ SCK is selecte d as the clock source for the ac tive clock generat or i f AGEX T i s 1.

§ The cl ock source is the act i ve gener ated bit cl ock with per i od TAGCK.

Frame Sync

Period High Time Low Time

AGFSLIM[10:0] TAGFS TAGFSH TAGFSL

15 16 × T AGCK 8 × TAGCK 8 × TAGCK

16 17 × T AGCK 8 × TAGCK 9 × TAGCK

2047 2048 × TAGCK 1024 × TAGCK 1024 × TAGCK

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 116. SIDR (SIU I nput Data) Register

Table 117. SODR (SIU Output Data) Register

The memory address for this register is 0x4301A for SIU0 and 0x4401A for SIU1.

15—0

Serial Input Data

Bit Field Description R/W Reset Value

15—0 Serial Input Data Read-only 16-bi t serial i nput data. The SIU can opti onall y expand the

data in the input shift register before latchi ng it into SIDR. The user

program controls thi s optional expansion by configuring the IFOR-

MAT[ 1:0] field ( SCON0[1:0]—Table 103 on page 185).

The memory address for this register is 0x4301C for SIU0 and 0x4401C for SIU1.

15—0

Serial Output Data

Bit Field Description R/W Reset Value

15—0 Serial Output Data W rite-only 16- bit serial output data. The SIU optional ly compresses

the data in SODR before lat ching it into the output shift register. The

user program controls this opti onal compression by conf iguring the

OFORMAT[ 1:0] field (SCON0[9:8]—Table 103 on page 185 ).

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 118. STAT (SIU Input/Output General Status) Regis ter

Table 119. FSTAT (SIU Input/Output Frame Status) Register

The memory address for this register is 0x4301E for SIU0 and 0x4401E for SIU1.

15—8 76543210

Reserved OUFLOW IOFLOW OFERR IFERR SODV Reserved SIBV SIDV

Bit Field Value Description R/W Reset

Value

15—8 Reserved 0 Reserved— write with zero. R/W 0

7OUFLOW

†0 Output underflow error has not occurred. R/Clear 0

1 Output underflow error has occurred.

6IOFLOW

†0 Input overflow error has not occurred. R/Clear 0

1 Input overflow error has occurred.

5OFERR

†0 Output fra me error has not occurred. R/Cl ear 0

1 Output fra me error has occurred.

4IFERR

†0 Input fr am e err or has not occurred. R/Cl ear 0

1 Input fr am e err or has occurred.

3SODV0SODR does not contain valid dat a. R 0

1SODR contains valid data.

2 Reserved 0 Reserved— write with zero. R/W 0

1SIBV0SIB‡ does not cont ain valid data. R 0

1SIB‡ contains valid data.

0SIDV0SIDR does not contai n valid data. R 0

1SIDR contains vali d data.

† The pr ogramm er clears th i s bit by wri ting i t wi th 1. Wri ting 0 to thi s bit leaves it unchanged .

‡ The SIB regist er is an i nt erm edia t e regi st er tha t holds the conte nts of t he i nput shif t regi st er and is not user acc ess ib l e.

The memory address for this register is 0x43020 fo r SIU0 and 0x44020 for SIU1.

15 14—8 7 6—0

OACTIVE OFIX[6:0] IACTIVE IFIX[6:0]

Bit Field Value Description R/W Reset

Value

15 OACTIVE 0 No output channel s have been processed. R 0

1 At least one output channel has been processed following output section reset

(ORESET(SCON2[10]) = 0). (Distinguishes the first (index 0) and last (index

×8) output subframes.)

14—8 OFIX[6:0] 0—127 Channel index of the next enabled output channel. R 0

7 IACTIVE 0 No in put channels have been proc essed. R 0

1 At least one input channel has been processed followi ng input sect ion reset

(IRESET(SCON1[10]) = 0). (Distinguishes the first (index 0) and l ast (i ndex

×8) input subframes.)

6—0 IFIX[ 6:0] 0—127 Current in put channel index. R 0

Advance Data Sheet

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 120. OCI X〈0—1〉 and ICIX〈0—1〉 (SIU Ou tput and Input Channel Index) Registers

Table 121. OCI X〈0—1〉 (S IU Output Channe l Index) Registers

SIU0 SIU1

OCIX0 0x43030 0x44030 Output channel index for t he active even subframe . Table 121

OCIX1 0x43032 0x44032 Output channel index for t he active odd subframe. Table 121

ICIX0 0x43040 0x44040 Input channel index for the active even subframe. Table 122 on page 199

ICIX1 0x43042 0x44042 Input channel index for the active odd subframe. Tabl e 122 on page 199

See Table 120 for the memory addresses of these registers.

1514131211109876543210

Channel Mode

(Each bit is m apped

to a logical channel

in the active sub-

frame.)

OCIX0 Subframe 01514131211109876543210

Subframe 247464544434241403938373635343332

Subframe 479787776757473727170696867666564

Subfram e 6 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

OCIX1 Subframe 131302928272625242322212019181716

Subframe 363626160595857565554535251504948

Subframe 595949392919089888786858483828180

Subfram e 7 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112

1514131211109876543210

Frame Mo de †

(Each bi t i s circ ularl y

map ped to four logi-

cal channels. )

OCIX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64

111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

OCIX1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80

127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112

Bit Value Description

(SIU0) Description

(SIU1) R/W Reset

Value

15—0 0 Use DMAU channel SWT0 for output to the

logi cal channel shown above. Use DMAU channel SWT2 for output to the

logi cal channel sho w n above. R/W 0

1 Use DMAU channel SWT1 for output to the

logi cal channel shown above. Use DMAU channel SWT3 for output to the

logi cal channel sho w n above.

† If the number of logi cal channe l s per fr am e is one (OF LI M[6:0] ( SCON2[6:0]) = 0) in frame m ode, bi ts 1 and 0 of OCIX0 (OCIX0[1:0]) must be pro-

gram med wi th the same value.

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

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4 Hardware Architecture (continued)

4.16 Serial Interface Unit (SIU) (continued)

4.16.15 Registers (continued)

Table 122 . ICIX〈0—1〉 (SIU Input Channel Index) Registers

See Ta ble 120 on page 198 for the memory addresses of these registers.

1514131211109876543210

Channel Mode

(Each bit is m apped

to a logical channel

in the active sub-

frame.)

ICIX0 Subframe 01514131211109876543210

Subframe 247464544434241403938373635343332

Subframe 479787776757473727170696867666564

Subfram e 6 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

ICIX1 Subframe 131302928272625242322212019181716

Subframe 363626160595857565554535251504948

Subframe 595949392919089888786858483828180

Subfram e 7 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112

1514131211109876543210

Frame Mo de †

(Each bi t i s circ ularl y

mapp ed to four logi-

cal channels. )

ICIX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64

111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96

ICIX1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80

127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112

Bit Value Description

(SIU0) Description

(SIU1) R/W Reset

Value

15—0 0 Use DM AU channel SWT0 f or input from th e

logi cal channel shown above. Use DMAU channel SWT2 for in put fr om the

logi cal channel sho w n above. R/W 0

1 Us e DMAU channe l SWT1 for i nput from the

logi cal channel shown above. Use DMAU channel SWT3 for in put fr om the

logi cal channel sho w n above.

† If the number of logical channels per frame is one (IFLIM[6:0](SCON1[6:0]) = 0) in frame mode, bit s 1 and 0 of ICIX0 (ICIX0[1:0]) m ust be pro g ramm e d

with the same value.

Advance Data Sheet

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4 Hardware Architecture (continued)

4.17 Internal Clock Selection

The DSP1641 1 i nternal clock can be driven from one of

two sources. The primary source clock is an on-chip

programmable clock synthesizer that can be driven by

an external clock input pin (CKI) at a fraction of the

required instruction rate. The clock synthesizer is

based on a phase-lock loop (PLL ). The terms clock

synthesizer and PLL are used interchan geably.

Section 4.18, beginning on page 201, describes the

PLL and its associated pllcon, pl l frq , pllf rq1, and

plldly registers in detail.

Note: Int ernal clock functions for the DSP16411 are

controlled by CORE0 because the registers

pllcon, pll frq, pllfrq1, and plldly are only avail-

able to programs executing in CORE0.

Figure 54 illustr at es th e inte rna l cl ock sele cti o n log i c

that selects the internal clock (CLK) from one of the fol-

lowi ng two source clocks:



CKI: This pin is dri ven by an ext ernal oscillator or the

pin’s associated boundary-s can logic under JTAG

control. If CKI is selected as the source clock, CLK

has the frequency and duty cycle of CKI. T he

DSP16411 consumes less power if clocked with CKI.



PLL: The PLL generates a source clock with a pro-

grammable frequency. If the PLL is selected as the

source clock, fCLK ha s the frequency and duty cycle

of the PLL output fSYN.

After device reset, the default source clock signal is

CKI.

The program me r can select the PLL as the source

clock by setting the PLLSE L field (pllcon[0]—see

Table 124 on page 202). Before selecting the PLL as

the clock source, the user program must first enable

(power up) the PLL by setting the PLLEN field

(pllcon[1]), and then wait for the P LL to lock. See

Sect ion 4.18, beginning on page 201, fo r details.

Table 123 summarizes the selection of the two source

clocks as a function of the PLLSEL field.

Table 123. Source Clock Selection

Internal Clock Selection Logic

† The multiplexer is designed so that no partial clocks or glitching occurs.

Figure 54. Internal Clock Selection Logic

PLLSEL

(pllcon[0]) fCLK Description

CKI CKI pin

SYN PLL

fCKI

CKI fCKI

fCLK

fSYN

PLLSEL

PLLEN

PLL

SYNC

MUX†

CLOCK SELECTION LOGIC

CLK

(pllcon[0])

(pllcon[1])

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

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4 Hardware Architecture (continued)

4.18 Clock Synthesis

Figure 55 is a block diagram of the clock synthesizer , or

phase-lock loop (PLL). The PLL is powered by two sup-

plie s: V DD1A and VDD2A. CORE0 enables, selects,

and configures the PLL by writing to four regist ers:

pllcon, pllfrq, pllfrq1, and plldly (see Section 4.18.3

on page 202). pllcon is used to enable and select the

PLL clock synthesizer (see Section 4.17 on page 200).

pllfrq and pl lf rq1 determine the frequency multiplier of

the PLL (see Section 4.18.1 on page 201). Befo re

selecting the PLL as the clock source, the user pro-

gram must first enable (power up) th e PLL by setting

the PLLEN field (pllcon[1]) and then wait for the PLL to

lock. plldly is used for PLL LOCK flag generation (see

Section 4. 18.2 on page 201).

4.18.1 PLL Operating Frequency

The PLL-synthesized clock frequency is determined by

the fields of t he pllfrq and pllfrq1 registers. The syn-

thesized clock frequency is calculated as:

where:



M is a value in the range 4—48 and is determined by

the program ming of the M[5:0] field (pllfrq[5:0]).



N is a value in the range 0—4 and is determined by

the programmi ng of the N[3:0] field (pllfrq1[3:0]).



P is the value 0 or 1 and is dete rmin ed by the pro-

gramm ing of the P f ield (pllfrq1[8]).

Table 188 on page 275 spec ifies the timing require-

me n ts for fSYN, for the phase detector input frequency

(fPD), and for the output frequency of the voltage-con-

trolled oscillator (fVCO). The M[5:0], N[3:0], and P fields

must be programmed to values suc h that the fSYN, fPD,

and fVCO frequencies are within the required ranges

specified in Table 188. The following equations specify

fPD and fVCO:

4.18.2 PLL LO CK Flag Generati on

The DSP16 411 does not provide a PLL-generated sta-

tus flag that indicates when the PLL has locked.

Instead, a user-program mable register, plldly

(Table 127 on page 202), and an associated delay

counter is used for this purpose. If the pllcon register is

written to enable the PLL, the DSP16411 loads the

delay counter with the value in plldly. The DSP16411

decrements this counter for each subsequent cycle of

the DSP input clock (CKI). When the counter reaches

zero, the LOCK status flag is assert ed. The st ate of t he

LOCK flag can be tested by conditional instruction s

(Section 6.1.1 on page 226 ) and is also visible in the

alf register (Table 144 on page 235). The LOCK flag is

cleared on reset or by a write to the pllcon register.

The PLL requires 0.5 ms to achieve lock. The applica-

tion software should set the plldly register to a va lue

that produces a minimum delay of 0.5 ms. The register

setting needed to achieve this delay is dependent on

the frequenc y of the input clock (CKI). The pro-

gramm ed value for plldly that results in a countdown

delay of 0.5 ms is the following:

plldly = 500 x fCKI

where fCKI is the input clock frequency in MHz.

See Section 4 .18.4 on page 203 for a PLL program-

ming example that includes the use of plldly.

Figure 55. Clock Synthesizer (PLL) Block Diagram

fSYN fCKI M2+

N1+()P1+()

--------------------------------------

×=

fVCO fCKI 2M 2+()

N1+

-----------------------

×=

fPD fCKI

N1+

--------------

PLL

fCKI

N[3:0]

M[5:0]

÷2(M + 2)

÷(N + 1) PHASE

DETECTOR CHARGE

PUMP VCO

CKI

fSYN

(pllfrq1[14:11])

(pllfrq[5:0])

÷(P + 1)

(pllfrq1[8])

fPD ÷2

fVCO

(pllcon[1])

PLLEN

VDD2A

VSS2A

VDD1A

VSS1A

Advance Data Sheet

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4 Hardware Architecture (continued)

4.18 Clock Synthesis (continued)

4.18.3 PLL Registers

Table 124. pllco n (Phase-L ock Loop Contro l) Register

Table 125. pllfrq (Phase-Lo ck Loop Fr equency Control) Register

Table 126. pllfrq 1 (Phase-Lo ck Loop F requenc y Contro l 1) Register

Table 127. plldly (P hase -Lock Loop Delay Control) Register

Note: pllcon is ac c e s si ble in C OR E 0 only.

15—2 1 0

Reserved PLLEN PLLSEL

Bit Fiel d Value Description R/W Reset Value

15—2 Re served — Reserved—writ e wit h zero. R/W 0

1 PLLEN 0 Disable (power down) the PLL. R/W 0

1 Enable (pow er up) the PLL.

0 PLLSEL 0 Select the CKI input as the internal clock (CLK) source. R/W 0

1 Select the PLL as the internal clock (CLK) source.

Note: pllfrq is accessible in CORE0 only.

15—6 5—0

Reserved M[5:0]

Bit Field Value Description R/W Reset Value

15—6 Reserved — Res erved—write with zero. R/W 0

5—0 M[5:0] 4—48 Defines M, which determines t he feedback clock divider contro l setting

(2(M + 2)). The value of M must be in the range 4 ≤M≤48. R/W 0

Note: pllfrq1 is accessible in CORE0 only.

15—9 87—4 3—0

Reserved PReserved N[3:0]

Bit Field Value Descrip tion R/W Reset Value

15—9 Reserved — Reserved—write with zero. R/W 0

8 P 0—1 Defi nes P, which de termin es the VCO output divid er cont rol set ting (P + 1). (Fo r a

value of fPCK of 240 MHz or less, P must be set to 1.) R/W 0

7—4 Reserved — Reserved—write with zero. R/W 0

3—0 N[3:0] 0—4 Defines N, which determines the reference clock divider control setting (N + 1).

The value of N must be i n the range 0 ≤N≤4. R/W 0

Note: plldly is acc e s si ble in C OR E 0 only. 15—0

DLY[15:0]

Bit 15—0 Value Description R/W Reset Value

15—0 DLY[15:0] — The contents of DLY[15:0] are loaded int o the PLL delay

counter after a pllcon register write. If PLLEN

(pllcon[ 1]) i s 1 , the counter dec rement s each CKI cycl e.

When the counter reaches zero, the LOCK flag† for bot h

CORE0 and CORE1 is assert ed.

R/W 0x1388

† The state of the LOCK flag can be tested by conditional instructions (Section 6.1.1 on page 2 26) and is also visible in the alf register

(Table 144 on page 235). The LOCK flag is cleared by a device reset or a write to the pllcon register.

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4 Hardware Architecture (continued)

4.18 Clock Synthesis (continued)

4.18.4 PLL P rogrammi ng E xa m ple

The following code example illustrates the recommended PLL programming sequence. It assumes the following

parameters:



CKI = 30 MHz.



The required PLL outp ut frequency (fSYN) is 240 M Hz.



fVCO = 960 MHz.



The PL L multiplier is 8 (M = 30, N = 1, and P = 1).

As specified in Table 188 on page 275 , the ma x imum PLL lo ck t ime (tL) is 0.5 ms, or 15,00 0 CKI cycle s.

pllcon=0x0000 // Turn off the PLL

plldly=15000 // Set countdown delay = 0.5 ms (500 x 30 = 15,000)

pllfrq=0x001E // M=30

pllfrq1=0x0101 // P=1, N=1

pllcon=0x0002 // Turn on PLL

// (DSP16411 automatically loads delay counter from plldly)

4*nop // Wait for pllcon write to complete

pllwait:

if lock goto pllon // Wait for delay countdown to complete

goto pllwait

pllon:

pllcon=0x0003 // Select PLL as CLK source

4.18.5 Powering Down the PLL

Clearing the PLLEN field (pllcon[1]) powers down the PLL. Do not power down the PLL (do not clear PLLEN) if

the PLL is selected as the clock source (PLLSEL (pllcon[0]) = 1). The PLL mus t be deselected as the clock

source prior to or concurrent with powering down the PLL. See S ection 4.20, beginning on page 205, for general

information on power management.

Caution: Do not powe r down the PLL (PLLEN = 0) while it is selected as the clock source (PLLSEL = 1). If

this occurs, the device freezes because it has no clock source and cannot operate. To recover

from this condition, the RSTN, TRST0N, and TRST1N pins must be asserted to reset the device.

4.18.6 Phase-Lock Loo p (PLL) Frequency Accu racy an d Jitter

Although the average frequency of the PLL output has almost the same relative accuracy as the input clock, noise

sources within the DSP16411 produce jitter on the PLL clock. The PLL is guaranteed to have sufficiently low jitter

to operate the DSP1641 1. However , if the PLL clock is used as the clock source for external devices via the ECKO

pin, do not apply this clock to ji tter-sensitive devices. S ee Table 188 on page 275 for the input jitter requirements

for the PLL.

Note: J itter on the ECKO output clock pin does not need to be taken into account with respect to the t iming require-

ments and characteristics specified in Sec tion 11, beginning on page 274.

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4 Hardware Architecture (continued)

4.19 External Clock Selection

The ECKO pin can be programm ed using the

ECKOB[1:0] and ECKOA[1:0] fields

(ECON1[3:0]—Table 61 on page 112) to select one of

the following outputs:

1. CLK /2: The internal clock CLK divided by 2.

2. CLK /3: The internal clock CLK divided by 3.

3. CLK /4: The internal clock CLK divided by 4.

4. CLK: The internal clock CLK.

5. CKI: The buffered CKI pin.

6. ZE RO: Logic low.

Table 128 specifies the selection of the ECKO pin as a

funct ion of the E CK O B[1: 0] and ECK OA[1:0] fields

(ECON1[3:0]).

After reset, the ECKO out put pin is configured as

CLK/2 and CLK is configured as CKI. Therefore, aft er

reset, ECKO is configured as CKI/2.

The logic that controls the ECKO pin is illustrated in

Figure 56 on page 206. If the application does not

require a clock on t he ECKO pin, the user can program

ECKO as logic low during initialization to reduce power

consumption.

Note: Although ECON1 can be accessed by either

core, the programme r should selec t only one

core (such as CORE0) to control t he E CK O

pin. The programmer is responsible for develop-

ing a protocol between CORE0 and CORE 1.

Intercore coordination is not part of the

DSP16411 hardware.

Table 128. ECK O Output Clock Pin Configura tion

ECKOB[1:0] ECKOA[1:0] ECKO Pin

ECON1[3] ECON1[2] ECON1[1] ECON1[0] State Description

0000CLK/2†Frequency of CLK‡ divided by two.

0001CLK Frequency of CLK‡.

0010CKI Input clock pin.

00110 Logic zero.

0 1 X X Reserved —

1 0 X X CLK/3 Frequency of CLK‡ di vided by three .

1 1 X X CLK/4 Frequency of CLK‡ div ided by four .

† Default after reset. After reset, CLK = CKI, so ECKO = CKI/2.

‡ CLK is the internal (core) clock. See Section 4.17 on page 200 for details.

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4 Hardware Architecture (continued)

4.20 Power Management

A program running in a core can place that core into

low-power standby mode by setting the AWAIT field

(alf[15]—see Table 144 on page 235). In this mode,

the clock to t hat core and its associated TPRAM are

disabled except for the minimum core circuitry required

to process an i nc oming interrupt or trap. The clock to

the peripherals is unaffected.

F igure 56 on page 2 06 illustrates the following:



Distribution of CLK to the cores and peripherals.



Function of the AWAIT field.



Interrupts to the core used to exit low-power standby

mode.



ECK O pin selection logic (see Section 4. 19 on

page 204 for details).

If a core is in low-power standby mode, program exe-

cution in that core is suspended without loss of state. If

an interrupt that was enabled by that core occurs or if a

trap occurs, the core clears its AWAIT field, exits low-

power standby mode, resumes program execution, and

services the interrupt or trap. See Se ct i o n 4 .4.5 o n

page 30 and Section 4.4.6 on page 31 for inf ormation

on enabling interrupts.

If the DMAU accesses the TPRAM while the associ-

ated core is in standb y mode, the clock to the TP RA M

is re-enabled for that access. How ever, if the core

goes into standby mode w hile an access to a memory

component is in progress, it lock s out the DMAU from

accessing that compo nent . To prevent locking out the

DMAU, the user program must use the macro

SLEEP_ALF () in the 16411.h file. The 16411.h fi le is

included with the Agere software generation system

(SGS) t ools. Using SLEEP_ALF () guarantees that the

core completes all pending memory accesses before

entering standby mode.

SLEEP_ALF () expands to the following:

.align

goto .+1

alf=0x8000

3*nop

The DSP16 411 includes additional mechanism s for

saving power that are independent of standby mode:

1. CORE0 can temp orarily select the CK I pin as the

source clock to the cores and peripherals by clearing

the PLLS EL field (pllcon[0]—see Table 124 on

page 202). To save additional power, CORE0 can

temporarily disabl e (power down) the PLL by clear-

ing the PLLEN field (pllcon[1]).

2. CORE0 can drive the ECKO1 pin low by program-

ming the ECKO A[1:0] field (ECON1[1:0]—see

Table 61 on page 112) t o 0x 3 and the ECKOB [1:0]

field (ECON1[3 :2 ]) to 0x0.

3. E ach c ore can power down one or both of its timers

(set timer〈0,1〉c[6]) . Se e Section 4.10 on page 53

for details.

Prior to entering standby mode, CORE0 can perform

any of the above steps to save addition al power. Prior

to entering standby mode, CORE1 can direct CORE0

to perform steps 1 and 2, and CORE1 can perform

step 3 directly. (See Sec tion 4.8 on page 46 for infor-

mation on core-to-core communi c ation.)

An interrupt causes the associated core to exit standby

mode and immediat ely service the interrupt. If the pro-

gram running in CORE0 selects the CKI pin as the

source clock before entering standby mode , that clock

is selected as the source clock immed iately after the

core exits standby mode. Likewise, if the program run-

ning in CORE0 disable s the PLL before entering

standby mo de, the PLL is disabled immediate ly after

the core exits standby mode. Assuming the PLL is the

source clock for normal operation, the CORE0 program

must re-enable and then reselect the P LL af ter exiting

standby mo de in order to resume full-speed process -

ing. Only CORE 0 can control the PLL and clock selec-

tion. Therefore, if CORE1 exits standby mode and

needs to resume full-speed execution, it must direct

CORE0 to enable and reselect the PLL.

Note: If CORE0 selects the CKI pin as the source clock

before entering stan dby mode, the peripherals

also operate at the slower rate. This can result in

an increased delay for a peripheral to interrupt

the core to exit standby mode.

1. Although ECON1 can be access ed by either core, the pro gram-

mer should select only one core (such as CORE0) to control the

ECKO pin . The prog r amm er i s r es po ns ible fo r deve lo pi ng a p rot o-

col between CORE0 an d CORE1. Interc ore coordination is not

part of the DSP16411 hardware.

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4 Hardware Architecture (continued)

4.20 Power Management (continued)

Power Management and Clock Distribution

† CLK is des cri be d in Section 4.17 on page 200.

‡ The IMUX is described in Section 4.4.2, beginning on page 28.

Figure 56. Power Management and Clock Distribution

CORE0

INTERRUPT

LOGIC

CLK

CLK†

AWAIT

(alf[15])

SYNC

GATE

TPRAM0

CLOCK

ECK

ECKOB[1:0],

CLK/2

CKI

÷2

IMUX0‡

MXI[9:0]

IMUX1‡

XIO

MGIBF

SIGIN T, PTRAP

MGIBF

SIGIN T, PTRAP

SEMI

TIMER1_0

SIU0MGU0 DMAU PIU MGU1 SIU1

TIMER0_0

TIMER1_1

TIMER0_1

AWAIT

(alf[15])

SYNC

GATE

CORE1

INTERRUPT

LOGIC

CLK

TPRAM1

CLOCK

MXI[9:0]

INT[1:0]

TIME0

TIME1

TIME0

TIME1

INT[1:0]

PHINT

INT[1:0]

DMINT[5:4]

2 2

CLK/3

CLK/4

÷3

÷4

ECKOA[1:0]

(ECON1[3:0])

MUX

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4 Hardware Architecture (continued)

4.20 Power Management (continued)

Wake-up latency is the delay from the time that the core exits standby mode (due to an interrupt) to the time that

the core resume s full-speed execution. The wake-up latency i s dependent on the configuration of clocks prior to

entering standby mode, as summarized in Table 129. T he program mer must ensure that the wake-up latency is

acceptable in the application. Table 129 also illus t rate s the trade-off of wake-up latenc y vs. power consum pti on.

Disabling the PLL during low-power standby mode results in the minimum power co nsump tion and highest wake-

up latency. See Sec tion 10.3 on page 271 and S ectio n 11.2 on page 276 for details on power diss ipa tion and

wake-up latency for various operating mode s.

Table 129 . Wa ke-Up Latency and Power Con su mption for Low-P ow er S tandby Mo de

Source Clock

Selected In Standby

Mode

S tat us of PLL In

Standby Mode Wake-Up Latency L atency vs. Power Consumption Trade-Off

PLL Enabled 3 PLL cycles Minimum wake-up latency (highest power)

CKI Pin Enabled 3 CKI cycles —

Disabl ed 3 CKI cycles +

PLL lock-in time Minimum power (highest wake-up latency)

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5 Processor Boot-Up and Memory Download

The state of the EXM pin at the time of reset determines whether CORE0 and CORE1 boot from their internal boot

ROMs or from external memory, as specified in Table 130.

Table 131 sum marize s the contents of the internal boot ROMs, IROM0 and IRO M1. The content s of IROM0 and

IROM1 are identical.

If t he cores boot from their internal boot ROMs, then they execute a boot routine that is described in Section 5.1.

This routine simply waits for an external host to download code and data into the TPRAMs via the PIU. When the

download is complete, the boot routine causes each core to branch t o the first location in it s TPRAM.

If t he cores boot from EROM , then the user must place a boot routine for both cores into EROM prior to reset.

Section 5.2 on page 209 outlines a boot routine that downloads code and data into the TPRAMs via the DMAU and

then causes each core to branch to th e first location in its own TPRAM.

Note: After the deassertion of RSTN and during the execution of the boot routi ne, the clock synthesizer (PLL) is

disabled and the frequency of the internal clock (CLK) is the same as the input clock pin (CKI).

5.1 IROM Boot Routine and Host Download Via PIU

CORE0 and CORE1 boot from IROM0 and IR OM 1 if the EXM pin is low when RSTN is deasserted. The boot rou-

tine in IROM0 is identical to that in IROM1. The routine polls for the PHINT interrupt condition1 in the ins register

(Table 154 on page 242 ) to determine when the external host has completed downloading to TPRAM via the PIU.

While the cores wait for PHINT to be set, the host can download code and data to any of the memory spaces in the

Z-memory space, summarized below:



Internal me mory and I/O:

— TPRAM0

— TPRAM1

— Internal I/O (includes SLM and memory-mapped peripheral registers)



Exte rnal memory and I/O:

— EIO space

— ERAM space

— EROM space

Table 130. Core Boot-Up After Reset

State of EXM Pin

on Rising Edge of RSTN CORE0 Begins

Executing Code From CORE1 Begins

Executing Code From

EXM = 0 IROM0 (address 0x30000) IROM1 (address 0x30000)

EXM = 1 EROM (address 0x80000) EROM (address 0x80000)

Table 131. Contents of IROM0 an d IROM1 Boot ROMs

Address or Address Range Code

0x30000 Instruction : goto 0x30800 (boot routine).

0x30004—0x303FF Reserved for HDS code.

0x30800—0x308FF Boot routine.

0x30FFE— 0x30FFF Processor type: 0x00000005.

1. I nterru pts remain globally disabled during execu tion of the boot routine, and t he PHINT interrupt condition is detected by polling.

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5 Processor Boot-Up and Memory Download (continued)

5.1 IROM Boot Routine and Host Download Via PIU (continued)

The host accesses DSP164 11 memory by executing commands that cause the PIU to u se the DMAU bypass

channel for downloading. See Sect ion 4.15.5 on page 147 f or details. Wh en the host has completed the down-

load, it asserts the PHINT interrupt and sets the PHINT interrupt pending status field (ins[13]—see Table 154 on

page 242) by writing the HINT field (PCON[4]—see Table 75 on page 136). After each boot routine detects the

assertion of PHI NT, it branches to the first location of TPRAM (TPRAM0 for CORE0 and TPRAM1 for CORE1).

The boot routine is shown below:

.rsect “.rom” // Address 0x30000

goto PUPBOOT // Branch to boot routine.

// Other Vectors, HDS code, and Production test code go here.

.rsect “.PowerUpBoot” // Address 30800

PUPBOOT: pt0=0

pollboot: a0=ins

a0 & 0x0000002000 // Check ins[PHINT].

if eq goto pollboot // Wait for ins[PHINT] to be set.

r0=0x41000 // Point to the PCON register.

a0=0x0010

ins=0xffff // Clear pending interrupts in ins.

*r0=a0 // Write PCON to clear HINT bit.

a0=0; r0=0 // Cleanup.

goto pt0 // Jump to user code.

5.2 EROM Boot Routine and DMAU Download

CORE0 and CORE1 bot h boot from EROM at address 0x80000 if the EXM pin is high when RSTN is deasse rted.

The cores access EROM via the SEMI, and the SEMI interleaves the accesses so that CORE0 executes the

instruction at address 0x80000 first, then CORE1 executes the instruction at address 0x80000 next, etc. The user

must place a boot routine for both cores into EROM prior to reset. This boot routine can contain instruction s to

download code and data from ERAM to internal memory (TPRAM0 and TP RAM1 ) via the DMAU. The downlo ad

can be performed either by both cores or by one core while the other core waits. In either case, the boot routine

must distinguish whether CORE0 or CORE1 is executing it. I t does this by re ading t he processor ID (pid) register

(Table 157 on page 242). CO RE0’s pid register contains 0x0 and CORE1’s pid register contains 0x1. After deter-

mining the processor ID, the boot routi ne can branch to the correct boot procedure for that core. Once the down-

load is complete, both c ores c an terminate their boot procedures by executing the following instructions:

pt0=0x0

nop

goto pt0

This causes CORE0 to begin executing instructions at address 0x0 of T P RAM0 and CORE1 t o begin executing

instructions at address 0x0 of TP RA M 1.

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6 Software Architecture

6.1 Instruction Set Quick Reference

The DSP16411 instruction set consists of both 16-bit and 32-bit wide instructions and resembles C-code.

Table 132 defines the seven types of instructions. The assembler translates a line of assembly code into the most

eff icient DSP16411 instruction(s). See Table 1 34 on page 218 for instruction set notation conventions.

Table 132. DSP16 411 Instruction Grou ps

Instruction

Group F Title

(If Applicable) Description

MAC F1 TRANSFER

F1E TRANSFER

if CON F1E

The powerful MAC ins truction group is the primary g roup of ins tr uctions used for sig-

nal processing. Up to two data tra nsfers can be combin ed wit h up to four parallel

DAU operations in a single MAC instruction to execute simultaneously†. The DAU

operat ion com binat ions inc lude (bu t are not limited to ) eith er a dual- MAC‡ oper ation ,

an ALU operati on and a BMU operati on, or an ALU/ACS operation and an

ADDER/ACS operat ion. The F1E in str uctions th at do not include a transfer state-

ment can execute conditionally based on the state of flags§.

† Executes in one i nstru ction cycle in most cases.

‡ A dual-M AC o peration consists of two multiplies and an add or subt ract oper ation by the ALU, an add or subtract operation by the ADDER, or

both.

§See Section 6.1.1 on page 226 for a description of processor flags.

Special

Function if CON F2

ifc CON F2

if CON F2E

if c CON F2E

Special func tions i nclude roundi ng, negati on, absol ute v alue, and fixe d ari thmeti c lef t

and right shift oper ati ons. The operands are an accumulator, another DAU register,

or an accumulator and another DAU regi ster. Some special function inst ruction s

increment counters. Spe cial functions execute condi tionally based o n the state of

flags§.

ALU F3

if CON F3E ALU ins tr uctions oper ate on two accumulators or on an accumu lator a nd another

DAU regist er. Man y instructions can also operate on an accumulator and an imme-

diate data word. The ALU operations are add, subtract, logical AND, logical OR,

exclusive OR, ma ximum, m inimum, and divide-step. Some F3E instruct ions include

a parall el ADDER operat ion. The F3E in str uctions can execut e conditionally based

on the stat e of flags§.

BMU F4

if CON F4E Full barrel shifting, exponent computation, normali zation comput ation, bit- field

extraction or ins ertion, and data shuffli ng between two accumulators are BMU oper-

ation s that act on the accum ulat ors. BMU operati ons are cont roll ed by an accumula-

tor, an auxiliary register, or a 16-bit im mediate value. The F4E instruct ions can

execute conditionally based on the state of flags§.

Data Move

and

Pointer

Arithmetic

— Data move inst ructi ons transfer data between two registers or between a register

and me mory. This instruction gr oup also supports immed iate loa ds of regi sters, con-

ditional register-to-regi ster moves, pipel ine block moves, and specialized stack

operations. Pointer arithmetic instructions perform arithmetic on data pointers and

do not perform a memo ry access.

Control — The con trol instru cti on group contai ns branch and call subroutin e instructio ns with

eithe r a 20-bi t absol ute addre ss or a 12-bit or 16 -bit PC-relat ive add res s. This group

also inc ludes ins truct ions to enable and disabl e inter rupts. Some contr ol inst ructi ons

can execute condit ionally based on the state of processor flags§.

Cache — Cache instructions implement low-overhead loops by loading a set of up to

31 in structions into cache mem ory and repetitivel y executing them as many as

216 – 1 times.

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6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

See the

DSP16000 Digital Signal Processor Core

Information Manual

for a detailed description of:



The instruction set



Pipe line hazards1



Instruction encodi ng format s and field descriptions



Instruction set reference

Table 133 on page 212 li sts the entire instruction set with its cycle performance and the number of mem ory loca-

tions required for each. Figure 57 is an illustration of a single row of the table and a description of how to interpret

its contents.

Figure 57. Interpretation of the I ns truction Set Summary Table

Table 134 on page 218 summa rizes the instruction set notation convent ions for interpreting the instruction syntax

descriptions. Table 135 on page 219 is an overall replacement table that summa rizes the replacement for every

upper-case character string in the instruction set summary table (Table 133 on page 212) ex cept for F 1 and F1E in

the MAC instruction group. Table 136 on page 222 describes the replacement for the F1 field, and Table 137 on

page 224 desc ribes th e replacement for the F1E field.

1. A pipeline hazard occurs when a write to a register precedes an access that uses the same register and that register is not updat ed bec au se

of pipeline timing. The DSP16000 assembler automatically inserts a nop in this case to avoid the hazard.

Instruction Flags Cycles Words

szlme Out In

ALU Group

aD = aS OP 〈aTE , pE〉(F3) szlm– 1 1 1

INSTRUCTIO N SYNTAX.

INSTRUCTIONS ARE GROUPED INTO

CATEGORIES (ONE OF SEVEN).

QUANTITY OF PROGRAM MEMORY

USED BY THE INSTRUCTION.

(EITHER 1 OR 2 16-bit WORDS).

F TITLE

(IF APPLICAB LE).

THE NUMBER OF INSTRUCTION CYCLES

USED WHEN THE INSTRUCTION IS EXE-

CUTED OUTSIDE OF THE CACHE.

THE NUMBER OF INSTRUCTION CYCLES

USED WHEN THE INSTRUCTION IS EXE-

CUTED INSIDE OF THE CACHE.A DASH

(—) INDICA TE S THE INSTRUCTION IS NOT

CACHABLE.

FLAGS AFFECTED BY

THIS INST RU CTIO N†.

† szlme corresponds to the LMI (s), LEQ (z), LLV (l), LMV (m), and EPAR (e) flags.If a letter appears in this column, the corresponding flag is

af fe ct ed by t hi s i nstr uct io n.If a dash appears in this column, the corresponding flag is unaffected by this instruction.In th e e xam pl e sh own ,

the instruction affects all fl ags except f or EPAR.For MAC group instructions with both an ALU/ACS operation and an ADDER or BMU oper-

ation, the ALU/ACS result affects the LMI, LEQ, LLV, and LMV flags, and the EPAR flag is unaffected.

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6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Table 133. Instructi on Set Summ ary

Instruction Flags Cycles Words

szlme Out In

Multiply/Accumulate (MAC) Group

F1Yszlm– 1 1 1

F1x〈h,l〉 = Y szlm–

F1y〈h,l〉 = Y szlm–

F1a〈h,l〉 = Y szlm–

F1Y = y〈h,l〉szlm–

F1Y = aT〈h,l〉szlm–

F1y h = aT h xh = X szlm– 1+X C†

F1y h = Y xh = X szlm–

if CON F1E szlme 1 1 2

F1Eyh,l = aTEh,lszlme

F1EaTEh,l = yh,lszlme

F1Ey = aE_P h szlme

F1EaE_Ph = y szlme

F1Exh,l = Y E s zlm e

F1Eyh,l = Y E s zlm e

F1EaTEh,l = YE szlm e

F1EaE_Ph = YE szlme

F1EYE = xh,lszlme

F1EYE = yh,lszlme

F1EYE = aTEh,lszlme

F1EYE = aE_Ph szlme

F1Eyh = *r0 r0 = rN E + jhb s zl m e

F1EYE szlme

F1Exh,l = XE szlme 1+XC†

F1E aTEh,l = XE sz lm e

F1EaE_Ph = XE szlme

F1Ey = aE_P h xh = XE szlme

F1Eyh = aTEh xh = XE szlme

F1EaTEh = y hxh = XE szlme

F1Eyh,l = YE‡a4h = XE szlme

F1Eyh,l = Y E x h = XE szlme

F1EYE = yh,lxh = XE szlme

F1Eyh = YE‡a4_5h = XE szlme

F1EYE = a6_7h xh = XE szlme

F1EYE = a6h‡xh = XE szlme

F1EYE = a6h‡a4h = XE szlme

†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-

tion types and can only be avoided by use of the cache.

‡ For this transfer, the postincrement opti ons *rME an d *rME–– are not available for double-w ord loads.

§ The – (40 -bit subtraction) operation is encod ed as aDE=aSE+IM16 with the IM16 value negated.

†† For conditional branch instructions, the execution time is two cycles if the branch is not taken.

‡‡ The instruction perfo rms the same function wheth er or not near (optiona l) is inc lud e d.

§§ Not including the N instructions.

Table 133. Instruction Set Summary (continued)

Advance Data Sheet

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any instructions

6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Multiply/Accumulate (MAC) Group (continued)

F1Eyh = *r0 r0 = rNE+jlbj = kk

= XE szlme 1+XC†12

F1EXE szlme

Special Function Group

if CON aD = aS>>〈1,4,8,16〉(F2) szlme 1 1 1

ifc CON aD = aS>>〈1,4,8,16〉(F2) szlme

if CON aD = aS (F2) szlm–

ifc CON aD = aS ( F2) szlm–

if CON aD = –aS (F2) szlm–

ifc CON aD = –aS (F2) szlm–

if CON aD = ~aS (F2) szlm–

ifc CON aD = ~aS (F2) szlm–

if CON aD = rnd(aS) (F2) szlm–

ifc CON aD = rnd(aS) (F2) szlm–

if CON aDh=aSh+1 (F2) szlm–

ifc CON aDh = aSh+1 (F2) szlm–

if CON aD = aS+1 (F2) szlm–

ifc CON aD = aS+1 (F2) szlm–

if CON aD = 〈y,p0〉(F2) szlm–

ifc CON aD = 〈y,p0〉(F2) szlm–

if CON aD = aS<<〈1,4,8,16〉(F2) szlme

ifc CON aD = aS<<〈1,4,8,16〉(F2) szlme

if CON aDE = aSE>>〈1,2,4,8,16〉(F2E) szlme 1 1 2

ifc CON aDE = aSE>>〈1,2,4,8,16〉(F2E) szlme

if CON aDE = aSE (F2E) szlm–

ifc CON aDE = aSE (F2E) szlm–

if CON aDE = –aSE (F2E) szlm–

ifc CON aDE = –aSE (F2E) szlm–

if CON aDE = ~aSE (F2E) szlm–

ifc CON aDE = ~aSE (F2E) s zlm–

if CON aDE = rnd(〈aSE,pE〉)(F2E)szlm–

ifc CON aDE = rnd(〈aSE,pE〉)(F2E)szlm–

if CON aDE = rnd(–pE) (F2E) szlm–

ifc CON aDE = rnd(–pE) (F2E) szlm–

if CON aDE = rnd(aSE+pE) (F2E) szlm–

ifc CON aDE = rnd(aSE+pE) ( F2E) szlm–

if CON aDE = rnd(aSE–pE) (F2E) szlm–

ifc CON aDE = rnd(aSE–pE) (F2E) szlm–

Instruction Flags Cycles Words

szlme Out In

†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-

tion types and can only be avoided by use of the cache.

‡ For this transfer , the postincrement options *rME and *rME–– are not available for double-word loads.

§ The – (40 -bit subtraction) operation is encod ed as aDE=aSE+IM16 with the IM16 value negated.

†† For conditional branch instructions, the execution time is two c ycles if the branch is not taken.

‡‡ The inst ruction perform s the same function whether or not near (op t io na l) is inc lude d.

§§ Not including the N instructions.

Table 133. Instructi on Set Summ ary (continued)

6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Advance Data Sheet

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Special Function Group (continued)

if CON aDE = abs(aSE) (F2E) szlm– 1 1 2

ifc CON aDE = abs(aSE) (F2E) szlm–

if CON aDE = aSEh+1 (F2E) szlm–

ifc CON aDEh = aSEh+1 (F2E) szlm–

if CON aDE = aSE+1 (F2E) szlm–

ifc CON aDE = aSE+1 (F2E) szlm–

if CON aDE = 〈y,pE〉(F2E) szlm–

ifc CON aDE = 〈y,pE〉(F2E) szlm–

if CON aDE = 〈–y,–pE〉(F2E) szlm–

ifc CON aDE = 〈–y,–pE〉(F2E) szlm–

if CON aDE = aSE<<〈1,2,4,8,16〉(F2E) szlme

ifc CON aDE = aSE<<〈1,2,4,8,16〉(F2E) szlme

ALU Group

aD = aS OP 〈aTE,pE〉(F3) szlm– 1 1 1

aD = 〈aTE,pE〉 – aS (F3) szlm–

aD = FUNC(aS,〈aTE,pE〉)(F3)szlm–

aS – 〈aTE,pE〉(F3) szlm–

aS&〈aTE,pE〉(F3) szlm–

if CON aDE = aSE OP 〈pE,y〉(F3E) szlm– 1 1 2

if CON aDE = aSE OP aTE (F3E) szlm–

if CON aDE = 〈pE,y〉–aSE (F3E) szlm–

if CON aDE = FUNC(aSE,〈pE,y〉) (F3E) szlm–

if CON aDE = FUNC(aSE,aTE) (F3E) szlm–

if CON aSE – 〈pE,y〉(F3E) szlm–

if CON aSE&〈pE,y〉(F3E) szlm–

if CON aSE – aTE (F3E) szlm–

if CON aSE&aTE (F3E) szlm–

if CON aDEE = aSEE±aTEE aDPE = aSPE±aTPE (F3E) szlm–

if CON aDE = aSE+aTE el se aDE = aSE–aTE (F3E) szlm–

aDE = aSE〈h,l〉 OP IM16§(F3 with immediate) szlm– 1 1 2

aDE = IM16–aSE〈h,l〉(F 3 wit h imm ediate) szlm–

aSE〈h,l〉 – IM16 ( F3 with immediate) szlm–

aSE〈h,l〉 & IM16 (F3 with immediate) szlm–

Instruction Flags Cycles Words

szlme Out In

†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-

tion types and can only be avoided by use of the cache.

‡ For this transfer, the postincrement opti ons *rME an d *rME–– are not available for double-w ord loads.

§ The – (40 -bit subtraction) operation is encod ed as aDE=aSE+IM16 with the IM16 value negated.

†† For conditional branch instructions, the execution time is two cycles if the branch is not taken.

‡‡ The instruction perfo rms the same function wheth er or not near (optiona l) is inc lud e d.

§§ Not including the N instructions.

Table 133. Instruction Set Summary (continued)

Advance Data Sheet

April 2002 DSP16411 Digital Signal Processor

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any instructions

6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

BMU Group

aD = aS SHI FT 〈aTEh,arM〉(F4) szlme 1 1 1

aDh = exp(aTE) (F4) szlme

aD = norm(aS, 〈aTEh,arM〉)(F4)szlme

aD = extr acts(aS,aTEh) (F4)

aD = extr actz(aS,aTEh) szlme

aD = inserts(aS,aTEh) (F4)

aD = insertz(aS,aTEh) szlme

aD = extract(aS,arM) (F4)

aD = extracts(aS,arM)

aD = extractz(aS,arM)

szlme

aD = ins e rt(a S ,arM ) (F4 )

aD = inserts(aS,arM)

aD = insertz(aS,arM)

szlme

aD = aS:aTE (F4) szlm–

aDE = extr act(aSE,IM8W,IM8O) (F4 with immediat e)

aDE = extr acts(aSE,IM8W,IM8O)

aDE = extr actz(aSE,IM8W,IM8O)

szlme 1 1 2

aDE = inser t( aSE,IM8W,IM8O) (F4 with immediat e)

aDE = inser ts(aSE,IM8W,IM8O)

aDE = inser tz(aSE,IM8W,IM8O)

szlme

aDE=aSE SHIFT IM16 (F4 wit h immediate) szlme

if CON aDE = aSE SHIFT〈aTEh,arM〉 (F4E) szlme 1 1 2

if CON aDEh = exp(aTE) (F4E) szlme

if CON aDE = norm(aSE,〈aTEh,arM〉)(F4E)szlme

if CON aDE = extracts(aSE,aTEh) (F4E)

if CON aDE = extractz(aSE,aTEh) szlme

if CON aDE = inserts(aSE,aTEh) (F4E)

if CON aDE = insertz(aSE,aTEh) szlme

if CON aDE = extract(aSE,arM) (F4E)

if CON aDE = extracts(aSE,arM)

if CON aDE = extractz(aSE,arM)

szlme

if CON aDE = insert(aSE,arM) (F4E)

if CON aDE = inserts(aSE,arM)

if CON aDE = insertz(aSE,arM)

szlme

if CON aDE = aSE:aTE (F4E) szlm–

Instruction Flags Cycles Words

szlme Out In

†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-

tion types and can only be avoided by use of the cache.

‡ For this transfer , the postincrement options *rME and *rME–– are not available for double-word loads.

§ The – (40 -bit subtraction) operation is encod ed as aDE=aSE+IM16 with the IM16 value negated.

†† For conditional branch instructions, the execution time is two c ycles if the branch is not taken.

‡‡ The inst ruction perform s the same function whether or not near (op t io na l) is inc lude d.

§§ Not including the N instructions.

Table 133. Instructi on Set Summ ary (continued)

6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Advance Data Sheet

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Data Move and Pointer Arit hm etic Group

RAB = IM20 —112

RA = IM4 — 1 1 1

RAD = RAS—111

if CONRABD = RABS—2

RB = aTE〈h,l〉—111

aTE〈h,l〉 = RB —

RA = Y — 1 1 1

Y = RA —

RAB = YE — 1 1 2

YE = RC —

RAB = *sp++2 — 1 1 1

*sp––2 = RC —

sp––2 —

*sp = R C —

push RC

pop RAB —

r3––sizeof(RAB) —

RA = *(sp+IM5) — 2 2 1

*(sp+IM5) = RA —

RAB = *(RP+IM12) — 2 2 2

*(RP+IM12) = RC —

RAB = *(RP+〈j,k〉)—

*(RP+〈j,k〉) = RC —

RY = RP+IM12 — 1 1 2

RY = RP+〈j,k〉—

RAB = *r7 r7 = sp+IM11 — 1 1 2

*r7 = RC r7 = sp+IM11 —

YE‡ = xhxh = XE —1+XC†12

Instruction Flags Cycles Words

szlme Out In

†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-

tion types and can only be avoided by use of the cache.

‡ For this transfer, the postincrement opti ons *rME an d *rME–– are not available for double-w ord loads.

§ The – (40 -bit subtraction) operation is encod ed as aDE=aSE+IM16 with the IM16 value negated.

†† For conditional branch instructions, the execution time is two cycles if the branch is not taken.

‡‡ The instruction perfo rms the same function wheth er or not near (optiona l) is inc lud e d.

§§ Not including the N instructions.

Table 133. Instruction Set Summary (continued)

Advance Data Sheet

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6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Control Grou p

near goto IM12‡‡ —3—1

near call IM 12‡‡ —

if CON goto IM16 —3

†† —2

if CON ca ll IM 1 6 —

far go to IM20 —3—

far call IM20 —

if CON goto ptE — 3†† —1

if CON call ptE —

if CON call pr —

tcall —3—

ic a ll IM6 —

if CON return — 3†† —

ireturn — 3 —

treturn —

di —11

Cache Group

do K {N_INSTR} — 1§§ —1

§§

redo K —2—1

do cloop {N_I NSTR} — 1§§ —1

§§

redo cloop —2—1

Instruction Flags Cycles Words

szlme Out In

†XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruc-

tion types and can only be avoided by use of the cache.

‡ For this transfer , the postincrement options *rME and *rME–– are not available for double-word loads.

§ The – (40 -bit subtraction) operation is encod ed as aDE=aSE+IM16 with the IM16 value negated.

†† For conditional branch instructions, the execution time is two c ycles if the branch is not taken.

‡‡ The inst ruction perform s the same function whether or not near (op t io na l) is inc lude d.

§§ Not including the N instructions.

Advance Data Sheet

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any instructions

6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Table 134 defines the sym bols used in instruction descript ions. Som e sym bol s and characters are part of t he

instruction syntax, and must appear as shown within the instruction. Other symbols are repres entational and are

replaced by other characters. The table groups these two type s of symbols separate ly.

Table 134. Notation Conventions for Instruction Set Descriptions

Symbol Meaning

Part of

Syntax * 16-bi t x 16-bit multi plication resulting in a 32-bit product.

Exception: if used as a prefix to an address regist er, denotes register-indirect addressing, e.g.,

*r3.

**2 Squaring is a 16-bi t x 16-bit multiplication of t he operand with itself, r esulting in a 32-bit product.

+ 40-bit addition†.

† The ALU/ACS and ADDER perform 40-bit operations, but the operands can be 16 bits, 32 bits, or 40 bits. In the special case of the split-mode

F1E instruction (xh=aSPEh±yh, xl=aSPEl±yl, aDE=aSEE+p0+p1, p0=xh**2, p1=xl**2), the ALU performs two 16-bit addition/subtraction

operations in parallel.

– 40-bit subtraction†.

++ Re gister postin crement.

–– Regis ter postdecrement.

>> Arithmetic ri ght shif t (wit h sign-extension from bit 39).

<< Arithmetic left shift (padded with zeros).

>>> Logical right shift (zero guard bits before shift).

<<< Logical lef t shi ft (padded with zeros; sign-extended from bit 31).

& 40-bit bit w is e logical AND†.

| 40-bi t bit w ise logical OR†.

^ 40-bit bitwise logical exclusive-OR†.

: Register shuffle‡.

‡ Note that this symbol does not denote compound addressing as it does for the DSP16XX family.

~ Ones complement (bitwise inverse).

( ) Parent heses enclose mult ipl e operands delim ited by commas that are also part of the synt ax.

{ } Braces encl ose m ultiple ins tructions wit hin a cache l oop.

(underscore) T he under scor e c haract er in dic ates a n ac cumul ator vector ( concaten ation of the h igh halve s of a

pair of sequential accumula tor s, e.g. , a0_1h).

lower-case Lower-case characters appear as shown in the instruction.

Not Part

of Syntax

(Replaced)

〈 〉Angle brackets enclose items delim ited by commas, one of which must be chosen.

 Mid braces enclos e one or more opti onal items delimited by commas.

±Replaced by either + or –.

UPPER-

CASE Upper-case char acters, character strings, and characters plus numerals (e.g., M, CON, and

IM16) are replaced. Replacement t ables accompany each inst ruction group descript ion.

F Titl es Represents a statement of a DAU function:

F1 MAC.

F1E Extended MAC.

F2 Special funct ion.

F2E Extended special function.

F3 ALU.

F3E Extended ALU.

F4 BMU.

F4E Extended BMU.

Advance Data Sheet

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6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Table 135 . Overall Repl acemen t Table

Symbol Used in

Instruction

Type(s)

Replaced By Description

aD F1 , F2, F3 ,

F4 a0 or a1

(DSP16XX-compatible) D indicates destination of an operation.

aS S indicates source of an operation.

aT F1 T indi cates an a ccumul ator that is th e so urce of a data

transf er.

a indi cates an accumulator other than the destination

accumulator.

aDE F1E, F2E,

F3/E, F4 /E a0, a1, a2, a3, a4, a5, a6, or a7 D indicates destination of an operation. Sindicates

source of an operation. T i ndicates an accu m ul a tor

that i s eit her an addit ional source for an operation or

the source or dest ination of a data transfer. E indi -

cates the extended set of accumulators.

aSE

aTE F 1E, F3/ E,

F4/E,

data move

aDEE F1E, F3E a〈DPE – 1〉 → a0, a2, a4, or a6 D indicates destination of an operation. Sindicates

source of an operation. T i ndicates an accu m ul a tor

that i s eit her an addit ional source for an operation or

the source or de sti nation of a data t ransfer. The first E

indicates an even accumulat or that is pai red with its

corresponding paired extended ( odd) accumulator,

i.e., the matchin g aDPE, aSPE, or aTPE accumul ator.

The second E indicat es the extended set of accumu-

lators.

aSEE a〈SPE – 1〉 → a0, a2, a4, or a6

aTEE F3E a〈TPE – 1〉 → a0, a2, a4, or a6

aDPE F1E, F3E a〈DEE + 1〉 → a1, a3, a5, or a7 P indicates an odd accumulato r that is paired with an

even extended accumulator, i.e., the mat ching aDEE,

aSEE, or aTEE accumulator. E indi cates the

extended set of accumulators.

aSPE a〈SEE + 1〉 → a1, a3, a5, or a7

aTPE F3E a〈TEE + 1〉 → a1, a3, a5, or a7

aE_Ph F1E a0_1h, a2_3h, a4_5h, or a6_7h An accumulator vector, i.e., t he concatenated 16-bit

high hal ves of two adjacent accu mulators to form a

32-bit vector.

arM F4, F4E ar0, ar1, ar2, or ar3 One of the four auxiliary accum ulat ors.

CON F1E, F2,

F2E , F3E,

F4E,

control,

data move

mi, pl, eq, ne, lvs, lvc, mvs, mvc, heads,

tails, c0ge, c0lt, c1ge, c1lt, true, false, gt,

le, oddp, evenp, smvs, smvc, jobf, jibe,

jcont, lock, mgibe, mgobf, somef, somet,

allf, or allt

Conditi onal mnemonics. Certain ins tr uctions ar e con-

diti onally executed, e. g., if CON F2E. Se e Table 138

on page 226.

FUNC F3, F3E max, min, or divs One o f three ALU f unctions: maximum, minimum, or

divide-step.

IM4 data move 4-bit unsigned immedi ate val ue (0 to 15) Signed/unsi gne d statu s of the I M4 value mat ches that

of the dest ination register of the dat a move assign-

ment instruction.

4-bit signed immediate val ue (–8 to +7)

IM5 data move 5-bit unsigned immedi ate val ue (0 to 31) Added to stack pointer sp to form stack address.

IM6 c ontrol 6-bit unsigned i mmediate value (0 to 63) Vector for icall instruction.

IM8O

IM8W F4 8-bit unsi gned immediate val ue (0 to 255) Off set and width for bit-field insert and extract instruc-

tions. The BMU truncates these val ues to 6 bits.

IM11 data move 11-bit unsigned imm ediate value

(0 to 2047) Added to stack pointer sp to form stack address.

† The s ize of the transfer (single- or double-word) depends on the size of the register on the other si de of the equal sign.

‡ These pos tmodification options are not available for a double-word load except for a load of an accumulator vector .

Table 135. Over all Repl acemen t Table (continued)

6 Software Architecture (continued)

6.1 Instruction Set Quick Reference (continued)

Advance Data Sheet

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IM12 control 12-bit si gned imme diate value

(–2048 to +2047) PC-relat ive near address for goto and call instruc-

tions.

data move

and

pointer

arithmetic

Postmodi ficat ion t o a general YAAU poi nter regist er to

form address for data move.

Added to t he val ue o f a ge nera l YAAU point er re gi ster,

and the result is stored into any YAAU regist er.

IM16 control 16-bit si gned imme diate value

(–32,768 to +32,767) Offs et for conditi onal PC-relati ve goto/call instruc-

tions.

F3, F4 Operand for ALU or BMU operatio n.

IM20 control,

data move 20-bit unsigned immedi ate value

(0 to 1, 048,576) Absolute ( unsigned) far address for goto and call

instr u ctions. For data mov e instructions, the

signed/unsigned status of the IM20 value matches

that of the destination register of the assignment

instruction.

20-bit signed immediate value

(–524,288 to 524,287)

K cache 1 to 127 or the val ue in cloop For the do K {N_INSTR} and redo K cache instruc-

tions.

N 1 to 31

OP F1, F1E, F3,

F3E +, –, &, |, o r ^40-bit ALU opera ti on.

pE F2E, F3,

F3E p0 or p1 One of the product registers as source for a special

functi on or ALU oper ation.

ptE F1E, control,

data move pt0 or pt1 One of the t w o XAAU pointer registers as address for

an XE memory access ( see XE entry in this table).

RA data move a0, a1, a2, a3, a4, a5, a6, a7, a0 h , a1h,

a2h, a3h, a4h, a5h, a6h , a7h, a0l, a1l , a2l,

a3l, a4l, a5 l, a6l, a7l, al f, auc0, c0, c1, c2,

h, i, j, k, p0, p0h, p0l, p1, p1h , p1l, pr,

psw0, pt0, pt1, r0, r1, r2, r3, r4, r5, r6, r7,

rb0, rb 1, re0, re1, sp, x, xh , xl, y, yh, or yl

One of the main core regist ers that is specified as the

source or desti nation of a data move operation. The

subscripts are used to indicate that two dif ferent regis-

ters can be specified, e.g. , RAD = RAS describes a

regist er-to-register move instruction where RAD and

RAS are, i n general, two dif ferent registers.

RAD

RAS

RB core a0g, a1g, a2 g , a3g, a4g, a5 g ,

a6g, a7g, a0_1h, a2_3h, a4_5h,

a6_7h, ar0, ar1, ar2, ar3, auc1,

cloop, cstate, csave, inc0, inc1, ins ,

pi, psw1, ptrap, vbase, or vsw

One of the s econd ary regi ster s that i s speci fied as t he

source or desti nation of a data move operation. This

set includes core and off-core regi sters.

off-core cbit, imux, jiob, mgi, mgo, pid,

pllcon, pllfrq, pllfrq1, plldly, sbit,

signal, timer0, timer1, timer0c,

timer1c

RAB Any of the RA or RB registers

(see rows above) Any one of the re gisters in the main (RA) or second-

ary (RB) set s of regi sters that is spe cified as the

source or desti nation of a data move operation. The

subscripts are used to indicate that two dif ferent regis-

ters can be specified.

RABD

RABS

RC Any of the RA registers or any of the core RB

registers (see rows above) Any core register that is spe cified as the sour ce of a

data move operation.

rM F1,

data move r0, r1, r2, or r3 One of four general YAAU pointer registers used for a

Y-memory access (see Y entry in this table).

Symbol Used in

Instruction

Type(s)

Replaced By Description

† The s ize of the transfer (single- or double-word) depends on the size of the register on the other si de of the equal sign.

‡ These postmodification opt ions are not available for a double-word load except for a load of an a ccumulator vector.

Table 135 . Overall Repl acemen t Table (continued)

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6.1 Instruction Set Quick Reference (continued)

rME F1E,

data move r0, r1, r2, r3, r4, r5, r6, or r7 One of eight general YAAU pointer registers used for

a YE memory access (s ee YE entry in this table). E

indicates the extended set of pointer registers.

rNE F1E r1, r2, r3, r4, r5, r6 , or r7 One of seven gener al YAAU pointer regis ters us ed f or

a table l ook-up pointer update.

RP data move

and

pointer

arithmetic

r0, r1 , r2, r3, r4, r5, r6, or sp One of seven general YAAU pointer registers or t he

YAAU stack pointer.

RY r0, r1, r2, r3, r4, r5, r6, r7, sp,

rb0, rb 1, re0, re1, j, or kAny one of the YAAU registers, incl uding the stack

pointer , cir cular buffer pointers, and increment regi s-

ters.

XF1 *pt0++ or *pt0++iA single-word location pointed to by pt0.

YF1 *rM, *rM++, *rM––, or *rM++j A si ngle- word location pointed to by rM.

F1YrM++, rM––, or rM++j Modification of rM pointer register (no mem ory

access).

data move *rM, *rM++, *rM––, or *rM++j A single- or doub le-word† location pointed to by rM.

XE F1E,

data move *ptE‡, *ptE++, *ptE––‡, *ptE++h,

or *ptE++i A si ngle- word or double-word† memory location

pointed to by ptE.

F1EXE ptE++, ptE––, ptE++h, ptE++i,

or ptE++2 Modi fication of ptE pointer register (no memory

access).

YE F1E,

data move *rME, *rME++, *rME––, *rME++j,

or *rME++k A single-word or double-word† memory location

pointed to by rME.

F1EYE rME++, rME––, rME++j, rME++k, rME++2,

or rME––2 Modification of rME pointer register (no mem ory

access).

Symbol Used in

Instruction

Type(s)

Replaced By Description

† The s ize of the transfer (single- or double-word) depends on the size of the register on the other si de of the equal sign.

‡ These pos tmodification options are not available for a double-word load except for a load of an accumulator vector .

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6.1 Instruction Set Quick Reference (continued)

Table 136 defines the F1 instruction syntax as any function s tate men t combined with any transfer statement. Two

types of F1 function statements are shown: the MAC (multiply/accumulate) type and the arithmetic/logic type. The

MAC type is formed by combining any two items from the designated AL U and Multiplier columns. The arith-

metic/logic type is chosen from the items in the designated F1 Arithmetic/Logi c Function Statement co lumn.

Table 136. F1 Instru ction Sy ntax

Combine Any F1 Function Statement with Any Trans fer Stat em ent

F1 MAC Function Statement—

Combine Any Items in Following Two Columns: Transfer Statement Cycles

(Out/In

Cache)†

† Not including conflict, misalignment, or external wait-states (see the

DSP16000 Di gital Signal Processor Core

Information Manual).

16-Bi t

Words

ALU Multiplier

aD = aS ± p0 p0 = xh * yh Y‡

‡ This Y transfer statement must increment or decrement the contents of an rM register. It is not necessary to include the * before the rM reg-

is ter because no access is made to a memory location.

1/1 1

(no ALU operati on)§

§ Leave the ALU column blank to specify no ALU operation, the multiplier column blank to specify no multiply operation, or both columns

blank to specify no F1 function statement. If both columns are left blank and a transfer statement is used (a transfer-only F1 instruction,

i.e., yh = *r2 xh = *pt0++), the assembler int erprets th e F1 functi on statement as a nop.

(no multipl y operation)§〈x, y, a ††〉〈h, l〉 = Y

†† For this instruction, a must be the opposite of aD, e.g., if aD is a0, a mu s t b e a1 an d vi ce ver s a .

1/1

F1 Arithmeti c/Logic Function Stat em ent (ALU) Y = 〈y, aT〉〈h, l〉1/1

aD = aS OP yyh = 〈Y, aTh〉xh = X 1 + XC‡‡/1

‡‡ XC is one cycle if XAAU contention occurs and zero cycles otherwise. XAAU contention occurs frequently for these instruction types an d

can only be avoided by use of the cache. See the

DSP16000 Di gital Signal Processor Cor e

Information Manual.

aS – y (no tran sfer)§§

§§ The assembler encodes an instruction that consists of a function statement F1 with no transfer statement as F1 *r0.

1/1

aS & y

nop†††

†††nop is no-oper ation. A programmer can write nop with or wit hout an accompanying transfer statement. The assembler encodes nop with-

out a transf er statement as nop *r0.

(no F1 function statement)§

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6.1 Instruction Set Quick Reference (continued)

Table 137 on page 224 summarizes the syntax for F1E function statements and the following paragraphs describe

each class of instruction.

Note: Each function s tat eme nt can be combined with a parallel transfer statement to form a single DSP16411

instruction.

General -Pu rp ose MAC Com bine any ALU, ADDE R, or A LU and ADDE R operation from the left column

with any single- or dual-multiply operation from the right column. Either column

can be left blank.1

Additional General-Purpose MAC

These statements are general-purpose. The combinations of operations must be

as shown. The first statement clears two accumulators and both product

registers. The second statement is the equivalent of the F1 statement

aD = p0 p0 = xh * yh exc ept that any accum ulator aDE can be specifi ed. T he

third statement is the equivalent of the F1 statement aD = p0 exce pt that any

accumulator aDE can be specified. The fourth statement is a no-operation and,

as with all F1E function statements, can be combined with a transfer statement.

Special-Purpose MAC for Mixed Precision

Combine any AD DER operation or any ALU and ADDER operation from the left

column with any dual-multiply operation from the right column. Either column can

be left blank.1These statemen ts are intended for, but are not lim ited to, mixed -

precision MAC applications. Mixed-precision multiplication is 16 bits x 31 bits.

Special-Purpose MAC for Double Precision

These statements are intended for , but are not limited to, double-precision MAC

applications. The combinations of operations must be as shown. Double-preci-

sion multiplication is 31 bits x 31 bits.

Special-Purpose MAC for Viterbi

These statements are intended for, but are not limited to, Viterbi decoding applica-

tions. The combinations of operations must be as shown. This group includes

ALU split-mode operations.

Special-Purpose MAC for FFT This statement is intended for, but is not limited to, FFT applications.

ALU These statements are ALU operations. The first three statements in this group

are the equivalent of the F1 arithmet ic/logic function statement s.

Special-P u rpose ALU/ACS, ADDER/ACS for Viterbi

These statements are intended for, but are not limited to, Viterbi decoding applica-

tions. They provide either an ALU/ACS operation with or wit hout a parallel

ADDER/ACS operation or split-mode ALU and ADDER operations. The combina-

tions of operations must be as shown. Thi s group includes the Viterbi compare

functions.

Special-Purpose ALU, BMU These statements are intend ed for, but are not limited to, special-purpose

applications. They provide a BMU operation with or without a parallel ALU opera-

tion. The combinations of operations must be as shown.

1. If both columns are lef t blank and a transfer statement is used, th e DSP16000 assembler inter prets the F1E f unction statement as a no-oper-

at io n (nop).

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6.1 Instruction Set Quick Reference (continued)

Table 137. F1E Functi on Statement Syntax

General-Purpose M AC Function Statement s—Combine Any Item s in Two Columns

ALU†ADDER†Multipliers

aDE=aSE±p0 p0=xh*yh

aDE=aSE±p0±p1‡p0=xh*yh p1=xl*yl

aDEE=aSEE±p0 aDPE=aSPE±p1 p0=xh*yl p1=xl*yh

(no ALU/ACS or ADDER operation) p0=xh*yh p1=xh*yl

p0=xl*yh p1=xl*yl

(no multiply operation)

Additional General-Purpose MAC Function Stat em ents

ALU†ADDER†Multipliers

aDE=0 aSE=0 p0=0 p1=0

aDE=p0 p0=xh*yh

aDE=p0

nop

Special- Purpose MAC Function Statem ents for Mixed Preci sion—Combine Any Items in Two Columns

ALU†ADDER†Multipliers

aDE=p0+(p1>>15)§p0=xh*yh p1=xh*(yl>>>1)

aDEE=aSE+aDPE aDPE=p0+(p1>>15)§p0=xl*yh p1=xl*(yl>>>1)

(no ALU/ACS or ADDER operation) (no multiply operation)

Special-Purpose MAC Function Stat em ents for Doubl e Precision

ALU†ADDER†Multipliers

aDE=aSE+p0+(p1>>15)‡ § p0=xh*yh p1=xh*(yl>>>1)

aDE=aSE+p0+(p1>>15)‡ §

aDE=p0+(p1>>15)§p0=0 p1=(xl>>>1)*yh

aDEE=aSE+aDPE aDPE=p0+(p1>>15)§p0=0 p1=(xl>>>1)*yh

aDE=(p0>>1)+(p1>>16) p0=(xl>>>1)*yh p1=xh*yh

aDEE=aSE+aDPE aDPE=(p0>>1)+(p1>>16) p0=(xl>>>1)*yh p1=xh*yh

aDE=aSE+(p0>>1) p0=xh*(yl>>>1) p1=(xl>>>1)*(yl>>>1)

aDE=(aSE>>14)+p1 p0=xh*(yl>>>1) p1=(xl>>>1)*(yl>>>1)

aDE=(aSE>>14)+p1

† DAU f l ags ar e aff ected by the ALU or ALU /A CS operat i on (exce pt for the split-m ode fun ct i on whi ch doe s not affe ct the fla gs). If ther e i s no AL U or

ALU/ ACS operation, the DA U flags are affecte d by the ADDER or BMU operation.

‡If auc0[10] (FSAT field) is set, the result of the add/subtract of the first two operands is saturated to 32 bits prior to adding/subtracting the third operand

and the final result is satu rated to 32 bits .

§If auc0[9] = 1, the l east signi ficant bit of p1>>15 is cleared.

†† T hi s is a 16-bit operat i on. The DA U st ores the res ul t i n the high hal f of the desti nation ac cumul ator and clears t he low hal f.

‡‡ T hi s spli t-mode in struct io n does not affe ct the DA U flags. Do not set F SAT for thi s i nstruct i on becaus e i f FSAT is set, the entire 3 2 bits are sa turated.

Table 137 . F1E Function Statement Syntax (continued)

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Special-Purpose MAC Function Sta tem ents for Viterbi

ALU†ADDER†Multipliers

xh=aSPEh+yh xl=aSPEl+yl†† aDE=aSEE+p0+p1 p0=xh**2 p1=xl**2

xh=aSPEh–yh xl=aSPEl–yl†† aDE=aSEE+p0+p1 p0=xh**2 p1=xl**2

aDE=aSE+p0+p1‡p0=xh**2 p1=xl**2

Special- Purpose MAC Function Statement for FFT

ALU†ADDER†Multipliers

aDEE=–aSEE+p0 aDPE=–aSPE+p1 p0=xh*yh p1=xl*yl

ALU Function Statem ents

aDE=aSE OPy

aSE–y

aSE&y

aDE=aDE±aSE

Special -Purpose ALU/ACS, ADDER/ACS Function State men ts fo r Vit erbi

ALU/ACS†ADDER†

aDEE=cmp0(aSEE,aDEE) aDPE=aDPE+aSPE

aDEE=cmp0(aSEE,aDEE) aDPE=cmp0(aSPE,aDPE)

aDE=cmp0(aSE,aDE)

aDEE=cmp1(aSE,aDEE) aDPE=aDEE–aSE

aDEEh=cmp1(aSEEh,aSEEl)†† aDPEh=cmp1(aSPEh,aSPEl)††

aDE=cmp1(aSE,aDE)

aDEE=cmp2(aSE,aDEE) aDPE=aDEE–aSE

aDE=cmp2(aSE,aDE)

aDEE=aSEE+y aDPE=aSPE–y

aDEE=aSEE−y aDPE=aSPE+y

aDEEh=aSEh+yh aDEEl=aSEl+yl‡‡ aDPEh=aSEh−yh aDPEl=aSEl−yl‡‡

aDEEh=aSEh−yh aDEEl=aSEl−yl‡‡ aDPEh=aSEh+yh aDPEl=aSEl+yl‡‡

Special-Purpose ALU, BMU Functi on Statements

ALU†BMU†

aDEE=rnd(aDPE) aDPE=aSEE>>aSPEh

aDE=aSEE>>aSPEh

aDE=abs(aDE) aSE=aSE<<ar3

aDE=aSE<<ar3

aDE=aSE<<<ar3

aDEE=min(aDPE,aDEE) aDPEh=exp(aSE)

† DAU f l ags ar e aff ected by the ALU or ALU /A CS operat i on (exce pt for th e split-mode fun ct i on whi ch doe s not affe ct the fla gs). If ther e i s no AL U or

ALU/ ACS operation, the DA U flags are affecte d by the ADDER or BMU operation.

‡If auc0[10] (FSAT field) is set, the result of the add/subtract of the first two operands is saturated to 32 bits prior to adding/subtracting the third operand

and the final result is satu rated to 32 bits .

§If auc0[9] = 1, the l east signi ficant bit of p1>>15 is cleared.

†† T hi s is a 16-bit operat i on. The DA U st ores the res ul t i n the high hal f o f the dest i nation ac cumul ator and clears t he low hal f.

‡‡ T hi s spli t-mode in struct io n does not affe ct the DA U flags. Do not set F SAT for thi s i nstruct i on becaus e i f FSAT is set, the entire 3 2 bits are sa turated.

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6.1 Instruction Set Quick Reference (continued)

6.1.1 Conditions Based on the State of Flags

A conditional instruction begins with either if C O N or ifc CON, where CON is repla ce d with a condition that is

tested. Table 138 describes the complete set of condition codes available for use in conditional instructions. It also

includes the state of the internal flag or flags that cause the condition to be true.

Table 138. DSP16411 Conditional Mnemo nics

CON

Encoding CON

Mnemonic Flag(s)

If CON Is True Type†

† Al l peripheral (off-co re) flags are acce ssible in the alf register.

Description

00000 mi LMI = 1 Core Most recent DAU result is negative.

00001 pl LMI ≠ 1 Core Most recent DAU result is positive or zero.

00010 eq LEQ = 1 Core Most rec ent DAU result is equal to zero.

00011 ne LEQ ≠ 1 Core Most rec ent DAU resul t is not equal to zero.

00100 lvs LLV = 1 Core Most rec ent DAU resul t has overflowed 40 bit s.

00101 lvc LLV ≠ 1 Core Most recent DAU result has not overflowed 40 bits .

00110 mvs LMV = 1 Core Most recent DAU result has overflowed 32 bi ts.

00111 mvc LMV ≠ 1 Core Most rec ent DAU result has not overflowed 32 bits .

01000 heads — Core Pseudor andom sequence generat or output is set.

01001 tail s — Core Pseudorandom bit i s cle ared.

01010 c0ge‡

‡ Eac h te st of c0ge or c0lt causes counter c0 to postincrement . Each test of c1ge or c1lt causes counter c1 to post in crem en t.

— Core Current value in count er c0 is greater than or equal to zer o.

01011 c0lt‡— Core Current value in counter c0 is less than zero.

01100 c1ge‡— Core Current value in count er c1 is greater than or equal to zer o.

01101 c1lt‡— Core Current value in counter c1 is less than zero.

01110 true 1 Core Always.

01111 false 0 Core Never.

10000 gt (LMI ≠ 1)

and (LEQ ≠ 1) Core Most rec ent DAU result is great er than zer o.

10001 le (LMI = 1)

or (LEQ = 1) Core Most recent DAU result is less than or equal to zero.

10010 smvs SLMV = 1 Core A previous result has overf lowed 32 bits (sticky flag).

10011 smvc SLMV ≠ 1 Core A previous resul t has not overflowed 32 bits since SLMV last cleared.

10100 oddp EPAR ≠ 1 Core Most recent 40-bit BMU resul t has odd parity.

10101 evenp EPAR = 1 Core Most recent 40-bit BMU resu lt has even pari ty.

10110 jobf JO BF = 1 JTAG jiob output buffer full.

10111 j ibe JIBE = 1 J TAG jiob input buffer empty.

11000 jcont JCONT = 1 JTAG JTAG continue.

11001 lock LOCK = 1 CLOCK PLL delay counter has reached zero.

11010 mgibe MGIBE = 1 MGU Input mes sage buff er register mgi is empty.

11011 mgobf MGOBF = 1 MGU Input message buff er register mgo is full.

11100 somef SOMEF = 1 BIO Some false, some input bits tested did not compare successful ly.

11101 somet SOMET = 1 BIO Some true, som e input bits test ed compared successfully.

11110 allf ALLF = 1 BIO All false, no BIO input bits tested compared successfully.

11111 allt ALLT = 1 BIO All true , al l BIO input bit s tested compare d successful ly.

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6.2 Reg is te rs

DSP16411 registers fall into one of the following three

categories:

■Directly program-ac cessible (or register-mapped)

registers are directly accessible in instructions and

are designate d with lower-case bold, e.g., timer0.

These re gisters are described in Section 6.2.1.

■Mem ory-map ped registers are accessible at a mem-

ory address and are designated with upper-case

bold, e.g., DSTAT. These registers are described in

Sect ion 6.2.2 on page 231.

■Pin-accessible registers are accessible only through

the external device pins and are designated with

upper-case bold, i.e., ID. Each JTA G port contain s

the pin-accessible identification register, ID,

described in Table 1 52 on page 241. This regis ter is

accessible via its associated JTAG port.

Note: The program counter (PC) is an addres sing reg-

ister not accessible to the programmer or

through external pins. The core automatical ly

controls this register to properly sequence the

instructions.

6.2.1 Directly Progra m-Ac cessibl e (Register-

Mapped) Registers

F igure 58 on page 2 28 depicts the directly program-

accessible (register-mappe d) registers. The figure dif-

ferentiates core and of f-core registers. As the figure

indicates, the pllcon, pllfrq, pllfrq1, and plld ly regis-

ters are available in CORE0 only.

Note: There is write-to-read latency associated with

the pipelined IDB. The assembler compensates

for thi s. S ee the

DSP16000 Dig ital Signal Pro-

cess o r C or e

Information Manual for further

details.

As shown in Figure 58 on page 228 , the register-

mappe d registers cons ist of three types:

Data registers store data either from the result of

instruction execution or from memo ry. Data registers

become source operands for instructions. This class of

registers also includes postincreme nt registers whose

contents are added to address registers to form new

addresses.

Co nt ro l an d Sta tus r egist ers are used t o deter m ine

the state of the machine or to set differen t configura-

tions to control the machine.

Address registers are used to hold memory location

point ers. In some ca ses, the user can treat address

registers as general-purpose dat a registe rs accessible

by data move instruc tions.

Table 139 on page 229 su mmarizes the register-

mapped registers. It lists all valid register designators

as they appear in an instruction syntax. For each reg-

ister, the table specifies its size, whether it i s readab le

or writable, its type, whet her it is sig ned or unsigned,

and the hardware function block in which it is located. It

also indicates whether the register is in the core or is

off-core. Off-core register-mapped regist ers canno t be

stored to memo ry in a single instruction. For example,

the fo llowing ins truct ion is not allo wed and w ill gener-

ate an error by the assembler:

*r0 = mgi // NOT ALLOWED

To store the contents of an of f-core register t o memory,

first store the register to an intermediate register and

then store the intermediate register to memory. See the

example below:

a0h = mgi // a0h is intermediate reg.

*r0 = a0h // store mgi to memory

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6.2 Reg is te rs (continued)

6.2.1 Directly Program -Accessible (R egister-M app ed) Registers (continued)

DS P16410B Program-Acce ssible R egisters for Each C ore

Figure 58. DSP 16411 P rog ram-Accessible Registers for Each Core

XAAU DAUSYS

YAAU

JTAG

auc0

psw0

CONTROL &

STATUS ADDRESS DATA

jiob

inc0

ins

cloop

alf

pt0 x

auc1

ar0

pt1

vbase

rb0

rb1

re0

re1

inc1

cstate

csave

ar1

ar2

ar3

ptrap

16 16

TIMER0

timer0c

timer0

BIO

TIMER1

DSP16000 CORE

CLOCKS

psw1

vsw

IMUX

imux

MGU

signal

pid

mgi

mgo

COR E 0 ON LY

CORE0

sbit

cbit

timer1c

timer1

pllfrq

plldly

pllcon

pllfrq1pllfrq1

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6.2 Reg is te rs (continued)

6.2.1 Directly Program -Accessible (R egister-M app ed) Registers (continued)

Table 139 . Program-Accessible (Register-Map ped ) Registers by Type, Listed Alphabetical ly

(Bits) R/W†Type‡Signed§/

Unsigned Core/

Off-Core Function

Block

a0, a1, a2, a3, a4, a5, a6, a7 Accumulators 0—7 40 R/W data signed core DAU

a0h, a1h, a2h, a3h,

a4h, a5h, a6h, a7h Accumulators 0—7,

high hal ves (bits 31—16) 16 R/W data signed core DAU

a0l, a1l, a2l, a3l,

a4l, a5l, a6l, a7l Accumulator s 0—7,

low halv es (bi ts 15—0) 16 R/W data signed core DAU

a0g, a1g, a2g, a3g,

a4g, a5g, a6g, a7g Accumulators 0—7,

guard bits (bits 39—32) 8 R/W data signed core DAU

a0_1h, a2_3h,

a4_5h, a6_7h Accu m u lator ve cto rs

(concatenated high halves

of two adjacent accu mu lators)

32 R/W data signed core DAU

alf AWAIT and fl ags 16 R/W c & s unsigned core SYS

ar 0 , ar1, ar 2, ar3 Au x ilia r y re g is te r s 0 — 3 16 R /W data s igned core DAU

auc0, auc1 Arithmetic unit control 16 R/W c & s unsigned core DAU

c0, c1 Counters 0 and 1 16 R/W data signed core DAU

c2 Counter holdi ng register 16 R/W data signed core DAU

cbit BIO contr ol 16 R/W cont rol unsigned off-core BIO

cloop Cache loop count 16 R/W data unsigned core SYS

csave Cache save 32 R/W control unsigned core SYS

cstate Cache state 16 R/W contr ol unsigned core SYS

hPoint er postincrement 20 R/W data signed core XAAU

iPoint er postincrement 20 R/W data signed core XAAU

imux Interrupt multiplex control 16 R/W contr ol unsigned off-core IMUX

inc0, inc1 Interrupt control 0 and 1 20 R/W control unsigned core SYS

ins Interrupt status 20 R/C†† status unsigned core SYS

jPointer postincr em ent/offset 20 R/W data signed core YAAU

jhb High byte of j (bit s 15—8) 8 R data unsigned core YAAU

jlb Low byte of j (bit s 7—0) 8 R data unsigned core YAAU

jiob JTAG test 32 R/W data unsigned off-core JTAG

kPointer postincr em ent/offset 20 R/W data signed core YAAU

mgi Core-to-core message input 16 R data unsigned off- core MGU

mgo Core-to-core message output 16 W data unsigned off-core MGU

p0 Product 0 32 R/W data signed core DAU

p0h High hal f of p0 ( bit s 31—16) 16 R/W data signed core DAU

p0l Low half of p0 (bits 15—0) 16 R/W data signed core DAU

p1 Product 1 32 R/W data signed core DAU

p1h High half of p1 (bit s 31—16) 16 R/W data signed core DAU

p1l Low half of p1 (bit s 15— 0) 16 R/W data signed core DAU

pi Program interrupt return 20 R/W address unsigned core XAAU

pid Processor identificat ion 16 R c & s unsigned off -core MGU

† R i ndi cat es that the regist er i s read abl e by i nstruct i ons; W in di cat es the regist er is writable by inst ructi ons.

‡ c & s m eans co nt rol and sta tus.

§ Signed registers are in two’s complement format.

†† C i ndi cates th at the regist er i s cleared and not set.

‡‡ T he I EN fie l d (bi t 14) of t he psw1 re gi ste r i s read only (writes to this bi t are ignored).

§§ T he VALUE [6:0] field (bi t s 6—0) are read only (w ri tes to these bits are ig nored).

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6 Software Architecture (continued)

6.2 Registers (continued)

Table 139. Prog ram-Accessible (Register-Map ped ) Registers by Type, Listed Alphabetical ly (continued)

6.2.1 Directly Program -Accessible (R egister-M app ed) Registers (cont inued )

pllcon Phase-lock loop control

(CORE0 only) 16 R/W control unsigned off-core Clocks

plldly Phase-lock loop delay control

(CORE0 only) 16 R/W control unsigned off-core Clocks

pllfrq, pllfrq1 Phase-lock loop frequency control

(CORE0 only) 16 R/W control unsigned off-core Clocks

pr Subroutine return 20 R/W address unsigned core XAAU

psw0, psw1 Program status words 0 and 1 16 R/W‡‡ c & s unsigned core DAU

pt0, pt1 Pointers 0 and 1 to X-memory space 20 R/W address unsigned core XAAU

ptrap Pr ogram trap r eturn 20 R/W address unsigned core XAAU

r0 , r1, r2, r3,

r4, r5, r6, r7 Point ers 0—7 to Y-memory space 20 R/W address unsigned core YAAU

rb0 , rb 1 Circular buffer point ers 0 and 1

(begin address) 20 R/W address unsigned core YAAU

re0, re1 Circular buff er point ers 0 and 1

(end address) 20 R/W address unsigned core YAAU

sbit BIO stat us/contro l 16 R/W§§ c & s unsigned off-core BIO

signal Core-to-core signal 16 W control unsigned off- core MGU

sp Stack pointer 20 R/W address unsigned core YAAU

timer0, timer1 T imer running count 0 and 1

fo r Timer0 a nd Ti mer1 16 R/W data unsigned off-core Timer

tim e r0 c, tim e r1 c Timer control 0 and 1

fo r Timer0 a nd Ti mer1 16 R/W control unsigned off-core Timer

vbase Vector base offset 20 R/W address unsigned core XAAU

vsw Viterbi support word 16 R/W control unsigned core DAU

xMulti plier input 32 R/W data signed core DAU

xh High hal f of x (bits 31—16) 16 R/W data signed core DAU

xl Low half of x (bits 15—0) 16 R/W data signed core DAU

yMulti plier input 32 R/W data signed core DAU

yh High hal f of y (bits 31—16) 16 R/W data signed core DAU

yl Low half of y (bits 15—0) 16 R/W data signed core DAU

(Bits) R/W†Type‡Signed§/

Unsigned Core/

Off-Core Function

Block

† R i ndi cat es that the regist er i s read abl e by i nstruct i ons; W in di cat es the regist er i s writ abl e by inst ructi ons.

‡ c & s m eans co nt rol and sta tus.

§ Signed registers are in two’s complement format.

†† C i ndi cates th at the regist er i s cleared and not s et.

‡‡ Th e IEN field (bi t 14) of t he psw1 re gi ste r i s read only (writes to this bi t are ignored).

§§ Th e VALUE [6: 0] fiel d (bi t s 6—0) are read only (w ri tes to t hese b its are ignored).

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6 Software Architecture (continued)

6.2 Reg is te rs (continued)

6.2.2 Memory -Map ped Registers

The memory-mapped registers located in their associated peripherals are each mapped to an even address. The

sizes of these registers are 16 bits, 20 bit s, or 32 bits. A regist er that is 20 bits or 32 bits mus t be accessed as an

aligned double word. A register that is 16 bits can be accessed as a single word with an even address or as an

aligned double word with the same even address. If a register that is 1 6 bits or 20 bi ts is accessed as a double

word, the contents of the reg ister are right-justified. Mem ory-mappe d registers have the same internal format as

other registers and are diff erent from memory. Figure 59 illustr at es three mem ory -m apped r egist ers .

Figure 59. Example Memory-Mapped Registers

Note: Accessing memory-mapped registers with an odd address yields undefined results. The memory-m apped

registers are defined by name and equated to t hei r even memo ry addresses in the include file that i s pro-

vided with the

LUxWORKS

tools, 16411_mmregs.h. To dif ferentiate the memory-mapped registers for SIU0

and SIU1, 16411_mmregs.h appends the suff ix _U0 or _U1 to the register name. For example,

16411_mmregs.h defines SCON0_U0 as the address for the SIU0 SCON0 registe r and FSTAT_U1 as the

address for the SIU1 FSTAT registe r.

Memory-mapped regist ers are designated with upper-case bold. Fo r example, the 32-bit DMAU status register

DSTAT is mapped to address 0x4206C. The code segm ent example below acce sses DSTAT:

r0 = 0x4206C // Address of DSTAT.

nop

a0 = *r0 // Copy the contents of DSTAT to a0.

Alternatively:

#include "16411_mmregs.h"

r0 = DSTAT // Address of DSTAT (DSTAT defined as 0x4206C in 16411_mmregs.h).

nop

a0 = *r0 // Copy the contents of DSTAT to a0.

After the above code segme nt executes , the register a0 contains the value stored in DSTAT. T he periph erals that

contain memory-m apped registers are lis ted below:

■DMAU (See Table 140 on page 232).

■SEMI (See Table 141 on page 233).

■PIU (See Table 142 on page 234 ).

■SIU0 and SIU1 (See Table 143 on page 234.)

CTL00x42060

0x4206C

ADDRESS

16 bits

32 bits

20 bits

SBAS0

DSTAT

0x42040

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6 Software Architecture (continued)

6.2 Reg is te rs (continued)

6.2.2 Memory -Map ped Registers (continued)

Table 140 summarizes the DMAU memory-mapped registers. These registers are described in detail in

Section 4. 13.2 on page 67.

Table 140. DMAU Memor y-Mappe d Registers

Type Register

Name Channel Address Size

(Bits) R/W Type Signed/

Unsigned Reset

Value†

DMAU Status DSTAT All 0x4206C 32 R status unsigned X

DMAU Master Control 0 DMCON0 All 0x4205C 16 R/W control unsigned 0

DMAU Master Control 1 DMCON1 All 0x4205E

Channel Cont rol CTL0 SWT0 0x42060 16 R/W control unsigned X

CTL1 SWT1 0x42062

CTL2 SWT2 0x42064

CTL3 SWT3 0x42066

CTL4 MMT4 0x42068

CTL5 MMT5 0x4206A

Source Address SADD0 SWT0 0x42000 32 R/W address unsigned X

Destination Address DADD0 0x42002

Source Address SADD1 SWT1 0x42004

Destination Address DADD1 0x42006

Source Address SADD2 SWT2 0x42008

Destination Address DADD2 0x4200A

Source Address SADD3 SWT3 0x4200C

Destination Address DADD3 0x4200E

Source Address SADD4 MMT4 0x42010

Destination Address DADD4 0x42012

Source Address SADD5 MMT5 0x42014

Destination Address DADD5 0x42016

Source Count SCNT0 SWT0 0x42020 20 R/W data unsigned X

Destination Count DCNT0 0x42022

Source Count SCNT1 SWT1 0x42024

Destination Count DCNT1 0x42026

Source Count SCNT2 SWT2 0x42028

Destination Count DCNT2 0x4202A

Source Count SCNT3 SWT3 0x4202C

Destination Count DCNT3 0x4202E

Source Count SCNT4 MMT4 0x42030

Destination Count DCNT4 0x42032

Source Count SCNT5 MMT5 0x42034

Destination Count DCNT5 0x42036

† For this colum n, X indicate s unkn own on powerup res et and unaff ect ed on subse quent res et. Any re served fi el ds wi t hi n t he regi ster are reset to zero.

‡ T he rei ndex register s are in sign-m agni tud e format.

6 Software Architecture (continued)

6.2 Registers (continued)

Table 140 . D MAU Memor y-Mappe d Registers (continued)

6.2.2 Memory -Map ped Registers (continued)

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Table 141 sum marizes the SEMI memory-m apped registers . T hese registers are described in detail in

Section 4. 14. 4 on page 110.

Table 141 . SEMI Memor y-Mapped Registers

Limit LIM0 SWT0 0x42050 20 R/W data unsigned X

LIM1 SWT1 0x42052

LIM2 SWT2 0x42054

LIM3 SWT3 0x42056

LIM4 MMT4 0x42058

LIM5 MMT5 0x4205A

Source Base SBAS0 SWT0 0x42040 20 R/W address unsigned X

Destination Base DBAS0 0x42042

Source Base SBAS1 SWT1 0x42044

Destination Base DBAS1 0x42046

Source Base SBAS2 SWT2 0x42048

Destination Base DBAS2 0x4204A

Source Base SBAS3 SWT3 0x4204C

Destination Base DBAS3 0x4204E

Stride STR0 SWT0 0x42018 16 R/W data unsigned X

STR1 SWT1 0x4201A

STR2 SWT2 0x4201C

STR3 SWT3 0x4201E

Reindex RI0 SWT0 0x42038 20 R/W data signed‡X

RI1 SWT1 0x4203A

RI2 SWT2 0x4203C

RI3 SWT3 0x4203E

(Bits) R/W Type Reset Value

ECON0 0x40000 SEMI Contro l 16 R/W Contr ol 0x0FFF

ECON1 0x40002 SEMI Status and Control 16 R/W†

† Some bi ts in t hi s regis ter ar e read-only or writ e-onl y.

Control 0‡

‡ With the fol l owin g exce pt i ons: ECON1[6,4 ] ar e a reflect i on of the sta te o f ex t ernal pi ns and are unaff ected by reset, and ECON1[5] i s se t.

EXSEG0 0x40004 External X Segment Regist er f or CORE0 16 R/W Address 0

EYSEG0 0x40006 External Y Segment Regist er f or CORE0

EXSEG1 0x40008 External X Segment Regist er f or CORE1

EYSEG1 0x4000A Exter nal Y Segment Register for CORE1

Type Register

Name Channel Address Size

(Bits) R/W Type Signed/

Unsigned Reset

Value†

† For this colum n, X indicate s unkn own on powerup res et and unaff ect ed on subse quent res et. Any re served fi el ds wi t hi n t he regi ster are reset to zero.

‡ T he rei ndex register s are in sign-m agni tud e format.

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6 Software Architecture (continued)

6.2 Reg is te rs (continued)

6.2.2 Memory -Map ped Registers (continued)

Table 142 summarizes the PIU memory-mapped registers. These registers are described in detail in

Section 4. 15.1 on page 135.

Table 142. PIU Registers

Table 143 summarizes the SIU memory-mapped registers. These registers are described in detail in

Section 4. 16.15 on page 184.

Table 143. SIU Mem ory-Mapp ed Registers

(Bits) R/W Type†Reset Value‡

PCON 0x41000 PIU Control and St atus 32 R/W§c & s 0x 5

PDI 0x41008 PIU Data In from Host 32 R data X

PDO 0x4100A PIU Data Out to Host R/W

PA 0x41004 PIU Address for Host Access to DSP Memory 32 R/W address 0x0

DSCRATCH 0x41002 DSP Scratch 32 R/W data 0x0

HSCRATCH 0x41006 Host Scratch R

† c & s mean s control and sta tu s.

‡ For thi s column, X indi cat es unk nown on power up reset and unaff ected on subseq uent reset .

§ Some bi ts of PCON are read-only and s om e bi ts are writable by eit her the host or th e DS P, but not both.