N ESIG W D CT E N F OR OD U D ED U T E PR N E S TI T 19 OM M REC LE SUB , ISL224Data Sheet T O 6 N SIB L2241 P OS IS X9421 S (R) Low Noise/Low Power/SPI Bus January 14, 2009 FN8196.4 Single Digitally Controlled (XDCPTM) Potentiometer Features Description * 64 Resistor Taps The X9421 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. * SPI Serial Interface for Write, Read, and Transfer Operations of the Potentiometer The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. * 4 Non-Volatile Data Registers The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. * Single Voltage Potentiometer * Wiper Resistance, 150 Typical at 5V * Non-Volatile Storage of Multiple Wiper Positions * Power-on Recall. Loads Saved Wiper Position on Power-up. * Standby Current < 5A Max * VCC : 2.7V to 5.5V Operation * 2.5k, 10k End to End Resistance * 100 yr. Data Retention * Endurance: 100, 000 Data Changes per Bit per Register * 14 Ld TSSOP, 16 Ld SOIC * Low Power CMOS * Pb-Free Available (RoHS Compliant) Block Diagram VCC ADDRESS DATA STATUS SPI BUS INTERFACE RH/VH WRITE READ TRANSFER INC / DEC WIPER COUNTER REGISTER (WCR) BUS INTERFACE & CONTROL CONTROL VSS 1 10k POWER-ON RECALL WIPER 64-TAPS POT DATA REGISTERS 4 BYTES RW/VW RL/VL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9421 Ordering Information PART NUMBER PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (C) 5 10% 2.5 0 to +70 16 Ld SOIC (300 mil) 16 Ld SOIC (300 mil) (Pb-Free) PACKAGE X9421YS16* X9421YS X9421YS16Z* (Note) X9421YS Z 0 to +70 X9421YS16I* X9421YS I -40 to +85 16 Ld SOIC (300 mil) X9421YS16IZ* (Note) X9421YS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) X9421YV14* X9421 YV 0 to +70 14 Ld TSSOP (4.4mm) X9421YV14Z* (Note) X9421 YVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) X9421YV14I* X9421 YV I -40 to +85 14 Ld TSSOP (4.4mm) X9421YV14IZ* (Note) X9421 YVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) X9421WS16* X9421WS X9421WS16Z* (Note) 10 0 to +70 16 Ld SOIC (300 mil) X9421WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-Free) X9421WS16I* X9421WS I -40 to +85 16 Ld SOIC (300 mil) X9421WS16IZ* (Note) X9421WS ZI -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) X9421WV14* X9421 WV 0 to +70 14 Ld TSSOP (4.4mm) X9421WV14Z* (Note) X9421 WV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) X9421WV14I* X9421 WV I -40 to +85 14 Ld TSSOP (4.4mm) X9421WV14IZ* (Note) X9421 WVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) X9421YS16-2.7* X9421YS F X9421YS16Z-2.7* (Note) 2.7 to 5.5 2.5 0 to +70 16 Ld SOIC (300 mil) X9421YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-Free) X9421YS16I-2.7* X9421 YS G -40 to +85 16 Ld SOIC (300 mil) X9421YS16IZ-2.7* (Note) X9421 YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) X9421YV14-2.7* X9421 YVF 0 to +70 14 Ld TSSOP (4.4mm) X9421YV14Z-2.7* (Pb-free) X9421 YVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) X9421YV14I-2.7* X9421 YVG -40 to +85 14 Ld TSSOP (4.4mm) X9421YV14IZ-2.7* (Pb-free) X9421 YVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) X9421WS16-2.7* X9421WS F X9421WS16Z-2.7* (Note) 10 0 to +70 16 Ld SOIC (300 mil) X9421WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-Free) X9421WS16I-2.7* X9421WS G -40 to +85 16 Ld SOIC (300 mil) X9421WS16IZ-2.7* (Note) X9421WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) X9421WV14-2.7* X9421 WVF 0 to +70 14 Ld TSSOP (4.4mm) X9421WV14Z-2.7* (Pb-free) X9421 WVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) X9421WV14I-2.7* X9421 WVG -40 to +85 14 Ld TSSOP (4.4mm) -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) X9421WV14IZ-2.7* (Pb-free) X9421 WVZG *Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 2 FN8196.4 January 14, 2009 X9421 Detailed Functional Diagrams VCC DR0 DR1 CS SO SI 10k 64-taps WIPER HOLD SCK POWER-ON RECALL CONTROL INTERFACE AND CONTROL CIRCUITRY A0 COUNTER REGISTER (WCR) DR2 DR3 RH/VH RL/VL RW/VW D ATA WP VSS Circuit Level Applications System Level Applications * Vary the Gain of a Voltage Amplifier * Adjust the contrast in LCD displays * Provide Programmable DC Reference Voltages for Comparators and Detectors * Control the Power Level of LED Transmitters in Communication Systems * Control the Volume in Audio Circuits * Set and Regulate the DC Biasing Point in an RF Power Amplifier in Wireless Systems * Trim Out the Offset Voltage Error in a Voltage Amplifier Circuit * Set the Output Voltage of a Voltage Regulator * Control the Gain in Audio and Home Entertainment Systems * Trim the Resistance in Wheatstone Bridge Circuits * Provide the Variable DC Bias for Tuners in RF Wireless Systems * Control the Gain, Characteristic Frequency and Q-factor in Filter Circuits * Set the Operating Points in Temperature Control Systems * Set the Scale Factor and Zero Point in Sensor Signal Conditioning Circuits * Vary the Frequency and Duty Cycle of Timer ICs * Control the Operating Point for Sensors in Industrial Systems * Trim Offset and Gain Errors in Artificial Intelligent Systems * Vary the DC Biasing of a Pin Diode Attenuator in RF Circuits * Provide a Control Variable (I, V, or R) in Feedback Circuits 3 FN8196.4 January 14, 2009 X9421 X9421 (16 LD SOIC) TOP VIEW X9421 (14 LD TSSOP) TOP VIEW S0 1 14 VCC NC 1 16 VCC NC 2 13 RL/VL SO 2 15 NC NC 3 14 RL/VL CS 4 13 RH/VH NC 3 12 RH/VH CS 4 11 RW/VW SCK 5 10 HOLD SI 6 9 A0 NC 7 10 AO VSS 7 8 WP VSS 8 9 WP SCK 5 SI 6 12 RW/VW 11 ISEN Pin Assignments TSSOP PIN NO. SOIC PIN NO. SYMBOL 1 2 SO Serial Data Output 2, 3 3, 1, 7, 5 NC No Connect 4 4 CS Chip Select 5 5 SCK Serial Clock 6 6 SI Serial Data Input 7 8 VSS System Ground 8 9 WP Hardware Write Protect 9 10 A0 Device Address 10 DESCRIPTION HOLD Device select. Pause the serial bus. 11 12 RW/VW Wiper Terminal of the Potentiometer. 12 13 RH/VH High Terminal of the Potentiometer. 13 14 RL/VL Low Terminal of the Potentiometer. 14 16 VCC System Supply Voltage Pin Descriptions CHIP SELECT (CS) Host Interface Pins SERIAL OUTPUT (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the potentiometer and pot register are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9421. 4 When CS is HIGH, the X9421 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9421, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. FN8196.4 January 14, 2009 X9421 DEVICE ADDRESS (A0) The address input is used to set the least significant bit of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9421. A maximum of two devices may occupy the SPI serial bus. Potentiometer Pins VH/RH, VL/RL The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW The wiper output is equivalent to the wiper output of a mechanical potentiometer. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Writing to the Wiper Counter Register is not restricted. SYSTEM/DIGITAL SUPPLY (VCC) VCC is the supply voltage for the system/digital section. VSS is the system ground. Principles of Operation The X9421 is a highly integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the XDCP potentiometer. Serial Interface The X9421 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. enable, one of sixty-four switches. The block diagram of the potentiometer is shown in Figure 1. Wiper Counter Register (WCR) The X9421 contains a Wiper Counter Register. The WCR can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9421 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers The potentiometer has four 6-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Register Descriptions TABLE 1. DATA REGISTERS, (6-BIT), NONVOLATILE 0 0 D5 D4 D3 D2 (MSB) D1 D0 (LSB) There are four 6-bit Data Registers associated with the potentiometer. Array Description The X9421 is comprised of one resistor array containing 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within the individual array only one switch may be turned on at a time. * {D5~D0}: These bits are for general purpose Nonvolatile data storage or for storage of up to four different wiper values. TABLE 2. WIPER COUNTER REGISTER, (6-BIT), VOLATILE 0 0 (MSB) WP5 WP4 WP3 WP2 WP1 WP0 (LSB) * {WP5~WP0}: These bits specify the wiper position of the potentiometer. These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and 5 FN8196.4 January 14, 2009 X9421 SERIAL DATA PATH VH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 0 8 REGISTER 2 C O U N T E R REGISTER 1 6 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) REGISTER 3 D E C O D E INC/DEC LOGIC IF WCR = 00[H] THEN VW = VL IF WCR = 3F[H] THEN VW = VH UP/DN MODIFIED SCK UP/DN VL CLK VW FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM Write In Process The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. DEVICE TYPE IDENTIFIER 0 1 0 1 1 1 0 A0 DEVICE ADDRESS FIGURE 2. ADDRESS/IDENTIFICATION BYTE FORMAT Instructions Instruction Byte Address/Identification (ID) Byte The first byte sent to the X9421 from the host, following a CS going HIGH to LOW, is called the Address or Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9421 this is fixed as 0101[B] (refer to Figure 2). The least significant bit in the ID byte selects one of two devices on the bus. The physical device address is defined by the state of the A0 input pin. The X9421 compares the serial data stream with the address input state; a successful compare of the address bit is required for the X9421 to successfully continue the command sequence. The A0 input can be actively driven by a CMOS input signal or tied to VCC or VSS. The remaining three bits in the ID byte must be set to 110. 6 The next byte sent to the X9421 contains the instruction and register pointer information. The four most significant bits are the instruction. The next two bits point to one of four Data Registers. The format is shown below in Figure 3. REGISTER SELECT I3 I2 I1 I0 R1 R0 0 0 INSTRUCTIONS FIGURE 3. INSTRUCTION BYTE FORMAT The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits are defined as 0. FN8196.4 January 14, 2009 X9421 Registers or directly between the host and the WCR. These instructions are: Two of the eight instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: * Read Wiper Counter Register--read the current wiper position of the pot, * XFR Data Register to Wiper Counter Register --This instruction transfers the contents of one specified Data Register to the Wiper Counter Register. * Write Wiper Counter Register--change current wiper position of the pot, * XFR Wiper Counter Register to Data Register--This instruction transfers the contents of the Wiper Counter Register to the specified associated Data Register. * Read Data Register--read the contents of the selected data register; * Write Data Register--write a new value to the selected data register. The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. * Read Status--This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 5 and Figure 6. The final command is Increment/Decrement. It is different from the other commands, because it's length is indeterminate. Once the command is issued, the master can clock the wiper up and/or down in one resistor segment step; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 7 and 8. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9421; either between the host and one of the Data CS SCK SI 0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0 FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE CS SCL SI 0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0 0 0 D5 D4 D3 D2 D1 D0 FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE (WRITE) 7 FN8196.4 January 14, 2009 X9421 CS SCL SI DON'T CARE 0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0 S0 0 0 D5 D4 D3 D2 D1 D0 FIGURE 6. THREE-BYTE INSTRUCTION SEQUENCE (READ) CS SCK SI 0 1 0 1 1 1 0 A0 I3 I2 I1 I0 0 0 0 0 I N C 1 I N C 2 I N C n D E C 1 D E C n FIGURE 7. INCREMENT/DECREMENT INSTRUCTION SEQUENCE tWRID SCK SI VOLTAGE OUT VW INC/DEC CMD ISSUED FIGURE 8. INCREMENT/DECREMENT TIMING LIMITS 8 FN8196.4 January 14, 2009 X9421 TABLE 3. INSTRUCTION SET INSTRUCTION SET INSTRUCTION I3 I2 I1 I0 R1 R0 OPERATION Read Wiper Counter Register 1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register Write Wiper Counter Register 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by R1 - R0 Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by R1 - R0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by R1 R0 to the Wiper Counter Register XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register to the Data Register pointed to by R1 - R0 Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter Register Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by checking the WIP bit. Instruction Format NOTES: 1. "A0": stands for the device addresses sent by the master. 2. WPx refers to wiper position data in the Wiper Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). 3. "D": stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register (WCR) DEVICE TYPE IDENTIFIER CS FALLING EDGE 0 1 0 1 DEVICE ADDRESSES 1 1 0 INSTRUCTION OPCODE A0 1 0 0 WIPER POSITION (SENT BY X9421 ON SO) 1 0 0 0 0 0 0 WP5 WP4 WP3 WP2 WP1 WP0 CS RISING EDGE Write Wiper Counter Register (WCR) DEVICE TYPE IDENTIFIER CS FALLING EDGE 0 1 0 1 DEVICE ADDRESSES 1 1 0 INSTRUCTION OPCODE A0 1 0 1 DATA BYTE (SENT BY HOST ON SI) 0 0 0 0 0 0 0 WP5 WP4 WP3 WP2 WP1 WP0 CS RISING EDGE Read Data Register (DR) Read the contents of the Register pointed to by R1 - R0. CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE 0 1 1 1 0 1 1 0 A0 0 1 1 REGISTER ADDRESSES R1 R0 0 DATA BYTE (SENT BY X9421 ON SO) 0 0 0 WP5 WP4 WP3 WP2 CS RISING WP1 WP0 EDGE Write Data Register (DR) Write a new value to the Register pointed to by R1 - R0. DEVICE TYPE IDENTIFIER CS FALLING 0 EDGE 1 0 1 DEVICE ADDRESSES INSTRUCTION OPCODE REGISTER ADDRESSES 1 1 R 1 1 9 0 A 0 1 0 0 R 0 0 0 DATA BYTE (SENT BY HOST ON SI) 0 0 WP WP WP 5 4 3 WP 2 WP 1 WP 0 CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE FN8196.4 January 14, 2009 X9421 Transfer Data Register (DR) to Wiper Counter Register (WCR) Transfer the contents of the Register pointed to by R1 - R0 to the WCR. CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES 1 1 0 A0 INSTRUCTION OPCODE 1 1 0 REGISTER ADDRESSES 1 R1 R0 0 CS RISING EDGE 0 Transfer Wiper Counter Register (WCR) to Data Register (DR) CS FALLIN G EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE 0 1 1 1 0 1 1 0 A0 1 1 REGISTER ADDRESSES 0 R1 R0 0 0 CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE Increment/Decrement Wiper Counter Register (WCR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES 1 1 0 INSTRUCTION OPCODE A0 0 0 1 INCREMENT/DECREMENT (SENT BY MASTER ON SDA) 0 0 0 0 0 I/D I/D . . . . I/D I/D CS RISING EDGE Read Status CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE 0 1 0 1 0 1 1 10 0 A0 1 0 1 DATA BYTE (SENT BY X9421 ON SO) 0 0 0 1 0 0 0 0 0 0 0 CS W RISING IP EDGE FN8196.4 January 14, 2009 X9421 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC Limits) X9421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% X9421-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Voltage on SCK, SDA any address input with respect to VSS: . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V V = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Any VH/RH, VL/RL, VW/RW . . . . . . . . . . . . . . . . . . . . . VSS to VCC Thermal Resistance (Typical, Note 1) JA (C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details Analog Specifications (Over recommended operating conditions unless otherwise stated.) LIMITS SYMBOL Rtotal RW VTERM PARAMETER TEST CONDITIONS End to End Resistance Tolerance MIN. (Note 5) TYP. (Note 6) -20 MAX. (Note 5) UNITS +20 % 50 mW Power Rating +25C, each pot Wiper Resistance Wiper Current Iw = (VH - VL)/RTOTAL, VCC = 5V 150 250 Wiper Current Iw = (VH - VL)/RTOTAL, VCC = 3V 400 1000 VCC V Voltage on any VH/RH, VL/RL, VSS = 0V VW/RW VSS Noise Ref: 1kHz -120 dBV Resolution (Note 4) (Note 5) 1.6 % Absolute Linearity (Note 1) Vw(n)(actual) - Vw(n)(expected) Relative Linearity (Note 2) Vw(n + 1) - [Vw(n) + MI] Temperature Coefficient of RTOTAL (Note 5) 300 ppm/C Ratio metric Temperature Coefficient (Note 5) 20 ppm/C CH/CL/CW Potentiometer Capacitances See "Circuit #3 SPICE Macro Model" on page 13 10/10/25 pF IAL Rh, RI, Rw leakage current VIN = VSS to VCC. Device is in stand-by mode. 0.1 11 -1 +1 MI (Note 3) -0.2 +0.2 MI (Note 3) 10 A FN8196.4 January 14, 2009 X9421 DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified). LIMITS SYMBOL PARAMETER MIN (Note 5) TEST CONDITIONS TYP (Note 6) MAX (Note 5) UNITS ICC1 VCC Supply Current (Active) fSCK = 2MHz, SO = Open, Other Inputs = VSS 400 A ICC2 VCC Supply Current (Nonvolatile Write) fSCK = 2MHz, SO = Open, Other Inputs = VSS 3.5 mA ISB VCC Current (Standby) SCK = SI = VSS, Addr. = VSS 3 A ILI Input Leakage Current VIN = VSS to VCC 10 A ILO Output Leakage Current VOUT = VSS to VCC 10 A VIH Input HIGH Voltage VCC x 0.7 VCC + 0.3 V VIL Input LOW Voltage -0.5 VCC x 0.1 V VOL Output LOW Voltage 0.4 V IOL = 3mA ENDURANCE AND DATA RETENTION PARAMETER MIN Minimum Endurance 100,000 Data Retention 100 UNITS Data Changes per Bit per Register Years CAPACITANCE SYMBOL COUT (Note 5) CIN (Note 5) TEST TYP UNITS TEST CONDITIONS Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (A0, SI, and SCK) 6 pF VIN = 0V MIN MAX UNITS 0.2 50 V/msec POWER-UP TIMING SYMBOL tRVCC(Note 5) PARAMETER VCC Power-up Ramp NOTES: 1. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 2. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT/63 or (VH - VL)/63, single pot 4. Typical = Individual array resolution. 5. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 6. Limits should be considered typical and are not production tested. 7. This parameter is not production tested. Parameter established by characterization. Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC and then the potentiometer pins, RH, RL, and RW. Voltage should not be applied to the potentiometer pins before VCC is applied. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper 12 position will not be complete until VCC reaches its final value. FN8196.4 January 14, 2009 X9421 AC Test Conditions Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 Equivalent AC Load Circuit 5V 2.7V 1533 SDA Output 100pF 100pF Circuit #3 SPICE Macro Model RTOTAL RH CL CH CW 10pF RL 10pF 25pF RW 13 FN8196.4 January 14, 2009 X9421 AC Timing SYMBOL PARAMETER MIN (Note 5) TYP (Note 6) MAX (Note 5) UNITS 2.0 MHz fSCK SSI/SPI Clock Frequency tCYC SSI/SPI Clock Cycle Time 500 ns tWH SSI/SPI Clock High Time 200 ns tWL SSI/SPI Clock Low Time 200 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SI, SCK, HOLD and CS Input Setup Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI(7) SI, SCK, HOLD and CS Input Rise Time 2 s tFI(7) SI, SCK, HOLD and CS Input Fall Time 2 s tDIS SO Output Disable Time 500 ns 150 ns 0 tV SO Output Valid Time tHO SO Output Hold Time tRO SO Output Rise Time 50 ns tFO SO Output Fall Time 50 ns 0 ns tHOLD HOLD Time 400 ns tHSU HOLD Setup Time 100 ns tHH HOLD Hold Time 100 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS Deselect Time 2 s tWPASU WP, A0 and A1 Setup Time 0 ns tWPAH WP, A0 and A1 Hold Time 0 ns High-Voltage Write Cycle Timing SYMBOL tWR PARAMETER High-voltage Write Cycle Time (Store Instructions) TYP (NOTE 6) MAX (NOTE 5) UNITS 5 10 ms XDCP Timing SYMBOL tWRPO PARAMETER MIN MAX (NOTE 5) (NOTE 5) UNITS Wiper Response Time After The Power Supply Is Stable 10 s tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 10 s tWRID Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction) 10 s 14 FN8196.4 January 14, 2009 X9421 Symbol Table WAVEFORM INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM LOW TO HIGH WILL CHANGE FROM LO W TO HIGH MAY CHANGE FROM HIGH TO LOW WILL CHANGE FROM HIGH TO LOW DON'T CARE: CHANGES ALLOWED CHANGING: STATE NOT KNOWN N/A CENTER LINE IS HIGH IMPEDANCE Timing Diagrams Input Timing tCS CS SCK tSU tH ... tWH tWL tRI tFI ... MSB SI tLAG tCYC tLEAD LSB HIGH IMPEDANCE SO Output Timing CS SCK ... tV MSB SO SI tHO tDIS ... LSB ADDR 15 FN8196.4 January 14, 2009 X9421 Hold Timing CS tHSU tHH SCK ... tRO tFO SO tHZ tLZ SI tHOLD HOLD XDCP Timing (for All Load Instructions) CS SCK ... tWRL SI ... MSB LSB VW SO HIGH IMPEDANCE XDCP Timing (for Increment/Decrement Instruction) CS SCK ... tWRID ... VW SI SO ADDR INC/DEC INC/DEC ... HIGH IMPEDANCE 16 FN8196.4 January 14, 2009 X9421 Write Protect and Device Address Pins Timing (ANY INSTRUCTION) CS tWPASU tWPAH WP A0 A1 Applications information 2. The flexibility of computer-based digital controls) 1. Electronic potentiometers provide three powerful application advantages: The variability and reliability of a solid-state potentiometer, 3. the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers VR VR VH VW VL I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER 17 TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT FN8196.4 January 14, 2009 X9421 Application Circuits BUFFERED REFERENCE VOLTAGE CASCADING TECHNIQUES R1 +V +V +5V +V VS +5V VW VW VO - -5V VOUT = VW - LM308A + X OP-07 + NONINVERTING AMPLIFIER VW R2 +V -5V R1 VW (a) OFFSET VOLTAGE ADJUSTMENT VOLTAGE REGULATOR VIN VO (REG) 317 R1 COMPARATOR WITH HYSTERITISIS R2 VS VS - + 100k R1 VO - VO + 10k 10k 10k VO (REG) = 1.25V (1+R2/R1)+Iadj R2 +12V } TL072 R2 } Iadj 18 VO = (1+R2/R1)VS (b) R1 R2 VUL = {R1/CR1+R2} VO(max) VLL = {R1/CR1+R2} VO(min) -12V FN8196.4 January 14, 2009 X9421 Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- e A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE A2 c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX 14 0o 14 7 8o Rev. 2 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 19 FN8196.4 January 14, 2009 X9421 Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E -B1 2 3 L SEATING PLANE -A- A D h x 45 -C- e A1 B C 0.10(0.004) 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS 16 0 16 8 0 7 8 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8196.4 January 14, 2009