16K x 8/9 Dual-Port Static RAM
with Sem, Int, Bus
y
CY7C006
CY7C016
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Februar
y
1995 – Revised Nov em ber 1996
Features
• True Dual-Ported memory cells which allow
simultaneous reads of the same memory location
• 16K x 8 organization (CY7C006)
• 16K x 9 organization (CY7C016)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Lo w operating power: ICC = 140 mA (typ.)
• Fully asynchronous operation
• Automatic power-down
• T TL c om p at ib le
• Exp andable data b us to 16/18 bit s or mor e using
Master/Sla ve chip select when using more than one
device
• Busy arbitration scheme provided
• Semaph ores inclu ded to permit software hand shaking
between ports
•INT
flag f or port-t o-port communication
• Avail able in 68-pi n PLCC, 64- pin (7C006) and 80-pin
(7C016)TQFP
• Pin compatible and functional equiva lent to
IDT7006/IDT7016
Functional Description
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration
schemes are included on the CY7C006/016 to handle situa-
tions when mult iple pr ocessors ac cess the s ame piec e of data .
Two ports are pro vided permitting i ndependent, async hronous
access for reads and writes to any location in memory. The
CY7C006/016 can be utilized as a standalone 128-/144-Kbit
dual-por t static RAM or multi pl e devices can be com bi ned in
order to function as a 16-/18-bit or wider master/slave du-
al-port static RAM. An M/S pin is provided for implementing
16-/18-bit or wider memory applications without the need for
separa te master and sla ve devices or addition al discret e log ic .
Application areas include interprocessor/multiprocessor de-
signs, communications status buffering, and dual-port vid-
eo/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write en able (R/W) , and ou tpu t enable (OE). T wo flags,
BUSY and INT, are provided on each port . BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communicati on between ports or systems by m eans of a mail
box. The semaphores are used to pass a flag, or t oken, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared latch-
es. Only one side can control the latch (semaphore) at any
time . Con trol of a semapho re indi cates that a share d resour ce
is i n use. An automatic power-do wn featur e is controlled inde-
pendently on each port by a chip enable (CE) pin or SEM pin .
The CY7C006 and CY7C016 are available in 68-pin PLCCs,
and 64- pin (7C006) TQFP and 80-pin (7C016) TQFP.
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
C006-1
R/WL
CEL
OEL
A13L
A0L A0R
A13R
R/W R
CER
OER
CER
OER
CEL
OEL
R/WLR/WR
I/O7L
I/O0L
I/O7R
I/O0R
INTERRUPT
SEMAPHORE
ARBITRATION
CONTROL
I/O CONTROL
I/O
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
DECODER
SEMLSEMR
BUSYLBUSYR
INTLINTR
M/S
(7C016)I/O8L I/O8R(7C016)
[1,2]
[1,2]
[2]
[2]
Logic Block Diagram
with Sem, Int, Busy
CY7C006
CY7C016
2
Pin Configurations
Note:
3. I/O for 7C016 only.
64-Pin TQFP
Top Vie w
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 50
32 49
16
GND
OER
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
GND
VCC
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
BUSYR
M/S
A0R
A1R
A2R
A3R
A4R
INTL
INTR
I/O7R
A5R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A13R
CER
SEMR
R/WR
VCC
OEL
I/O1L
I/O0L
A5L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A13L
CEL
SEML
R/WL
CY7C006
C006-2
Top Vie w
68-Pin PLCC
VCC
OEL
I/O1L
I/O0L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A13L
CEL
SEML
R/WL
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
GND
VCC
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
BUSYR
M/S
A0R
A1R
A2R
A3R
A4R
INTL
INTR
GND
OER
I/O7R
A5R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A13R
CER
SEMR
R/WR
A5L
NC
NC(I/O8L )
NC
I/O6R
CY7C006/16
24
25
26
10
11
12
13
14
15
48
47
46
45
44
40
41
27
42
28
43
29
30
31
32
33
68
34
67
35
66
36
65
37
64
38
63
39
62
61
16
59
58
57
56
55
54
53
52
51
50
49
60
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
NC(I/O8R )
C006-3
[3]
[3]
CY7C006
CY7C016
3
Pin Definitions
Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
37
36
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
45
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
64
65
63
62
61
80-Pin TQFP
Top View
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
2R
I/O3R
I/O4R
5R
GND
VCC
VCC
OE L
I/O0L
I/O8L
A5L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
CEL
SEM L
R/WL
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
M/S
A0R
A1R
A2R
A3R
A4R
INTL
GND
OER
I/O6R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
NC
CER
SEMR
R/WR
CY7C016
BUSYR
INTR
I/O8R
NC
ANC
NC
NC
NC
NC
NC
NC
NC
NC
C006-4
NC
A5R
I/O7R
NC
I/O
I/O
NC
I/O1L
13R A13L
Left Port Right Port Descript ion
I/O0L–7L(8L) I/O0R–7R(8R) Data Bus Input/Output
A0L–13L A0R–13R Address Li nes
CELCERChi p En abl e
OELOEROutput Enab le
R/WLR/WRRead/Write Enable
SEML SEMRSemaphore Enable. Whe n asserted LOW, allows access to eight sema-
phores. The three leas t significan t bi ts of the address lines will determine
which semaphore to wri te or read. The I/O0 pin is used when writing to a
semapho re. Semaphore s are re quested by writi ng a 0 int o the respective
location.
INTLINTRInterrupt Flag. INTL is set when right por t writes locat ion 3FFE and is
cleared when left port reads location 3FFE. INTR is set when left port writes
location 3FFF and is cl eared when right port reads loc ation 3FFF.
BUSYLBUSYRBusy Flag
M/S Ma ster or Sl ave Select
VCC Power
GND Ground
CY7C006
CY7C016
4
Maximum Ratings
(Above whi ch the useful l ife ma y be imp air ed. For user guide-
li nes, not tested.)
Sto ra g e Tem p e ra tu re ...... ... ..... .. ..... .. ..... ... ..–6 5°C to +150°C
Ambient Tempera tur e wit h
Power Applied.............................................–55°C to +125°C
Supply Voltage t o Ground Potential... ...... .. .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
DC Input Voltage[4]......................................... –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current..... ...... .. .... .......... ................. ........ >200 mA
Selectio n Gu ide
7C006–15
7C016–15 7C006–25
7C016–25 7C006–35
7C016–35 7C006–55
7C016–55
Maximum Access Time (ns) 15 25 35 55
Maximum Operating
Current (mA) 260 220 210 200
Maximum Standby
Current for ISB1 (mA) 70 60 50 40
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Note:
4. Pulse width < 20 ns.
Electrica l Characteristics Over the Operati ng Range
7C006–15
7C016–15 7C006–25
7C016–25
Parameter Description Test Conditi ons Min. Typ. Max. Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC = Min ., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min ., IOL = 4.0 mA 0.4 0.4 V
VIH 2.2 2.2 V
VIL Input LOW Voltage 0.8 0.8 V
IIX Input Leakage Current GND ≤ VI ≤ VCC –10 +10 –10 +10 µA
IOZ Output Leakage Current Outputs Disabled, GND ≤ VO ≤ VCC –10 +10 –10 +10 µA
ICC Operati ng Curr ent VCC = Max. , IOUT = 0 mA
Output s Disabled Com’l 170 260 160 220 mA
Ind 160 270
ISB1 Standby Current
(Both Ports TTL Levels) CEL and CER ≥ VIH,
f = fMAX[5] Com’l 50 70 40 60 mA
Ind 40 75
ISB2 Standby Current
(One Port TTL Level) CEL or CER ≥ VIH,
f = fMAX[5] Com’l 110 170 90 130 mA
Ind 90 150
ISB3 Standby Current
(Both Ports CMOS
Levels)
Both Ports
CE and CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0[5]
Com’l 315 315 mA
Ind 315
ISB4 Standby Current
(One Port CMOS Le vel) One Port
CEL or CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or
VIN ≥ 0.2 V, Activ e
Port Outpu ts , f = fMAX[5]
Com’l 100 150 80 120 mA
Ind 80 130
CY7C006
CY7C016
5
Electrica l Characteristics (continued)
7C006–35
7C016–35 7C006–55
7C016–55
Parameter Description Test Conditi ons Min. Typ. Max. Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC = Min., I OH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., I OL = 4.0 mA 0.4 0.4 V
VIH 2.2 2.2 V
VIL Input LOW Voltage 0.8 0.8 V
IIX Input Leakage Current GND ≤ V I ≤ VCC –10 +10 –10 +10 µA
IOZ Output Leakage Current Outputs Disabled, GND ≤ VO ≤ VCC –10 +10 –10 +10 µA
ICC Operati ng Curr ent VCC = Max. , IOUT = 0 mA
Output s Disabled Com’l 150 210 140 200 mA
Ind 150 250 140 240
ISB1 Standby Current
(Both Ports TTL Levels) CEL and CER ≥ VIH,
f = fMAX[5] Com’l 30 50 20 40 mA
Ind 30 65 20 55
ISB2 Standby Current
(One Port TTL Level) CEL or CER ≥ VIH,
f = fMAX[5] Com’l 80 120 70 100 mA
Ind 80 130 70 115
ISB3 Standby Current
(Both Ports CMOS
Levels)
Both Ports
CE and CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V, f = 0[5]
Com’l 315 315 mA
Ind 315 315
ISB4 Standby Current
(One Port CMOS Le vel) One Port
CEL or CER ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2 V, Activ e
Port Outpu ts , f = fMAX[5]
Com’l 70 100 60 90 mA
Ind 70 110 60 95
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CIN Input Capacit ance TA = 25°C , f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms
Notes:
5. fMAX = 1/tRC = All inp uts c ycling at f = 1/tRC (except outpu t enab le) . f = 0 me ans no add ress or contr ol li nes c hange. T his applies only to i npu ts at C MOS le v el standb y ISB3.
6. Tested initially and after any design or process changes that may affec t these parameters.
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
5V
OUTPUT
C= 30pF
VTH =1.4V
OUTPUT
C=30pF
(b) ThéveninEquivalent (Load) (c)Three-St ate Delay ( Load 3)
C = 30 pF
OUTPUT
Load (Load 2)
C006-5 C006-6 C006-7
C006-8 C006-9
5
V
OUTPUT
C= 5pF
R1=893Ω
R2=347Ω
RTH =250ΩR1=893Ω
R2=347Ω
≤
≤
CY7C006
CY7C016
6
Swi tch i ng C h aracteri sti cs Ov er the Opera ti ng Range [7]
7C006–15
7C016–15 7C006–25
7C016–25 7C006–35
7C016–35 7C006–55
7C016–55
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 15 25 35 55 ns
tAA Address to Data Valid 15 25 35 55 ns
tOHA Output Hold From Address Change 3 3 3 3 ns
tACE CE LOW to Data Valid 15 25 35 55 ns
tDOE OE LOW to Data Valid 10 13 20 25 ns
tLZOE[8,9,10] OE Lo w to Lo w Z 3 3 3 3 ns
tHZOE[8,9,10] OE HIGH to High Z 10 15 15 25 ns
tLZCE[8,9,10] CE LOW to Low Z 3 3 3 3 ns
tHZCE[8,9,10] CE HIGH to High Z 10 15 15 25 ns
tPU[10] CE LOW t o Power-Up 0 0 0 0 ns
tPD[10] CE HIGH to Power-Down 15 25 35 55 ns
WRITE CYCLE
tWC W rite C y cle T im e 15 25 35 55 ns
tSCE CE LOW t o Wri te End 12 20 30 45 ns
tAW Address Set-Up to Write End 12 20 30 45 ns
tHA Address Hold From Write End 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 ns
tPWE Wr it e Pu ls e Wid th 12 20 25 40 ns
tSD Da t a Se t- U p to W r it e E n d 10 15 15 25 ns
tHD[11] Data Hold Fr om Write End 0 0 0 0 ns
tHZWE[9,10] R/W LOW to High Z 10 15 20 25 ns
tLZWE[9,10] R/W HIGH to Lo w Z 3 3 3 3 ns
tWDD[12] Write Pulse to Data Delay 30 50 60 80 ns
tDDD[12] Write Data Va lid to Read Data Valid 25 30 35 60 ns
BUSY TIMING[13]
tBLA BUSY LOW f rom Address Match 15 20 20 30 ns
tBHA BUSY HIGH from Address
Mismatch 15 20 20 30 ns
tBLC BUSY LOW from CE LOW 15 20 20 30 ns
tBHC BUSY HIGH from CE HIGH 15 17 25 30 ns
tPS Port Set-Up for Priority 5 5 5 5 ns
tWB R/W LOW after BUSY LOW 0 0 0 0 ns
tWH R/W HIGH a fter B USY HIGH 13 17 25 30 ns
tBDD[14] BUSY HIGH to Data Valid Note
13 Note
13 Note
13 Note
13 ns
Notes:
7. Test c onditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30- pF loa d capaci tance.
8. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less tha n tLZOE.
9. Test conditions used are Load 3.
10. This parameter is guaranteed but not tested.
11. Must be met by the device writing to the RAM under all operating conditions.
12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Test conditions used are Load 2.
14. tBDD is a calc ulated p arameter and is the g reat er of tWDD – t PWE (actual ) or tDDD – tSD (actual).
CY7C006
CY7C016
7
INTERRUPT TIMI NG[13]
tINS INT Set Time 15 25 25 30 ns
tINR INT Reset Time 15 25 25 30 ns
SEMAPHORE TIMI NG
tSOP SEM Flag Update Pulse (OE
or S EM )10 10 15 20 ns
tSWRD SEM Fl ag Writ e to Read Ti me 5 5 5 5 ns
tSPS SEM Flag Cont ention Window 5 5 5 5 ns
Swi tch i ng C h aracteri sti cs Ov er the Opera ti ng Range [7] (continued)
7C006–15
7C016–15 7C006–25
7C016–25 7C006–35
7C016–35 7C006–55
7C016–55
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Swi tch i ng Waveform s
Notes:
15. R/W is HIGH for read c ycle .
16. Device is continuously selected CE = LO W and O E = L OW. This w a vef orm cannot be used f or s emaphore r eads .
17. Address valid prior to or coincident with CE trans ition LOW.
18. CEL = L, SEM = H w hen acces sing RAM. CE = H, S EM = L when ac ces sing semaphor es.
tRC
tAA
tOHA
DATA VA LI DPREVIOUS D ATA VALID
DA TA OUT
ADDRESS
C006-10
Read Cycle No. 1 (Either Por t Address Access)[15,16]
tACE
tLZOE tDOE tHZOE
tHZCE
DATA VA LI D
DA TA OUT
SEMor CE
OE
tLZCE
tPU
ICC
ISB
tPD
C006-11
Read Cycle No.2 (Either Port CE/OE Access)[15,17,18]
CY7C006
CY7C016
8
Notes:
19. BUSY = HIG H f or the writing port.
20. CEL = CER = LOW.
21. The internal write time of the memory is defined by the ov erlap of C E or SEM LOW and R/W LO W . Both si gnals must be LO W to initiate a writ e, and either signa l can
terminate a write by go ing HIGH. The data inp ut set- up an d hold t iming sh ould be refer enced to the risin g edge of the s ignal that terminates t he wr ite.
22. If OE i s LOW during a R/W control led write c ycle , the write pulse width mus t be the larger of tPWE or (tHZWE + tSD) to all ow th e I /O driv ers to turn o ff and data to be placed on
the b us for the r equired tSD. If OE i s H IGH during a R/ W cont rolled write cycle (a s in this example) , this r equirement does not appl y and the write pulse can be as sho rt as the
speci fied tPWE.
23. R/W m ust be H IGH durin g all addr ess transi tions.
Swi tch i ng Waveform s (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/W R
DATA INR
DATAOUTL
C006-12
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
Read Timing with Port-to-Port Delay (M/S=L)[19,20]
C006-13
tAW
tWC
DATA VA LI D
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
tHZOE tLZOE
SEMOR CE
R/W
ADDRESS
OE
DATA OUT
DA TA IN
Write Cycle No.1: OE Three-State Data I/Os (Either Port)[21,22,23]
CY7C006
CY7C016
9
Notes:
24. Data I/O pins enter high impedance when OE is held LOW du ring writ e.
25. CE = H IGH f or the duration of the abo v e tim ing (b oth write and rea d cycle) .
Swi tch i ng Waveform s (continued)
tAW
tWC
tSCE
tSA tPWE
tHD
tSD
tHZWE
tHA
HIGH IMPEDANCE
SEMOR CE
R/W
ADDRESS
DATA OUT
DATA IN
tLZWE
DATA VALID
C006-14
Write Cycl e No.2: R/W Three-State Data I/O s (Either Port)[20,22,24]
tSOP
SEM
R/W
OE
I/O0
C006-15
VA LID ADDRESS VA LID ADDRESS
tHD
DATAIN VALID DATAOUTVALID
tOHA
A0–A2
tHA tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
Semaph ore Read After Write Timing, Eit her Side [25]
tAW
tAA
CY7C006
CY7C016
10
Notes:
26. I/O0R = I/O 0L = LO W ( reques t semap hore); CER = CEL = HIGH.
27. Semaphores are reset (available to both ports) at cycle start.
28. If tSPS is violat ed, th e semaphore w ill d efini tely be ob tai ned by one side or the ot her , b ut there i s no gu ar antee whi ch sid e will control the semaphore.
Swi tch i ng Waveform s (continued)
MATCH
C006-16
tSPS
A0L–A2L
MATCH
R/WL
SEML
A0R–A2R
R/WR
SEMR
Semaph ore Contention [26,27,28]
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA IN R
DATA OUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
C006-17
Read wit h BUSY (M/S=HIGH)[19]
tPWE
R/W
BUSY tWB tWH
Write Timing with Busy Input (M/S=LOW)
C006-18
CY7C006
CY7C016
11
Notes:
29. If tPS is vi olated, the b usy signal will be asserted on one side o r t he oth er , b ut t here i s no gua ra ntee on whi ch si de BU SY will be asserted.
30. tHA depends on which enab le pi n (CEL or R/WL) is deasserted first.
31. tINS or tINR depends o n which en abl e pin (CEL or R/WL) is asserted last.
Swi tch i ng Waveform s (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CERValid First:
ADDRESSL,R
BUSYR
CE L
CE R
BUSYL
CER
CEL
ADDRESSL,R
C006-19
C006-20
CELVal id First:
Busy Timing Dia gram No.1 (CE Arbitration)[29]
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSYL
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First: C006-21
C006-22
Left Addr essValid Fir st:
Busy Timing Diagram No.2 (Address Arbitr ation)[28]
CY7C006
CY7C016
12
Swi tch i ng Waveform s (continued)
Inter rupt Timing Diagrams
WRITE 3FFF
tWC
Right Side Cl ears INTR:
tHA
READ 3FFF
tRC
tINR
WRITE 3FFF
tWC
Right Side Sets INTL:
Left Side Sets INTR:
Left Side Clears INTL:
READ 3FFF
tINR
tRC
ADDRESS R
CEL
R/WL
INTL
OEL
ADDRESS R
R/WR
CER
INTL
ADDRESS R
CER
R/WR
INTR
OER
ADDRESSL
R/WL
CEL
INT
R
tINS
tHA
tINS
C006-23
C006-24
C006-25
C006-26
[30]
[30]
[30]
[31]
CY7C006
CY7C016
13
Architecture
The CY7C006/016 consi sts of a an array of 16K wor ds of 8/9
bits each of dual-por t RAM cells, I/O and address lines, and
control signals (CE, OE, R/W). These contr ol pins permit indepen-
dent access f or reads or writes to an y location i n memory. To handle
simultaneous writes/reads t o the same location, a BUSY pin is pro-
vided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communicat ion. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the
CY7C006/016 can f unction as a Master (BUSY pins ar e outputs) or
as a slave (BUSY pins are inputs). The CY7C006/016 has an auto-
matic power-down feature controlled by CE. Each por t is provided
with its own output enable control ( OE), which allo ws data to be read
from the device.
Functional Description
Write Operati on
Data must be set up for a duration of tSD before the rising edge
of R/ W in order to guarantee a valid wr ite. A write operation is con-
trolled by either the OE pi n (see Write Cycle No.1 waveform) or the
R/W pin (see Write Cycle No. 2 waveform). Data can be written to the
device tHZOE after the OE is deasser ted or tHZWE af te r the fa lli ng
edge of R/W. Required inputs for non-contention operations are sum-
marized in
Table 1
.
If a location is being written to by one port and the opposite
port attempts to read that location, a por t-to-port f lowt hrough
delay must be met before the data is read on the output; oth-
erwise the data read is not deterministic. Data wi ll be valid on
the port tDDD aft er the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE are
asserted. If the user of the CY7C006/ 016 wishes to access a sema-
phore flag, then the SEM pin must be asserted instead of the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 3FFF(HEX), the right port’s
interrupt flag (INTR) is set. This flag is cleared when the right port
reads that same location. Setting the left port’ s interrupt flag (INTL) is
accomplished when the right port writes to location 3FFE(HEX). This
flag is cleared when the left port reads location 3FFE(HEX). The mes-
sage at 3FFE(HEX) and 3FFF(HEX) is user-defined. See
Table 2
for
input requirements for INT. INTR and INTL are push-pull outputs and
do not require pull-up resi stors to operate.
Busy
The CY7C006/016 provides on-chip arbitration to resolve si-
multaneous memory location access (contention). If both
por ts’ CEs are asserted and an address match occurs within tPS of
each other the Busy logic will determine which port has access. If tPS
is violated, one port will definitely gain permission to the location, b ut
it is not guaranteed which one. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW. BUSYL and BUSYR
in mast er mode are push-pull outputs and do not require pull-up re-
sistors to operate.
Master/Slave
An M/S pin is pro vided i n order to expand the word width by config-
ur ing the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device w ith no external com po-
nents.Writing of slave devices must be delayed unti l after the BUSY
input has settled (tBLA). Otherwise , the sla ve chip ma y begin a write
cycle during a contention situation.When presented a HIGH input, the
M/S pin allows the device to be used as a master and therefore the
BUSY line is an output. BUSY can then be used to send the arbitra-
tion outcome to a slave .
Semaphore Operati on
The CY7C006/016 provides eight semaphore latches which
are separate from the dual-port memory locations. Sema-
phores are used to reserve resources that are shared between
the two ports.The state of the semaphore indicates that a re-
source is in use. For example, if the left port want s to request
a given resource, it sets a la tch by writi ng a 0 to a sem aphore
location. The left port then verifies its success in setting the
latch by reading it. After writing to the semaphore, SEM or OE
must be deasser ted for tSOP before attempting to read the sema-
phore. The semaphore value will be av ailab le t SWRD + tDOE after the
rising edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control over the shar ed resource, otherwise
(reads a 1) it assumes the right port has control and continues to poll
the semaphor e.When the ri ght side has relinquished co ntrol of t he
semaphore (by writing a 1), the left side will succeed in gaining control
of the semaphore. If the left side no l onger requires the semaphore,
a 1 is written to cancel its request.
Table 1. Non-Contending Read/Writ e
Inputs Outputs
CE R/W OE SEM I/O0–7/8 Operation
H X X H Hi gh Z Power-Down
H H L L Data Out Read Data in
Semaphore
X X H X High Z I/ O Lines Disabled
H X L Data In Write t o Semaphore
L H L H Data Out Read
L L X H Data In Write
L X X L Ill egal Condition
Table 2. Interrupt Oper ati on Exam ple (assum es BUSYL=BUSYR=HIGH)
Left Port Right Port
Function R/W CE OE A0L–13L INT R/W CE OE A0R–13R INT
Set Left I NT X X X X L L L X 3FFE X
Reset Left INT X L L 3FFE H X L L X X
Set Right INT L L X 3FFF X X X X X L
Reset Right INT X X X X X X L L 3FFF H
CY7C006
CY7C016
14
Semaphores are accessed by asser ting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE must
remain HIGH during SEM LOW). A 0–2 represents the semaphor e
address. OE and R/W ar e used in t he same manner as a norma l
memory access.When writing or reading a semaphore, the other ad-
dress pins hav e no eff ect.
When writing t o t he semap hore, only I /O 0 is used. If a 0 is written
to the left port of an un used semaphore, a 1 wil l appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side sho wing 0 (the left port in this case). If the left
por t now rel inquishe s control by wr iting a 1 to the s emaphore, the
semaphore will be set to 1 for both sides. However, if the right port had
requested the semaphore (written a 0) while the left port had control,
the right port would immediately own t he semaphore as soon as the
left port released it.
Table 3
shows sample semaphore operations.
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both por ts attempt t o access the
semaph ore within tSPS of each other , the semaphore will definitely
be obtained b y one side or the other , but there is no guarantee which
side will control the semaphore .
Initialization of the semaphore is not autom atic and must be
reset during initialization program at power-up. All Sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
Table 3. Semap hore O peration Example
Function I/O0-7/8 Left I/O0-7/8 Right Status
No action 1 1 Semaphore free
Left port wri tes semaphore 0 1 Left port obtains sem aphore
Right port writes 0 to semaphore 0 1 Right side is denied access
Left port wri tes 1 to semaphore 1 0 Right port is granted access to sema phore
Left port wri tes 0 to semaphore 1 0 No change. Left port is denied access
Right port writes 1 to semaphore 0 1 Left port obtains sem aphore
Left port wri tes 1 to semaphore 1 1 No port accessing semaphor e address
Right port writes 0 to semaphore 1 0 Right port obtains sem aphore
Right port writes 1 to semaphore 1 1 No port accessing semaphor e
Left port wri tes 0 to semaphore 0 1 Left port obtains sem aphore
Left port wri tes 1 to semaphore 1 1 No port accessing semaphor e
Orde ring Information
16K x8 Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Packag e Ty pe Operating
Range
15 CY7C006–15AC A65 64 -L ea d Th in Q uad F l a t Packag e Commercial
CY7C006–15JC J81 68-Lead Plasti c Leaded Chip Carrier
25 CY7C006–25AC A65 64 -L ea d Th in Quad F l a t Pack ag e Commercial
CY7C006–25JC J81 68-Lead Plasti c Leaded Chip Carrier
CY7C006–25AI A65 64-L ead Th i n Q uad F lat Pack age Industrial
CY7C006–25JI J81 68-Lead Plasti c Leaded Chip Carrier
35 CY7C006–35AC A65 64 -L ea d Th in Quad F l a t Pack ag e Commercial
CY7C006–35JC J81 68-Lead Plasti c Leaded Chip Carrier
CY7C006–35AI A65 64-L ead Th i n Q uad F lat Pack age Industrial
CY7C006–35JI J81 68-Lead Plasti c Leaded Chip Carrier
55 CY7C006–55AC A65 64 -L ea d Th in Quad F l a t Pack ag e Commercial
CY7C006–55JC J81 68-Lead Plasti c Leaded Chip Carrier
CY7C006–55AI A65 64-L ead Th i n Q uad F lat Pack age Industrial
CY7C006–55JI J81 68-Lead Plasti c Leaded Chip Carrier
CY7C006
CY7C016
15
Document #: 38-00416-A
Orde ring Information (continued)
16K x9 Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Packag e Ty pe Operating
Range
15 CY7C016–15AC A80 80 -L ea d Th in Q uad F l a t Packag e Commercial
CY7C016–15JC J81 68-Lead Plasti c Leaded Chip Carrier
25 CY7C016–25AC A80 80 -L ea d Th in Quad F l a t Pack ag e Commercial
CY7C016–25JC J81 68-Lead Plasti c Leaded Chip Carrier
CY7C016–25AI A80 80-L ead Th i n Q uad F lat Pack age Industrial
CY7C016–25JI J81 68-Lead Plasti c Leaded Chip Carrier
35 CY7C016–35AC A80 80 -L ea d Th in Quad F l a t Pack ag e Commercial
CY7C016–35JC J81 68-Lead Plasti c Leaded Chip Carrier
CY7C016–35AI A80 80-L ead Th i n Q uad F lat Pack age Industrial
CY7C016–35JI J81 68-Lead Plasti c Leaded Chip Carrier
55 CY7C016–55AC A80 80 -L ea d Th in Quad F l a t Pack ag e Commercial
CY7C016–55JC J81 68-Lead Plasti c Leaded Chip Carrier
CY7C016–55AI A80 80-L ead Th i n Q uad F lat Pack age Industrial
CY7C016–55JI J81 68-Lead Plasti c Leaded Chip Carrier
Package Di ag ra ms
64-Lead Thin Plasti c Quad Flat Pac k A65
CY7C006
CY7C016
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semic onductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag ra ms (continued)
80-Pin Thi n Plastic Quad Flat Pack A80
68-Lead Plastic Leaded Chip Carrier J81
