ICs for Communications
ISDN Echocancellation Circuit for NT and Terminal Applications
IEC-Q NTE
PSB 21910 Version 5.1
Delta Sheet 01.97 T2191-0V51-L1-7600
Edition 01.97
T his ed ition was realized using the software sy stem FrameMaker.
Published by Siemens AG,
HL IT
© Siemens AG 1997.
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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
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PSB 21910
Revision History: Current Version: 01.97
Previous Version: n one
Page
(in pr evious
Version)
Page
(in new
Version)
Subjects (major changes since last r evision)
PS B 219 10
Overview
Semiconductor Group 3 01.97
1Overview
The PSB 21910 IEC-Q NTE Version 5.1 is a specifi c vers ion of the PEB 2091 IEC -Q for
terminal and PBX applications. It features all necessary functi ons required for NTs and
terminal applications like PC add-on cards and terminal adapters. This Delta Sheet
refers to the IEC-Q V 4.3 User’s Manual 2.95, IEC-Q V4.4 and V5.1 Delta Sheet and
IEC-Q V5.1 Errata Sheet.
P-LCC-44
T-QFP 64
ISDN Echocancellation Ci rcuit for NT and Terminal
Applications
IEC-Q NTE
PSB 21910
Semiconductor Group 4 01.97
Delta Sheet for the Version 5.1 CMO S
Type Ordering Code Package
PSB 21910F V5.1 Q 67101-H6886 T-QFP 64
PSB 21910N V5.1 Q 67107-H6873 P-LCC-44
2 Features
• Compatible to PEB 2091 IEC-Q V5.1 in NT modes
and TE mode
• IOM-2 interface in NT mode compatible to PEB 2081
(SBCX)
• IOM-2 interface in TE mode compatible to PSB2186
and PSB 7110 for D-channel access
The IEC-Q NTE V 5.1 comes in a PLCC-44 package or
a T-QFP 64 packa ge.
PSF version with extended temperature range
(-40 ... +85 C) available on request.
PS B 219 10
Features
Semiconductor Group 5 01.97
2.1 Pin Configuration
Figure 1
Pin Configuration P-LCC-44 and T-Q FP 64 Package (top view)
ITP09426
MCLK/DISS
D5/AD5/PCA0
D6/AD6/PCA1
A1/MS2
A2/MS1
A3/MS0
DCL
FSC
TP
PS1
GNDd
RST/AUTO
INT/INT/INT
CCLK/ALE/TP1
PS2
A0/SMODE/GNDd
D7/AD7/GNDd
DIN
DOUT
RES
AIN
BIN
N.C.
XIN
PMODE
DDa1
V
N.C.
N.C.
N.C.
GNDa2
N.C.
V
DDd
AOUT
GNDa1
BOUT
PCD0/AD0/D0
PCD1/AD1/D1
PCD2/AD2/D2
PCRD/AD3/D3
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
3334353637383940414243444546
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
161514131211109876543
32 DOD/WR/R/WN.C. 48 47
64 21
PCWR/AD4/D4
N.C.
N.C.
N.C.
DDd
V
TSP/CS
V
DDd
N.C.
V
DDa1
XOUT
V
REF
V
DDa2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
CLS
N.C.
DS/RD/MTO
N.C.
N.C.
PSB 21910 V5.1
IEC-Q NTE
PS B 219 10
Features
Semiconductor Group 6 01.97
2.2 Pin Definitions and Functions
Pin names and pin numbers of the P-LCC 44 package in stand alone mode are as in
former versions of the I EC-Q.
Pin No.
P-LCC-44 Pin No.
T-QFP64 Symbol Input (I)
Output (O) Function
Power Supply Pins
1, 2 7, 8, 12 VDDD I5 V
± 5 % digital sup ply voltage
5 14 GNDA1 I 0 V analog
7, 8 18, 19 VDDA1 I5 V ±
5 % analog supply voltage
921
V
REF OVREF pin to buffer internally generated
voltage with capa citor 100 nF vs GND
13 26 VDDA2 I5 V ±
5 % analog supply voltage
16 30 GNDA2 I 0 V analog
23 41 GNDD I 0 V digit al
Mode Selection Pins
310TSPI Single pulse test mode (Stand alone
mode): For activation refer to table 2
on page 48 in the IEC-Q V 4.3 user´s
manual. When active, alternating 2.5 V
pulses are issued in 1.5 ms intervals.
Tie to GND if not used.
310CS
IChip select (Multiplexed,
demultiplexed and serial modes):
Low act ive.
18 35 AUTO I Auto (Stand al one mode): Selection
between auto- and transparent mode
for EOC channel processing.
(Automode = (1))
18 35 RST OReset output (Multiplexed,
demultiplexed and serial modes):
Low act ive.
PS B 219 10
Features
Semiconductor Group 7 01.97
24 43 GNDd I GNDd (Stand alone mode): Must be
connected to GNDd in stand alone
mode.
24 43 SMODE I Serial mode pin: SMODE = 1 sel ect s
serial mode, SMODE = 0 enables the
multiplexed mode.
24 43 A0 I Address bus pin (Demultiplexed
mode)
25 44 GNDd I GNDd (Stand alone mode): Must be
connected to GNDd in stand alone
mode.
25 44 D7 I/O Data bus pin (Multiplexed,
demultiplexed modes)
25 44 not used I (Serial mode ) tie to GND.
33 55 MS0 I Mode Selection 0 (Stand alone
mode)
33 55 not used I (Multiplexed m ode) tie to GND.
33 55 A3 I Address bus pin (Demultiplexed
mode).
33 55 not used I (Se rial mode ) tie to GND.
35 58 MS1 I Mode Selection 1 (Stand alone
mode)
35 58 not used I/O (Multiplexed mode) tie to GND.
35 58 A2 I/O Address bus pin (Demultiplexed
mode).
35 58 CDOUT O Controller Da ta Out (Serial mode):
CCLK determines th e data rate.
CDOUT is "high Z" if no data is
transmitted.
36 59 MS2 I Mode Selection 2 (Stand alone
mode)
36 59 not used I (Multiplexed m ode) tie to GND.
36 59 A1 I Address bus pin (Demultiplexed
mode).
Pin No.
P-LCC-44 Pin No.
T-QFP64 Symbol Input (I)
Output (O) Function
PS B 219 10
Features
Semiconductor Group 8 01.97
36 59 CDIN I Controller Data In (Serial mod e):
CCLK determines th e data rate.
28 47 RES IReset: Low active , must be (0) at least
for 10 ns.
Powe r C o n troll e r In terfa ce P in s
44 5 PCD0 I/O Data Bus of power controller
interface 0 (Stand alone mode):
internal pull-up.
44 5 AD0 I/O Address/Data bus pin (Multiplexed
mode)
44 5 D0 I/O Data bus pin (Demultiplexed mode)
44 5 not used I (Se rial mode ) ti e to GND.
43 4 PCD1 I/O Data Bus of power controller
interface 1 (Stand alone mode):
Internal pull-up.
43 4 AD1 I/O Address/Data bus pin (Multiplexed
mode)
43 4 D1 I/O Data bus pin (Demultiplexed mode)
43 4 not used I (Serial mod e ) tie to GND.
42 3 PCD2 I/O Data Bus of power controller
interface 2 (Stand alone mode):
Internal pull-up.
42 3 AD2 I/O Address/Data bus pin (Multiplexed
mode)
42 3 D2 I/O Data bus pin (Demultiplexed mode)
42 3 not used I (Se rial mode ) ti e to GND.
39 62 PCA0 O Address bus of power controller
interface (Stand alone mode).
39 62 D5 I/O Data bus pin (Multiplexed,
demultiplexed modes)
39 62 not used I (Serial mod e ) tie to GND.
38 61 PCA1 O Address bus of power controller
interface (Stand alone mode).
Pin No.
P-LCC-44 Pin No.
T-QFP64 Symbol Input (I)
Output (O) Function
PS B 219 10
Features
Semiconductor Group 9 01.97
38 61 D6 I/O Data bus pin (Multiplexed,
demultiplexed modes)
38 61 not used I (Serial mode ) tie to GND.
41 2 PCRD OPower controller bus read request
(Stand alone mode): Low active.
41 2 AD3 I/O Address/Data bus pin (Multiplexed
mode)
41 2 D3 I/O Data bus pin (Demultiplexed mode)
41 2 not used I (Se rial mode ) ti e to GND.
40 1 PCWR OPower controller bus write request
(Stand alone mode): Low act iv e.
40 1 D4 I/O Data bus pin (Multiplexed and
demultiplexed modes)
40 1 not used I (Serial mod e ) tie to GND.
19 36 INT I Interrupt (Stand alone mode):
Change-sensitive. After a change of
level has been detected the C/I code
“INT” will be issued on IOM. Tie to
GND during operat ion.
19 36 INT OInterrupt line (Multiplexed,
demultiplexed and serial modes):
Low active.
37 60 DISS O Disable power supply (Stand alone
mode): This pin is set to ’1’ after
receipt of MON-0 LBBD in auto-mod e.
37 60 MCLK O Microprocessor clock output
(Multiplexed, demultiplexed and
serial modes): provided with four
programmable clock rates: 7.68 MHz,
3.84 MHz, 1.92 MHz and 0.96 MH z.
21 38 PS1 I Power status 1 (primary). ’1’
indicates primary power supply ok. The
pin value is identical to the overhead bit
’PS1’ value.
Pin No.
P-LCC-44 Pin No.
T-QFP64 Symbol Input (I)
Output (O) Function
PS B 219 10
Features
Semiconductor Group 10 01.97
22 39 PS2 I Power status 2 (secondary). ’1’
indicates secondary power supply ok.
The pin value is identical to the
overhead bit ’PS2’ value.
Miscellaneous Function Pins
10 22 XOUT O Crystal OUT: 15.36-MHz crystal is
connected with 30 pF in parallel. Leave
open if not used .
11 23 XIN I Crystal IN: External 15.36-MHz clock
signal or 15.36-MH z cry stal with 30 pF
in parallel is connected.
17 32 DOD I DOUT open drain (Stand alone
mode): Select open drain with DOD =
(1) (external pull-up resistor required)
and tristate with DOD = ( 0) .
17 32 WR IWrite (Siemens/Intel multiplexed
and demultiplexed modes):
indicates a write operat ion , active low.
17 32 R/W IRead/Write (Motorola demultiplexed
mode): indicates a read (high) or write
(low) operation.
17 32 not used I (Ser ia l mo d e ) tie to GND.
29 51 TP I Test pin: Not available to user. Do not
connect. Internal pull-dow n resistor .
20 37 TP1 I Test pin (Stand alone mode): Not
available to user. Do not connect.
Internal pull-down resis tor .
20 37 ALE I Address Latch Enable (Multiplexed
mode): In the Siemens/Int el µP
interface modes a high indicates an
address on the AD0..3 pins which is
latched with the fall ing edge of ALE.
Pin No.
P-LCC-44 Pin No.
T-QFP64 Symbol Input (I)
Output (O) Function
PS B 219 10
Features
Semiconductor Group 11 01.97
20 37 ALE I Address Lat ch Enable
(Demultiplexed mode): ALE tied to
GND selects the Siemens/Int el type.
ALE tied to VDD select s the Moto rola
type.
20 37 CCLK I Controller data clock (Serial
mode): Shifts data from or to the
device.
32 54 CLS O Clock Signal: A 7.68MHz clock,
synchronous to the U-interface, is
provided on this pin.
12 24 PMODE I Processor Interface Enable: Setting
PMODE to “1“ enables the Processor
Interface (Multiplexed, demulti-
plexed and serial modes). Tie to
GND or do not connect t o sele ct st and
alone mode. Internal pull down .
34 57 MTO I Monitor procedure timeout (Stand
alone mode): Disables the internal 6
ms monitor timeout when set to (1).
Internal pull-down resis tor.
34 57 RD IRead (Siemens /Intel mult ip lexed
and demultiplexed modes):
indicates a read operatio n, active low.
34 57 DS Data Strobe (Motorola
demultiplexed mode): indicates a
data transfer, active low.
34 57 not used I (Ser ia l mo d e ) tie to GND.
IOM®-Pins
31 53 DCL I/O Data clock: Clock output 512 or 1536
kHz. Remains input in processor mode
until programming of STCR registe r.
Pin No.
P-LCC-44 Pin No.
T-QFP64 Symbol Input (I)
Output (O) Function
PS B 219 10
Features
Semiconductor Group 12 01.97
30 52 FSC I/O Frame synchronization clock: The
start of the B1-channel in time-slot 0 is
marked. FSC = (1) for one DCL-period
indicates a supe rframe marker. FSC =
(1) for at least t w o D CL- per iods m ar ks
a standard frame.
Remains input in process or mode unt il
programming of STCR register.
26 45 DU I Data Upstream: Input of IOM-data
synchronous to D CL-clock.
27 46 DD O Data Downstream: Output of IOM-
data synchronous to DCL-cl ock.
U-Interface Pins
15 29 AIN I Differential U-Interface input:
Connect to hybrid.
14 28 BIN I Differential U-Interface input:
Connect to hybrid.
616AOUTODifferential U-Interface output:
Connect to hybrid.
413BOUTODifferential U-Interface output:
Connect to hybrid.
Pin No.
P-LCC-44 Pin No.
T-QFP64 Symbol Input (I)
Output (O) Function
PS B 219 10
Features
Semiconductor Group 13 01.97
2.3 Operation Modes
Table 1 Modes of Operation
The IEC-Q NTE support s the operating modes NT, NT-Auto, TE and NT-Repeater. The
selection is done via the MS2-0 inputs in stand alone mode and via the register bits MS2-
0 in the STCR register in processor mode .
2.4 STCR Register
Defau lt: C4H
The Status Control Register (STCR) selects the operating modes of the IEC-Q NTE
V 5.1 as given in the section 2.2 on page 47 of the IEC-Q V 4.3 user´s manual.
Input Pins Output Pins U
Synchronized
Mode MS2 MS1 MS0 DCL
OUT CLS
OUT Super-
frame-
marker
NT 0 0 0 512 7680 no
NT 1 0 0 512 7680 yes
NT-Auto 0 0 1 512 7680 no
TE 0 1 0 1536 7680 no
TE 1 1 0 1536 7680 yes
NT-RP 1 0 1 512 7680 yes
Name: 7 6543210 Default
STCR TEST1 TEST2 MS2 MS1 MS0 TM1 TM2 AUTO C4H
TEST1: Test Bit 1
Must be written to ’0’ together with mod e setting of MS2-0 after
reset.
TEST2: Test Bit 2
Must be written to ’0’ together with mod e setting of MS2-0 after
reset.
PS B 219 10
Features
Semiconductor Group 14 01.97
MS2: Mode Selection 2
Selects operation mode according to table above.
MS1: Mode selection 1
Selects operation mode according to table above.
MS0: Mode Selection 0
Selects operation mode according to table above.
TM1: Test-Mode- Bit 1
This bit determines, in combination with STCR:TM2, the
operation modes. See table bel ow.
TM2: Test-Mode- Bit 2
This bit determines, in combination with STCR:TM1, the
operation modes. See table bel ow.
AUTO: Selection betw een aut o- and transp arent mod e
AUTO = 1 sets the automode for EOC channel processing.
AUTO = 0 sets the transparent mode for EOC channel
processing.
Test-Mode TM1 TM2
Norma l Mode 1 0
Send Single-Pulses 1 1
Data-Through 0 1
PS B 219 10
Package Outlines
Semiconductor Group 15 01.97
3 Package Outlines
For package outlines of the P-LCC 44 package please refer to the PEB 2091 V4.3 User’s
Manual 2.9 5, page 217.
T-QFP 64
(Thin Quad Flat Pack age)
GPM05247
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
