CY7C006A
16K × 8 Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-06045 Rev. *K Revised January 5, 2018
16K × 8 Dual-Port Static RAM
Features
■True dual-ported memory cells which allow simultaneous
access of the same memory location
■16K × 8 organization (CY7C006A)
■0.35-micron CMOS for optimum speed/power
■High-speed access: 20 ns
■Low operating power
❐Active: ICC = 180 mA (typical)
❐Standby: ISB3 = 0.05 mA (typical)
■Fully asynchronous operation
■Automatic power-down
■Expandable data bus to 16 bits or more using Master/Slave
chip select when using more than one device
■On-chip arbitration logic
■Semaphores included to permit software handshaking
between ports
■INT flags for port-to-port communication
■Pin select for Master or Slave
■Commercial temperature range
■Available in 68-pin PLCC (CY7C006A), 64-pin TQFP
(CY7C006A)
■Pb-free packages available
Functional Description
For a complete list of related documentation, click here.
I/O
Control
Address
Decode
A
0L
–A
13L
CE
L
OE
L
R/W
L
BUSY
L
I/O
Control
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
Logic Block Diagram
A
0L
–A
13L
True Dual-Ported
RAM Array
A
0R
–A
13R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
Address
Decode A
0R
–A
13R
[1] [1]
R/W
L
OE
L
I/O
0L
–I/O
7L
CE
L
R/W
R
OE
R
I/O
0R
–I/O
7R
CE
R
14
8
14
8
14 14
Note
1. BUSY is an output in master mode and an input in slave mode.
CY7C007A16K × 8 Dual-Port Static RAM
CY7C006A
Document Number: 38-06045 Rev. *K Page 2 of 22
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 4
Pin Definitions .................................................................. 4
Architecture ...................................................................... 4
Functional Overview ........................................................ 4
Write Operation ........................................................... 4
Read Operation ........................................................... 5
Interrupts ..................................................................... 5
Busy ............................................................................ 5
Master/Slave ............................................................... 5
Semaphore Operation ................................................. 5
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
Electrical Characteristics ................................................. 6
Capacitance ...................................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Mode ........................................................ 7
Timing ................................................................................ 7
Switching Characteristics ................................................ 8
Switching Waveforms .................................................... 10
Non-Contending Read/Write .......................................... 16
Interrupt Operation Example ......................................... 16
Semaphore Operation Example ....................................16
Ordering Information ...................................................... 17
16K × 8 Asynchronous Dual-Port SRAM .................. 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
CY7C006A
Document Number: 38-06045 Rev. *K Page 3 of 22
Pin Configurations
Figure 1. 68-pin PLCC pinout
Top View
Figure 2. 64-pin TQFP pinout
Top View
VCC
OEL
I/O1L
I/O0L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A13L
CEL
SEML
R/WL
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
GND
VCC
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
BUSYR
M/S
A0R
A1R
A2R
A3R
A4R
INTL
INTR
GND
OER
I/O7R
A5R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A13R
CER
SEMR
R/WR
A5L
NC
I/O6R
24
25
26
10
11
12
13
14
15
48
47
46
45
44
40
41
27
42
28
43
29
30
31
32
33
68
34
67
35
66
36
65
37
64
38
63
39
62
61
16
59
58
57
56
55
54
53
52
51
50
49
60
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
NC
NC
NC
CY7C006A (16K × 8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 50
32 49
16
GND
OER
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
GND
VCC
A4L
A3L
A2L
A1L
A0L
GND
BUSYL
BUSYR
M/S
A0R
A1R
A2R
A3R
A4R
INTL
INTR
I/O7R
A5R
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A13R
CER
SEMR
R/WR
VCC
OEL
I/O1L
I/O0L
A5L
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A13L
CEL
SEML
R/WL
CY7C006A (16K × 8)
CY7C006A
Document Number: 38-06045 Rev. *K Page 4 of 22
Architecture
The CY7C006A consists of an array 16K words of 8 bits of
dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two Interrupt (INT) pins can be utilized
for port-to-port communication. Two Semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin,
the devices can function as a master (BUSY pins are outputs) or
as a slave (BUSY pins are inputs). The devices also have an
automatic power-down feature controlled by CE. Each port is
provided with its own Output Enable control (OE), which allows
data to be read from the device.
Functional Overview
The CY7C006A is low-power CMOS 16K × 8 dual-port static
RAMs. Various arbitration schemes are included on the devices
to handle situations when multiple processors access the same
piece of data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as standalone 8-bit
dual-port static RAMs or multiple devices can be combined in
order to function as a 16-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 16-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a Chip Select (CE) pin.
The CY7C006A is available in 68-pin PLCC package, the
CY7C006A is also available in 64-pin TQFP package.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summarized
Selection Guide
Description CY7C006A
-20 Unit
Maximum Access Time 20 ns
Typical Operating Current 180 mA
Typical Standby Current for ISB1 (Both Ports TTL Level) 45 mA
Typical Standby Current for ISB3 (Both Ports CMOS Level) 0.05 mA
Pin Definitions
Left Port Right Port Description
CELCERChip Enable
R/WLR/WRRead/Write Enable
OELOEROutput Enable
A0L–A13L A0R–A13R Address
I/O0L–I/O7L I/O0R–I/O7R Data Bus Input/Output
SEML SEM
RSemaphore Enable
INTLINTRInterrupt Flag
BUSYLBUSYRBusy Flag
M/S Master or Slave Select
VCC Power
GND Ground
NC No Connect
CY7C006A
Document Number: 38-06045 Rev. *K Page 5 of 22
in Non-Contending Read/Write on page 16.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF) is the mailbox for
the right port and the second-highest memory location (3FFE) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. The operation of the interrupts and their interaction with
Busy are summarized in Interrupt Operation Example on page 16.
Busy
The CY7C006A provides on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of
each other, the busy logic will determine which port has access.
If tPS is violated, one port will definitely gain permission to the
location, but it is not predictable which port will get that
permission. BUSY will be asserted tBLA after an address match
or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (tBLC or tBLA), otherwise,
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C006A provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two ports.
The state of the semaphore indicates that a resource is in use.
For example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be deasserted
for tSOP before attempting to read the semaphore. The
semaphore value will be available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to cancel
its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set to
one for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Semaphore Operation Example on page 16
shows sample semaphore operations.
When reading a semaphore, all data lines output the semaphore
value. The read value is latched in an output register to prevent
the semaphore from changing state during a write from the other
port. If both ports attempt to access the semaphore within tSPS
of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
CY7C006A
Document Number: 38-06045 Rev. *K Page 6 of 22
Maximum Ratings
Exceeding maximum ratings [2] may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Supply Voltage to Ground Potential .............–0.3 V to +7.0 V
DC Voltage Applied to Outputs
in High Z State .............................................–0.5 V to +7.0 V
DC Input Voltage [3] .....................................–0.5 V to +7.0 V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 2001V
Latch-Up Current ...................................................> 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0 °C to +70 °C 5 V 10%
Electrical Characteristics
Over the Operating Range
Parameter Description
CY7C006A
Unit-20
Min Typ Max
VOH Output HIGH Voltage (VCC = Min, IOH = –4.0 mA) 2.4 – – V
VOL Output LOW Voltage (VCC = Min, IOH = +4.0 mA) – 0.4 V
VIH Input HIGH Voltage 2.2 – V
VIL Input LOW Voltage – 0.8 V
IOZ Output Leakage Current –10 10 A
ICC Operating Current (VCC = Max, IOUT = 0 mA),
Outputs Disabled
Commercial – 180 275 mA
Industrial – mA
ISB1 Standby Current (Both Ports TTL Level),
CEL & CER VIH, f = fMAX
Commercial 45 65 mA
Industrial – mA
ISB2 Standby Current (One Port TTL Level),
CEL | CER VIH, f = fMAX
Commercial 110 160 mA
Industrial – mA
ISB3 Standby Current (Both Ports CMOS Level),
CEL & CER VCC 0.2 V, f = 0
Commercial 0.05 0.5 mA
Industrial – mA
ISB4 Standby Current (One Port CMOS Level),
CEL | CER VIH, f = fMAX[3, 4] Commercial 100 140 mA
Industrial – mA
Notes
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. Pulse width < 20 ns.
4. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
CY7C006A
Document Number: 38-06045 Rev. *K Page 7 of 22
Data Retention Mode
The CY7C006A is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 V).
Capacitance
Parameter [5] Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz, VCC = 5.0 V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
(a) Normal Load (Load 1)
R1 = 893
5 V
OUTPUT
R2 = 347
C= 30pF
VTH = 1.4 V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)
R1 = 893
R2 = 347
5 V
OUTPUT
C= 5pF
RTH = 250
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
Timing
Parameter Test Conditions [6] Max Unit
ICCDR1 @ VCCDR = 2 V 1.5 mA
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
CY7C006A
Document Number: 38-06045 Rev. *K Page 8 of 22
Switching Characteristics
Over the Operating Range
Parameter [7] Description
CY7C006A
Unit-20
Min Max
READ CYCLE
tRC Read Cycle Time 20 –ns
tAA Address to Data Valid –20 ns
tOHA Output Hold From Address Change 3 – ns
tACE[8] CE LOW to Data Valid –20 ns
tDOE OE LOW to Data Valid –12 ns
tLZOE[9, 10, 11] OE LOW to Low Z 3 – ns
tHZOE[9, 10, 11] OE HIGH to High Z –12 ns
tLZCE[9, 10, 11] CE LOW to Low Z 3 – ns
tHZCE[9, 10, 11] CE HIGH to High Z –12 ns
tPU[11] CE LOW to Power-Up 0 – ns
tPD[11] CE HIGH to Power-Down –20 ns
WRITE CYCLE
tWC Write Cycle Time 20 –ns
tSCE[8] CE LOW to Write End 15 –ns
tAW Address Valid to Write End 15 –ns
tHA Address Hold From Write End 0 – ns
tSA[8] Address Set-Up to Write Start 0 – ns
tPWE Write Pulse Width 15 –ns
tSD Data Set-Up to Write End 15 –ns
tHD[12] Data Hold From Write End 0 – ns
tHZWE[10, 11] R/W LOW to High Z –12 ns
tLZWE[10, 11] R/W HIGH to Low Z 3 – ns
tWDD[13] Write Pulse to Data Delay –45 ns
tDDD[13] Write Data Valid to Read Data Valid –30 ns
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 30-pF load capacitance.
8. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
9. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
10. Test conditions used are Load 3.
11. This parameter is guaranteed but not tested.
12. For 15 ns industrial parts tHD Min. is 0.5 ns.
13. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
CY7C006A
Document Number: 38-06045 Rev. *K Page 9 of 22
BUSY TIMING [14]
tBLA BUSY LOW from Address Match –20 ns
tBHA BUSY HIGH from Address Mismatch –20 ns
tBLC BUSY LOW from CE LOW –20 ns
tBHC BUSY HIGH from CE HIGH – 17 ns
tPS Port Set-Up for Priority 5 – ns
tWB R/W HIGH after BUSY (Slave) 0 – ns
tWH R/W HIGH after BUSY HIGH (Slave) 15 –ns
tBDD[15] BUSY HIGH to Data Valid –20 ns
INTERRUPT TIMING [14]
tINS INT Set Time –20 ns
tINR INT Reset Time –20 ns
SEMAPHORE TIMING
tSOP SEM Flag Update Pulse (OE or SEM)10 –ns
tSWRD SEM Flag Write to Read Time 5 – ns
tSPS SEM Flag Contention Window 5 – ns
tSAA SEM Address Access Time –20 ns
Switching Characteristics (continued)
Over the Operating Range
Parameter [7] Description
CY7C006A
Unit-20
Min Max
Notes
14. Test conditions used are Load 2.
15. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
CY7C006A
Document Number: 38-06045 Rev. *K Page 10 of 22
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port Address Access) [16, 17, 18]
Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) [16, 19, 20]
Figure 6. Read Cycle No. 3 (Either Port) [16, 18, 19, 20]
tRC
tAA
tOHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU tPD
ISB
ICC
DATA OUT
OE
CE
CURRENT
DATA OUT
tRC
ADDRESS
tAA tOHA
CE
tLZCE
tABE
tHZCE
tACE
tLZCE
Notes
16. R/W is HIGH for read cycles.
17. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
18. OE = VIL.
19. Address valid prior to or coincident with CE transition LOW.
20. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
CY7C006A
Document Number: 38-06045 Rev. *K Page 11 of 22
Figure 7. Write Cycle No. 1 (R/W Controlled Timing) [21, 22, 23, 24]
Figure 8. Write Cycle No. 2 (CE Controlled Timing) [21, 22, 23, 28]
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE tLZWE
[26]
[26]
[24]
[25]
NOTE 27 NOTE 27
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
[25]
Notes
21. R/W or CE must be HIGH during all address transitions.
22. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
23. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
24. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tPWE.
25. To access RAM, CE = VIL, SEM = VIH.
26. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CY7C006A
Document Number: 38-06045 Rev. *K Page 12 of 22
Figure 9. Semaphore Read After Write Timing, Either Side [29]
Figure 10. Timing Diagram of Semaphore Contention [30, 31, 32]
Switching Waveforms (continued)
tSOP
tAA
VALID ADRESS VALID ADRESS
tHD
DATAIN VALID DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA tPWE
tSWRD tDOE
WRITE CYCLE READ CYCLE
OE
R/W
I/O0
SEM
A0–A 2
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A0R–A2R
R/WR
SEM R
Notes
29. CE = HIGH for the duration of the above timing (both write and read cycle).
30. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
31. Semaphores are reset (available to both ports) at cycle start.
32. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
CY7C006A
Document Number: 38-06045 Rev. *K Page 13 of 22
Figure 11. Timing Diagram of Read with BUSY (M/S = HIGH) [33]
Figure 12. Write Timing with Busy Input (M/S = LOW)
Switching Waveforms (continued)
VALID
tDDD
tWDD
MATCH
MATCH
R/WR
DATA INR
DATAOUTL
tWC
ADDRESSR
tPWE
VALID
tSD tHD
ADDRESSL
tPS
tBLA tBHA
tBDD
BUSYL
tPWE
R/W
BUSY
tWB tWH
Note
33. CEL = CER = LOW.
CY7C006A
Document Number: 38-06045 Rev. *K Page 14 of 22
Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) [34]
Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) [34]
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC tBHC
ADDRESS MATCH
tPS
tBLC tBHC
CERValid First:
ADDRESS L,R
BUSY
R
CEL
CER
BUSYL
CER
CE L
ADDRESSL,R
CELValid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA tBHA
ADDRESSR
ADDRESS MATCH ADDRESS MISMATCH
tPS
ADDRESSL
BUSY L
tRC or tWC
tBLA tBHA
ADDRESSR
Right Address Valid First:
Left Address Valid First:
Note
34. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
CY7C006A
Document Number: 38-06045 Rev. *K Page 15 of 22
Figure 15. Interrupt Timing Diagrams
Switching Waveforms (continued)
WRITE 3FFF
tWC
tHA
READ 3FFF
tRC
tINR
WRITE 3FFE
tWC
READ 3FFE
tINR
tRC
ADDRESSR
CE L
R/W L
INT L
OE L
ADDRESSR
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
ADDRESSL
R/WL
CE L
INTR
tINS
tHA
tINS
[35]
[36]
[36]
[36]
[35]
[36]
Left Side Sets INTR:
Right Side Clears INTR:
Right Side Sets INTL:
Left Side Clears INTL:
Notes
35. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
36. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
CY7C006A
Document Number: 38-06045 Rev. *K Page 16 of 22
Non-Contending Read/Write
Inputs Outputs
CE R/W OE SEM I/O0–I/O8Operation
H X X H High Z Deselected: Power-Down
H H L L Data Out Read Data in Semaphore Flag
X X H X High Z I/O Lines Disabled
H X L Data In Write into Semaphore Flag
LHLHData Out Read
L L X H Data In Write
L X X L Not Allowed
Interrupt Operation Example
(Assumes BUSYL = BUSYR = HIGH)
Left Port Right Port
Function R/WLCELOELA0L–14LINTLR/WRCEROERA0R–14R INTR
Set Right INTR Flag L LX 3FFF XXXX X L
[37]
Reset Right INTR Flag X X X X X X L L 3FFF H[38]
Set Left INTL Flag XXX X L
[38] LLX 3FFE X
Reset Left INTL Flag X L L 3FFE H[37] XXXXX
Semaphore Operation Example
Function I/O0–I/O8 Left I/O0–I/O8Right Status
No action 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore free
Notes
37. If BUSYL = L, then no change.
38. If BUSYR = L, then no change.
CY7C006A
Document Number: 38-06045 Rev. *K Page 17 of 22
Ordering Information
Ordering Code Definitions
16K × 8 Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
20 CY7C006A-20AXC A65 64-pin TQFP (Pb-free) Commercial
CY7C006A-20AXI A65 64-pin TQFP (Pb-free) Industrial
CY7C006A-20JXC J81 68-pin PLCC (Pb-free) Commercial
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type: X = A or J
A = 64-pin TQFP
J = 68-pin PLCC
Speed Grade: 20 ns
Depth: 06A = 16K
Width: 0 = × 8
Technology Code: C = CMOS
Marketing Code: 7 = Dual Port SRAM
Company ID: CY = Cypress
CCY 0 06A - 20 XX X7
CY7C006A
Document Number: 38-06045 Rev. *K Page 18 of 22
Package Diagrams
Figure 16. 64-pin TQFP (14 × 14 × 1.4 mm) A64SA Package Outline, 51-85046
ș 1
ș
ș 2
L11.00 REF
L
c
0.45 0.60 0.75
0.20
NOM.MIN.
D1
R2
E1
E
0°
0.08
D
2
A
A
1
A
1.35 1.40
SYMBOL MAX.
7°
0.20
1.45
1.60
0.15
ș
b0.30 0.35 0.40
e0.80 TYP
DIMENSIONS
1
R0.08
L20.25 BSC
0.05
0.20
15.75 16.00 16.25
13.95 14.00 14.05
L30.20
0°ș1
11° 13°ș212°
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
MOLD PROTRUSION/END FLASH SHALL
3. DIMENSIONS IN MILLIMETERS
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
INCLUDE MOLD PROTRUSION/END FLASH
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY SIZE INCLUDING MOLD MISMATCH
15.75 16.00 16.25
13.95 14.00 14.05
51-85046 *H
CY7C006A
Document Number: 38-06045 Rev. *K Page 19 of 22
Figure 17. 68-pin PLCC (0.958 × 0.958 Inches) Package Outline, 51-85005
Package Diagrams (continued)
51-85005 *D
CY7C006A
Document Number: 38-06045 Rev. *K Page 20 of 22
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
INT Interrupt
OE Output Enable
PLCC Plastic Leaded Chip Carrier
R/W Read/Write
SRAM Static Random Access Memory
TQFP Thin Quad Flat Pack
TTL Transistor-Transistor Logic
Symbol Unit of Measure
°C degree Celsius
µA microampere
mA milliampere
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
CY7C006A
Document Number: 38-06045 Rev. *K Page 21 of 22
Document History Page
Document Title: CY7C006A, 16K × 8 Dual-Port Static RAM
Document Number: 38-06045
Rev. ECN No. Orig. of
Change Issue Date Description of Change
** 110197 SZV 09/29/2001 Changed from Spec number: 38-00831 to 38-06045.
*A 122295 RBI 12/27/2002 Updated Maximum Ratings:
Added Note 2 and referred the same note in “maximum ratings” in description
below the heading.
*B 237620 YDT 06/25/2004 Updated Features:
Removed “Pin-compatible and functionally equivalent to IDT7006 and
IDT7007”.
*C 345376 AEQ 04/19/2005 Removed Industrial Temperature Range related information across the
document.
Updated Ordering Information:
Updated part numbers.
*D 387333 PCX 08/11/2005 Included Pb-Free Logo at the top of the document.
Added Industrial Temperature Range related information across the
document.
Updated Ordering Information:
Updated part numbers.
*E 2896210 RAME 03/22/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85046 – Changed revision from *B to *D.
spec 51-85065 – Changed revision from *B to *C.
spec 51-85005 – Changed revision from *A to *B.
*F 3110296 EYB 12/14/2010 Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Minor edits.
Updated to new template.
*G 3889996 SMCH 01/30/2013 Removed CY7C007A, CY7C016A, CY7C017A related information across the
document.
Updated Package Diagrams:
spec 51-85046 – Changed revision from *D to *E.
Removed spec 51-85065 *C (corresponding to 80-pin TQFP package).
spec 51-85005 – Changed revision from *B to *C.
Added Acronyms and Units of Measure.
*H 4227411 SMCH 12/20/2013 Updated Ordering Information (Updated part numbers).
Updated to new template.
Completing Sunset Review.
*I 4580622 SMCH 11/26/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85046 – Changed revision from *E to *F.
*J 5553780 NILE 12/14/2016 Updated Package Diagrams:
spec 51-85046 – Changed revision from *F to *G.
spec 51-85005 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*K 6015072 NILE 01/05/2018 Updated Package Diagrams:
spec 51-85046 – Changed revision from *G to *H.
Updated to new template.
Document Number: 38-06045 Rev. *K Revised January 5, 2018 Page 22 of 22
CY7C006A
© Cypress Semiconductor Corporation, 2001-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
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