Datasheet 1 Rev. 1.0
www.infineon.com/hitfet 2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
1 Overview
Basic Features
• Single channel device
• Very low output leakage current in OFF state
• Electrostatic discharge protection (ESD)
• Embedded protection functions (see below)
• ELV compliant package
• Green Product (RoHS compliant)
• AEC Qualified
Applications
• Suitable for resistive, inductive and capacitive loads
• Replaces electromechanical relays, fuses and discrete circuits
Description
The BTS3125EJ is a 125 mΩ single channel Smart Low-Side Power Switch with in a PG-TDSO8-31 package
providing embedded protective functions. The power transistor is built by an N-channel vertical power
MOSFET.
The device is monolithically integrated. The BTS3125EJ is automotive qualified and is optimized for 12 V
automotive applications.
Type Package Marking
BTS3125EJ PG-TDSO8-31 S3125EJ
Table 1 Product Summary
Operating voltage range VOUT 0 .. 31 V
Maximum load voltage VBAT(LD) 40 V
Maximum input voltage VIN 5.5 V
Maximum On-State resistance at TJ = 150°C,VIN = 5 V RDS(ON) 250 mΩ
Nominal load current IL(NOM) 2A
Minimum current limitation IL(LIM) 7A
Maximum OFF state load current at TJ ≤85°C IL(OFF) 1µA
Datasheet 2 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Overview
Diagnostic Functions
• open-drain status output
Protection Functions
• Over temperature shut-down with automatic-restart
• Active clamp over voltage protection
•Current limitation
Detailed Description
The device is able to switch all kind of resistive, inductive and capacitive loads, limited by maximum clamping
energy and maximum current capabilities.
The BTS3125EJ offers ESD protection on the IN pin which refers to the Source pin (Ground).
The over temperature protection prevents the device from overheating due to overload and/or bad cooling
conditions. The temperature information is given by a temperature sensor in the power MOSFET.
The BTS3125EJ has an auto-restart thermal shut-down function. The device will turn on again, if input is still
high, after the measured temperature has dropped below the thermal hysteresis.
The over voltage protection can be activated during load dump or inductive turn off conditions. The power
MOSFET is limiting the drain-source voltage, if it rises above the VOUT(CLAMP).
Datasheet 3 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin Assignment BTS3125EJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.2 Transient Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Output On-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Resistive Load Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.1 Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.1.1 Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Reverse Current capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Inverse Current capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Over Voltage Clamping on OUTput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Short Circuit Protection / Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.3 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.4 Diagnostics (STATUS Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 Characterization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.1 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.3 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.4 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table of Contents
Datasheet 4 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
11.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Datasheet 5 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Block Diagram
2 Block Diagram
Figure 1 Block Diagram
OUT
GND
IN
Gate
Driving
Unit
Over-
temperature
Protection
STATUS
ESD
Protection
Status
Feedback
Over
Voltage
Protection
Short circuit
detection /
Current
limitation
Datasheet 6 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment BTS3125EJ
Figure 2 Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol Function
1 IN Input pin
2 NC not connected
3 STATUS Open-drain status feedback (low active)
4 NC not connected
5 NC not connected
6, 7, 8 GND Ground, Source of power DMOS1)
1) All GND pins must be connected together.
cooling
tab
OUT Drain, Load connection for power DMOS
8
7
6
1
2
3
45
1
3
2
8
7
6
45
Datasheet 7 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Pin Configuration
3.3 Voltage and current definition
Figure 3 shows all external terms used in this datasheet, with associated convention for positive values.
Figure 3 Naming definition of electrical parameters
VBAT
GND T4if
IN
VBAT
VIN
IIN
GND
ZL
VOUT,
VDS
OUT
IDD
VDD
VDD
STATUS
ISTATUS
RSTATUS
IL,ID
VSTATUS
Datasheet 8 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings 1)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Voltages
Output voltage VOUT – – 40 V internally clamped P_4.1.1
Battery voltage for short
circuit protection
VBAT(SC) ––31V l = 0 or 5 m
RSC = 20 mΩ + RCable
RCable = l * 16 mΩ/m
LSC = 5 µH + LCable
LCable = l * 1 µH/m
VIN = 5 V
P_4.1.2
Battery voltage for load
dump protection
VBAT(LD) ––40V 2)
RI = 2 Ω
RL = 4.5 Ω
tD = 400 ms
suppressed pulse
P_4.1.4
Input Pin
Input Voltage VIN -0.3 – 5.5 V – P_4.1.7
Input current
in inverse condition on OUT
to GND)
IIN ––2 mA
3)
VOUT < -0.3 V
P_4.1.10
Status Pin
Status Voltage VSTATUS -0.3 – 5.5 V – P_4.1.11
Status current ISTATUS – – 5 mA -0.3 V < VSTATUS < 5.5 V P_4.1.12
Status current in inverse
current condition on STATUS
ISTATUS_L -1 – – mA VSTATUS < -0.3 V P_4.1.13
Power Stage
Load current | IL |––IL(LIM) A– P_4.1.14
Energies
Unclamped single inductive
energy single pulse
EAS ––30mJIL(0) = IL(NOM)
VBAT = 13.5 V
TJ(0) = 150°C
P_4.1.21
Unclamped repetitive
inductive energy pulse with
10k
EAR(10k) ––24mJIL(0) = IL(NOM)
VBAT = 13.5 V
TJ(0) = 105 °C
P_4.1.33
Datasheet 9 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
General Product Characteristics
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Unclamped repetitive
inductive energy pulse with
100k cycles
EAR(100k) ––19mJIL(0) = IL(NOM)
VBAT = 13.5 V
TJ(0) = 105 °C
P_4.1.39
Unclamped repetitive
inductive energy pulse with
1M cycles
EAR(1M) ––15mJIL(0) = IL(NOM)
VBAT = 13.5 V
TJ(0) = 105 °C
P_4.1.45
Temperatures
Operating temperature TJ-40 – +150 °C – P_4.1.52
Storage temperature TSTG -55 – +150 °C – P_4.1.53
ESD Susceptibility
ESD susceptibility (all pins) VESD -3 – 3 kV HBM4) P_4.1.54
ESD susceptibility OUT-pin to
GND
VESD -10 – 10 kV HBM5) P_4.1.55
ESD susceptibility VESD -1 – 1 kV CDM6) P_4.1.56
ESD susceptibility non-
corner pins
VESD -1 – 1 kV CDM7) P_4.1.57
1) Not subject to production test, specified by design.
2) VBAT(LD) is setup without the DUT connected to the generator per ISO 7637-1;
RI is the internal resistance of the load dump test pulse generator;
tD is the pulse duration time for load dump pulse (pulse 5) according ISO 7637-1, -2.
3) Maximum allowed value. Consider also inverse input current in inverse condition IIN(-VOUT) in Chapter 9
4) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
5) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
6) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
7) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
Table 2 Absolute Maximum Ratings 1) (cont’d)
Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Datasheet 10 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
General Product Characteristics
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Table 3 Functional Range 1)
Please refer to “Electrical Characteristics” on Page 22 for test conditions
1) Not subject to production test, specified by design
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Battery Voltage Range for
Nominal Operation
VBAT(NOR) 6.0 13.5 18.0 V – P_4.2.1
Extended Battery Voltage Range
for Operation
VBAT(EXT) 0 – 31 V parameter deviations
possible
P_4.2.2
Input Voltage Range for Nominal
Operation
VIN(NOR) 3.0 – 5.5 V – P_4.2.3
Junction Temperature TJ-40 – 150 °C – P_4.2.5
Datasheet 11 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
General Product Characteristics
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
4.3.1 PCB set up
The following PCB set up was implemented to determine the transient thermal impedance1)
Figure 4 Cross section JEDEC2s2p
Table 4 Thermal Resistance PG-TDSO8-31
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Junction to Soldering Point RthJSP –5.7–K/W
1) 2)
1) Not subject to production test, specified by design
2) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient
temperature).
TA = 85°C. Device is loaded with 1 W power.
P_4.3.6
Junction to Ambient (2s2p) RthJA(2s2p) – 39 – K/W 1) 3)
3) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board;
The product (Chip + Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm
Cu, 2 x 35 µm Cu). Where applicable a thermal via array under the ex posed pad contacted the first inner copper layer.
TA = 85°C, Device is loaded with 1 W power.
P_4.3.12
Junction to Ambient
(1s0p+600 mm2 Cu)
RthJA(1s0p) – 50 – K/W 1) 4)
4) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 1s0p board;
The product (Chip + Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper
area of 600 mm2 and 70 µm thickness. TA = 85°C, Device is loaded with 1 W power.
P_4.3.18
Junction to Ambient
(1s0p+300 mm2 Cu)
RthJA(1s0p) –60–K/W
1) 5)
5) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 1s0p board;
The product (Chip + Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper
area of 300 mm2 and 70 µm thickness. TA = 85°C, Device is loaded with 1 W power.
P_4.3.24
1) (*) means percentual Cu metalization on each layer
70µm modelled (traces)
35µm, 100% metalization*
1
,
5 mm
70µm, 5% metalization*
Datasheet 12 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
General Product Characteristics
Figure 5 Cross section JEDEC1s0p
Figure 6 PCB layout
4.3.2 Transient Thermal Impedance
70µm modelled (traces, cooling area)
1
,
5 mm
70µm; 5% metalization*
Datasheet 13 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
General Product Characteristics
Figure 7 Typical transient thermal impedance ZthJA = f(tp), TA = 85°C
Value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The
product (Chip + Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner
copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Device is dissipating 1 W power.
Figure 8 Typical transient thermal impedance ZthJA = f(tp), Ta = 85°C
Value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board. Device is
dissipating 1 W power.
0
20
40
60
0,000001 0,0001 0,01 1 100 10000
Zth Ja [K/W]
Tp[s]
JEDEC 2s2p
Datasheet 14 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Power Stage
5 Power Stage
5.1 Output On-state Resistance
The on-state resistance depends on the junction temperature TJ. The Figure below show this dependencies in
terms of temperature and voltage for the typical on-state resistance RDS(ON). The behavior in reverse polarity is
described in“Reverse Current capability” on Page 16
Figure 9 Typical On-State Resistance,
RDS(ON) = f(TJ), VIN = 3 V; VIN = 5 V
5.2 Resistive Load Output Timing
Figure 10 shows the typical timing when switching a resistive load.
Figure 10 Definition of Power Output Timing for Resistive Load
0
40
80
120
160
200
240
280
320
-40 -20 0 20 40 60 80 100 120 140
R
DS(ON)
[m:]
T
J
[°C]
3V
5V
t
V
OUT
V
BAT
Switching.
t
10 %
90 %
t
ON
t
DON
t
OFF
t
DOFF
V
IN
V
IN(TH)
50 %
-(
Δ
V/
Δ
t)
ON
(
Δ
V/
Δ
t)
OFF
t
F
t
R
Datasheet 15 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Power Stage
5.3 Inductive Load
5.3.1 Output Clamping
When switching off inductive loads with low side switches, the Drain-Source voltage VOUT rises above battery
potential, because the inductance intends to continue driving the current. To prevent unwanted high voltages
the device has a voltage clamping mechanism to keep the voltage at VOUT(CLAMP). During this clamping
operation mode the device heats up as it dissipates the energy from the inductance. Therefore the maximum
allowed load inductance is limited. See Figure 11 and Figure 12 for more details.
Figure 11 Output Clamp Circuitry
Figure 12 Switching an Inductive Load
GND ( DMOS Source)
OUT ( DMOS Drain
I
GND
V
BAT
Z
L
I
L
V
OUT
t
t
V
OUT
V
BAT
Id ti Ot tCl f
t
I
OUT
V
OUT(CLAMP)
V
IN
Datasheet 16 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Power Stage
5.3.1.1 Maximum Load Inductance
While demagnetization of inductive loads, energy has to be dissipated in the BTS3125EJ.
This energy can be calculated by the following equation:
(5.1)
Following equation simplifies under assumption of RL = 0
(5.2)
For maximum single avalanche energy please also refer to EAS value in “Energies” on Page 8
Figure 13 Maximum load inductance for single pulse
L = f(IL), TJ(0) = TJ, start = 150°C, VBAT = 13.5 V
5.4 Reverse Current capability
A reverse battery situation means the OUT pin is pulled below GND potentials to -VBAT via the load ZL.
L
L
CLAMPOUTBAT
LL
L
CLAMPOUTBAT
CLAMPOUT R
L
I
VV
IR
R
VV
V×
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
×
−×
−
×=
)(
)(
)( 1lnE
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
−×=
)(
2
1
2
1
CLAMPOUTBAT
BAT
L
VV
V
LIE
1
10
100
1000
10000
0,5 1 2 4
I
L
[A]
L [mH]
Datasheet 17 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Power Stage
In this situation the load is driven by a current through the intrinsic body diode of the BTS3125EJ. During
Reverse Battery all protection functions like current limitation, over temperature shut down and over voltage
clamping are not available.
The device is dissipating a power loss which is defined by the driven current and the voltage drop on the DMOS
reverse body diode “-VOUT”.
5.5 Inverse Current capability
An inverse current situation means the OUT pin is pulled below GND potential by a current flowing from GND
to OUT (for example in half-bridge configuration and inductive load using freewheeling via the low side path).
In this situation the load is driven by a current through the intrinsic body diode (device off) of the BTS3125EJ.
During Inverse operation all protection functions like current limitation, over temperature shut down and over
voltage clamping are not available.
The device is dissipating a power loss which is defined by the driven current and the voltage drop on the DMOS
reverse body diode “-VOUT”.
Input current behavior during inverse condition on Output
Please note that during inverse current on drain an increased input current can flow ( IIN(-VOUT)). To limit this
current it is needed to place a resistor (RIN) in line with the input, also to prevent the microcontroller I/O pins
from latching up in this case. The value of this resistor is a compromise of input voltage level in normal
operation and maximum allowed device input current IIN or I/O current (for example of microcontroller).
(5.3)
with IIN(max) = 2 mA (see also “Absolute Maximum Ratings” on Page 8) allow for the device;
VOHµC(max) maximum high level voltage of the control signal (microcontroller I/O)
and assuming -VOUT = 1.1 V (worst case) in inverse condition on the output
If inverse current occurs while the STATUS is active (LOW), the STATUS will be reset (HIGH) after the inverse
current disappears.
5.6 Characteristics
Please see “Power Stage” on Page 14 for electrical characteristic table.
(max)
(max)
(min)
IN
OHuC
IN
I
V
R=
Datasheet 18 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Protection Functions
6 Protection Functions
The device provides embedded protection functions. Integrated protection functions are designed to prevent
IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside”
normal operation. Protection functions are not designed for continuous repetitive operation.
6.1 Over Voltage Clamping on OUTput
The BTS3125EJ is equipped with a voltage clamp circuitry that keeps the drain-source (output to GND) voltage
VDS at a certain level VOUT(CLAMP). The over voltage clamping is overruling the other protection functions. Power
dissipation has to be limited to not exceed the maximum allowed junction temperature.
This function is also used in terms of inductive clamping. Please see also Chapter 5.3.1 for more details.
6.2 Thermal Protection
The device is protected against over temperature due to overload and / or bad cooling conditions. To ensure
this a temperature sensor is located in the power MOSFET.
The BTS3125EJ has a thermal protection function with automatic restart. After the device has switched off due
to over temperature the device will stay off until the junction temperature has dropped down below the
thermal hysteresis “Thermal Protection” on Page 18.
Figure 14 Thermal protective switch OFF scenario with thermal restart
The device also features a digital feedback on the dedicated status pin. This feedback is latched and can be
read out easily by the microcontroller. Please see “Diagnostics” on Page 21 for details on this feedback.
6.3 Short Circuit Protection / Current limitation
The condition short circuit is an overload condition to the device. If the load current reaches the limitation
value of IL(LIM) the device limits the current and therefore will start heating up. When the thermal shutdown
temperature is reached, the device turns off.
The time from the beginning of current limitation until the over temperature switch off depends strongly on
the cooling conditions.
IN
0V
5V
t
Thermal shutdown
t
T
j
T
J(SD)
ΔT
J(SD)_HYS
Thermal _ f ault_ rest art .emf
V
OUT
V
BAT
t
Thermal restart
Datasheet 19 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Protection Functions
If input is still high the device will turn on again after the measured temperature has dropped below the
thermal hysteresis.
Figure 15 shows this simplified behavior.
Figure 15 Short circuit protection via current limitation and over temperature switch off with auto-
restart
6.4 Characteristics
Please see “Protection Functions” on Page 18 for electrical characteristic table.
IN
0
5V
t
T
j
T
J(SD)
Short_circuit_restart.emf
Turn off due to over temperature
I
D
I
L(lim )
Restart into short circuit after cooling down
Restart into normal load condition
V
bat
/Z
sc
ΔT
J(SD)_HYS
t
t
Occurrence of Over current
or high ohmic Short circuit
Datasheet 20 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Input Stage
7 Input Stage
7.1 Input Circuit
Figure 16 shows the input circuit of the BTS3125EJ. In case of open or floating input pin the device will
automatically switch off and remain off. An ESD Zener structure protects the input circuit against ESD pulses.
Figure 16 Simplified Input circuitry
7.2 Characteristics
Please see “Input Stage” on Page 25 for electrical characteristic table.
IN
GND
ESD protection circuit
Input circuit.emf
Datasheet 21 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Diagnostics
8 Diagnostics
The BTS3125EJ provides a latching digital status signal via an open drain style feedback on the STATUS pin.
In case of a detected over temperature condition, the device pulls the STATUS pin down to GND (pin) by an
internal pull-down intend to signal a low level to the micro controller. This pull-down signal stays active also
during thermal restart until the input pin is pulled-down below the input threshold.
In normal operation the status needs to be externally pulled up to a 3 V/5 V supply to signal a high level.
Figure 17 shows this simplified behavior.
Figure 17 Short circuit protection via current limitation and over temperature switch off with auto-
restart and signaling via STATUS pin
IN
0
5V
t
Thermal shutdown
t
T
J
T
J(SD)
V
STATU S
3V/ 5V (V
DD
)
t
0
Auto restart
Status Latch reset
by IN=low
Thermal shutdown
Error Status Latch
ΔT
J( SD ) _ H YS
Datasheet 22 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Electrical Characteristics
9 Electrical Characteristics
9.1 Power Stage
Please see Chapter “Power Stage” on Page 14 for parameter description and further details.
Table 5 Electrical Characteristics: Power Stage
Tj = -40°C to +150°C, VBAT =6 V to 18 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Power Stage
On-State resistance
at hot temperature (150°C)
RDS(ON)_150 – 208 250 mΩTJ = 150°C;
VIN = 5 V;
IL = IL(NOM)
P_9.1.6
On-State resistance
at ambient temperature (25°C)
RDS(ON)_25 – 108 – mΩTJ = 25°C;
VIN = 5 V;
IL = IL(NOM)
P_9.1.12
Nominal load current IL(NOM) –2–A1)
TJ < 150°C;
TA = 85°C
VIN = 5 V
P_9.1.42
OFF state load current,
Output leakage current
IL(OFF)_85 ––0.6µA
2)
VBAT = 13.5 V;
VIN = 0 V;
TJ ≤85°C
P_9.1.48
OFF state load current,
Output leakage current
IL(OFF)_150 –0.51.1µAVBAT = 18 V;
VIN = 0 V;
TJ= 150°C
P_9.1.54
Reverse body diode forward voltage -VOUT –0.81.1VIL = -IL(NOM);
VIN = 0 V
P_9.1.67
Datasheet 23 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Electrical Characteristics
Dynamic characteristics - switching timessingle pulseVBAT = 13.5 V, RL = 10Ω;
for definition details see Figure 10 “Definition of Power Output Timing for Resistive Load” on Page 14
Turn-on time tON 35 75 115 µs 3)
VIN = 0 V to 5 V;
VOUT = 10% VBAT
P_9.1.68
Turn-off time tOFF 70 135 210 µs 4)
VIN = 5 V to 0 V;
VOUT = 90% VBAT
P_9.1.69
Turn-on delay time tDON 51525µsVIN = 0 V to 5 V;
VOUT = 90% VBAT
P_9.1.70
Turn-off delay time tDOFF 40 75 120 µs VIN = 5 V to 0 V;
VOUT = 10% VBAT
P_9.1.71
Fall time, Falling output voltage (turn-
on)
tF30 60 90 µs VIN = 0 V to 5 V;
VOUT = 90% VBAT to
VOUT = 10% VBAT
P_9.1.72
Rise time, Rising output voltage tR30 60 90 µs VIN = 5 V to 0 V;
VOUT = 10% VBAT to
VOUT = 90% VBAT
P_9.1.73
Turn-on Slew rate -(ΔV/Δt)ON 0.22 0.45 0.65 V/µs 5)
VOUT = 90% VBAT to
VOUT = 50% VBAT
P_9.1.74
Turn-off Slew rate (ΔV/Δt)OFF 0.22 0.45 0.65 V/µs 6)
VOUT = 50% VBAT to
VOUT = 90% VBAT
P_9.1.75
1) Not subject to production test, calculated by RthJA (JEDEC 2s2p, PCB) and RDS(ON)
2) Not subject to production test, specified by design;
3) Not subject to production test, calculated with delay time ON and fall time
4) Not subject to production test, calculated with delay time OFF and rise time
5) Not subject to production test, calculated slew rate between 90% and 50% VOUT
6) Not subject to production test, calculated slew rate between 50% and 90% VOUT
Table 5 Electrical Characteristics: Power Stage (cont’d)
Tj = -40°C to +150°C, VBAT =6 V to 18 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 24 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Electrical Characteristics
9.2 Protection
Please see Chapter “Protection Functions” on Page 18 for parameter description and further details.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the data sheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation
Table 6 Electrical Characteristics: Protection
Tj = -40°C to +150°C, VBAT =6 V to 18 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Thermal Protection
Thermal shut down
junction temperature
TJ(SD) 150 175 – °C 1)
3V < VIN < 5.5 V
1) Not subject to production test, specified by design.
P_9.2.1
Thermal hysteresis ΔTJ_HYS –15– K 1) P_9.2.3
Minimum status latch reset time tRESET 50 – – µs 1) 2)
VIN < 0.8 V;
2) Minimum time needed to reset the STATUS latch feedback signal
P_9.2.8
Overvoltage Protection
Drain clamp voltage VOUT(CLAMP) 40 45 – V VIN = 0 V;
IL = 4 mA
P_9.2.14
Current limitation (see also Figure 15)
Current limitation IL(LIM) 7 10.5 14 A VIN = 5 V P_9.2.20
Datasheet 25 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Electrical Characteristics
9.3 Input Stage
Please see Chapter “Input Stage” on Page 20 for description and further details.
9.4 Diagnostics (STATUS Pin)
Please see Chapter “Diagnostics” on Page 21 for description and further details.
Table 7 Electrical Characteristics: Input
Tj = -40°C to +150°C, VBAT =6 V to 18 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Input
Input Current,
normal ON state
IIN(ON) – 82 120 µA VIN = 5.0 V; P_9.3.1
Input Current,
protection mode
IIN(PROT) – 124 180 µA VIN = 5.0 V; P_9.3.8
Input current, inverse condition on
OUT to GND
IIN(-VOUT) – 15 – mA 1) 2)
VOUT < -0.3 V;
-0.3 V ≤ VIN <5.5 V
1) Not subject to production test, specified by design
2) Input current must not exceed the maximum ratings in Chapter 4, P_4.1.10
P_9.3.9
Input pull down current IIN-GND 10 – – µA 3)
VIN = VIN(TH)
3) Not subject to production test, specified by design
P_9.3.10
Input Voltage on-threshold VIN(TH) 0.8 2.3 3 V IL =0.4mA;
Power DMOS
active
P_9.3.11
Table 8 Electrical Characteristics: Diagnostics
Tj = -40°C to +150°C, VBAT =6 V to 18 V, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Status pin voltage drop VSTATUS(ON) ––0.65VISTATUS = 1 mA;
latched fault;
3V≤ VIN < 5.5 V
P_9.4.1
Status pin leakage current
(85°C)
ISTATUS(OFF)_85 –1.56µA
1)
VSTATUS ≤ 5.5 V; TJ
≤ 85°C;
3V≤ VIN < 5.5 V
1) Not subject to production test, specified by design.
P_9.4.2
Status pin leakage current
(150°C)
ISTATUS(OFF)_150 –612µAVSTATUS ≤ 5.0 V;
TJ = 150°C;
3V≤ VIN < 5.5 V
P_9.4.3
Datasheet 26 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
10 Characterization Results
Typical performance characteristics.
10.1 Power Stage
Figure 18 Typical RDS(ON) vs. VIN @ TJ = -40 … 150°C, IL = IL(NOM)
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
3 3.5 4 4.5 5 5.5
RDS(ON) [Ω]
VIN [V]
150°C
85°C
25°C
-40°C
Datasheet 27 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 19 Typical RDS(ON) vs. TJ @ VIN = 3 … 5.5 V; IL = IL(NOM)
Figure 20 Typical Reverse Diode |VOUT| vs. TJ @ IL = -IL(NOM)
0
0.05
0.1
0.15
0.2
0.25
0.3
-40-200 256085105125150
RDS(ON) [Ω]
TJ[°C]
3V
3.5V
4V
5V
5.5V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-40 0 85 150
|V
OUT
| [V]
T
J
[°C]
Datasheet 28 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 21 Typical IL(OFF) vs. VDS @ TJ = -40 … 150°C, VIN = 0 V
Figure 22 Typical IL(OFF) vs. VIN @ TJ = -40 … 150°C, VBAT = 6 … 18 V
0.0E+00
5.0E-07
1.0E-06
1.5E-06
2.0E-06
2.5E-06
0 5 10 15 20 25 30
IL(OFF)[A]
V
DS
[V]
150°C
85°C
-40°C
25°C
0.0E+00
5.0E-07
1.0E-06
1.5E-06
2.0E-06
2.5E-06
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
I
L(OFF)
[A]
V
IN
[V]
6V - -40°C
6V - 25°C
6V - 85°C
6V - 150°C
13.5V - -40°C
13.5V - 25°C
13.5V - 85°C
13.5V - 150°C
18V - -40°C
18V - 25°C
18V - 85°C
18V - 150°C
Datasheet 29 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 23 Typical destruction point. EAS vs. IL @ TJ(0) = 25°C and 150°C, VBAT = 13.5 V
Figure 24 Typical EAR vs. IL @ TJ(0)= 25°C and 105°C, VBAT = 13.5 V
0
500
1000
1500
2000
2500
3000
3500
0.5 1 2 4
25°C
150°C
IL[A]
EAS [mJ]
0
10
20
30
40
50
60
2 2,2 2,4 2,6 2,8 3 3,2 3,4 3,6 3,8 4
E
AR
[mJ]
I
L
[A]
10K cycles, 25°C
100k cycles, 25°C
10k cycles, 105°C
100k cycles, 105°C
Datasheet 30 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 25 Typical EAR vs. Nr of cycles @ TJ(0) = 25°C and 105°C, VBAT = 13.5 V
Dynamic characteristics (switching times):
Figure 26 Typical tF, tR vs VIN @ TJ = -40 … 150°C
0
10
20
30
40
50
60
1,0E+0 10,0E+0 100,0E+0 1,0E+3 10,0E+3 100,0E+3 1,0E+6 10,0E+6
EAR [mJ]
Nr. of Cycles
2A, 25°C
4A, 25°C
2A, 105°C
4A, 105°C
0
50
100
150
200
250
3 3.5 4 4.5 5 5.5
t
F
, t
R
[us]
V
IN
[V]
-40°C - Fall time
25°C - Fall time
150°C - Fall time
-40°C - Rise time
25°C - Rise time
150°C - Rise time
Datasheet 31 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 27 Typical tDON, tDOFF vs VIN @ TJ = -40 … 150°C
Figure 28 Typical -(ΔV/Δt)ON, (ΔV/Δt)OFF vs VIN @ TJ = -40 … 150°C
0
10
20
30
40
50
60
70
80
90
3 3.5 4 4.5 5 5.5
tOON, tDOFF [us]
VIN [V]
-40°C - Delay off time
25°C - Delay off time
150°C - Delay off time
-40°C - Delay on time
25°C - Delay on time
150°C - Delay on time
0
0.1
0.2
0.3
0.4
0.5
0.6
3 3.5 4 4.5 5 5.5
-(ΔV/Δt)
ON
, (ΔV/Δt)
OFF
[V/us]
V
IN
[V]
150°C - Slew rate on
25°C - Slew rate on
-40°C - Slew rate on
-40°C - Slew rate off
25°C - Slew rate off
150°C - Slew rate off
Datasheet 32 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 29 Tyipcal tF, tR vs VBAT @ VIN = 5 V, TJ = -40 … 150°C
Figure 30 Typical tDON, tDOFF vs VBAT @ VIN = 5 V, TJ = -40 … 150°C
0
10
20
30
40
50
60
70
80
90
6 1116212631
t
F
, t
R
[us]
V
BAT
[V]
-40°C - Rise time
25°C - Fall time
150°C - Fall time
150°C - Rise time
25°C - Rise time
-40°C - Rise time
0
20
40
60
80
100
120
6 1116212631
tDON, tDOFF [us]
VBAT [V]
-40°C - Delay off time
25°C - Delay off time
150°C - Delay off time
-40°C - Delay on time
25°C - Delay on time
150°C - Delay on time
Datasheet 33 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 31 Typical -(ΔV/Δt)ON, (ΔV/Δt)OFF vs VBAT @ VIN = 5 V, TJ = -40 … 150°C
Figure 32 Typical tF, tR vs IL @ VIN = 5 V, TJ = -40 … 150°C
0
0.2
0.4
0.6
0.8
1
1.2
6 1116212631
-(ΔV/Δt)
ON
,(ΔV/Δt)
OFF
[V/us]
V
BAT
[V]
150°C - Slew rate on
25°C - Slew rate on
-40°C - Slew rate on
-40°C - Slew rate off
25°C - Slew rate on
150°C - Slew rate off
0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5 3
-40°C - Fall time
25°C - Fall time
150°C - Fall time
150°C - Rise time
25°C - Rise time
-40°C - Rise time
I
L
[A]
t
R
, t
F
[us]
Datasheet 34 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 33 Typical tDON, tDOFF vs IL @ VIN = 5 V, TJ = -40 … 150°C
Figure 34 Typical -(ΔV/Δt)ON, (ΔV/Δt)OFF vs IL @ VIN = 5 V, TJ= -40 … 150°C
0
10
20
30
40
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3
-40°C - Delay off time
25°C - Delay off time
150°C - Delay off time
-40°C - Delay on time
25°C - Delay on time
150°C - Delay on time
IL[A]
tDON, tDOFF [us]
0
0.1
0.2
0.3
0.4
0.5
0.6
0 0.5 1 1.5 2 2.5 3
150°C - Slew rate on
25°C - Slew rate on
-40°C - Slew rate on
-40°C - Slew rate off
25°C - Slew rate off
150°C - Slew rate off
I
L
[A]
-(ΔV/Δt)
ON
, (ΔV/Δt)
OFF
[V/us]
Datasheet 35 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 35 Typical tF, tR vs TJ @ VIN = 5 V
Figure 36 Typical tDON, tDOFF vs TJ @ VIN = 5 V
0
10
20
30
40
50
60
70
-40 25 85 150
5 - Rise time
5 - Fall time
T
J
[°C]
t
F
, t
R
[us]
0
10
20
30
40
50
60
70
80
90
-40 25 85 150
5 - Delay on time
5 - Delay off time
T
J
[°C]
t
DON
, t
DOFF
[us]
Datasheet 36 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 37 Typical -(ΔV/Δt)ON, (ΔV/Δt)OFF vs TJ @ VIN = 5 V
0
0.1
0.2
0.3
0.4
0.5
0.6
-40 25 85 150
5 - Average of Slew rate on
5 - Average of Slew rate off
T
J
[°C]
-(ΔV/Δt)
ON
, (ΔV/Δt)
OFF
[us]
Datasheet 37 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
10.2 Protection
Figure 38 Typical VOUT(CLAMP) vs. TJ @ IL = 4 mA
Figure 39 Typical IL(LIM) vs. VBAT @ TJ = -40 … 150°C, VIN = 3 V and 5 V
40
41
42
43
44
45
46
47
48
49
50
-40 0 85 150
V
OUT(CLAMP)
[V]
T
J
[°C]
0
2
4
6
8
10
12
6 1116212631
I
L(LIM)
[A]
V
BAT
[V]
5V - -40°C
5V - 25°C
5V - 85°C
5V - 150°C
3V - -40°C
3V - 25°C
3V - 85°C
3V - 150°C
Datasheet 38 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
10.3 Input Stage
Figure 40 Typical VIN(TH) vs. TJ @ IL = 0.4 mA
Figure 41 Typical IIN(ON) vs. VIN @ TJ = -40 … 150°C, IL = IL(NOM)
0
0.5
1
1.5
2
2.5
3
-40 25 85 150
V
IIN(TH)
[V]
T
J
[°C]
Vth_rising
Vth_falling
0.0E+00
2.0E-05
4.0E-05
6.0E-05
8.0E-05
1.0E-04
1.2E-04
1.4E-04
1.6E-04
3.00 3.50 4.00 4.50 5.00 5.50
IIN(ON) [A]
V
IN
[V]
150°C
85°C
25°C
-40°C
Datasheet 39 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 42 Typical IIN(PROT) vs. VIN @ TJ = -40 … 150°C, IL = IL(NOM)
000.0E+0
20.0E-6
40.0E-6
60.0E-6
80.0E-6
100.0E-6
120.0E-6
140.0E-6
160.0E-6
3 3.5 4 4.5 5 5.5
I
IN(PROT)
[A]
V
IN
[V]
150°C
85°C
25°C
-40°C
Datasheet 40 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
10.4 Diagnosis
Figure 43 Typical VSTATUS(ON) vs. VIN @ TJ = -40 … 150°C
Figure 44 Typical ISTATUS(OFF) vs. TJ @ VSTATUS = 3 … 5.5 V, VIN = 0 V
0
0.1
0.2
0.3
0.4
0.5
0.6
3 3.5 4 4.5 5 5.5
V
STATUS(ON)
[V]
V
IN
[V]
150°C
85°C
25°C
-40°C
0.0E+00
1.0E-06
2.0E-06
3.0E-06
4.0E-06
5.0E-06
6.0E-06
7.0E-06
-40 25 85 150
3V
4V
5V
5.5V
T
J
[°C]
I
STATUS(OFF)
[A]
Datasheet 41 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Characterization Results
Figure 45 Typical tRESET vs TJ @ VIN = 0 … 0.8 V
0
1
2
3
4
5
6
7
-40 25 85 150
0V
0.4V
0.8V
T
J
[°C]
t
RESET
[us]
Datasheet 42 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Application Information
11 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
11.1 Application Diagram
An application example with the BTS3125EJ is shown below.
Figure 46 Application example circuitry
Recommended values for VIN= 5 V and VDD= 5 V:
RSTATUS=4.7 kΩ
RSTATUS(PROT)=3.3 kΩ
RIN=3.3 kΩ
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application.
V
BAT
R
IN
Voltage
Regulator
IN
OUT
Load
R
ST ATU S
OUT
GND
IN
ST ATUS
I/O
PW M
Micro
controller
GND
VDD
I
R
ST ATU S (PR O T )
Datasheet 43 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Package Outlines
12 Package Outlines
Figure 47 PG-TDSO8-31
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
Datasheet 44 Rev. 1.0
2016-09-12
HITFET - BTS3125EJ
Smart Low-Side Power Switch
Revision History
13 Revision History
Version Date Changes
Rev. 1.0 2016-09-12 Datasheet released
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2016-09-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
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characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
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hereby disclaims any and all warranties and liabilities
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