PRELIMINARY CY7C109A 128K x 8 Static RAM Features Functional Description Reading from the device NCE and ont. . . : by taking chip enable one (CE)) and out- e High speed The CY7C109A is a high-performance put enable (OE) LOW while forcing write ta, = 12 ns CMOS static RAM organized as 131,072 enable (WE) and chip enable two (CE) CMOS for optimum speed/power @ Low active power words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE}), an active HIGH chip enable (CE), HIGH. Under these conditions, the con- tents of the memory location specified by the address pins will appear on the I/O 1020 mW an active LOW output enable (OE), and jing e Low standby power three-state drivers. This device has an au- P* 250 mw ype tomatic power-down teahare that reduces The eight input/output pins (I/O through m power consumption by more than 75% 1/),) are placed in a high-impedance state * 2.0V data retention (optional) when deselected, when the device is deselected (CE, HIGH 100 nw Writing to the device is accomplished by or CE; LOW), the outputs are disabled e Automatic power-down when deselected @ TITL-compatible inputs and outputs Easy memory expansion with CE;, taking chip enable one (CE1) and write en- able (WE) inputs LOW and chip enable two (CE,) input HIGH. Data on the eight V/O pins (/Op through O07} is then written into the location specified on the address (OE HIGH), or during a write operation (CE; LOW, CE; HIGH, and WE LOW). The CY7C109 is available in standard 400-mil-wide DIPs and SOJs and aleadless CE, and OE options pins (Ap through Aig). chip carrier. Logic Block Diagram Pin Configurations DIP/SOJ rrrentee Citta cot VOo INPUT BUFFER vO, i VOo 3 # a 512x256x8 = VO3 = ARRAY 3 @ a VO4 VOs VOg __ COLUMN CE! DECODER We VO 1094-1 Top View Selection Guide FICH9A-T2 7C109A15 7C109A20 701094 25 7C109A35 Maximum Access Time (ns} 12 15 20 25 35 Maximum Operating | Commercial 185 170 155 145 140 Current (mA) Military 180 170 160 150 Maximum Standby Commercial 45 40 30 30 25 Current (mA) Military 40 30 30 25 Shaded area contains advanced information, 3901 North First Street @ SanJose @ CA95134 408-943-2600 December 1992 Revised February 1996 Cypress Semiconductor Corporation PRELIMINARY _CY7C109A Maximum Ratings (Above whichthe useful life may be impaired. For user guidelines, Latch-Up Current .................. 0002 e eee >200 mA not tested.) Storage Temperature ............0000055 -65C to +150C Operating Range Ambient Temperature with Ambient QR] Power Applied .........0cceeeevcereees =55C to 125C Range Temperature Yec Supply Voltage on Vcc to Relative GNDU) .. -0.5V to +7.0V Commercial 0C to +70C 5V + 10% DC Voltage Applied to Outputs Military 55C to +125C $V + 10% in High Z Statell] 1.0.02... -0.5V to Vcc +0.5V DC Input Voltagel!) .... 0... -0.5V to Vcc +0.5V rae (arin) = ~200V for pulee durations of leas than 20 . . IL (mMn.} = <2! Or pulse durations of less than ns. Current into Outputs (LOW) .............0000 ee eee 20 mA 2. Ta is the instant on case temperature. Static Discharge Voltage ...............000000 005 >2001V (per MIL-STD-883, Method 3015) Electrical Characteristics Over the Operating Rangel?) FCIOIA12 TCIOVA-15 7C109A20 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Vcc = Min., Jog = 40 mA 2.4 24 24 Vv Voltage VoL Output LOW Vcc = Min., Io, = 8.0 mA 0.4 0.4 0.4 Vv Voltage Vin Input HIGH 22 PVeot] 22 [Vocot] 22 [Vecot+] V Voltage 0.3 0.3 0.3 VIL Input LOW 03 | G8 0.3 0.8 -0.3 0.8 Vv Voltagel] Ix Input Load GND < V1 < Vcc ~1 +1 -1 +1 -1 +1 pA Current loz Output Leakage GND < V] <= Veo -5 +5 -5 +5 -5 +5 pA Current Output Disabled los Output Short Vcc = Max., Vout = GND +300 300 -300 | mA Circuit Currentl4] Icc Vcc Operating Vcc = Max., Com! 185 170 155 mA Supply Current lout = OmA, - f = fMax = Ltrc Mil 180 170 Igpi Automatic CE Max. Vcc, CEy > Vy | Com'l 4 40 30 mA Power-Down or CE, < Viz, Current Vin > Ving or ; TIL Inputs Vin < Vi. f = imax Mil 40 30 Isp Automatic CE Max. Vcc, Com'l 10 10 10 mA Power-Down CE, = Voc 0.3V, L 3 3 z Current or CE; < 0.3V, . CMOS Inputs | Vn > Vec 0.3V, Mil 10 10 or fy <03V,f=0 L 2 2 Shaded area contains advanced information.. eh PE a ee a co & CYPRESS PRELIMINARY _CY7C109A Electrical Characteristics Over the Operating Rangel] (continued) 7C109A25 7C1O9A35 Parameter Description Test Conditions Min. Max. Min. Max. Unit Vou Output HIGH Voltage | Vcc = Min., Ion = 4.0 mA 2.4 24 Vv VoL Output LOW Voltage | Vcc = Min., IoL = 8.0 mA 0.4 0.4 Vv Vi Input HIGH Voltage 2.2 Vecot+ 2.2 Veco t+ Vv 0.3 0.3 VIL Input LOW Voltagel!] -0,3 08 -063 0.8 Vv Ix Input Load Current GND < VV] < Vcc -1 +1 -1 +1 pA loz. Output Leakage GND < V|< Vcc, -5 +5 -5 +5 pA Current Output Disabled los Output Short Vcc = Max., Vout = GND 300 300 mA Cireuit Currentl4] Iec Vcc Operating Voc = Max Com'l 145 140 mA Supply Current Jour = OmA, - f = fax = IAtrc Mil 160 150 Ispi Automatic CE Max. Voc, CE) > Vin Com'l 30 25 mA Power-Down or CEs < Vin, Current Vin = Vin or ; TIL Inputs Vin < Vib. f = imax Mil 30 25 Isp Automatic CE Max. Voc, Com'l 10 10 mA Power-Down CE > Vcc 039, L 3 Current or CE) < 0,3, - CMOS Inputs Vin > Voc 0.3V, Mil 10 10 or =< 03V,f=0 L 2 2 Capacitancel>) Parameter Description Test Conditions Max. Unit Cin: Addresses Input Capacitance Ta = 25C, f = 1 MHz, 7 pF Cin: Controls Voc = 9.0V 10 pF CouT Output Capacitance 10 pF Notes: 3. See the last page of this specification for Group A subgroup testing ALL INPUT PULSES information. these parameters. 4, Notmore than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. AC Test Loads and Waveforms Ri 4802 Ri 4808 NV Os Nw 3.0V OUTPUT oT 3 OUTPUT oT 4 30 pF s Re 5 pF $ R2 GND 2550 2552 INCLUDING L L INCLUDING L L <3ns JIG AND JIG AND SCOPE (a) SCOPE (b) 1098-4 Equivalent to: THEVENIN EQUIVALENT 1672 OUTPUT Ovrr0__si.73V 90% 10% . 1 5. Tested initially and after any design or process changes that may affect O9A-5PRELIMINARY _CY7C109A Switching Characteristics). 6 Over the Operating Range 7C109A12 | 7C109A-15 | 7C109A20 | 7C109A25 | 7C109A35 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Min. | Unit READ CYCLE tre Read Cycle Time 12 15 20 25 35 ns tad Address to Data Valid 12 15 20 25 35 ns toHA Data Hold from Address Change 3 3 3 3 3 ns tace CE, LOW to Data Valid, CE2 HIGH 12 15 20 25 35 ns to Data Valid tpog OE LOW to Data Valid 6 7 8 10 10 | ns tLZOE OE LOW to Low Z 0 0 0 0 0 ns tHZOE OE HIGH to High ZI? 8) 6 7 8 10 10 | ns tLZCE CE, LOW to Low Z,CE2 HIGH to] 3 3 3 3 3 ns Low ZI] tHzcE CE, HIGH to High Z, CE; LOW to 6 7 8 10 10 ns High ZI7. 3] teu CE; LOW to Power-Up,CE,HIGH | 0 0 0 0 0 ns to Power-Up tpp CE, HIGH to Power-Down, 12 15 20 25 35 | ns CE, LOW to Power-Down WRITE CYCLEL?. 10] twe Write Cycle Time 12 15 20 25 35 ns tscE CE} LOW to Write End,CE;HIGH | 10 12 15 20 25 ns to Write End taw Address Set-Up to Write End 10 12 15 20 25 ns tHa Address Hold from Write End 0 0 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 0 0 ns tpwE WE Pulse Width 10 12 15 20 25 ns tsp Data Set-Up to Write End 7 8 10 15 20 ns typ Data Hold from Write End 0 0 0 0 0 ns tLZWE WE HIGH to Low Z/I 3 3 3 3 3 ns tuzwe WE LOW to High zl: 3] 6 7 8 10 10 | ns Shaded area contains advanced information. Notes: 6, Test conditions assume signal transition time of 3 ns or less.timingref- 9, The internal write time of the memory is defined by the overlap of CE, erence levels of 1.5 V, input pulse levels of 0 to 3.0V, and output loading of the specified Ip) /Igy and 30-pF load capacitance. tyzor. tzce. and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage. At any given temperature and voltage condition. tyzcr is less than tuzcR. tyzog is less than tL7og. and tyzwep is less than tz wefor any given device. 10. LOW. CE, HIGH, and WE LOW. CE, and must be LOW and CE, HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. The minimum write cycle time for Write Cycle No. 3 (WE controlled, GE LOW) is the sum of tyzwe and tsp.PRELIMINARY _CY7C109A Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions!) Min. | Max. | Min. | Max. | Unit VDR Vcc for Retention Data 2.0 2.0 Vv Iccpr Data Retention Current Vec = Vor = 2.0V, 50 70 LA CE; > Vcc 0.3V or tcprb) Chip Deselect to Data Retention Time CE) < 0.3V, 0 0 ns : = VIN = Vec 0.3V or tpl) Operation Recovery Time Vin <.0.3V tre tre ns Note: 11. No input may exceed Voc +0.5V. Data Retention Waveform DATA RETENTION MODE >+ Voc 4.5V Vor = 2V A 45v topp tp e Z 109A-6 Switching Waveforms Read Cycle No. 1112: 13] # tre | ADDRESS x nat taa | DATA OUT PREVIOUS DATA VALID *KxXKXK DATA VALID 100A-7 Read Cycle No. 2 (OE Controlled)[!3: 14] ADDRESS CE tooe HIGH IMPEDANCE tLz0E HIGH IMPEDANCE DATA OUT DATA VALID tLzce to Voc tpu \ ICG SUPPLY 50% 50% X CURRENT ISB 1098-8 Notes: 12. Device is continuously selected. OE. CE, = Vy_. CE2 = Vyy. 14. Address valid prior to or coincident with CE transition LOW and CE, 13. WE is HIGH for read cycle. transition HIGH.PRELIMINARY _CY7C109A Switching Waveforms (continued) Write Cycle No. 1 (CE, or CE; Controllea)l"5. 16] ADDRESS CE, CE> WE DATA VO two tpwe <n fT) tup DATA VALID 1094-9 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)l!>: 16] two ADDRESS x* tsce LZ Yj [* tsce YY SS taw tHa " - wm r i AMS tpwe oY tsp tp rt tHZ0E DATAin VALID > 1094-10 Notes: 15. Data /O is high impedance if OE = Vyy. 16. If CE, goes HIGH or CE, goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.PRELIMINARY _CY7C109A Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW). 16] 7 twe > ADDRESS x x * tsce * CE, MX, LE LZ CE2 WLW Ze t 7 YX S SCE * * taw re tha i toa a tpwe * We x ae tsp eea Hp DATAW/O KKK KK KK DATA VALID / xxx tHZzwe bt tL 2WE 1090-11 Truth Table CE, | CE; | OE | WE | Input/Output Mode Power H xX | X | X | HighZ Power-Down Standby (Isp) x L |X |] X | HighZ Power-Down Standby (Isp) L H L | H | Data Out Read Active (Icc} L H | X | L | DatalIn Write Active (Icc} L H | H | H | HighZ Selected, Outputs Disabled | Active cc} Ordering Information Speed Package Package Type Operating (ns) Ordering Code Name Range 12 CY7CLIO9A12PC P43 32-Lead (400-Mil}) Molded DIP | Commercial CY7TCLO9A-12VC V33 32-Lead (400-Mil) Molded SO} 15 CY7C109A-15PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109A-15VC V33 32-Lead (400-Mil) Molded SO] CY7C109A15DMB Dd4 32-Lead (400-Mil} CerDIP Military CY7C109A15LMB Lis 32-Pin Leadless Chip Carrier 20 CY7C109A20PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7CLOIA20VC V33 32-Lead (400-Mil) Molded SOJ CY7C109A20DMB Dd4 32-Lead (400-Mil} CerDIP Military CY7C109A 20LMB L75 32-Pin Leadless Chip Carrier Shaded area contains advanced information. Contact factory for L version availability.PRELIMINARY _CY7C109A Ordering Information (continued) Speed Package Operating (ns) Ordering Code Name Package Type Range 25 CY7C109A25PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7TC1N9A25VC V33 32-Lead (400-Mil) Molded SOJ CY7C109A25DMB p44 32-Lead (400-Mil) CerDIP Military CY7C109A-25LMB L75 32-Pin Leadless Chip Carrier 35 CY7C109A35PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109A35VC V33 32-Lead (400-Mil) Molded SOJ CY7C109A-35DMB D44 32-Lead (400-Mil) CerDIP Military CY7C109A-35LMB L7s 32-Pin Leadless Chip Carrier Contact factory for L version availability. MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics DC Characteristics Parameter Subgroups Parameter Subgroups READ CYCLE Vou 1,2,3 tre 7,8, 9,10, 11 VoL 1,2,3 taAA 7,8, 9, 10,11 VIH 1,2,3 toHA 7, 8, 9, 10, 11 Vir, Max. 1,2,3 tack 7, 8, 9, 10, 11 Ix 1, 2,3 tpoE 7, 8,9, 10, 11 loz 1,2,3 WRITE CYCLE Tec 1,2,3 twe 7,8, 9, 10, 11 Isp1 1,2,3 tsce 7,8, 9, 10, 11 Isp2 1,2,3 taw 7, 8, 9, 10, 11 THA 7, 8, 9, 10, 11 tsa 7,8, 9, 10,11 tpwE 7,8, 9, 10,11 tsp 7, 8, 9, 10, 11 typ 7, 8, 9, 10, 11 Document #; 38-00233-BeRe i PRELIMINARY _CY7C109A eee CYPRESS Package Diagrams 32-Lead (400-Mil) CerDIP D44 32-Pin Leadless Chip Carrier L75 PIN 1 aa .. ALO ws [~ DIMENSIONS IM INCHES PIN L., Ee = e nar ocean cme im meee: 5 ct Htriririty DIMEN 31063 IM INCHE 5 E a \ a. MIM, = ct MAY Fo ol 740 Eb Cy Feo 4 qo 7 008 P. fet I cy fe PLACE BATE PLANE FI ce Ef] ci oo Fo oq ee Aet fr] Gy ets 5 qo = = qa oF be ogo Lod | - 15 colin 32-Lead (400-Mil) Molded DIP P43 PIN 1 Lia 1a nn nn th 1 )) (iar Twrt)it?,r fret 2 i DIMENSIONS IN INCHES MIM, Mar. 0.040 0.070 L580 . Leet SEATING PLANE ES th - \A les Oel0 Mar, n135 OS 0.015 MIN, pwr . m6 01S J 3 MIt ~ 0.014 o-410 0.022 14es=e 3s % POP Pag ered - Cre Package Diagrams (continued) DIMEMIION IM INCHES MIM MAS, PRELIMINARY _CY7C109A 32-Lead (400-Mil) Molded SOJ V33 ExTEPMAL LEAD Mf} fff 4} ff ff ff ff Pe 1 a} iat tt - Paul iT. UUUUUUUUUUUUUUUY i Oat TIP, Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied ina Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or otherrights. Cypress Semicon- ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in lite support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.