IS62WV12816ALL IS62WV12816BLL 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES NOVEMBER 2013 DESCRIPTION The ISSI IS62WV12816ALL/ IS62WV12816BLL are high- * High-speed access time: 45ns, 55ns, 70ns speed, 2M bit static RAMs organized as 128K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. * CMOS low power operation - 36 mW (typical) operating - 9 W (typical) CMOS standby * TTL compatible interface levels When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. * Single power supply - 1.65V--2.2V Vdd (62WV12816ALL) - 2.5V--3.6V Vdd (62WV12816BLL) * Fully static operation: no clock or refresh required Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. * Three state outputs * Data control for upper and lower bytes * Industrial temperature available The IS62WV12816ALL and IS62WV12816BLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). * 2CS Option Available * Lead-free available FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS2 CS1 OE WE UB LB CONTROL CIRCUIT Copyright (c) 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 1 IS62WV12816ALL, IS62WV12816BLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) 48-Pin mini BGA (6mm x 8mm) (Package Code B) 1 2 3 4 5 6 1 2 3 4 5 6 A LB OE A0 A1 A2 N/C A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CSI C I/O9 I/O10 A5 A6 I/O1 I/O0 B I/O8 UB A3 A4 CS1 I/O0 I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC 44-Pin mini TSOP (Type II) (Package Code T) A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816ALL, IS62WV12816BLL TRUTH TABLE I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Not Selected X H X X X X High-Z High-Z X X L X X X High-Z High-Z X X X X H H High-Z High-Z Output Disabled H L H H L X High-Z High-Z H L H H X L High-Z High-Z Read H L H L L H Dout High-Z H L H L H L High-Z Dout H L H L L LDoutDout Write L L H X L H Din High-Z L L H X H L High-Z Din L L H X L LDinDin Vdd Current Isb1, Isb2 Isb1, Isb2 Isb1, Isb2 Icc Icc Icc Icc ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Tstg Pt Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value -0.2 to Vdd+0.3 -65 to +150 1.0 Unit V C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE (Vdd) Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C IS62WV12816ALL 1.65V - 2.2V 1.65V - 2.2V Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816BLL 2.5V - 3.6V 2.5V - 3.6V 3 IS62WV12816ALL, IS62WV12816BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Vdd Voh Output HIGH Voltage Ioh = -0.1 mA 1.65-2.2V Ioh = -1 mA 2.5-3.6V Vol Output LOW Voltage Iol = 0.1 mA 1.65-2.2V Iol = 2.1 mA 2.5-3.6V Vih Input HIGH Voltage 1.65-2.2V 2.5-3.6V (1) Vil Input LOW Voltage 1.65-2.2V 2.5-3.6V Ili Input Leakage GND Vin Vdd Ilo Output Leakage GND Vout Vdd, Outputs Disabled Min. 1.4 2.2 -- -- 1.4 2.2 -0.2 -0.2 -1 -1 Max. -- -- 0.2 0.4 Vdd + 0.2 Vdd + 0.3 0.4 0.8 1 1 Unit V V V V V V V V A A Notes: 1. Vil (min.) = -1.0V for pulse width less than 10 ns. CAPACITANCE(1) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 8 10 Unit pF pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. 4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816ALL, IS62WV12816BLL IS62WV12816ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Max. 70 Icc Vdd Dynamic Operating Vdd = Max., Com. 15 Supply Current Iout = 0 mA, f = fmax Ind. 20 Icc1 Operating Supply Vdd = Max., Com. 3 Current Iout = 0 mA, f = 0 Ind.3 Isb1 TTL Standby Current Vdd = Max., Com. 0.3 (TTL Inputs) Vin = Vih or Vil Ind. 0.3 CS1 = Vih , CS2 = Vil, f = 1 MHz OR ULB Control Isb2 CMOS Standby Current (CMOS Inputs) Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Vdd = Max., Com. CS1 Vdd - 0.2V, Ind. CS2 0.2V, Vin Vdd - 0.2V, or Vin 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, CS2=Vih Vin 0.2V, f = 0; UB / LB = Vdd - 0.2V 5 10 Unit mA mA mA A IS62WV12816BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test ConditionsMax. 45 Icc Vdd Dynamic Operating Vdd = Max., Com. 35 Supply Current Iout = 0 mA, f = fmax Ind. 40 typ.(2) 25 Icc1 Operating Supply Vdd = Max., Com. 3 Current Iout = 0 mA, f = 0 Ind.3 Isb1 TTL Standby Current Vdd = Max., Com. 0.3 (TTL Inputs) Vin = Vih or Vil Ind.0.3 CS1 = Vih , CS2 = Vil, f = 1 MHz OR ULB Control Isb2 CMOS Standby Current (CMOS Inputs) Vdd = Max., Vin = Vih or Vil CS1 = Vil, f = 0, UB = Vih, LB = Vih Vdd = Max., Com. 10 CS1 Vdd - 0.2V, Ind. 10 CS2 0.2V, typ.(2) 3 Vin Vdd - 0.2V, or Vin 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = Vil, CS2=Vih Vin 0.2V, f = 0; UB / LB = Vdd - 0.2V Max. Unit 55 25 mA 30 20 3 mA 3 0.3 mA 0.3 10 10 3 A Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 5 IS62WV12816ALL, IS62WV12816BLL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 62WV12816ALL (Unit) 0.4V to Vdd-0.2V 5 ns Vref See Figures 1 and 2 1.65-2.2V 2.5V - 3.6V R1() 3070 3070 R2() 3150 3150 Vref 0.9V 1.5V Vtm 1.8V 2.8V 62WV12816BLL (Unit) 0.4V to Vdd-0.3V 5ns Vref See Figures 1 and 2 AC TEST LOADS R1 VTM OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 6 R1 VTM R2 5 pF Including jig and scope R2 Figure 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816ALL, IS62WV12816BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter 45 ns Min. Max. 55 ns Min. Max. 70 ns Min. Max. Unit trc Read Cycle Time 45 -- 55 -- 70 -- ns taa Address Access Time -- 45 -- 55 -- 70 ns toha Output Hold Time 10 -- 10 -- 10 -- ns tacs1/tacs2 CS1/CS2 Access Time -- 45 -- 55 -- 70 ns tdoe OE Access Time -- 20 -- 25 -- 35 ns thzoe OE to High-Z Output -- 15 -- 20 -- 25 ns tlzoe(2) OE to Low-Z Output 5 -- 5 -- 5 -- ns thzcs1/thzcs2(2) CS1/CS2 to High-Z Output 0 15 0 20 0 25 ns tlzcs1/tlzcs2 CS1/CS2 to Low-Z Output 10 -- 10 -- 10 -- ns tba LB, UB Access Time -- 45 -- 55 -- 70 ns thzb LB, UB to High-Z Output 0 15 0 20 0 25 ns tlzb LB, UB to Low-Z Output 0 -- 0 -- 0 -- ns (2) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 7 IS62WV12816ALL, IS62WV12816BLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = Vil, CS2 = WE = Vih, UB or LB = Vil) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1 tHZOE tLZOE tACE1/tACE2 CS2 tLZCE1/ tLZCE2 tHZCS1/ tHZCS2 LB, UB tLZB DOUT tBA tHZB HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = Vil. CS2=WE=Vih. 3. Address is valid prior to or coincident with CS1 LOW transition. 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816ALL, IS62WV12816BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol twc Parameter Write Cycle Time 45ns Min. Max. 55 ns Min. Max. 70 ns Min. Max. Unit 45 -- 55 -- 70 -- ns tscs1/tscs2 CS1/CS2 to Write End 35 -- 45 -- 60 -- ns taw Address Setup Time to Write End 35 -- 45 -- 60 -- ns tha Address Hold from Write End 0 -- 0 -- 0 -- ns tsa Address Setup Time 0 -- 0 -- 0 -- ns tpwb LB, UB Valid to End of Write 35 -- 45 -- 60 -- ns tpwe WE Pulse Width 35 -- 40 -- 50 -- ns tsd Data Setup to Write End 20 -- 25 -- 30 -- ns thd Data Hold from Write End 0 -- 0 -- 0 --ns (3) thzwe WE LOW to High-Z Output -- 20 -- 20 -- 20 ns (3) tlzwe WE HIGH to Low-Z Output 5 -- 5 -- 5 -- ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 9 IS62WV12816ALL, IS62WV12816BLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tPWB LB, UB tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). 10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816ALL, IS62WV12816BLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 tHD DATA-IN VALID 11 IS62WV12816ALL, IS62WV12816BLL AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 12 tHD DATA-IN VALID Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816ALL, IS62WV12816BLL AC WAVEFORMS WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW CS2 HIGH t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 13 IS62WV12816ALL, IS62WV12816BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 1.0 3.6 V Idr Data Retention Current Vdd = 1.0V, CS1 Vdd - 0.2V -- 10 A tsdr Data Retention Setup Time See Data Retention Waveform 0 -- ns trdr Recovery Time See Data Retention Waveform trc -- ns DATA RETENTION WAVEFORM (CS1 Controlled) Data Retention Mode tSDR tRDR VDD VDR CS1 VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode VDD CS2 tSDR tRDR VDR CS2 0.2V GND 14 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 IS62WV12816ALL, IS62WV12816BLL ORDERING INFORMATION: IS62WV12816ALL (1.65V - 2.2V) Commercial Range: 0C to +70C Speed (ns) 70 Order Part No. IS62WV12816ALL-70T Package TSOP (Type II) Industrial Range: -40C to +85C Speed (ns) 70 70 70 70 Order Part No. IS62WV12816ALL-70TI IS62WV12816ALL-70BI IS62WV12816ALL-70BLI IS62WV12816ALL-70B2I Package TSOP (Type II) mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free mini BGA (6mm x 8mm), 2 CS Option ORDERING INFORMATION: IS62WV12816BLL (2.5V - 3.6V) Commercial Range: 0C to +70C Speed (ns) 45 45 55 Order Part No. IS62WV12816BLL-45B IS62WV12816BLL-45B2 IS62WV12816BLL-55T Package mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), 2 CS Option TSOP (Type II) Industrial Range: -40C to +85C Speed (ns) 45 45 55 Order Part No. IS62WV12816BLL-45TLI IS62WV12816BLL-45BLI IS62WV12816BLL-55TI Package TSOP (Type II), Lead-free mini BGA (6mm x 8mm), Lead-free TSOP (Type II) IS62WV12816BLL-55TLI IS62WV12816BLL-55BI IS62WV12816BLL-55BLI IS62WV12816BLL-55B2I IS62WV12816BLL-55B2LI TSOP (Type II), Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free mini BGA (6mm x 8mm), 2 CS Option mini BGA (6mm x 8mm), 2 CS Option, Lead-free 55 55 55 55 55 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 15 16 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS62WV12816ALL, IS62WV12816BLL Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. J 11/19/2013 Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : IS62WV12816ALL, IS62WV12816BLL 17