INTEGRATED CIRCUITS DATA SHEET TDA1545A Stereo continuous calibration DAC Preliminary specification Supersedes data of March 1993 File under Integrated Circuits, IC01 1997 Sep 04 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A FEATURES GENERAL DESCRIPTION * Space saving packages The TDA1545A is the first device of a new generation of the digital-to-analog converters which embodies the innovative technique of continuous calibration. The largest bit-currents are repeatedly generated by one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy insensitive to ageing, temperature and process variations. * Low power consumption * Low total harmonic distortion * Wide dynamic range (16-bit resolution) * Continuous calibration concept * Easy application: single 3 to 5.5 V rail power supply and output- and bias current are proportional to the supply voltage The device is fabricated in a 1.0 m CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the high coarse current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the continuous calibration digital-to-analog converter is eminently suitable for use in (portable) digital audio equipment. * Fast settling time permits 2x, 4x and 8x oversampling (serial input) or double speed operation at 4x oversampling * Internal bias current ensures maximum dynamic range * Wide operating temperature range of -40 to +85 C * Compatible with most of the Japanese input formats: time multiplexed, two's complement and TTL * No zero crossing distortion. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA1545A DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 TDA1545AT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 TDA1545ATT 1997 Sep 04 TSSOP14 2 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage 3 5 5.5 V IDD supply current VDD = 5 V; at code 0000H - 3.0 4.0 mA IFS full-scale output current VDD = 5 V 0.9 1.0 1.1 mA VDD = 3 V - 0.6 - mA THD total harmonic distortion at 0 dB - -88 -78 dB at 0 dB - 0.004 0.01 % at -60 dB - -33 -24 dB at -60 dB - 2.2 6 % at -60 dB; - -35 - dB - 1.7 - % - 1.4 - % A-weighting; at code 0000H 86 98 - dB R3 = R4 = 11 k; IFS = 2 mA - 101 - dB including noise A-weighting at -60 dB; A-weighting at -60 dB; A-weighting; R3 = R4 = 11 k; IFS = 2 mA S/N signal-to-noise ratio at bipolar zero tcs current settling time to 1 LSB - 0.2 - s BR input bit rate at data input - - 18.4 Mbits/s fBCK clock frequency at clock input - - 18.4 MHz TCFS full-scale temperature coefficient at analog outputs (IOL; IOR) - 400 - ppm Ptot total power dissipation VDD = 5 V - 15 20 mW VDD = 3 V - 6 - mW -40 - +85 C Tamb at code 0000H operating ambient temperature 1997 Sep 04 3 1997 Sep 04 4 3 (6) 2 (2) CONTROL AND TIMING RIGHT INPUT LATCH LEFT INPUT LATCH Fig.1 Block diagram. 32 (5-BIT) CALIBRATED CURRENT SOURCES AND 1 CALIBRATED SPARE SOURCE TDA1545A 11 k R REF REFERENCE SOURCE I BL IREF I BR IREF 11-BIT PASSIVE DIVIDER BL (7) 4 (9) 5 REF (13) 7 MCD287 - 1 I BR (14) 8 I (10) 6 ground 33 k (E24) R4 VREF IOR VREF IOL C2 C3 100 nF (E24) V REF VDD R3 22 k OP2 R2 3.9 k 1 nF OP1 R1 3.9 k C1 C4 1 F Vout right Vout left Stereo continuous calibration DAC The numbers given in parenthesis refer to the TDA1545ATT (SOT402-1) version. DATA WS BCK 1 (1) I REF 32 (5-BIT) CALIBRATED CURRENT SOURCES AND 1 CALIBRATED SPARE SOURCE RIGHT BIT SWITCHES LEFT BIT SWITCHES 11-BIT PASSIVE DIVIDER RIGHT OUTPUT LATCH k, full pagewidth LEFT OUTPUT LATCH I 1 nF Philips Semiconductors Preliminary specification TDA1545A Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A PINNING PIN SYMBOL DESCRIPTION SOT96-1; SOT97-1 SOT402-1 BCK 1 1 bit clock input WS 2 2 word select input DATA 3 6 data input GND 4 7 ground VDD 5 9 positive supply voltage IOL 6 10 left channel output IREF 7 13 reference current input IOR 8 14 right channel output n.c. - 3, 4, 5, 8, 11, 12 not connected handbook, halfpage handbook, halfpage BCK 1 8 IOR 7 I REF DATA 3 6 IOL GND 4 5 VDD WS 2 TDA1545A BCK 1 14 IOR WS 2 13 IREF n.c. 3 12 n.c. n.c. 4 TDA1545ATT 11 n.c. n.c. 5 10 IOL DATA 6 MCD288 - 1 9 VDD GND 7 8 n.c. MBK230 Fig.2 Pin configuration (SOT96-1; SOT97-1). 1997 Sep 04 Fig.3 Pin configuration (SOT402-1). 5 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A The TDA1545A accepts input serial data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The format of data input is shown in Figs 5 and 6. With a LOW level on the word select input (WS) input data is placed in the right input register and with a HIGH level on the WS input data is placed in the left input register. FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.4. The figure shows the calibration principle (Fig.4a) and operation principle (Fig.4b). During calibration of the MOS current source (Fig.4a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value IREF, the switch S1 is opened and S2 is switched to the other position (Fig.4b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the Iout terminal. The 32 current sources and the spare current source of the TDA1545A are continuously calibrated (see Fig.1). The data in the input registers is simultaneously latched in the output registers which control the bit switches. An internal bias current Ibias (see IBL and IBR in Fig.1) is added to the full-scale output current IFS in order to achieve the maximum dynamic range at the outputs of OP1 and OP2 (see Fig.1). The reference input current IREF controls with gain AFS the current IFS which is a sink current and with gain Abias the Ibias which is a source current (note 1). The current IREF is proportional to VDD so the IFS and Ibias will also be proportional to VDD (note 2) because AFS and Abias are constant. The spare current is included to allow for continuous convertor operation. The output of one calibrated source is connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed only by the LSB currents. The reference output voltage VREF in Fig.1 is 23VDD. In this way the maximum dynamic range is achieved over the entire power supply range. The tolerance of the reference input current in Fig.1 depends on the tolerance of the resistors R3, R4 and RREF (note 3). Notes to the functional description 1. IFS = AFS x IREF and Ibias = Abias x IREF 2. V DD1 I FS1 I bias1 ------------- = ---------- = -------------V DD2 I FS2 I bias2 3. V DD I REF = I REF - -------------------------------------------------------------------------------------------------------R3 + R3 + R4 + R4 + R REF + R REF 1997 Sep 04 6 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A out handbook, full pagewidth out I REF I REF I REF S2 S2 S1 S1 M1 M1 Vgs C gs Cgs Vgs MCD289 - 1 (a) (b) Fig.4 Calibration principle; (a) calibration, (b) operation. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP positive supply voltage - 6 V Txtal(max) maximum crystal temperature - +150 C Tstg storage temperature -55 +150 C Tamb operating ambient temperature -40 +85 C Ves electrostatic handling note 1 -2000 +2000 V note 2 -200 +200 V Notes 1. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 2. Machine model; C = 200 pF, L = 0.5 H, R = 10 , 3 zaps positive and negative. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1997 Sep 04 PARAMETER VALUE UNIT SOT97-1 100 K/W SOT96-1 160 K/W SOT402-1 155 K/W thermal resistance from junction to ambient in free air 7 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A CHARACTERISTICS VDD = 5 V; Tamb = 25 C; measured in the circuit of Fig.1; unless otherwise specified. SYMBOL PARAMETER VDD supply voltage IDD supply current RR ripple rejection CONDITIONS MIN. TYP. MAX. 5.5 UNIT 3.0 5.0 V note 1 - 3.0 4.0 mA note 2 - 30 - dB Digital inputs (WS; BCK; DATA) |IIL| input leakage current LOW VI = 0.8 V - - 10 A |IIH| input leakage current HIGH VI = 2.4 V - - 10 A fBCK bit clock input frequency - - 18.4 MHz BR bit rate data input - - 18.4 Mbits/s fWS word select input - - 384 kHz Timing (see Fig.5) tr rise time - - 12 ns tf fall time - - 12 ns tCY bit clock cycle time 54 - - ns tHB bit clock HIGH time 15 - - ns tLB bit clock LOW time 15 - - ns tSU;DAT data set-up time 12 - - ns tHD;DAT data hold time 2 - - ns tHD;WS word select hold time 2 - - ns tSU;WS word select set-up time 12 - - ns 7.4 11.0 14.6 k - - 16 bit Analog input (IREF) RREF reference resistor see Fig.1 Analog outputs (IOL and IOR) RES resolution VDCC DC output voltage compliance 2.0 - VDD - 1 V IFS full-scale current 0.9 1.0 1.1 mA TCFS full-scale temperature coefficient - 400 - ppm A Ibias bias current 643 714 785 AFS reference input current to full-scale output current gain - 13.2 - Abias reference input current to bias current gain - 9.42 - 1997 Sep 04 8 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC SYMBOL THD TDA1545A PARAMETER CONDITIONS MIN. TYP. MAX. total harmonic distortion including noise at 0 dB; - -88 note 3; see Fig.7 - 0.004 0.01 % including noise at -60 dB; - -33 -24 dB note 3; Fig.7 - 2.2 6 % including noise at -60 dB, - -35 - dB A-weighting - 1.8 - % R3 = R4 = 11 k see Fig.1; IFS = 2 mA - 1.4 - % including noise at 0 dB; note 4 - -84 -70 dB -78 UNIT dB - 0.006 0.03 % tcs settling time 1 LSB - 0.2 - s channel separation 86 95 - dB |dIO| unbalance between outputs |td| delay time between outputs S/N signal-to-noise ratio (A-weighting) note 3 - 0.2 0.3 dB - 0.2 - s at bipolar zero note 1 86 98 - dB note 5 - 101 - dB Notes 1. At code 0000H. 2. Vripple = 1% of supply voltage and fripple = 100 Hz. 3. Measured with 1 kHz sinewave generated at a sampling rate of 192 kHz. 4. Measured with 1 kHz sinewave over a 20 Hz to 20 kHz bandwidth generated at a sampling rate of 192 kHz. 5. R3 = R4 = 11 k; see Fig.1; IFS = 2 mA. 1997 Sep 04 9 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A TEST AND APPLICATION INFORMATION LEFT handbook, full pagewidth WS RIGHT tr 12 t f 12 t HB 15 t HD;WS 2 t LB 15 t SU;WS 12 BCK t CY 54 t SU;DAT 12 DATA LSB t HD;DAT 2 MSB MLB001 SAMPLE OUT Fig.5 Timing and input signals. 1997 Sep 04 10 Philips Semiconductors Preliminary specification TDA1545A Fig.6 Format of input signals. MSB RIGHT LSB MLB002 Stereo continuous calibration DAC 1997 Sep 04 11 WS BCK DATA SAMPLE OUT MSB LEFT LSB handbook, full pagewidth Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A APPLICATION INFORMATION MGA054 full pagewidth 10 20 THD (dB) (1) THD (%) 30 40 1 50 0.1 60 70 0.01 80 (2) 90 10 10 2 10 3 frequency (Hz) 10 4 (1) Measured including all distortion plus noise at a level of -60 dB. (2) Measured including all distortion plus noise at a level of -0 dB. The sample frequency 4FS: 176.4 kHz. The graphs are constructed from average values of a small amount of engineering samples therefore no guarantee for typical values is implied. Fig.7 Total harmonic distortion as a function of frequency (4FS). 1997 Sep 04 12 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A MGA056 MGA055 50 100 handbook, halfpage handbook, halfpage THD (dB) THD (dB) 80 60 60 70 (2) 80 40 (1) 90 20 0 100 100 80 60 40 20 1 0 2 3 4 5 6 VDD (V) signal level (dB) The sample frequency 4FS: 176.4 kHz. The graphs are constructed from average values of a small amount of engineering samples therefore no guarantee for typical values is implied. (1) Measured within the specified operating supply voltage range. (2) Measured outside the specified operating supply voltage range. The sample frequency 4FS: 176.4 kHz. The graphs are constructed from average values of a small amount of engineering samples therefore no guarantee for typical values is implied. Fig.8 Fig.9 Total harmonic distortion as a function of signal level (4FS). 1997 Sep 04 13 Total harmonic distortion as a function of supply voltage VDD (4FS). Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 1.15 inches 0.17 0.020 0.13 0.068 0.045 0.021 0.015 0.042 0.035 0.014 0.009 0.39 0.36 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT97-1 050G01 MO-001AN 1997 Sep 04 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 14 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index Lp L 4 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1997 Sep 04 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 15 o 8 0o Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 1997 Sep 04 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 16 o Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). If wave soldering is used - and cannot be avoided for TSSOP packages - the following conditions must be observed: DIP * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. REPAIRING SOLDERED JOINTS Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. SO and TSSOP REPAIRING SOLDERED JOINTS REFLOW SOLDERING Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Reflow soldering techniques are suitable for all SO and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. 1997 Sep 04 17 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Sep 04 18 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC TDA1545A NOTES 1997 Sep 04 19 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com (c) Philips Electronics N.V. 1997 SCA55 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547027/1200/03/pp20 Date of release: 1997 Sep 04 Document order number: 9397 750 02703