Preliminary Information AMD Athlon TM Processor Model 4 Data Sheet Publication # 23792 Rev: K Issue Date: November 2001 Preliminary Information (c) 2000, 2001 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. 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Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Contents Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AMD Athlon System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 6 3 Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 4.2 4.3 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12 Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 Contents AMD AthlonTM Processor Model 4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 24 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 24 VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 25 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 27 SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 28 AMD Athlon System Bus AC and DC Characteristics . . . . . 30 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 34 iii Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 8 Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 35 8.1 8.2 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AMD Athlon Processor Model 4 CPGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 10.2 10.3 iv Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 35 Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 37 Serial Initialization Packet (SIP) Protocol . . . . . . . . . . . . . . . 38 Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 38 The AMD Athlon Processor Model 4 and Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 9.2 9.3 10 23792K--November 2001 Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 43 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . 60 Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . . . . 60 CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . . . . 60 CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 61 CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 63 Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . 64 Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SYSCLK and SYSCLK# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Contents Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 SYSVREFMODE Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ZN, VCC_Z, ZP, and VSS_Z Pins . . . . . . . . . . . . . . . . . . . . . . . 66 11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Standard AMD Athlon Processor Model 4 Products . . . . . . . . . . . . . 71 Appendix A Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 73 Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Contents v Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet vi 23792K--November 2001 Contents Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 List of Figures Figure 1. Typical AMD AthlonTM Processor Model 4 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. AMD Athlon Processor Model 4 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Example of an AMD Athlon System Bus Disconnect Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Exiting Stop Grant State/Bus Reconnect Sequence . . . . . . . . . 14 Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 28 Figure 9. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 10. Signal Relationship Requirements During Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11. AMD Athlon Processor Model 4 CPGA Package. . . . . . . . . . . . 41 Figure 12. AMD Athlon Processor Model 4 Pin Diagram-- Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 13. AMD Athlon Processor Model 4 Pin Diagram-- Bottomside View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 14. PGA OPN Example for the AMD Athlon Processor Model 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 List of Figures vii Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet viii 23792K--November 2001 List of Figures Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 List of Tables List of Tables Table 1. Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2. Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 3. VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 4. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6. Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 8. VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . 27 Table 9. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 28 Table 10. SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 29 Table 11. AMD AthlonTM System Bus DC Characteristics . . . . . . . . . . . . 30 Table 12. AMD Athlon System Bus AC Characteristics . . . . . . . . . . . . . . 31 Table 13. General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 32 Table 14. APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 34 Table 15. CPGA Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 16. Dimensions for the AMD Athlon Processor Model 4 CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 17. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 18. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 19. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 62 Table 20. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 66 Table 21. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 22. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ix Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet x 23792K--November 2001 List of Tables Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Revision History Date Rev Description This revision of the AMD AthlonTM Processor Model 4 Data Sheet covers changes since September 2001 that include the following: November 2001 K In Chapter 5, revised Table 1, "Thermal Design Power," on page 19 In Chapter 7, revised Table 8, "VCC_CORE Voltage and Current," on page 27 In Chapter 11, revised Figure 14, "PGA OPN Example for the AMD AthlonTM Processor Model 4" on page 71 This revision of the 1400 MHz AMD AthlonTM Processor Model 4 covers changes since June 2001 that include the following: September 2001 J In Chapter 9, added Table 16, "Dimensions for the AMD AthlonTM Processor Model 4 CPGA Package," on page 40, and revised Figure 11, "AMD AthlonTM Processor Model 4 CPGA Package" on page 41. This revision is for the 1400 MHz AMD AthlonTM Processor Model 4 and covers changes since March 2001 that include the following: June 2001 I In Chapter 4, included APIC information in "Halt State" on page 10 and "Stop Grant States" on page 10 In Chapter 5, updated Table 1, "Thermal Design Power," on page 19 In Chapter 7, updated Table 8, "VCC_CORE Voltage and Current," on page 27 In Chapter 10, revised description of "FERR Pin" on page 61 and in Table 18 on page 52 This revision is for the 1333 MHz speed grade and covers changes since October 2000. March 2001 H In Chapter 1, revised description on the AMD AthlonTM system bus. In Chapter 4, revised Figure 3, "AMD AthlonTM Processor Model 4 Power Management States" on page 9 In Chapter 5, updated Table 1, "Thermal Design Power," on page 20 In Chapter 7, updated IoL specification to 12 mA in Table 14, "APIC Pins AC and DC Characteristics," on page 34. Updated Table 8, "VCC_CORE Voltage and Current," on page 27, revised Table 10, "SYSCLK and SYSCLK# AC Characteristics," on page 29, and revised Note 1 in Table 11, "AMD AthlonTM System Bus DC Characteristics," on page 30. In Chapter 8, revised description of "Serial Initialization Packet (SIP) Protocol" on page 38 In Chapter 10, revised Table 16, "Pin Name Abbreviations," on page 48, added description of "APIC Pins, PICCLK, PICD[1:0]#" on page 62, and revised description of "AMD Pin" on page 62 Added information about the 133 MHz front side bus (FSB) as follows: October 2000 G Revision History "AMD AthlonTM Processor Model 4 Microarchitecture Summary" on page 2 Table 1, "Thermal Design Power," on page 19 Table 8, "VCC_CORE Voltage and Current," on page 27 Table 10, "SYSCLK and SYSCLK# AC Characteristics," on page 29 Chapter 11, "Ordering Information" on page 71 xi Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet Date Rev October 2000 F 23792K--November 2001 Description Revised VID[4:0] information in Table 3 on page 24 and "VID[4:0] Pins" on page 65 Added Information about the 1.2 GHz AMD AthlonTM Processor Model 4 as follows: Chapter 1, "Overview" on page 3 Table 1, "Thermal Design Power," on page 21 Table 6, "Operating Ranges," on page 25 Table 8, "VCC_CORE Voltage and Current," on page 27 Revised OPN to include the new 1200 MHz speed grade in Chapter 10, "Ordering Information" on page 71 Revised Maximum and Typical Thermal Power numbers in Table 1, "Thermal Design Power," on page 19. Added note to Table 6 for new Die temperature. Revised table note 2 as "The Sleep Voltage is used for the S1 sleep state and as the Powerup voltage before PWROK and PWRGD are asserted." Table 6, "Operating Ranges," on page 25. Updated "Motherboard PGA Design Guide, order# 90009" with new document name of "Socket A Motherboard Design Guide, order# 24363" throughout book. Added SAI#[0] pin in location AJ29 to Figure 15, "AMD AthlonTM Processor Model 4 Pin Diagram--Topside View" on page 46. Added the AMD Pin (AH6) to Table 16, "Pin Name Abbreviations," on page 47, Table 17, "Socket A Pin Cross-Reference by Pin Location," on page 55Revised all no connect (NC) pins on the pin grid array (PGA) as follows: October 2000 E Figure 15, "AMD AthlonTM Processor Model 4 Pin Diagram--Topside View" on page 46. Table 15, "Pin Name Abbreviations," on page 47. Table 16, "Socket A Pin Cross-Reference by Pin Location," on page 55. Revised KLCKOUT/KCLKOUT# verbiage in Chapter , "K7CLKOUT and K7CLKOUT# Pins" on page 65. Added information about the 1.1-GHz AMD AthlonTM Processor Model 4 as follows: August 2000 D xii Chapter 1, "Overview" on page 3 Table 1, "Thermal Design Power," on page 21 Table 6, "Operating Ranges," on page 25 Table 8, "VCC_CORE Voltage and Current," on page 27 Revised and reorganized the AC and DC characteristics for SYSCLK and SYSCLK#. See Table 10, "SYSCLK and SYSCLK# AC Characteristics," on page 28, and Table 9, "SYSCLK and SYSCLK# DC Characteristics," on page 27. Revision History Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Date Rev Description Added Table 1, "Thermal Design Power," on page 21 to Chapter 5, "Thermal Design". Revised Chapter 6, "Electrical Data" on page 23 as follows: Added JTAG, APIC, Test, Miscellaneous rows to Table 2, "AMD AthlonTM Processor Model 4 Interface Signal Groupings," on page 23. Reorganized signals into their correct categories. Added "Conventions" on page 23. Revised information in Table 3, "VID[4:0] DC Characteristics," on page 24. Revised information in Table 4, "FID[3:0] DC Characteristics," on page 24. Added and revised information in Table 6, "SYSCLK/SYSCLK# AC and DC Characteristics," on page 23. Revised IVCCA information in Table 5, "VCCA AC and DC Characteristics," on page 25. Revised maximum values in Table 7, "Absolute Ratings," on page 26. Revised and reorganized information in Table 8, "VCC_CORE Voltage and Current," on page 27. For thermal information, see Table 1, "Thermal Design Power," on page 21. Changed VCC_CORE to 1.75V for all speed grades. Made the following changes in Chapter 7: August 2000 C Revision History Changed PLL power source signal name from VDDA to VCCA. Revised Figure 10, "Signal Relationship Requirements during Power-Up Sequence" on page 36. Revised the timing requirements in Step 4 on page 37. Revised and reorganized Table 11, "SYSCLK and SYSCLK# AC and DC Characteristics," on page 27. Added VCROSS symbol to this table. xiii Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet Date Rev 23792K--November 2001 Description Revised all figures and information in Chapter 8, "Mechanical Data" on page 41. Revised Chapter 9, "Pin Descriptions" on page 45 as follows: Changed FERR# to FERR in Figure 15, "AMD AthlonTM Processor Model 4 Pin Diagram-- Topside View" on page 46. See "FERR Pin" on page 63 for more information. Revised definition of the Reference column in Table 17, "Socket A Pin Cross-Reference by Pin Location," on page 55 in "Pin List" on page 53. In Table 17, "Socket A Pin Cross-Reference by Pin Location," on page 55, revised information for the following pin locations: N1 (PICCLK), N3 (PIC[0]#), N5 (PIC[1]#), AC7 (VCC_Z), AE33 (SADDIN[5]#), AE35 (SDATAOUTCLK[0]#), AE37 (SDATA[9]#), AG1 (FERR), AJ21 (CLKFWDRST), AJ23 (VCCA), AN13 (PLLMON1), AN15 (PLLBYPASSCLK), AN21 (K7CLKOUT#), AN29 (SADINN[12]#), AN31 (SADINN[14]#), AN33 (SDATAINVAL#), AN35 (SADINN[13]#), AN37 (SADINN[9]#) Revised information in "K7CLKOUT and K7CLKOUT# Pins" on page 65. Removed all specific resistor values in "Detailed Pin Descriptions" on page 62. For specific implementation information, see the Motherboard PGA Design Guide, order# 90009. Revised Chapter 10, "Ordering Information" on page 71. August 2000 C June 2000 B xiv Initial public release. Revision History Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 1 Overview The AMD AthlonTM processor model 4 powers the next generation in computing platforms, delivering compelling performance for cutting-edge applications and an unprecedented computing experience. The AMD Athlon processor model 4 with performance-enhancing cache memory is a member of the AMD Athlon family of processors that are designed to meet the computation-intensive requirements of cutting-edge software applications running on high-performance desktop systems, workstations, and servers. Delivered in a CPGA package and achieving frequencies of 1.4 GHz (1400 MHz), the AMD Athlon processor model 4 delivers the integer, floating-point and 3D multimedia performance needed for highly demanding applications running on x86 system platforms. For cutting-edge software applications, including digital content creation, digital photo editing, digital video, image compression, video encoding for streaming over the internet, soft DVD, commercial 3D modeling, workstation-class computer-aided design (CAD), commercial desktop publishing, and speech recognition, the A M D A t h l o n p ro c e s s o r m o d e l 4 d e l ive rs c o m p e l l i n g performance. It also offers the scalability and reliability that IT managers and business users require for enterprise computing. T h e A M D A t h l o n p r o c e s s o r m o d e l 4 f e a t u re s t h e seventh-generation microarchitecture with an integrated L2 cache, which supports the growing processor and system bandwidth requirements of emerging software, graphics, I/O, and memory technologies. The high-speed execution core of the AMD Athlon processor model 4 includes multiple x86 instruction decoders, a dual-ported 128-Kbyte split level-one (L1) cache, a 256-Kbyte on-chip L2 cache, three independent integer pipelines, three address calculation pipelines, and a s u p e rs c a l a r, f u l ly p i p e l i n e d , o u t -o f -o rd e r, t h re e -way floating-point engine. The floating-point engine is capable of delivering outstanding performance on numerically complex applications. Chapter 1 Overview 1 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 The AMD Athlon processor model 4 microarchitecture i n c o r p o ra t e s e n h a n c e d 3 D N ow ! TM t e c h n o l o gy, a high-performance cache architecture, and both a 200-MHz, 1.6-Gigabyte per second system bus, and a 266 MHz, 2.1Gigabyte per second system bus. The AMD Athlon system bus c o m b i n e s t h e l a t e s t t e ch n o l og i c a l a dva n c e s , s u ch a s point-to-point topology, source-synchronous packet-based transfers, and low-voltage signaling, to provide an extremely powerful, scalable bus for an x86 processor. The AMD Athlon processor model 4 is binary-compatible with existing x86 software and backwards compatible with applications optimized for MMXTM and 3DNow! instructions. Using a data format and single-instruction multiple-data (SIMD) operations based on the MMX instruction model, the AMD Athlon processor model 4 can produce as many as four, 32-bit, single-precision floating-point results per clock cycle. The enhanced 3DNow! technology implemented in the AMD A thl on process o r mod el 4 inc ludes new integer multimedia instructions and software-directed data movement instructions for optimizing such applications as digital content creation and streaming video for the internet, as well as new instructions for digital signal processing (DSP)/communications applications. 1.1 AMD AthlonTM Processor Model 4 Microarchitecture Summary The following features summarize the AMD Athlon processor model 4 microarchitecture: 2 An advanced, superpipelined, superscalar x86 processor microarchitecture designed for high clock frequencies Multiple x86 instruction decoders Three out-of-order, superscalar, fully pipelined floating-point execution units, which execute all x87 (floating-point), MMX and 3DNow! instructions Three out-of-order, superscalar, pipelined integer units Three out-of-order, superscalar, pipelined address calculation units A 72-entry instruction control unit Advanced dynamic branch prediction Enhanced 3DNow! technology with new instructions to enable improved integer math calculations for speech or video encoding and improved data movement for internet plug-ins and other streaming applications Overview Chapter 1 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 200-MHz and 266 MHz AMD Athlon system bus (scalable beyond 400 MHz) enabling leading-edge system bandwidth for data movement-intensive applications High-performance cache architecture featuring an integrated 128-Kbyte L1 cache and a 16-way, on-chip 256-Kbyte L2 cache for a total of 384-Kbytes of on-chip cache The AMD Athlon processor model 4 delivers excellent system performance in a cost-effective, industry-standard form factor. The AMD Athlon processor model 4 is compatible with motherboards based on AMD's Socket A. Figure 1 on page 3 shows a typical AMD Athlon processor model 4 system block diagram. AMD AthlonTM Processor AGP Bus AGP Memory Bus System Controller (Northbridge) DRAM PCI Bus Peripheral Bus Controller (Southbridge) LAN SCSI System Management ISA Bus USB Dual EIDE BIOS Figure 1. Typical AMD AthlonTM Processor Model 4 System Block Diagram Chapter 1 Overview 3 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 4 23792K--November 2001 Overview Chapter 1 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 2 2.1 Interface Signals Overview The AMD AthlonTM system bus architecture is designed to de liver unprecede nt ed da ta m oveme nt bandw idth fo r next-generation x86 platforms, as well as the high performance required by enterprise-class application software. The system bus architecture consists of three high-speed channels (a unidirectional processor request channel, a unidirectional probe channel, and a 72-bit bidirectional data channel), source-synchronous clocking, and a packet-based protocol. In addition, the system bus supports several control, clock, and legacy signals. The interface signals use an impedance controlled push-pull low-voltage swing signaling technology contained within the Socket A socket. For more information, see "AMD AthlonTM System Bus Signals" on page 6, Chapter 10, "Pin Descriptions" on page 43, and the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902. 2.2 Signaling Technology The AMD Athlon system bus uses a low-voltage, swing signaling technology, which has been enhanced to provide larger noise margins, reduced ringing, and variable voltage levels. The signals are push-pull and impedance compensated. The signal inputs use differential receivers, which require a reference voltage (VREF). The reference signal is used by the receivers to determine if a signal is asserted or deasserted by the source. Termination resistors are not needed because the driver is impedance matched to the motherboard and a high impedance reflection is used at the receiver to bring the signal past the input threshold. For more information about pins and signals, see Chapter 10, "Pin Descriptions" on page 43. Chapter 2 Interface Signals 5 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 2.3 23792K--November 2001 Push-Pull (PP) Drivers The Socket A AMD Athlon processor model 4 supports Push-Pull (PP) drivers. The system logic configures the AMD Athlon processor model 4 with the configuration parameter called SysPushPull (1=PP). The impedance of the PP drivers is set to match the impedance of the motherboard by two external resistors connected to the ZN and ZP pins. See "ZN, VCC_Z, ZP, and VSS_Z Pins" on page 66 for more information. 2.4 AMD AthlonTM System Bus Signals T h e A M D A t h l o n s y s t e m b u s i s a c l o ck -f o r wa rd e d , point-to-point interface with the following three point-to-point channels: A 13-bit unidirectional output address/command channel A 13-bit unidirectional input address/command channel A 72-bit bidirectional data channel For more information, see Chapter 7, "Electrical Data" on page 23 and the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902. 6 Interface Signals Chapter 2 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 3 Logic Symbol Diagram Figure 2 is the logic symbol diagram of the processor. This diagram shows the logical grouping of the input and output signals. Clock SYSCLK Data Probe/SysCMD Request Power Management and Initialization SYSCLK# SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SDATAINVAL# SDATAOUTVAL# SFILLVAL# SADDIN[14:2]# SADDINCLK# VID[4:0] COREFB COREFB# PWROK AMD AthlonTM Processor Model 4 SADDOUT[14:2]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET# Voltage Control FID[3:0] Frequency Control FERR IGNNE# INIT# INTR NMI A20M# SMI# Legacy PICCLK PICD[1:0]# APIC Figure 2. Logic Symbol Diagram Chapter 3 Logic Symbol Diagram 7 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 8 Logic Symbol Diagram 23792K--November 2001 Chapter 3 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 4 Power Management 4.1 Power Management States The AMD AthlonTM processor model 4 supports low-power Halt and Stop Grant states. These states are used by Advanced Configuration and Power Interface (ACPI) enabled operating systems for processor power management. Figure 3 shows the power management states of the AMD Athlon processor model 4. The figure includes the ACPI "Cx" naming convention for these states. Execute HLT C1 Halt 4 C0 Working SMI#, INTR, NMI, INIT#, RESET# de ass LK ert #a ed 3 sse rte d2 Incoming Probe Probe Serviced STPCLK# deasserted K# STPCLK# asserted STP C (Read PLVL2 register or throttling) Probe Serviced Incoming Probe Probe State1 STP CL ST P ST PC LK CL K# # de ass ass ert ed ert ed C3/S1 S1 Stop Grant Cache Not Snoopable Sleep C2 Stop Grant Cache Snoopable Legend: AthlonTMBus System Bus is connected the following The AMD System is connected during theduring following states: states: 1) The Probe state statestate to Stop Grant 2) During transitions from Halt the Halt to the Stopstate Grant state Stop Grant state tofrom the Halt 3) During transitions Stopstate Grant state to the Halt state 4) The C0 Working state Hardware transitions Software transitions Figure 3. AMD AthlonTM Processor Model 4 Power Management States Chapter 4 Power Management 9 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 The following paragraphs descr ibe each of the powe r management states. Note: In all power management states, the system must not disable the system clock (SYSCLK/SYSCLK#) to the processor. Working State The Working state refers to the state in which the processor is executing instructions. Halt State When the AMD Athlon processor model 4 executes the HLT instruction, the processor issues a Halt special cycle to the system bus. The Phase-Lock Loop (PLL) continues to run, enabling the processor to monitor bus activity and provide a quick resume from the Halt state. The processor enters a lower power state if the system logic (Northbridge) disconnects the AMD Athlon system bus in response to the Halt special cycle. The Halt state is exited when the processor detects the assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR or NMI pins, or via a local APIC interrupt message. Stop Grant States The AMD Athlon processor model 4 enters the Stop Grant state upon recognition of assertion of STPCLK# input. There are two mechanisms for asserting STPCLK#--hardware and software. The Southbridge can force STPCLK# assertion for throttling to protect the processor from exceeding its maximum case temperature. This task is accomplished by asserting the THERM# input to the Southbridge. Throttling asserts STPCLK# for a percentage of a predefined throttling period: STPCLK# is repetitively asserted and deasserted until the THERM# pin is deasserted. Software can force the processor into the Stop Grant state by accessing ACPI-defined registers typically located in the Southbridge. Software places the processor in C2 by reading the PLVL_2 register in the Southbridge. In C2, probes are allowed, as shown in Figure 3 on page 9. If an ACPI Thermal Zone is defined for the processor, the OS can initiate throttling with STPCLK# using the ACPI defined P_CNT register in the Southbridge. The processor enters the P ro b e s t a t e t o s e rv i c e c a ch e s n o o p s i n i t i a t e d by t h e Northbridge during Stop Grant for C2 or throttling. 10 Power Management Chapter 4 Preliminary Information 23792K--November 2001 AMD AthlonTM Processor Model 4 Data Sheet The Stop Grant state is also entered for the S1 system sleep state based on a write to the SLP_TYP field in the ACPI-defined power management 1 control register. During the S1 sleep state, system software ensures no bus master or probe activity occurs. After recognizing the assertion of STPCLK#, the AMD Athlon processor model 4 completes all pending and in-progress bus cycles and acknowledges the STPCLK# assertion by issuing a Stop Grant special bus cycle to the AMD Athlon system bus. After the Northbridge disconnects the AMD Athlon system bus in response to the Stop Grant special bus cycle, the processor enters a low-power state dictated by the CLK_Ctl register. During the Stop Grant states, the processor latches INIT#, INTR, NMI, and SMI#, or a local APIC interrupt message if they are asserted. The Stop Grant state is exited upon the deassertion of STPCLK# or the assertion of RESET#. When STPCLK# is deasserted, the processor initiates a connection of the AMD Athlon system bus if it is disconnected. After the processor enters the Working state, any pending interrupts are recognized and serviced and the processor resumes execution at the instruction boundary where STPCLK# was initially recognized. If RESET# is sampled asserted during the Stop Grant state, the processor returns to the Working state and the reset process begins. Probe State The Probe state is entered when the Northbridge initiates an AMD Athlon system bus connect as required to probe the processor. If the processor has been disconnected from the system bus, the Northbridge must initiate a system bus connection before it probes the processor to snoop the caches of the processor . The processor responds to a probe cycle in the Probe state in the same way it does during the Working state. When the probe has been serviced, the processor returns to the same state as when it entered the Probe state (Halt or Stop Grant state). Once in the Halt or Stop Grant state, a low-power s t a t e i s o n ly a ch i eve d i f t h e N o r t h b r i d g e i n i t i a t e s a disconnection from the system bus. Chapter 4 Power Management 11 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 4.2 23792K--November 2001 Connect and Disconnect Protocol Significant power savings of the AMD Athlon processor model 4 only occurs if the processor is disconnected from the system bus by the Northbridge while in the Halt or Stop Grant state. The Northbridge can optionally initiate a bus disconnect upon the receipt of a Halt or Stop Grant special cycle. The option of disconnecting is controlled by an enable bit in the Northbridge. If the Northbridge requires the processor to service a probe after the system bus has been disconnected, it must first initiate a system bus connect. Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop Grant special cycles, the AMD Athlon system bus connect protocol includes the CONNECT, PROCRDY, and CLKFWDRST signals and a Connect special cycle. AMD Athlon system bus disconnects are initiated by the Northbridge in response to the receipt of a Halt or Stop Grant special cycle. Reconnect is initiated by the processor in response to an interrupt for Halt, STPCLK# deassertion, or by the Northbridge to service a probe. The Northbridge contains BIOS programmable registers to enable the system bus disconnect in response to Halt and Stop Grant special cycles. When the Northbridge receives the Halt or Stop Grant special cycle from the processor and, if there are no outstanding probes or data movements, the Northbridge deasserts CONNECT a minimum of eight SYSCLK periods after the last command sent to the processor. The processor detects the deassertion of CONNECT on a rising edge of SYSCLK, and deasserts PROCRDY to the Northbridge. In return, the Northbridge asserts CLKFWDRST in anticipation of reestablishing a connection at some later point. Note: The Northbridge must disconnect the processor from the AMD Athlon system bus before issuing the Stop Grant special cycle to the PCI bus, or passing the Stop Grant special cycle to the Southbridge for systems that connect to the Southbridge with HyperTransportTM technology. This note applies to current chipset implementation: alternate chipset implementations that do not require this are possible. 12 Power Management Chapter 4 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Note: In response to Halt special cycles, the Northbridge passes the Halt special cycle to the PCI bus or Southbridge immediately. The processor can receive an interrupt after it sends a Halt special cycle, or STPCLK# deassertion after it sends a Stop Grant special cycle to the Northbridge but before the disconnect actually occurs. In this case, the processor sends the Connect special cycle to the Northbridge, rather than continuing with the disconnect sequence. In response to the Connect special cycle, the Northbridge cancels the disconnect request. The system is required to assert the CONNECT signal before returning the C-bit for the connect special cycle (assuming CONNECT has been deasserted). For more information, see the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902 for the definition of the C-bit and the Connect special cycle. Figure 4 shows the sequence of events from a Northbridge perspective, which leads to disconnecting the processor from the AMD Athlon system bus and placing the processor in the Stop Grant state. STPCLK# SystemBus StopGrant CONNECT PROCRDY CLKFWDRST StopGrant PCIBus Figure 4. Example of an AMD AthlonTM System Bus Disconnect Sequence The following sequence of events describes how the processor is placed in the Stop Grant state when bus disconnect is enabled within the Northbridge: 1. The Southbridge asserts STPCLK# to place the processor in the Stop Grant state. 2. When the processor recognizes STPCLK# asserted, the processor enters the Stop Grant State, then issues a Stop Grant special cycle on the AMD Athlon system bus. Chapter 4 Power Management 13 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 3. When the Stop Grant special cycle is received by the Northbridge and no probe traffic is pending, the Northbridge deasserts CONNECT, initiating a bus disconnect to the processor. 4. The processor responds to the Northbridge by deasserting PROCRDY, acknowledging the bus disconnect request. 5. The Northbridge asserts CLKFWDRST to complete the bus disconnect sequence. 6. After the processor is disconnected from the bus, the Northbridge passes the Stop Grant special cycle to the Southbridge. Figure 5 shows the signal sequence of events that take the processor out of the Stop Grant state, reconnect the processor to the AMD Athlon system bus, and put the processor into the Working state. STPCLK# PROCRDY CONNECT CLKFWDRST Figure 5. Exiting Stop Grant State/Bus Reconnect Sequence The following sequence of events removes the processor from the Stop Grant state and reconnects it to the AMD Athlon system bus: 1. The Southbridge deasserts STPCLK# in response to a resume event. 2. When the processor recognizes STPCLK# deassertion, it asserts PROCRDY, notifying the Northbridge to reconnect to the bus. 3. The Northbridge asserts CONNECT. 4. The Northbridge finally deasserts CLKFWDRST, which synchronizes the forwarded clocks between the processor and the Northbridge. 14 Power Management Chapter 4 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Connect State Diagram Figu re 6 be low and Figure 7 on pa ge 16 d escrib e t h e Northbridge and processor connect state diagrams, respectively. 4/A 1 2/A Disconnect Pending Disconnect Requested Connect 3 3/C 5/B 8 8 Reconnect Pending Disconnect Probe Pending 2 7/D,C 6/C 7/D Probe Pending 1 Condition Action 1 A disconnect is requested and probes are still pending 2 A disconnect is requested and no probes are pending A Deassert CONNECT eight SYSCLK periods after last SysDC sent 3 A CONNECT special cycle from the processor B Assert CLKFWDRST 4 No probes are pending C Assert CONNECT 5 PROCRDY is deasserted D Deassert CLKFWDRST 6 A probe needs service 7 PROCRDY is asserted Three SYSCLK periods after CLKFWDRST is deasserted. Although reconnected to the system interface, the 8 Northbridge must not issue any non-NOP SysDC commands for a minimum of four SYSCLK periods after deasserting CLKFWDRST. Figure 6. Northbridge Connect State Diagram Chapter 4 Power Management 15 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Connect 6/B 1 2/B Connect Pending 2 Disconnect Pending 5 Connect Pending 1 3/A 4/C Disconnect Condition 1 Action CONNECT is deasserted by the Northbridge (for a previously sent Halt or Stop Grant special cycle). Processor receives a wake-up event and must cancel 2 the disconnect request. 3 Deassert PROCRDY and slow down internal clocks. 4 A CLKFWDRST is asserted by the Northbridge. B Issue a CONNECT special cycle.* C Return internal clocks to full speed and assert PROCRDY * The Connect special cycle is only issued after a Processor wake-up event or CONNECT asserted by Northbridge. 5 CLKFWDRST is deasserted by the Northbridge. 6 Forward clocks start three SYSCLK periods after CLKFWDRST is deasserted. processor wake-up event (interrupt or STPCLK# deassertion) occurs. If the AMD Athlon system bus is connected so the Northbridge can probe the processor a Connect special cycle is not issued at that time (it is only issued after a subsequent processor wake-up event). Figure 7. Processor Connect State Diagram 16 Power Management Chapter 4 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 4.3 Clock Control The processor implements a Clock Control (CLK_Ctl) MSR (address C001_001Bh) that determines the internal clock divisor when the AMD Athlon system bus is disconnected. Refer to the AMD AthlonTM and AMD DuronTM Processors BIOS, Software, and Debug Developers Guide, order# 21656, for more details on the CLK_Ctl register. Chapter 4 Power Management 17 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 18 Power Management 23792K--November 2001 Chapter 4 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 5 Thermal Design For information about thermal design for the AMD AthlonTM processor model 4, including layout and airflow considerations, see the AMD Thermal, Mechanical, and Chassis Cooling Design G u i d e , o rd e r # 2 3 7 9 4 , a n d t h e c o o l i n g g u i d e l i n e s o n www.amd.com. Table 1 shows the thermal design power. The thermal design power represents the maximum sustained power dissipated while executing publicly available software or instruction sequences under normal system operation at nominal VCC_CORE. Thermal solutions must monitor the processor temperature to prevent the processor from exceeding its maximum die temperature. Table 1. Thermal Design Power Frequency (MHz) Maximum Thermal Typical Thermal Max Die Power Power Temperature 900 51.0 W 45.8 W 950 53.1 W 47.6 W 1000 55.1 W 49.5 W 1100 60.3 W 54.1 W 62.1 W 55.7 W 1200 65.7 W 58.9 W 1266 66.9 W 60.1 W 1300 68.3 W 61.3 W 1333 69.8 W 62.6 W 1400 72.1 W 64.7 W 1133 Chapter 5 Nominal Voltage 1.75 V Thermal Design 90C 95C 19 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 20 23792K--November 2001 Thermal Design Chapter 5 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 6 CPUID Support AMD AthlonTM processor model 4 version and feature set recognition can be performed through the use of the CPUID instruction that provides complete information about the processor--vendor, type, name, etc., and its capabilities. Software can make use of this information to accurately tune the system for maximum performance and benefit to users. For information on the use of the CPUID instruction, see the AMD Processor Recognition Application Note , order# 20734. Chapter 6 CPUID Support 21 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 22 23792K--November 2001 CPUID Support Chapter 6 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 7 Electrical Data 7.1 Conventions The conventions used in this chapter are as follows: 7.2 Current specified as being sourced by the processor is negative. Current specified as being sunk by the processor is positive. Interface Signal Groupings The electrical data in this chapter is presented separately for each signal group. Table 2 defines each group and the signals contained in each group. Table 2. Interface Signal Groupings Signal Group Signals Notes Power VID[4:0], VCC_CORE, VCCA, COREFB, COREFB# See "Voltage Identification (VID[4:0])" on page 24, "VID[4:0] Pins" on page 65, and "VCCA AC and DC Characteristics" on page 25. Frequency FID[3:0] See "Frequency Identification (FID[3:0])" on page 24 and "FID[3:0] Pins" on page 61. System Clocks SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK See "SYSCLK and SYSCLK# DC Characteristics" on page 28. SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, AMD AthlonTM SADDOUTCLK#, SFILLVAL#, SDATAINVAL#, System Bus SDATAOUTVAL#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, CONNECT See "AMD AthlonTM System Bus AC and DC Characteristics" on page 30. Southbridge RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, FLUSH# See "General AC and DC Characteristics" on page 32. JTAG TMS, TCK, TRST#, TDI, TDO See "General AC and DC Characteristics" on page 32. APIC PICD[1:0]#, PICCLK See "APIC Pins AC and DC Characteristics" on page 34 and "APIC Pins, PICCLK, PICD[1:0]#" on page 60 Chapter 7 Electrical Data 23 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet Table 2. Interface Signal Groupings (continued) Signal Group Test 23792K--November 2001 Signals Notes PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG Miscellaneous DBREQ#, DBRDY, PWROK, PLLBYPASS# 7.3 See "General AC and DC Characteristics" on page 32. See "General AC and DC Characteristics" on page 32. Voltage Identification (VID[4:0]) Table 3 shows the VID[4:0] DC characteristics. For more information, see "VID[4:0] Pins" on page 65. Table 3. VID[4:0] DC Characteristics Parameter Description IOL Output Current Low VOH Output High Voltage Min Max 16 mA 2.625 V * Note: * 7.4 The VID pins must not be pulled above this voltage by an external pullup resistor. Frequency Identification (FID[3:0]) Table 4 shows the FID[3:0] DC characteristics. For more information, see "FID[3:0] Pins" on page 61. Table 4. FID[3:0] DC Characteristics Parameter Description IOL Output Current Low VOH Output High Voltage Min Max 16 mA 2.625 V * Note: * 24 The FID pins must not be pulled above this voltage by an external pullup resistor. Electrical Data Chapter 7 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 7.5 VCCA AC and DC Characteristics Table 5 shows the AC and DC characteristics for VCCA. For more information, see "VCCA Pin" on page 65. Table 5. VCCA AC and DC Characteristics Symbol Parameter Min Nominal Max Units Notes 2.5 2.75 V 1 50 mA/GHz 2 VVCCA VCCA Pin Voltage 2.25 IVCCA VCCA Pin Current 0 Notes: 1. Minimum and maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted. 2. Measured at 2.5 V. 7.6 Decoupling See the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363, or contact your local AMD office for information about the decoupling required on the motherboard for use with the AMD AthlonTM processor model 4. 7.7 Operating Ranges The AMD Athlon processor model 4 is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in Table 6. Table 6. Operating Ranges Parameter Description VCC_CORE Processor core supply 900-1400 MHz VCC_CORESLEEP Processor core supply in Sleep state TDIE Temperature of processor die Min Nominal Max Notes 1.65 V 1.75 V 1.85 V 1 1.2 V 1.3 V 1.4 V 2 95C 3 Notes: 1. For normal operating conditions (nominal VCC_CORE is 1.75 V). 2. Sleep Voltage can be used for the S1 sleep state. For more information see the AMD AthlonTM and AMD DuronTM Processors BIOS, Software, and Debug Developers Guide, order# 21656. 3. Die temperature is 90C for frequencies of 1100 MHz and lower. Chapter 7 Electrical Data 25 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 7.8 23792K--November 2001 Absolute Ratings The AMD Athlon processor model 4 should not be subjected to conditions exceeding the absolute ratings listed in Table 7, as such conditions can adversely affect long-term reliability or result in functional damage. Table 7. Absolute Ratings Parameter Description Min Max VCC_CORE AMD AthlonTM Processor Model 4 core supply -0.5 V VCC_CORE Max + 0.5 V VCCA AMD Athlon Processor Model 4 PLL Supply -0.5 V VCCA Max + 0.5 V VPIN Voltage on any signal pin -0.5 V VCC_CORE Max + 0.5 V TSTORAGE Storage temperature of processor -40C 100C 26 Electrical Data Chapter 7 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 7.9 VCC_CORE Voltage and Current Table 8 shows the power and current of the processor during normal and reduced power states. Table 8. VCC_CORE Voltage and Current Frequency (MHz) Nominal Voltage Maximum Voltage Stop Grant (Maximum)1 Maximum ICC (Power Supply Current)2 900 29.2 A 950 30.3 A 1000 31.5 A 1100 34.5 A 1133 1.75 V 1.85 V 5W Die Temperature 90C 35.5 A 1200 37.5 A 1266 38.3 A 1300 39.0 A 1333 39.9 A 1400 41.2 A 95C Notes: 1. Measured at 1.3 V for Sleep state operating conditions. The BIOS must program the CLK_Ctrl MSR to fff0_d22fh for the AMD AthlonTM Processor Model 4. 2. Measured at Nominal voltage of 1.75 V. Chapter 7 Electrical Data 27 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 7.10 23792K--November 2001 SYSCLK and SYSCLK# AC and DC Characteristics Table 9 shows the DC characteristics of the SYSCLK and SYSCLK# differential clocks. The SYSCLK signal represents CLKIN and RSTCLK tied together while the SYSCLK# signal represents CLKIN# and RSTCLK# tied together. Figure 8 shows the waveforms of the SYSCLK and SYSCLK# signals. Table 9. SYSCLK and SYSCLK# DC Characteristics Symbol Description Min Max Units VThreshold-DC Crossing before transition is detected (DC) 400 mV VThreshold-AC Crossing before transition is detected (AC) 450 mV --1 mA ILEAK_P Leakage current through P-channel pullup to VCC_CORE ILEAK_N Leakage current through N-channel pulldown to VSS (Ground) VCROSS Differential signal crossover CPIN Capacitance 4 VCROSS VThreshold-DC = 400mV 1 mA VCC_CORE/2 +/- 100 mV 12 pF VThreshold-AC = 450mV Figure 8. SYSCLK and SYSCLK# Differential Clock Signals 28 Electrical Data Chapter 7 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 10 shows the SYSCLK/SYSCLK# differential clock AC characteristics of the AMD Athlon processor model 4. Figure 9 shows a sample waveform. Table 10. SYSCLK and SYSCLK# AC Characteristics Symbol Parameter Description Min @ Max @ Units Clock Frequency 100 133 100 133 Duty Cycle 30% 30% 70% 70% MHz t1 Period 10 7.5 ns t2 High Time 1.8 1.05 ns t3 Low Time 1.8 1.05 ns t4 Fall Time 2 2 ns t5 Rise Time 2 2 ns 300 300 ps Period Stability Notes 1, 2 Notes: 1. Circuitry driving the SYSCLK and SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track the jitter. The -20 dB attenuation point, as measured into a 10 or 20-pF load must be less than 500 kHz. 2. Circuitry driving the SYSCLK and SYSCLK# inputs can purposely alter the SYSCLK and SYSCLK# period (spread spectrum clock generators). In no cases can the SYSCLK and SYSCLK# period violate the minimum specification above. SYSCLK and SYSCLK# inputs can vary from 100% of the specified period to 99% of the specified period at a maximum rate of 100 kHz. t2 VThreshold-AC VCROSS t3 t4 t5 t1 Figure 9. SYSCLK Waveform Chapter 7 Electrical Data 29 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 7.11 23792K--November 2001 AMD AthlonTM System Bus AC and DC Characteristics Table 11 shows the DC characteristics of the AMD Athlon system bus used by the AMD Athlon processor model 4. Table 11. AMD AthlonTM System Bus DC Characteristics Symbol VREF Parameter Condition Min Max (0.5*VCC_CORE) (0.5*VCC_CORE) -50 +50 DC Input Reference Voltage IVREF_LEAK_P VREF Tristate Leakage Pullup VIN = VREF Nominal IVREF_LEAK_N VREF Tristate Leakage Pulldown VIN = VREF Nominal Units Notes mV 1 A -100 +100 A VIH Input High Voltage VREF + 200 VCC_CORE + 500 mV VIL Input Low Voltage -500 VREF - 200 mV VOH Output High Voltage IOUT = -200A 0.85*VCC_CORE VCC_CORE+500 mV 2 VOL Output Low Voltage IOUT = 1 mA -500 400 mV 2 ILEAK_P Tristate Leakage Pullup VIN = VSS (Ground) -1 ILEAK_N Tristate Leakage Pulldown CIN Input Pin Capacitance VIN = VCC_CORE Nominal 4 mA +1 mA 12 pF 3 Notes: 1. VREF is nominally set to 50% of VCC_CORE with actual values that are specific to motherboard design implementation. VREF must be created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed above. 2. Specified at TDIE given in Table 6, and VCC_CORE in Table 8. 3. The following processor inputs have twice the listed capacitance because they connect to two input pads--SYSCLK, and SYSCLK#. SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#. For more information, see Table 17 on page 46 . 30 Electrical Data Chapter 7 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 The AC characteristics of the AMD Athlon system bus are shown in Table 12. The parameters are grouped based on the source or destination of the signals involved. Table 12. AMD AthlonTM System Bus AC Characteristics Group All Signals Forward Clocks Sync Symbol Parameter Min Max Units Notes TRISE Output Rise Slew Rate 1 3 V/ns 1 TFALL Output Fall Slew Rate 1 3 V/ns 1 TSKEWSAMEEDGE Output skew with respect to the same clock edge 385 ps 2 TSKEWDIFFEDGE Output skew with respect to a different clock edge 770 ps 2 TSU Input Data Setup Time 300 ps 3 THD Input Data Hold Time 300 ps 3 CIN Capacitance on input Clocks 4 12 pF COUT Capacitance on output Clocks 4 12 pF T VAL RSTCLK to Output Valid 250 2000 ps 4, 5 TSU Setup to RSTCLK 500 ps 4, 6 THD Hold from RSTCLK 1000 ps 4, 6 Notes: 1. Rise and fall time ranges are guidelines over which the I/O has been characterized. 2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to the same clock edge. TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock. 4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST. 5. T VAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF. 6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of RSTCLK. Chapter 7 Electrical Data 31 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 7.12 23792K--November 2001 General AC and DC Characteristics Table 13 shows the AMD Athlon processor model 4 AC and DC ch a ra c t e r i s t i c s o f t h e S o u t h b r i d g e , J TAG , t e s t , a n d miscellaneous pins. Table 13. General AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes VIH Input High Voltage (VCC_CORE/2) + 200mV VCC_CORE + 300mV V 1,2 VIL Input Low Voltage -300 350 mV 1,2 VOH Output High Voltage VCC_CORE - 400 VCC_CORE + 300 mV VOL Output Low Voltage -300 400 mV ILEAK_P Tristate Leakage Pullup ILEAK_N Tristate Leakage Pulldown IOH Output High Current IOL Output Low Current TSU VIN = VSS (Ground) -1 VIN = VCC_CORE Nominal mA 600 A -16 mA 3 16 mA 3 Sync Input Setup Time 2.0 ns 4, 5 THD Sync Input Hold Time 0.0 ps 4, 5 TDELAY Output Delay with respect to RSTCLK 0.0 ns 5 TBIT Input Time to Acquire 20.0 ns 7,8 TRPT Input Time to Reacquire 40.0 ns 9-13 6.1 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 32 Characterized across DC supply voltage range. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max. IOL and IOH are measured at VOL max and VOH min, respectively. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins. These are aggregate numbers. Edge rates indicate the range over which inputs were characterized. In asynchronous operation, the signal must persist for this time to ensure capture. This value assumes RSTCLK period is 10ns ==> TBIT = 2*fRST. The approximate value for standard case in normal mode operation. This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency. Reassertions of the signal within this time are not guaranteed to be seen by the core. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other configurations. Electrical Data Chapter 7 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 13. General AC and DC Characteristics (continued) Symbol Parameter Description Condition Min Max Units Notes TRISE Signal Rise Time 1.0 3.0 V/ns 6 TFALL Signal Fall Time 1.0 3.0 V/ns 6 CPIN Pin Capacitance 4 12 pF Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Characterized across DC supply voltage range. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max. IOL and IOH are measured at VOL max and VOH min, respectively. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins. These are aggregate numbers. Edge rates indicate the range over which inputs were characterized. In asynchronous operation, the signal must persist for this time to ensure capture. This value assumes RSTCLK period is 10ns ==> TBIT = 2*fRST. The approximate value for standard case in normal mode operation. This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency. Reassertions of the signal within this time are not guaranteed to be seen by the core. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other configurations. Chapter 7 Electrical Data 33 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 7.13 23792K--November 2001 APIC Pins AC and DC Characteristics Table 14 shows the AMD Athlon processor model 4 AC and DC characteristics of the APIC pins. Table 14. APIC Pins AC and DC Characteristics Symbol Parameter Description Condition Min Max Units Notes VIH Input High Voltage 1.7 2.625 V 1, 3 VIL Input Low Voltage -300 700 mV 1, 2 VOH Output High Voltage 2.625 V 3 VOL Output Low Voltage 400 mV ILEAK_P Tristate Leakage Pullup ILEAK_N Tristate Leakage Pulldown IOL Output Low Current TRISE Signal Rise Time 1.0 3.0 V/ns 4 TFALL Signal Fall Time 1.0 3.0 V/ns 4 CPIN Pin Capacitance 4 12 pF -300 VIN = VSS (Ground) -1 VIN = 2.5 V VOL Max mA 1 12 mA mA Notes: 1. 2. 3. 4. 34 Characterized across DC supply voltage range. Values specified at nominal VDD (1.5 V). Scale parameters with VDD. 2.625 V = 2.5 V + 5% maximum Edge rates indicate the range over which inputs were characterized. Electrical Data Chapter 7 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 8 Signal and Power-Up Requirements This chapter describes the AMD AthlonTM processor model 4 power-up requirements during system power-up and warm resets. 8.1 Power-Up Requirements Signal Sequence and Timing Description Figure 10 shows the relationship between key signals in the system during a power-up sequence. This figure details the requirements of the processor. 3.3V Supply VCCA (2.5V) (for PLL) VCC_CORE (Processor Core) 2 RESET# 6 1 4 NB_RESET# PWROK 5 3 System Clock Figure 10. Signal Relationship Requirements During Power-Up Sequence Notes: 1. Figure 10 represents several signals generically by using names not necessarily consistent with any pin lists or schematics. 2. Requirements 1-6 in Figure 10 are described in "Power-Up Timing Requirements" on page 36. Chapter 8 Signal and Power-Up Requirements 35 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Power-Up Timing Requirements. T h e f o l l o w i n g s i g n a l t i m i n g requirements correspond to numbers 1-6 in Figure 10 on page 35. 1. RESET# must be asserted before PWROK is asserted. The AMD Athlon processor model 4 does not set the correct clock multiplier if PWROK is asserted prior to a RESET# assertion. It is recommended that RESET# be asserted at least 10 ns prior to the assertion of PWROK. In practice, Southbridges assert RESET# milliseconds before PWROK is deasserted. 2. All motherboard voltage planes must specification before PWROK is asserted. be within PWROK is an output of the voltage regulation circuit on the motherboard. PWROK indicates that VCC_CORE and all other voltage planes in the system are within specification. The motherboard is required to delay PWROK assertion for a minimum of three milliseconds from the 3.3 V supply being within specification. This ensures that the system clock (SYSCLK/SYSCLK#) is operating within specification when PWROK is asserted. The processor core voltage, VCC_CORE, must be within specification as dictated by the VID[4:0] pins driven by the processor before PWROK is asserted. Before PWROK assertion, the AMD Athlon processor is clocked by a ring oscillator. The AMD Athlon processor PLL is powered by VCCA. The processor PLL does not lock if VCCA is not high enough for the processor logic to switch for some period before PWROK is asserted. VCCA must be within spec at least five microseconds before PWROK is asserted. In practice VCCA, VCC_CORE, and all other voltage planes must be within specification be for several milliseconds before PWROK is asserted. After PWROK is asserted, the processor PLL locks to its operational frequency. 36 Signal and Power-Up Requirements Chapter 8 Preliminary Information 23792K--November 2001 AMD AthlonTM Processor Model 4 Data Sheet 3. The system clock (SYSCLK/SYSCLK#) must be running within specification before PWROK is asserted. When PWROK is asserted, the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the PLL. The reference system clock should be valid at this time. The system clocks are guaranteed to be running after 3.3 V has been within specification for three milliseconds. 4. PWROK assertion to deassertion of RESET#. The duration of RESET# assertion during cold boots is intended to satisfy the time it takes for the PLL to lock with a less than 1-ns phase error. The processor PLL begins to run after PWROK is asserted and the internal clock grid is switched from the ring oscillator to the PLL. The PLL lock time may take from hundreds of nanoseconds to tens of microseconds. It is recommended that the minimum time between PWROK assertion to the deassertion of RESET# be at least 1.0 ms. AMD Southbridges enforce a delay of 1.5 to 2.0 milliseconds between PWRGD (Southbridge version of PWROK) assertion and NB_RESET# deassertion. 5. PWROK must be monotonic. The processor should not switch between the ring oscillator and the PLL after the initial assertion of PWROK. 6. NB_RESET# must be asserted (causing CONNECT to also assert) before RESET# is deasserted. In practice all Southbridges enforce this requirement. If NB_RESET# does not assert until after RESET# has deasserted, the processor misinterprets the CONNECT assertion (due to NB_RESET# being asserted) as the beginning of the SIP transfer (See "Serial Initialization Packet (SIP) Protocol" on page 38). There must be sufficient overlap in the resets to ensure that CONNECT is sampled asserted by the processor before RESET# is deasserted. Clock Multiplier Selection (FID[3:0]) When RESET# is deasserted, the chipset samples the FID[3:0] frequency ID from the processor in a chipset-specific manner. For more information, see "FID[3:0] Pins" on page 61. The chipset uses this FID information and other information sampled at the deassertion of RESET# to determine the correct Serial Initialization Packet (SIP) to send to the processor for configuration of the AMD system bus for the clock multiplier processor frequency indicated by the FID[3:0] code. The SIP is Chapter 8 Signal and Power-Up Requirements 37 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 sent to the processor using the SIP protocol. This protocol uses the PROCRDY, CONNECT, and CLKFWDRST signals, which are synchronous to SYSCLK. Serial Initialization Packet (SIP) Protocol 8.2 Processor Warm Reset Requirements The AMD AthlonTM Processor Model 4 and Northbridge Reset Pins 38 Refer to AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902 for details of the SIP protocol. RESET cannot be asserted to the processor without also being asserted to the Northbridge. RESET# to the Northbridge is the same in as PCI RESET#. The minimum assertion for PCI RESET# is one millisecond. AMD Southbridges enforce a minimum assertion of RESET# to the processor, Northbridge, or PCI of 1.5 to 2.0 milliseconds. Signal and Power-Up Requirements Chapter 8 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 9 9.1 Mechanical Data Introduction The AMD AthlonTM processor model 4 connects to the motherboard through a PGA socket named Socket A and utilizes the Ceramic Pin Grid Array (CPGA) package type described in "AMD AthlonTM Processor Model 4 CPGA Package Dimensions" on page 40. For more information, see the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. 9.2 Die Loading The processor die on the CPGA package is exposed at the top of the package. This is done to facilitate heat transfer from the die to an approved heat sink. It is critical that the mechanical loading of the heat sink does not exceed the limits shown in Table 15. Tool-assisted zero-insertion force sockets should be designed such that no load is placed on the ceramic substrate of the package.Any heat sink design should avoid loads on corners and edges of die. The CPGA package has compliant pads that serve to bring surfaces in planar contact. Table 15. CPGA Mechanical Loading Location Dynamic (MAX) Static (MAX) Units Note Die Surface 100 30 lbf 2 Die Edge 10 10 lbf 3 Notes: 1. Load specified for coplanar contact to die surface. 2. Load defined for a surface at no more than a two degree angle of inclination to die surface. Chapter 9 Mechanical Data 39 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 9.3 23792K--November 2001 AMD AthlonTM Processor Model 4 CPGA Package Dimensions Figure 11 on page 41 shows a diagram and notes for the AMD Athlon processor model 4 CPGA package. Table 16 provides the dimensions in millimeters assigned to the letters and symbols shown in the Figure 11 diagram. Table 16. Dimensions for the AMD AthlonTM Processor Model 4 CPGA Package Letter or Symbol D/E Minimum Maximum Dimension* Dimension* 49.27 49.78 Letter or Symbol Minimum Maximum Dimension* Dimension* E11 5.79 REF D1/E1 45.72 BSC G/H D2 9.10 REF A - 4.50 2.24 REF D3 3.30 3.60 A1 1.27 1.53 D4 10.64 11.19 A2 0.80 0.88 D5 10.64 11.19 A3 0.116 - D6 5.78 6.33 A4 - 1.90 D7 10.52 11.07 P - 6.60 D8 3.05 3.35 b 0.43 0.50 E3 2.35 2.65 b1 - 1.63 E4 7.25 7.80 S 1.435 2.375 E5 7.25 7.80 L 3.05 3.31 E6 14.15 14.42 M 37 E7 10.41 10.96 N 453 E8 14.84 15.39 e 1.27 BSC E9 1.66 1.96 e1 2.54 BSC E10 7.31 REF Note: * Dimensions are given in millimeters. 40 Mechanical Data Chapter 9 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Figure 11. AMD AthlonTM Processor Model 4 CPGA Package Chapter 9 Mechanical Data 41 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 42 23792K--November 2001 Mechanical Data Chapter 9 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 10 10.1 Pin Descriptions Pin Diagram and Pin Name Abbreviations Figure 12 on page 44 shows the staggered Ceramic Pin Grid Array (CPGA) for the AMD AthlonTM processor model 4. Because some of the pin names are too long to fit in the grid, they are abbreviated. Figure 13 on page 45 show s the bottomside view of the array. Table 17 on page 46 lists all the pins in alphabetical order by pin name, along with the abbreviation where necessary. Chapter 10 Pin Descriptions 43 44 Pin Descriptions Z X V T R P AK AN AM AL 1 INTR IGNNE# FERR A20M# STPC# DBRDY FID[2] FID[0] TDI SCNCK1 TCK PICCLK VID[0] SAO#0 SAO#10 SAO#11 SAO#7 1 2 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS 2 3 3 NMI FLUSH# INIT# RESET# PWROK PLTST# DBREQ# FID[3] FID[1] TRST# SCNINV TMS PICD#0 VID[1] SAO#1 SAO#14 SAOC# SAO#9 SAO#12 4 VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC 4 5 5 SMI# VCC VCC NC ZP ZN SVRFM NC VREF_S TDO SCNCK2 SCNSN PICD#1 VID[2] NC SAO#13 SAO#4 SAO#8 SAO#5 6 VSS CPR# AMD NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC VSS VSS VSS 6 7 7 NC NC NC KEY VSS_Z VCC_Z KEY NC NC NC KEY VID[3] VID[4] SAO#6 SAO#2 SAO#3 8 NC NC NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC NC VCC VCC 8 9 10 VCC VCC VCC NC NC VSS VSS VSS 10 11 11 NC NC NC COREFB NC SD#50 SDOC#3 SD#61 12 VSS VSS VSS VSS VCC VCC VCC VCC 12 13 13 PLMN1 PLMN2 ANLOG COREFB# NC SD#49 NC SD#53 14 VCC VCC VCC VCC VSS VSS VSS VSS 14 15 VCC VCC VCC VCC 16 17 KEY SD#48 SD#60 SD#62 VSS VSS VSS VSS 18 NC SD#58 SD#59 NC 19 VCC VCC VCC VCC 20 21 NC SD#36 SD#56 SD#57 VSS VSS VSS VSS 22 23 SD#46 SD#37 SD#39 15 PLBYC PLBYC# NC KEY 16 VSS VSS VSS VSS 17 CLKIN CLKIN# NC 18 VCC VCC VCC VCC 19 RCLK RCLK# NC NC 20 VSS VSS VSS VSS 21 K7CO# K7CO CLKFR NC 22 VCC VCC VCC VCC 23 PRCRDY CNNCT VCCA NC AMD AthlonTM Processor Model 4 Topside View SDIC#3 SD#51 SD#63 24 VSS VSS VSS VSS VCC VCC VCC VCC 24 25 25 NC NC PLBYP# NC KEY NC SD#47 SD#35 26 VCC VCC VCC VCC VSS VSS VSS VSS 26 27 27 NC NC NC NC SDIC#2 SD#38 SD#34 28 VSS VSS VSS NC NC VCC VCC VCC 28 29 29 SAI#12 SAI#1 SAI#0 KEY NC SD#33 SD#45 SD#44 Figure 12. AMD AthlonTM Processor Model 4 Pin Diagram--Topside View 9 NC NC NC KEY SD#52 SD#54 SD#55 30 VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS VSS 30 31 SAI#14 SDOV# SFILLV# NC NC NC NC NC NC NC NC NC NC NC NC NC SD#32 SD#43 NC 31 32 VSS VSS VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC VCC VCC VCC 32 33 33 SDINV# SAI#8 SAIC# SAI#2 SAI#5 SD#10 SD#8 NC SDIC#0 SD#5 SD#7 SD#24 SD#25 SD#26 SD#19 SD#20 NC SD#42 SDOC#2 34 VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS 34 35 35 SAI#13 SAI#4 SAI#6 SAI#11 SDOC#0 SD#14 SD#0 SD#3 SD#2 SD#4 SD#15 SD#17 SD#27 NC SDIC#1 SD#23 SD#31 SD#41 SD#40 36 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC 36 37 37 SAI#9 SAI#10 SAI#3 SAI#7 SD#9 SD#11 SD#13 SD#12 SD#1 NC SD#6 SD#16 SD#18 SD#28 SD#29 SD#21 SD#22 SDOC#1 SD#30 Z X V T R P AN AM AL AK AJ AH AG AF AE AD AC AB AA Y K H F D B M W U S Q N L J G E C A AMD AthlonTM Processor Model 4 Data Sheet AJ AH AG AF AE AD AC AB AA Y K H F D B M W U S Q N L J G E C A Preliminary Information 23792K--November 2001 Chapter 10 Chapter 10 8 6 4 2 10 Pin Descriptions 37 36 35 34 C C A SD#41 SD#42 SD#43 SD#45 SD#38 SD#47 SD#37 SD#56 SD#59 SD#60 SD#51 NC SDOC#3 SD#54 SAO#2 SAO#8 SAO#9 SAO#7 SDOC#1 B VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS B SD#30 SD#40 SDOC#2 NC SD#44 SD#34 SD#35 SD#39 SD#57 NC SD#62 SD#63 SD#53 SD#61 SD#55 SAO#3 SAO#5 SAO#12 A D VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC D E E SD#22 SD#31 NC SD#32 SD#33 SDIC#2 NC SD#46 SD#36 SD#58 SD#48 SDIC#3 SD#49 SD#50 SD#52 SAO#6 SAO#4 SAOC# SAO#11 F VCC VCC VCC NC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS NC VSS VSS VSS F G G SD#21 SD#23 SD#20 NC NC NC KEY NC NC KEY NC NC KEY SAO#13 SAO#14 SAO#10 J J SD#29 SDIC#1 SD#19 NC VID[4] NC SAO#1 SAO#0 K VCC VCC VCC NC NC VSS VSS VSS K L L SD#28 NC SD#26 NC VID[3] VID[2] VID[1] VID[0] M VSS VSS VSS VSS VCC VCC VCC VCC M N N SD#18 SD#27 SD#25 NC KEY PICD#1 PICD#0 PICCLK P VCC VCC VCC VCC VSS VSS VSS VSS P Q VCC VCC VCC VCC R S NC SCNCK2 SCNINV SCNCK1 VSS VSS VSS VSS T U NC TDO TRST# TDI VCC VCC VCC VCC V W NC VREF_S FID[1] FID[0] VSS VSS VSS VSS X Y KEY NC FID[3] FID[2] Q SD#16 SD#17 SD#24 NC R VSS VSS VSS VSS S SD#6 SD#15 SD#7 NC T VCC VCC VCC VCC U NC SD#4 SD#5 NC V VSS VSS VSS VSS W SD#1 SD#2 SDIC#0 NC X VCC VCC VCC VCC Y SD#12 SD#3 NC NC AMD AthlonTM Processor Model 4 Bottomside View SCNSN TMS TCK Z VSS VSS VSS VSS VCC VCC VCC VCC Z AA AA SD#13 SD#0 SD#8 NC SVRFM DBREQ# DBRDY AB VCC VCC VCC VCC VSS VSS VSS VSS AB AC AC SD#11 SD#14 SD#10 NC VCC_Z ZN PLTST# STPC# AD VSS VSS VSS NC NC VCC VCC VCC AD AE AE SD#9 SDOC#0 SAI#5 NC VSS_Z ZP PWROK A20M# AF VCC VCC NC NC NC VCC VSS VCC VSS VCC VSS VCC VSS NC NC NC VSS VSS AF Figure 13. AMD AthlonTM Processor Model 4 Pin Diagram--Bottomside View H VSS VSS NC NC NC VSS VCC VSS VCC VSS VCC VSS VCC NC NC NC VCC VCC H AG AG SAI#7 SAI#11 SAI#2 NC KEY NC NC NC NC KEY COREFB# COREFB KEY NC RESET# FERR AH VSS VSS VSS NC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC AMD VCC VCC AH AJ AJ SAI#3 SAI#6 SAIC# SFILLV# SAI#0 NC PLBYP# VCCA CLKFR NC NC NC ANLOG NC NC NC VCC INIT# IGNNE# AK VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC CPR# VSS VSS AK AL AL SAI#10 SAI#4 SAI#8 SDOV# SAI#1 NC NC CNNCT K7CO RCLK# CLKIN# PLBYC# PLMN2 NC NC NC VCC FLUSH# INTR AM VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC NC VSS VSS VCC AM AN SAI#9 SAI#13 SDINV# SAI#14 SAI#12 NC NC PRCRDY K7CO# RCLK CLKIN PLBYC PLMN1 NC NC NC SMI# NMI AN 8 6 4 2 10 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 7 5 3 1 AMD AthlonTM Processor Model 4 Data Sheet 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 7 5 3 1 Preliminary Information 23792K--November 2001 45 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 17. Pin Name Abbreviations (continued) Table 17. Pin Name Abbreviations Abbreviation ANLOG CLKFR CNNCT CPR# K7CO K7CO# 46 Full Name A20M# AMD ANALOG CLKFWDRESET CLKIN CLKIN# CONNECT COREFB COREFB# CPU_PRESENCE# DBRDY DBREQ# FERR FID[0] FID[1] FID[2] FID[3] FLUSH# IGNNE# INIT# INTR K7CLKOUT K7CLKOUT# KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY Pin AE1 AH6 AJ13 AJ21 AN17 AL17 AL23 AG11 AG13 AK6 AA1 AA3 AG1 W1 W3 Y1 Y3 AL3 AJ1 AJ3 AL1 AL21 AN21 G7 G9 G15 G17 G23 G25 N7 Q7 Y7 AA7 AG7 AG9 AG15 AG17 AG27 AG29 Abbreviation Pin Descriptions Full Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin A19 A31 C13 E25 E33 F8 F30 G11 G13 G19 G21 G27 G29 G31 H6 H8 H10 H28 H30 H32 J5 J31 K8 K30 L31 L35 N31 Q31 S7 S31 U7 U31 U37 W7 W31 Y5 Y31 Y33 AA31 Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 17. Pin Name Abbreviations (continued) Abbreviation Chapter 10 Full Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NMI PICCLK Pin AC31 AD8 AD30 AE31 AF6 AF8 AF10 AF28 AF30 AF32 AG5 AG19 AG21 AG23 AG25 AG31 AH8 AH30 AJ7 AJ9 AJ11 AJ15 AJ17 AJ19 AJ27 AK8 AL7 AL9 AL11 AL25 AL27 AM8 AN7 AN9 AN11 AN25 AN27 AN3 N1 Table 17. Pin Name Abbreviations (continued) Abbreviation PICD#0 PICD#1 PLBYP# PLBYC PLBYC# PLMN1 PLMN2 PLTST# PRCRDY RCLK RCLK# SAI#0 SAI#1 SAI#2 SAI#3 SAI#4 SAI#5 SAI#6 SAI#7 SAI#8 SAI#9 SAI#10 SAI#11 SAI#12 SAI#13 SAI#14 SAIC# SAO#0 SAO#1 SAO#2 SAO#3 SAO#4 SAO#5 SAO#6 SAO#7 SAO#8 SAO#9 Pin Descriptions Full Name PICD[0]# PICD[1]# PLLBYPASS# PLLBYPASSCLK PLLBYPASSCLK# PLLMON1 PLLMON2 PLLTEST# PROCREADY PWROK RESET# RSTCLK RSTCLK# SADDIN[0]# SADDIN[1]# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[0]# SADDOUT[1]# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# SADDOUT[9]# Pin N3 N5 AJ25 AN15 AL15 AN13 AL13 AC3 AN23 AE3 AG3 AN19 AL19 AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 AJ33 J1 J3 C7 A7 E5 A5 E7 C1 C5 C3 47 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 17. Pin Name Abbreviations (continued) Table 17. Pin Name Abbreviations (continued) Abbreviation SAO#10 SAO#11 SAO#12 SAO#13 SAO#14 SAOC# SCNCK1 SCNCK2 SCNINV SCNSN SD#0 SD#1 SD#2 SD#3 SD#4 SD#5 SD#6 SD#7 SD#8 SD#9 SD#10 SD#11 SD#12 SD#13 SD#14 SD#15 SD#16 SD#17 SD#18 SD#19 SD#20 SD#21 SD#22 SD#23 SD#24 SD#25 SD#26 SD#27 SD#28 Abbreviation SD#29 SD#30 SD#31 SD#32 SD#33 SD#34 SD#35 SD#36 SD#37 SD#38 SD#39 SD#40 SD#41 SD#42 SD#43 SD#44 SD#45 SD#46 SD#47 SD#48 SD#49 SD#50 SD#51 SD#52 SD#53 SD#54 SD#55 SD#56 SD#57 SD#58 SD#59 SD#60 SD#61 SD#62 SD#63 SDIC#0 SDIC#1 SDIC#2 SDIC#3 48 Full Name SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCANCLK1 SCANCLK2 SCANINTEVAL SCANSHIFTEN SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# SDATA[28]# Pin G1 E1 A3 G5 G3 E3 S1 S5 S3 Q5 AA35 W37 W35 Y35 U35 U33 S37 S33 AA33 AE37 AC33 AC37 Y37 AA37 AC35 S35 Q37 Q35 N37 J33 G33 G37 E37 G35 Q33 N33 L33 N35 L37 Pin Descriptions Full Name SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# SDATA[36]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]# SDATAINCLK[3]# Pin J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15 E9 A13 C9 A9 C21 A21 E19 C19 C17 A11 A17 A15 W33 J35 E27 E15 Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 17. Pin Name Abbreviations (continued) Abbreviation SDINV# SDOC#0 SDOC#1 SDOC#2 SDOC#3 SDOV# SFILLV# STPC# SVRFM VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Chapter 10 Full Name SDATAINVALID# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVALID# SFILLVALID# SMI# STPCLK# SYSVREFMODE TCK TDI TDO TMS TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin AN33 AE35 C37 A33 C11 AL31 AJ31 AN5 AC1 AA5 Q1 U1 U5 Q3 U3 B4 B8 B12 B16 B20 B24 B28 B32 B36 D2 D4 D8 D12 D16 D20 D24 D28 D32 F12 F16 F20 F24 F28 F32 Table 17. Pin Name Abbreviations (continued) Abbreviation VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Descriptions Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin F34 F36 H2 H4 H12 H16 H20 H24 K32 K34 K36 M2 M4 M6 M8 P30 P32 P34 P36 R2 R4 R6 R8 T30 T32 T34 T36 V2 V4 V6 V8 X30 X32 X34 X36 Z2 Z4 Z6 Z8 49 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 17. Pin Name Abbreviations (continued) Abbreviation VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 50 Full Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Pin AB30 AB32 AB34 AB36 AD2 AD4 AD6 AF14 AF18 AF22 AF26 AF34 AF36 AH2 AH4 AH10 AH14 AH18 AH22 AH26 AK10 AK14 AK18 AK22 AK26 AK30 AK34 AK36 AJ5 AL5 AM2 AM10 AM14 AM18 AM22 AM26 AM22 AM26 AM30 Table 17. Pin Name Abbreviations (continued) Abbreviation VCC VREF_S Pin Descriptions Full Name VCC_CORE VCCA VCC_Z VID[0] VID[1] VID[2] VID[3] VID[4] VREF_SYS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin AM34 AJ23 AC7 L1 L3 L5 L7 J7 W5 B2 B6 B10 B14 B18 B22 B26 B30 B34 D6 D10 D14 D18 D22 D26 D30 D34 D36 F2 F4 F6 F10 F14 F18 F22 F26 H14 H18 H22 H26 Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 17. Pin Name Abbreviations (continued) Abbreviation Full Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Chapter 10 Pin H34 H36 K2 K4 K6 M30 M32 M34 M36 P2 P4 P6 P8 R30 R32 R34 R36 T2 T4 T6 T8 V30 V32 V34 V36 X2 X4 X6 X8 Z30 Z32 Z34 Z36 AB2 AB8 AB4 AB6 AD32 AD34 Table 17. Pin Name Abbreviations (continued) Abbreviation Pin Descriptions Full Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_Z ZN ZP Pin AD36 AF2 AF4 AF12 AF16 AH12 AH16 AH20 AH24 AH28 AH32 AH34 AH36 AK2 AK4 AK12 AK16 AK20 AK24 AK28 AK32 AM4 AM6 AM12 AM16 AM20 AM24 AM28 AM32 AM36 AE7 AC5 AE5 51 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 10.2 23792K--November 2001 Pin List Table 18 cross-references Socket A pin location to signal name. The "L" (Level) column shows the electrical specification for this pin. "P" indicates a push-pull mode driven by a single source. "O" indicates open-drain mode that allows devices to share the pin. Note: The Socket A AMD Duron Processor supports push-pull drivers. For more information, see "Push-Pull (PP) Drivers" on page 6. The "P" (Port) column indicates if this signal is an input (I), output (O), or bidirectional (B) signal. The "R" (Reference) column indicates if this signal should be referenced to VSS (G) or VCC_CORE (P) planes for the purpose of signal routing with respect to the current return paths. Table 18. Cross-Reference by Pin Location Pin Name Table 18. Cross-Reference by Pin Location Description L P R page 63 - - - B2 Pin Name Description L P R VSS - - - A1 No Pin A3 SADDOUT[12]# P O G B4 VCC_CORE - - - A5 SADDOUT[5]# P O G B6 VSS - - - A7 SADDOUT[3]# P O G B8 VCC_CORE - - - A9 SDATA[55]# P B P B10 VSS - - - A11 SDATA[61]# P B P B12 VCC_CORE - - - A13 SDATA[53]# P B G B14 VSS - - - A15 SDATA[63]# P B G B16 VCC_CORE - - - A17 SDATA[62]# P B G B18 VSS - - - A19 NC Pin - - - B20 VCC_CORE - - - A21 SDATA[57]# P B G B22 VSS - - - A23 SDATA[39]# P B G B24 VCC_CORE - - - A25 SDATA[35]# P B P B26 VSS - - - A27 SDATA[34]# P B P B28 VCC_CORE - - - A29 SDATA[44]# P B G B30 VSS - - - A31 NC Pin - - - B32 VCC_CORE - - - A33 SDATAOUTCLK[2]# P O P B34 VSS - - - A35 SDATA[40]# P B G B36 VCC_CORE - - - A37 SDATA[30]# P B P C1 SADDOUT[7]# P O G 52 page 63 page 63 Pin Descriptions Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 18. Cross-Reference by Pin Location (continued)Table 18. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R C3 SADDOUT[9]# P O G D34 VSS - - - C5 SADDOUT[8]# P O G D36 VSS - - - C7 SADDOUT[2]# P O G E1 SADDOUT[11]# P O P C9 SDATA[54]# P B P E3 SADDOUTCLK# P O G C11 SDATAOUTCLK[3]# P O G E5 SADDOUT[4]# P O P C13 NC Pin - - - E7 SADDOUT[6]# P O G C15 SDATA[51]# P B P E9 SDATA[52]# P B P C17 SDATA[60]# P B G E11 SDATA[50]# P B P C19 SDATA[59]# P B G E13 SDATA[49]# P B G C21 SDATA[56]# P B G E15 SDATAINCLK[3]# P I G C23 SDATA[37]# P B P E17 SDATA[48]# P B P C25 SDATA[47]# P B G E19 SDATA[58]# P B G C27 SDATA[38]# P B G E21 SDATA[36]# P B P C29 SDATA[45]# P B G E23 SDATA[46]# P B P C31 SDATA[43]# P B G E25 NC Pin - - - C33 SDATA[42]# P B G E27 SDATAINCLK[2]# P I G C35 SDATA[41]# P B G E29 SDATA[33]# P B P C37 SDATAOUTCLK[1]# P O G E31 SDATA[32]# P B P D2 VCC_CORE - - - E33 NC Pin - - - D4 VCC_CORE - - - E35 SDATA[31]# P B P D6 VSS - - - E37 SDATA[22]# P B G D8 VCC_CORE - - - F2 VSS - - - D10 VSS - - - F4 VSS - - - D12 VCC_CORE - - - F6 VSS - - - D14 VSS - - - F8 NC Pin - - - D16 VCC_CORE - - - F10 VSS - - - D18 VSS - - - F12 VCC_CORE - - - D20 VCC_CORE - - - F14 VSS - - - D22 VSS - - - F16 VCC_CORE - - - D24 VCC_CORE - - - F18 VSS - - - D26 VSS - - - F20 VCC_CORE - - - D28 VCC_CORE - - - F22 VSS - - - D30 VSS - - - F24 VCC_CORE - - - D32 VCC_CORE - - - F26 VSS - - - Chapter 10 page 63 Pin Descriptions page 63 page 63 page 63 53 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 18. Cross-Reference by Pin Location (continued)Table 18. Cross-Reference by Pin Location Pin Name Description L P R Pin - - - H22 - - - Name Description L P R VSS - - - H24 VCC_CORE - - - - - - F28 VCC_CORE F30 NC Pin F32 VCC_CORE - - - H26 VSS F34 VCC_CORE - - - H28 NC Pin page 63 - - - F36 VCC_CORE - - - H30 NC Pin page 63 - - - G1 SADDOUT[10]# P O P H32 NC Pin page 63 - - - G3 SADDOUT[14]# P O G H34 VSS - - - G5 SADDOUT[13]# P O G H36 VSS - - - G7 Key Pin page 63 - - - J1 SADDOUT[0]# page 64 P O - G9 Key Pin page 63 - - - J3 SADDOUT[1]# page 64 P O - G11 NC Pin page 63 - - - J5 NC Pin page 63 - - - G13 NC Pin page 63 - - - J7 VID[4] page 65 O O - G15 Key Pin page 63 - - - J31 NC Pin page 63 - - - G17 Key Pin page 63 - - - J33 SDATA[19]# P B G G19 NC Pin page 63 - - - J35 SDATAINCLK[1]# P I P G21 NC Pin page 63 - - - J37 SDATA[29]# P B P G23 Key Pin page 63 - - - K2 VSS - - - G25 Key Pin page 63 - - - K4 VSS - - - G27 NC Pin page 63 - - - K6 VSS - - - G29 NC Pin page 63 - - - K8 NC Pin page 63 - - - G31 NC Pin page 63 - - - K30 NC Pin page 63 - - - G33 SDATA[20]# P B G K32 VCC_CORE - - - G35 SDATA[23]# P B G K34 VCC_CORE - - - G37 SDATA[21]# P B G K36 VCC_CORE - - - H2 VCC_CORE - - - L1 VID[0] page 65 O O - H4 VCC_CORE - - - L3 VID[1] page 65 O O - H6 NC Pin page 63 - - - L5 VID[2] page 65 O O - H8 NC Pin page 63 - - - L7 VID[3] page 65 O O - H10 NC Pin page 63 - - - L31 NC Pin page 63 - - - H12 VCC_CORE - - - L33 SDATA[26]# P B P H14 VSS - - - L35 NC Pin - - - H16 VCC_CORE - - - L37 SDATA[28]# P B P H18 VSS - - - M2 VCC_CORE - - - H20 VCC_CORE - - - M4 VCC_CORE - - - 54 page 63 Pin Descriptions page 63 Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 18. Cross-Reference by Pin Location (continued)Table 18. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R M6 VCC_CORE - - - R30 VSS - - - M8 VCC_CORE - - - R32 VSS - - - M30 VSS - - - R34 VSS - - - M32 VSS - - - R36 VSS - - - M34 VSS - - - S1 SCANCLK1 page 64 P I - M36 VSS - - - S3 SCANINTEVAL page 64 P I - N1 PICCLK page 60 O I - S5 SCANCLK2 page 64 P I - N3 PICD#[0] page 60 O B - S7 NC Pin page 63 - - - N5 PICD#[1] page 60 O B - S31 NC Pin page 63 - - - N7 Key Pin page 63 - - - S33 SDATA[7]# P B G N31 NC Pin page 63 - - - S35 SDATA[15]# P B P N33 SDATA[25]# P B P S37 SDATA[6]# P B G N35 SDATA[27]# P B P T2 VSS - - - N37 SDATA[18]# P B G T4 VSS - - - P2 VSS - - - T6 VSS - - - P4 VSS - - - T8 VSS - - - P6 VSS - - - T30 VCC_CORE - - - P8 VSS - - - T32 VCC_CORE - - - P30 VCC_CORE - - - T34 VCC_CORE - - - P32 VCC_CORE - - - T36 VCC_CORE - - - P34 VCC_CORE - - - U1 TDI page 63 P I - P36 VCC_CORE - - - U3 TRST# page 63 P I - Q1 TCK page 63 P I - U5 TDO page 63 P O - Q3 TMS page 63 P I - U7 NC Pin page 63 - - - Q5 SCANSHIFTEN page 64 P I - U31 NC Pin page 63 - - - Q7 Key Pin page 63 - - - U33 SDATA[5]# P B G Q31 NC Pin page 63 - - - U35 SDATA[4]# P B G Q33 SDATA[24]# P B P U37 NC Pin - - - Q35 SDATA[17]# P B G V2 VCC_CORE - - - Q37 SDATA[16]# P B G V4 VCC_CORE - - - R2 VCC_CORE - - - V6 VCC_CORE - - - R4 VCC_CORE - - - V8 VCC_CORE - - - R6 VCC_CORE - - - V30 VSS - - - R8 VCC_CORE - - - V32 VSS - - - Chapter 10 Pin Descriptions page 63 55 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 18. Cross-Reference by Pin Location (continued)Table 18. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R V34 VSS - - - AA1 DBRDY page 61 P O - V36 VSS - - - AA3 DBREQ# page 61 P I - W1 FID[0] page 62 O - - AA5 SYSVREFMODE page 64 P I - W3 FID[1] page 62 O - - AA7 Key Pin page 63 - - - W5 VREFSYS page 66 P - - AA31 NC Pin page 63 - - - W7 NC Pin page 63 - - - AA33 SDATA[8]# P B P W31 NC Pin page 63 - - - AA35 SDATA[0]# P B G W33 SDATAINCLK[0]# P I G AA37 SDATA[13]# P B G W35 SDATA[2]# P B G AB2 VSS - - - W37 SDATA[1]# P B P AB4 VSS - - - X2 VSS - - - AB6 VSS - - - X4 VSS - - - AB8 VSS - - - X6 VSS - - - AB30 VCC_CORE - - - X8 VSS - - - AB32 VCC_CORE - - - X30 VCC_CORE - - - AB34 VCC_CORE - - - X32 VCC_CORE - - - AB36 VCC_CORE - - - X34 VCC_CORE - - - AC1 STPCLK# page 64 P I - X36 VCC_CORE - - - AC3 PLLTEST# page 64 P I - Y1 FID[2] page 62 O - - AC5 ZN page 66 P - - Y3 FID[3] page 62 O - - AC7 VCC_Z page 66 - - - Y5 NC Pin page 63 - - - AC31 NC Pin page 63 - - - Y7 Key Pin page 63 - - - AC33 SDATA[10]# P B P Y31 NC Pin page 63 - - - AC35 SDATA[14]# P B G Y33 NC Pin page 63 - - - AC37 SDATA[11]# P B G Y35 SDATA[3]# P B G AD2 VCC_CORE - - - Y37 SDATA[12]# P B P AD4 VCC_CORE - - - Z2 VCC_CORE - - - AD6 VCC_CORE - - - Z4 VCC_CORE - - - AD8 NC Pin page 63 - - - Z6 VCC_CORE - - - AD30 NC Pin page 63 - - - Z8 VCC_CORE - - - AD32 VSS - - - Z30 VSS - - - AD34 VSS - - - Z32 VSS - - - AD36 VSS - - - Z34 VSS - - - AE1 A20M# P I - Z36 VSS - - - AE3 PWROK P I - 56 Pin Descriptions Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 18. Cross-Reference by Pin Location (continued)Table 18. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R AE5 ZP page 66 P - - AG21 NC Pin page 63 - - - AE7 VSS_Z page 66 - - - AG23 NC Pin page 63 - - - AE31 NC Pin page 63 - - - AG25 NC Pin page 63 - - - AE33 SADDIN[5]# P I G AG27 Key Pin page 63 - - - AE35 SDATAOUTCLK[0]# P O P AG29 Key Pin page 63 - - - AE37 SDATA[9]# P B G AG31 NC Pin page 63 - - - AF2 VSS - - - AG33 SADDIN[2]# P I G AF4 VSS - - - AG35 SADDIN[11]# P I G AF6 NC Pin page 63 - - - AG37 SADDIN[7]# P I P AF8 NC Pin page 63 - - - AH2 VCC_CORE - - - AF10 NC Pin page 63 - - - AH4 VCC_CORE - - - AF12 VSS - - - AH6 AMD Pin page 60 - - - AF14 VCC_CORE - - - AH8 NC Pin page 63 - - - AF16 VSS - - - AH10 VCC_CORE - - - AF18 VCC_CORE - - - AH12 VSS - - - AF20 VSS - - - AH14 VCC_CORE - - - AF22 VCC_CORE - - - AH16 VSS - - - AF24 VSS - - - AH18 VCC_CORE - - - AF26 VCC_CORE - - - AH20 VSS - - - AF28 NC Pin page 63 - - - AH22 VCC_CORE - - - AF30 NC Pin page 63 - - - AH24 VSS - - - AF32 NC Pin page 63 - - - AH26 VCC_CORE - - - AF34 VCC_CORE - - - AH28 VSS - - - AF36 VCC_CORE - - - AH30 NC Pin - - - AG1 FERR P O - AH32 VSS - - - AG3 RESET# - I - AH34 VSS - - - AG5 NC Pin page 63 - - - AH36 VSS - - - AG7 Key Pin page 63 - - - AJ1 IGNNE# page 63 P I - AG9 Key Pin page 63 - - - AJ3 INIT# page 63 P I - AG11 COREFB page 61 - - - AJ5 VCC_CORE - - - AG13 COREFB# page 61 - - - AJ7 NC Pin page 63 - - - AG15 Key Pin page 63 - - - AJ9 NC Pin page 63 - - - AG17 Key Pin page 63 - - - AJ11 NC Pin page 63 - - - AG19 NC Pin page 63 - - - AJ13 Analog page 60 - - - Chapter 10 page 61 Pin Descriptions page 63 57 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 18. Cross-Reference by Pin Location (continued)Table 18. Cross-Reference by Pin Location Pin Name Description L P R Pin Name Description L P R AJ15 NC Pin page 63 - - - AL9 NC Pin page 63 - - - AJ17 NC Pin page 63 - - - AL11 NC Pin page 63 - - - AJ19 NC Pin page 63 - - - AL13 PLLMON2 page 64 O O - AJ21 CLKFWDRST page 60 P I P AL15 PLLBYPASSCLK# page 64 P I - AJ23 VCCA page 65 - - - AL17 CLKIN# page 60 P I P AJ25 PLLBYPASS# page 64 P I - AL19 RSTCLK# page 60 P I P AJ27 NC Pin page 63 - - - AL21 K7CLKOUT page 63 P O - AJ29 SADDIN[0]# page 64 P I - AL23 CONNECT page 60 P I P AJ31 SFILLVALID# P I G AL25 NC Pin page 63 - - - AJ33 SADDINCLK# P I G AL27 NC Pin page 63 - - - AJ35 SADDIN[6]# P I P AL29 SADDIN[1]# page 64 P I - AJ37 SADDIN[3]# P I G AL31 SDATAOUTVALID# P O P AK2 VSS - - - AL33 SADDIN[8]# P I P AK4 VSS - - - AL35 SADDIN[4]# P I G AK6 CPU_PRESENCE# page 61 - - - AL37 SADDIN[10]# P I G AK8 NC Pin page 63 - - - AM2 VCC_CORE - - - AK10 VCC_CORE - - - AM4 VSS - - - AK12 VSS - - - AM6 VSS - - - AK14 VCC_CORE - - - AM8 NC Pin - - - AK16 VSS - - - AM10 VCC_CORE - - - AK18 VCC_CORE - - - AM12 VSS - - - AK20 VSS - - - AM14 VCC_CORE - - - AK22 VCC_CORE - - - AM16 VSS - - - AK24 VSS - - - AM18 VCC_CORE - - - AK26 VCC_CORE - - - AM20 VSS - - - AK28 VSS - - - AM22 VCC_CORE - - - AK30 VCC_CORE - - - AM24 VSS - - - AK32 VSS - - - AM26 VCC_CORE - - - AK34 VCC_CORE - - - AM28 VSS - - - AK36 VCC_CORE - - - AM30 VCC_CORE - - - AL1 INTR page 63 P I - AM32 VSS - - - AL3 FLUSH# page 63 P I - AM34 VCC_CORE - - - AL5 VCC_CORE - - - AM36 VSS - - - AL7 NC Pin - - - AN1 No Pin - - - 58 page 63 Pin Descriptions page 63 page 63 Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 18. Cross-Reference by Pin Location (continued) Pin Name Description L P R AN3 NMI P I - AN5 SMI# P I - AN7 NC Pin page 63 - - - AN9 NC Pin page 63 - - - AN11 NC Pin page 63 - - - AN13 PLLMON1 page 64 O B - AN15 PLLBYPASSCLK page 64 P I - AN17 CLKIN page 60 P I P AN19 RSTCLK page 60 P I P AN21 K7CLKOUT# page 63 P O - AN23 PROCRDY P O P AN25 NC Pin page 63 - - - AN27 NC Pin page 63 - - - AN29 SADDIN[12]# P I G AN31 SADDIN[14]# P I G AN33 SDATAINVALID# P I P AN35 SADDIN[13]# P I G AN37 SADDIN[9]# P I G Chapter 10 Pin Descriptions 59 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 10.3 23792K--November 2001 Detailed Pin Descriptions The information in this section pertains to Table 18 on page 52. A20M# Pin A20M# is an input from the system used to simulate address wrap-around in the 20-bit 8086. AMD Pin AMD Socket A processors do not implement a pin at location AH6. All Socket A designs must have a top plate or cover that blocks this pin location. When the cover plate blocks this location, a non-AMD part (e.g., PGA370) does not fit into the socket. However, socket manufacturers are allowed to have a contact loaded in the AH6 position. Therefore, motherboard socket design should account for the possibility that a contact could be loaded in this position. AMD AthlonTM System Bus Pins See the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902 for information about the system bus pins -- PROCRDY, PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#, SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#. Analog Pin Treat this pin as a NC. APIC Pins, PICCLK, PICD[1:0]# The Advanced Programmable Interrupt Controller (APIC) is a feature that provides a flexible and expandable means of delivering interrupts in a system using an AMD processor. The pins, PICD[1:0], are the bi-directional message-passing signals used for the APIC and are driven to the Southbridge or a dedicated I/O APIC. The pin, PICCLK, must be driven with a valid clock input. For more information, see Table 14, "APIC Pins AC and DC Characteristics," on page 34. CLKFWDRST Pin CLKFWDRST resets clock-forward circuitry for both the system and processor. CLKIN, RSTCLK (SYSCLK) Pins Connect CLKIN (AN17) with RSTCLK (AN19) and name it SYSCLK. Connect CLKIN# (AL17) with RSTCLK# (AL19) and name it SYSCLK#. Length match the clocks from the clock generator to the Northbridge and processor. See "SYSCLK and SYSCLK# Pins" on page 64 for more information. CONNECT Pin CONNECT is an input from the system used for power management and clock-forward initialization at reset. 60 Pin Descriptions Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 COREFB and COREFB# Pins COREFB and COREFB# are outputs to the system that provide processor core voltage feedback to the system. CPU_PRESENCE# Pin CPU_PRESENCE# is connected to VSS on the processor package. If pulled-up on the motherboard, CPU_PRESENCE# can be used to detect the presence or absence of a processor in the Socket A-style socket. DBRDY and DBREQ# Pins DBRDY (AA1) and DBREQ# (AA3) are routed to the debug connector. DBREQ# is tied to VCC_CORE with a pullup resistor. FERR Pin FERR is an output to the system that is asserted for any unmasked numerical exception independent of the NE bit in CR0. FERR is a push-pull active High signal that must be inverted and level shifted to an active Low signal. For more information about FERR and FERR#, see the "Required Circuits" chapter of the AMD AthlonTM Processor-Based Motherboard Design Guide order# 24363. FID[3:0] Pins See "Frequency Identification (FID[3:0])" on page 24 for the AC and DC characteristics for FID[3:0]. FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the 4-bit processor clock-to-SYSCLK ratio. Table 19 on page 62 describes the encodings of the clock multipliers on FID[3:0]. Chapter 10 Pin Descriptions 61 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 19. FID[3:0] Clock Multiplier Encodings FID[3] FID[2] FID[1] FID[0] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Processor Clock to SYSCLK Frequency Ratio 11 11.5 12 12.5* 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 Note: *All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011, which causes the SIP configuration for all ratios of 12.5x or greater to be the same. The FID[3:0] signals are open drain processor outputs that are pulled High on the motherboard and sampled by the chipset at the deassertion of RESET# to determine the SIP (Serialization Initialization Packet) that gets sent to the processor. See the AMD AthlonTM and AMD DuronTM System Bus Specification, order#21902 for more information about the Serialization Initialization Packets and SIP protocol. The processor FID[3:0] outputs are open drain and 2.5V tolerant. To prevent damage to the processor, if these signals are pulled High to above 2.5 V, they must be electrically isolated from the processor. For information about the FID[3:0] isolation circuit, see the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. 62 Pin Descriptions Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 FLUSH# Pin FLUSH# must be tied to VCC_CORE with a pullup resistor. If a debug connector is implemented, FLUSH# is routed to the debug connector. IGNNE# Pin IGNNE# is an input from the system that tells the processor to ignore numeric errors. INIT# Pin INIT# is an input from the system that resets the integer registers without affecting the floating-point registers or the internal caches. Execution starts at 0_FFFF_FFF0h. INTR Pin INTR is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. JTAG Pins TCK (Q1), TMS (Q3), TDI (U1), TRST# (U3), and TDO (U5) are the JTAG interface. Connect these pins directly to the motherboard debug connector. Pullup TDI, TCK, TMS, and TRST# to VCC_CORE with pullup resistors. K7CLKOUT and K7CLKOUT# Pins K7CLKOUT (AL21) and K7CLKOUT# (AN21) are each run for 2 to 3 inches and then terminated with a resistor pair, 100 ohms to VCC_CORE and 100 ohms to VSS. The effective termination resistance and voltage are 50 ohms and VCC_CORE/2. Key Pins These 16 locations are for processor type keying for forwards and backwards compatibility (G7, G9, G15, G17, G23, G25, N7, Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29). Motherboard designers should treat key pins like NC (no connect) pins. See "NC Pins" on page 63 for more information. A socket designer has the option of creating a top mold piece that allows PGA key pins only where designated. However, sockets that populate all 16 key pins must be allowed, so the motherboard must always provide for pins at all key pin locations. NC Pins The motherboard should provide a plated hole for an NC pin. The pin hole should not be electrically connected to anything. NMI Pin NMI is an input from the system that causes a non-maskable interrupt. PGA Orientation Pins No pin is present at pin locations A1 and AN1. Motherboard designers should not allow for a PGA socket pin at these locations. Chapter 10 Pin Descriptions 63 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 For more information, see the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. PLL Bypass and Test Pins PLLTEST# (AC3), PLLBYPASS# (AJ25), PLLMON1 (AN13), P L L M O N 2 ( A L 1 3 ) , P L L B Y PA S S C L K ( A N 1 5 ) , a n d PLLBYPASSCLK# (AL15) are the PLL bypass and test interface. This interface is tied disabled on the motherboard. All six pin signals are routed to the debug connector. All four processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup resistors. PWROK Pin The PWROK input to the processor must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specification. Fo r m o re i n f o r m a t i o n , S e e " S i g n a l a n d Po w e r -U p Requirements" on page 35. SADDIN[1:0]# and SADDOUT[1:0]# Pins The AMD A thlon processor mo del 4 does not support SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC with pullup resistors, if this bit is not supported by the Northbridge (future models can support SADDIN[1]#). SADDOUT[1:0]# are tied to VCC with pullup resistors if these pins are supported by the Northbridge. For more information, see the AMD AthlonTM and AMD DuronTM System Bus Specification, order# 21902. Scan Pins SCANSHIFTEN (Q5), SCANCLK1 (S1), SCANINTEVAL (S3), and SCANCLK2 (S5) are the scan interface. This interface is AMD internal and is tied disabled with pulldown resistors to ground on the motherboard. SMI# Pin SMI# is an input that causes the processor to enter the system management mode. STPCLK# Pin STPCLK# is an input that causes the processor to enter a lower power mode and issue a Stop Grant special cycle. SYSCLK and SYSCLK# Pins SYSCLK and SYSCLK# are differential input clock signals provided to the processor's PLL from a system-clock generator. See "CLKIN, RSTCLK (SYSCLK) Pins" on page 60 for more information. SYSVREFMODE Pin SYSVREFMODE (AA5) is Low to ensure that the external VREFSYS voltage is the actual voltage used by the input buffers and that no scaling occurs internally between the 64 Pin Descriptions Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 VREFSYS voltage and the input threshold. This pin is tied Low with a pulldown resistor. VCCA Pin VCCA is the processor PLL supply. For information about the VCCA pin, see Table 5, "VCCA AC and DC Characteristics," on page 25 and the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. VID[4:0] Pins The VID[4:0] (Voltage Identification) outputs are used to dictate the VCC_CORE voltage level. The VID[4:0] pins are strapped to ground or left unconnected on the processor's package. The VID[4:0] pins are pulled-up on the motherboard and used by the VCC_CORE DC/DC converter. These voltage ID values are defined Table 20 on page 66. Chapter 10 Pin Descriptions 65 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 20. VID[4:0] Code to Voltage Definition VID[4:0] VCC_CORE (V) VID[4:0] VCC_CORE (V) 00000 1.850 10000 1.450 00001 1.825 10001 1.425 00010 1.800 10010 1.400 00011 1.775 10011 1.375 00100 1.750 10100 1.350 00101 1.725 10101 1.325 00110 1.700 10110 1.300 00111 1.675 10111 1.275 01000 1.650 11000 1.250 01001 1.625 11001 1.225 01010 1.600 11010 1.200 01011 1.575 11011 1.175 01100 1.550 11100 1.150 01101 1.525 11101 1.125 01110 1.500 11110 1.100 01111 1.475 11111 No CPU For more information, see the "Required Circuits" chapter of the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. VREFSYS Pin VREFSYS (W5) drives the threshold voltage for the system bus input receivers. The value of VREFSYS is system specific. In addition, to minimize VCC_CORE noise rejection from V R E F S Y S , i n c l u d e d e c o u p l i n g c a p a c i t o rs . Fo r m o re information, see the AMD AthlonTM Processor-Based Motherboard Design Guide, order# 24363. ZN, VCC_Z, ZP, and VSS_Z Pins ZN (AC5), VCC_Z (AC7), ZP (AE5), and VSS_Z(AE7) are the push-pull compensation circuit pins. VCC_ Z is tied to VCC_CORE. VSS_Z is tied to VSS. In Push-Pull mode (selected by the SIP parameter SysPushPull asserted), ZN is tied to VCC_CORE with a resistor that has a resistance matching the impedance Z0 of the transmission line. ZP is tied to VSS with a resistor that has a resistance matching the impedance Z0 of the transmission line. 66 Pin Descriptions Chapter 10 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 11 Ordering Information Standard AMD AthlonTM Processor Model 4 Products AMD standard products are available in several operating ranges. The ordering part numbers (OPN) are formed by a combination of the elements, as shown in Figure 14. PGA OPN A 1400 A M S 3 C Max FSB: B = 200 MHz, C = 266 MHz Size of L2 Cache: 3 = 256 Kbytes Die Temperature: S = 95C, T = 90C Operating Voltage: M = 1.75V Package Type: A = PGA Speed: 0900=900 MHz, 1000=1000 MHz, 1100=1100 MHz, 1133= 1133 MHz, 1200=1200 MHz, 1266 = 1266 MHz, 1300=1300 MHz, 1333= 1333 MHz, 1400=1400 MHz Family/Architecture: A = AMD AthlonTM Processor Model 4 Architecture Note: Spaces are added to the number shown above for viewing clarity only. Figure 14. PGA OPN Example for the AMD AthlonTM Processor Model 4 Chapter 11 Ordering Information 71 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 72 Ordering Information 23792K--November 2001 Chapter 11 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Appendix A Conventions and Abbreviations This section contains information about the conventions and abbreviations used in this document. Signals and Bits Active-Low Signals--Signal names containing a pound sign, such as SFILL#, indicate active-Low signals. They are asserted in their Low-voltage state and negated in their High-voltage state. When used in this context, High and Low are written with an initial upper case letter. Signal Ranges--In a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (for example, D[63:0]). Reserved Bits and Signals--Signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. These bits and signals are reserved by AMD for future implementations. When software reads registers with reserved bits, the reserved bits must be masked. When software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. Three-State--In timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels. Appendix A 73 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Invalid and Don't-Care--In timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. Data Terminology The following list defines data terminology: Abbreviations--The following notation is used for bits and bytes: i Kilo (K, as in 4-Kbyte page) i Mega (M, as in 4 Mbits/sec) i Giga (G, as in 4 Gbytes of memory space) See Table 21 on page 75 for more abbreviations. Little-Endian Convention--The byte with the address xx...xx00 is in the least-significant byte position (little end). In byte diagrams, bit positions are numbered from right to left--the little end is on the right and the big end is on the left. Data structure diagrams in memory show low addresses at the bottom and high addresses at the top. When data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. Because byte addresses increase from right to left, strings appear in reverse order when illustrated. Bit Ranges--In text, bit ranges are shown with a dash (for example, bits 9-1). When accompanied by a signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a colon (for example, AD[31:0]). Bit Values--Bits can either be set to 1 or cleared to 0. Hexadecimal and Binary Numbers--Unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b. 74 Quantities i A word is two bytes (16 bits) i A doubleword is four bytes (32 bits) i A quadword is eight bytes (64 bits) Addressing--Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. Appendix A Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Abbreviations and Acronyms Table 21 contains the definitions of abbreviations used in this document. Table 21. Abbreviations Appendix A Abbreviation Meaning A Ampere F Farad G Giga- Gbit Gigabit Gbyte Gigabyte H Henry h Hexadecimal K Kilo- Kbyte Kilobyte M Mega- Mbit Megabit Mbyte Megabyte MHz Megahertz m Milli- ms Millisecond mW Milliwatt Micro- A Microampere F Microfarad H Microhenry s Microsecond V Microvolt n nano- nA nanoampere nF nanofarad nH nanohenry ns nanosecond ohm Ohm p pico- pA picoampere 75 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 21. Abbreviations (continued) Abbreviation Meaning pF picofarad pH picohenry ps picosecond s Second V Volt W Watt Table 22 contains the definitions of acronyms used in this document. Table 22. Acronyms 76 Abbreviation Meaning ACPI Advanced Configuration and Power Interface AGP Accelerated Graphics Port APCI AGP Peripheral Component Interconnect API Application Programming Interface APIC Advanced Programmable Interrupt Controller BIOS Basic Input/Output System BIST Built-In Self-Test BIU Bus Interface Unit DDR Double-Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DRAM Direct Random Access Memory EIDE Enhanced Integrated Device Electronics EISA Extended Industry Standard Architecture EPROM Enhanced Programmable Read Only Memory FIFO First In, First Out GART Graphics Address Remapping Table HSTL High-Speed Transistor Logic IDE Integrated Device Electronics ISA Industry Standard Architecture JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group Appendix A Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 22. Acronyms (continued) Appendix A Abbreviation Meaning LAN Large Area Network LRU Least-Recently Used LVTTL Low Voltage Transistor Transistor Logic MSB Most Significant Bit MTRR Memory Type and Range Registers MUX Multiplexer NMI Non-Maskable Interrupt OD Open-Drain PBGA Plastic Ball Grid Array PA Physical Address PCI Peripheral Component Interconnect PDE Page Directory Entry PDT Page Directory Table PLL Phase Locked Loop PMSM Power Management State Machine POS Power-On Suspend POST Power-On Self-Test RAM Random Access Memory ROM Read Only Memory RXA Read Acknowledge Queue SDI System DRAM Interface SDRAM Synchronous Direct Random Access Memory SIP Serial Initialization Packet SMbus System Management Bus SPD Serial Presence Detect SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory TTL Transistor Transistor Logic VAS Virtual Address Space VPA Virtual Page Address VGA Video Graphics Adapter USB Universal Serial Bus 77 Preliminary Information AMD AthlonTM Processor Model 4 Data Sheet 23792K--November 2001 Table 22. Acronyms (continued) 78 Abbreviation Meaning ZDB Zero Delay Buffer Appendix A