SST39VF1681-70-4C-EKE - Silicon Storage Technology, Inc.

Preliminary Specifications

S71243-03-000 11/03

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

16 Mbit (x8) Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FEATURES:

• Organized as 2M x8

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

• Low P o wer Consumption (typical values at 5 MHz)

– Active Current: 9 mA (typical)

– Standby Current: 3 µA (typical)

– Auto Low Power Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 64 KByte)

for SST39V F1682

– Bottom Block-Protection (bottom 64 KByte)

for SST39V F1681

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Block-Erase Capability

– Uniform 64 KByte blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Fast Read Access Time:

– 70 ns

– 90 ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Byte-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bits

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and Command sets

• Packages Availab le

– 48-ball TFBGA (6mm x 8mm)

– 48-lead TSOP (12mm x 20mm)

PRODUCT DESCRIPTION

The SST39V F168x devices are 2M x8 CMO S Multi-Pur-

pose Flash Plus (MPF+) manufactured with SST’s propri-

etary, high performance CMOS SuperFlash technology.

The split- gate cell design and thick-oxid e tunneling injec-

tor attain better reliability and manufacturability compared

with alternate approaches. The SST39VF168x write (Pro-

gram or Erase) with a 2.7-3.6V power supply. These

devices conform to JEDEC standard pinouts for x8 mem-

ories.

Featuring high performance Byte-Program, the

SST39VF168x devices provide a typical Byte-Program

time of 7 µsec. These devices use Toggle Bit or Data# Poll-

ing to indicate the completion of Program operation. To pro-

tect against inadvertent write, they have on-chip hardware

and Softwa re Data Prot ection sc hemes. Design ed, manu-

factured, and tested for a wide spectrum of applications,

these d evices ar e offered with a g ua rant eed typi c al en dur-

ance o f 100,000 cycles. Data retention is rated at greater

than 100 y ears .

The SST39VF168x devices are suited for applications that

require convenient and economical updating of program,

conf igu rat ion , or da ta mem ory. For al l s yst e m a ppl i ca tio ns,

they signifi c ant ly i mp r ove performa nc e an d reli ab il it y, while

lowering power consumption. They inherently use less

energy during Erase and Program than alternative flash

technologies. The total energy consumed is a function of

the appl ied volta ge, curre nt, and time of ap plicati on. S inc e

for any given voltage range, the SuperFlash technology

uses less current to program and has a shorter erase time,

the total energy consumed during any Erase or Program

operation is less than alternativ e flash technologies. These

devices also improve flexibility while lowering the cost for

program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gr am times, independent of the number of Er ase/Prog ram

cycles that have occurred. Therefore the system software

or hardwa re does not hav e to be modified or de-r ated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Prog ram cycles.

To meet high density, surface mount requirements, the

SST39VF168x are offered in both 48-ball TFBGA and

48-lead TSOP packages. See Figures 1 and 2 for pin

assignments.

SST39VF1681 / 16822.7V 16Mb (x8) MPF+ memories

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asse rtin g WE# low while keepi ng CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever oc curs l ast. T he data bus is latc hed o n

the rising edge of WE# or CE#, whiche ver occurs first.

The SST39VF168x also have the Auto Lo w Power mode

which puts the device in a near standby mode after data

has been accessed with a valid Read operation. This

reduce s th e IDD active read current from typically 9 mA to

typically 3 µA. The Auto Low P ow er mode reduces the typi-

cal IDD active read current to the range of 2 mA/MHz of

Read cycle time. The device exits the Auto Low Power

mode with any address transition or control signal transition

used to initiate another Read cycle, with no access time

penalty. Note that the device does not enter Auto-Low

Power mode after power-up with CE# held steadily low,

until the first address transition or CE# is driven high.

Read

The Read operation of the SST39VF168x is controlled

by CE# and OE#, both have to be low for the system to

obtain data from the outputs. CE# is used for device

selection. When CE# is high, the chip is deselected and

only standby power is consumed. OE# is the output con-

trol and is used to gate data from the output pins. The

data bus is in high impedance state when either CE# or

OE# is high. Refer to the Read cycle timing diagram for

further details (Figure 3).

Byte-P rogram Opera ti on

The SST39VF168x are programmed on a byte-by-byte

basis. Before programming, the sector where the byte

exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load byte address and byte data. During the Byte-

Prog ram o perat ion, th e address es are latched on the falli ng

edge of either CE# or WE#, whichever occurs last. The

data is latched on the rising edge of either CE# or WE#,

whichever occurs first. The third step is the internal Pro-

gram operation which is initiated after the rising edge of the

fourth WE# or CE#, whichever occurs first. The Program

operation, once initiated, will be completed within 10 µs.

See F i gu re s 4 a nd 5 for WE # an d CE # co nt ro ll ed P rogram

operation timing diagrams and Figure 19 for flowcharts.

During the Program operation, the only valid reads are

Data# Polling and Toggle Bit . During the inter nal Program

operatio n, the host i s free to perfor m additio nal tasks. Any

commands issued during the internal Program operation

are igno red. D uri ng the c omman d seq uence, WP # shoul d

be sta ticall y held hi gh or lo w.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39VF168x offer both Sector-Erase

and Block-Erase mode. The sector architecture is based

on unifor m sector size of 4 KByte. The Block-Erase mode

is based on uniform block size of 64 KByte. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (50H) and

sector address (SA) in the last bus cycle. The Bloc k-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (30H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, whil e the command (30H or 50H) is latched on th e

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

P olling or Toggle Bit methods. See Figures 9 and 10 for tim-

ing waveforms and Figure 23 for the flowchart. Any com-

mands i s su ed during the S ec tor- or Bl ock-Era se op erat io n

are ignored. When WP# is low, any attempt to Sector-

(Block-) Erase the protected block will be ignored. During

the command sequence, WP# should be statically held

high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memor y loca tion, or program dat a into any

sector /block that i s not sus pended for an Eras e operation .

The operation is executed by issuing one byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode typically within 20

µs after the Erase-Suspend command had been issued.

Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address

locati on within erase-suspended sectors/blocks will output

DQ2 toggling and DQ6 at “1”. While in Erase-Suspend

mode, a Byte-Pr ogram operation is allowed except for the

sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at an y address in the last Byte sequence .

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Chip-Erase Operation

The SST39VF16 8x provide a Chip-Erase o peration, w hich

allows the user to erase the en tire memory arra y to the “1”

state. This is useful when the entire de vice must be quickly

erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address AAAH in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or CE#, whichever occurs first. During the Erase

operation, the only valid read is Toggle Bit or Data# P olling.

See Table 6 for the command sequence, Figure 9 for tim-

ing diagram, and Figure 23 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored. When WP# is low, any attempt to Chip-Erase will

be ignored. During the command sequence, WP# should

be statically held high or lo w.

Write Operation Status Detection

The S ST39VF16 8x provide two so ftware mea ns to det ect

the completion of a Write (Program or Erase) cycle, in

order to optimi ze th e syste m write cycle t ime . The s oftw are

detection includes two status bits: Data# P olling (DQ7) and

Toggle Bit (DQ6). The End-of-Write detection mode is

enabled after the rising edge of WE#, which initiates the

internal Program or Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system; therefore, either a Data# Poll-

ing or Toggle Bit read may be simultaneous with the

completion of the write cycle. If this occurs, the system

may possibly get an erroneous result, i.e., valid data may

appear t o conf lict w it h e ith er D Q 7 or DQ6. In order to pre-

vent spurious rejectio n, if an erroneous result occurs , the

software routine should include a loop to read the

accessed location an additional two (2) times. If both

reads are va lid, then the device has completed the Write

cycle, ot herwise the reje ction is valid.

Data# Polling (DQ7)

When the SST39VF168x ar e in the internal Program ope r-

ation, any attempt to read DQ7 will produce the comple-

ment of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though D Q7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycle s a f ter an in te rv a l o f 1 µ s . Du ring internal Erase oper-

ation, an y at tempt t o read D Q7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. The Dat a# Polling is valid after the rising edge o f f ourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling is valid after the

rising edge of sixth WE# (or CE#) pulse. See Figure 6 for

Data# P olling t iming diagram and Fig ure 20 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 w ill pr od uc e a lt ernat in g “1 ”s

and “0”s, i.e., togg li ng between 1 and 0. Wh en t he inte rnal

Program or Erase op eration is compl eted, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. For Sector-, Block -, or Chip-Erase, the toggle bit (DQ6)

is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ6 will be set to “1” if a Read operation is attempted on an

Erase-Suspended Sector/Block. If Program operation is ini-

tiated in a sector/block not selected in Erase-Suspend

mode, DQ6 will to ggle .

An addi tio na l Toggl e B i t i s available on DQ2, which can be

used in conjunction with DQ6 to ch eck whethe r a particula r

sector is being actively erased or erase-suspended. Table 1

shows detailed status bits information. The Toggle Bit

(DQ2) is valid after the rising edge of the last WE# (or CE#)

pulse of Write operation. See Figure 7 for Toggle Bit timing

diagram and Figure 20 for a flowchart.

Note: DQ7 and DQ2 require a valid address when reading

status inf ormation.

TABLE 1: WRITE OPERATION STATUS

Status DQ7DQ6DQ2

Normal

Operation Standard

Program DQ7# Toggle No Toggle

Standard

Erase 0 Toggle Toggle

Erase-

Suspend

Mode

Read from

Erase Suspended

Sector/Block

1 1 Toggle

Read from

Non- Erase Suspended

Sector/Block

Data Data Data

Program DQ7# Toggle N/A

T1.0 1243

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Protection

The SST39VF168x provide both hardware and software

f eatur es to protect non vo latile data f rom inad vertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# o r CE# pulse of le ss than 5

ns will not ini tiate a w rite cycle .

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will in hi bit t he Write ope rati on . Thi s pr events i nad vert-

ent w rites durin g pow er-u p or po wer- dow n.

Hardware Block Protection

The SST39VF1682 supports top hardware block protec-

tion, which protects the top 64 KByte block of the device.

The SST39VF1681 suppor ts bottom hardware block pro-

tection, which protects the bottom 64 KByte block of the

device. The Boot Block address ranges are described in

Table 2. Program and Erase operations are prevented on

the 64 KBy te when WP # is low. If WP # is left floa ting, it is

internally held high via a pull-up resistor, and the Boot

Block is unprotected, enabling Program and Erase opera-

tions on that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

f or at least TRP, any in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of TRHR is

required after RST# is driven high bef ore a valid Read can

take place (see Figure 15).

The Erase or Program operation that has been interrupted

needs to be reinitiated after the device resumes normal

operation mode to ensure data integrity.

Software Data Protection (SDP)

The S ST39VF16 8x pro vide th e JEDEC ap prov ed S oftwar e

Data Protection scheme for all data alteration operations,

i.e., Program and Erase. Any Program operation requires

the inclusion of the three-byte sequence. The three-byte

load sequence is used to initiate the Program operation,

providing optimal protection from inad ver tent Write opera-

tions, e.g., during the system power-up or power-down.

Any Erase operation requires the inclusion of six-byte

sequence. These devices are shipped with the Software

Data Protection permanently enabled. See Table 6 for the

specific software command codes. During SDP command

sequence, invalid commands will abort the device to Read

mode within TRC.

Common Flash Memory Interface (CFI)

The SST39VF168x also contain the CFI information to

describe the characteristics of the device. In order to enter

the CFI Query mode, the system must write three-byte

sequence, same as product ID entry command with 98H

(CFI Query command) to address AAAH in the last byte

sequence. Once the de vice enters the CFI Query mode, the

system can read CFI data at the addresses given in Tables

7 through 9. The system must write the CFI Exit command

to return to Read mode from the CFI Query mode.

TABLE 2: BOOT BLOCK ADDRESS RANGES

Product Address Range

Bottom Boot Block

SST39VF1681 000000H-00FFFFH

Top Boot Block

SST39VF1682 1F0000H-1FFFFFH

T2.1 1243

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Product Identifica tion

The Produc t Identific ation mode identifies the devices as

the SST39VF1681 and SST39VF1682, and manufacturer

as SST. Users may use the software Product Identifica-

tion operation to identify the part (i.e., using the device ID)

when using multiple manufacturers in the same socket.

For details, se e Table 6 for software operation, Figure 11

for the software ID Entry and Read timing diagram, and

Figure 21 for the software ID Entry command sequence

flowchart.

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Produc t Ident ificati on mode must be exited. Exit is acco m-

plished by issuing the software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the software ID Exit/CFI

Exit command is ignored during an internal Program or

Erase operation. See Table 6 for software command

codes, Figur e 13 for timing wave form, an d Figu res 21 an d

22 for flowcharts.

Security ID

The SST39VF168x devices offer a 256-bit Security ID

space which is divided into two 128-bit segments. The first

segment is programmed and locked at SST with a random

128-bit number. The user segment is left un-programmed

f or the customer to pro gra m as desi red.

To program the user segment of the Security ID, the user

must use the Security ID Byte-Program command. To

detect end-of-write for the SEC ID, read the toggle bits. Do

not use Data# Polling. Once this is complete, the Sec ID

should be locked using the User Sec ID Program Lock-Out.

This dis ables any futur e c orrupti on of this sp ac e. Note tha t

regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Security ID space can be queried by executing a

three-byte command sequence with Enter-Sec-ID com-

mand (88H) at address AAAH in the last byte sequence.

Execute the Exit-Sec-ID command to exit this mode. Refer

to Table 6 for more details.

TABLE 3: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39VF1681 0001H C8H

SST39VF1682 0001H C9H

T3.1 1243

Y-Decoder

I/O Buffers and Data Latches

1243 B1.0

Address Buffer & Latches

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

WP#

RESET#

FUNCTIONAL BLOCK DIAGRAM

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TFBGA

FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP

1243 48-tfbga B3K P1.0

TOP VIEW (balls facing down)

A14

A10

WE#

A13

RST#

WP#

A18

A15

A11

A19

A16

A12

A20

A17

DQ7

DQ5

DQ2

DQ0

CE#

VDD

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

A B C D E F G H

A17

VSS

DQ7

DQ6

DQ5

DQ4

VDD

DQ3

DQ2

DQ1

DQ0

OE#

VSS

CE#

1243 48-tsop P2.0

Standard Pinout

To p View

Die Up

A16

A15

A14

A13

A12

A11

A10

A20

WE#

RST#

WP#

A19

A18

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

TABLE 4: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses.

During Sector-Eras e AMS-A12 address lines will select the sector.

During Bloc k- Er as e AMS-A16 address lines will select the block.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.

RST# Reset To reset and return the device to Read mod e .

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 2.7-3.6V

VSS Ground

NC No Connection Unconnected pins.

T4.1 1243

1. AMS = Most significant address

AMS = A20 for SST39VF1681/1682

TABLE 5: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Softw are Mode VIL VIL VIH See Table 6

T5.0 1243

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

TABLE 6: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th B us

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program AAAH AAH 555H 55H AAAH A0H BA2Data

Sector-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SAX350H

Block-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H BAX330H

Chip-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H

Erase-Suspend XXXXH B0H

Erase-Resume XXXXH 30H

Query Sec ID4AAAH AAH 555H 55H AAAH 88H

User Security ID

Byte-Program AAAH AAH 555H 55H AAAH A5H BA5Data

User Security ID

Program Lock-Out AAAH AAH 555H 55H AAAH 85H XXH500H

Software ID En tr y 6,7 AAAH AAH 555H 55H AAAH 90H

CFI Quer y Entry AAAH AAH 555H 55H AAAH 98H

Software ID Exit8,9

/CFI Exit/ Sec ID Ex it AAAH AAH 555H 55H AAAH F0H

Software ID Ex i t 8,9

/CFI Exit/ Sec ID Ex it XXH F0H

T6.1 1243

1. Address format A11-A0 (Hex).

Addresses A20-A12 can be VIL or VIH, b ut no other value, for Command sequence for SST39VF1681/1682.

2. BA = Program Byte Address

3. SAX for Sector-Erase; uses AMS-A12 address lines

BAX, for Block-Erase; uses AMS-A16 address lines

AMS = Most significant address

AMS = A20 for SST39VF1681/1682

4. With AMS-A5 = 0; Sec ID is read with A4-A0,

SST ID is read with A4 = 0 (Address range = 00000H to 0000FH),

User ID is read with A4 = 1 (Address range = 00010H to 0001FH).

Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

5. Valid Byte Addresses for Sec ID are from 000000H-00000FH and 000020H-00002FH.

6. The device does not remain in Software Product ID Mode if powered down.

7. With AMS-A1 =0; SST Manuf acturer ID = 00BFH, is read with A0 = 0,

SST39VF1681 Device ID = C8H, is read with A0 = 1,

SST39VF1682 Device ID = C9H, is read with A0 = 1,

AMS = Most significant address

AMS = A20 for SST39VF1681/1682

8. Both Software ID Exit operations are equivalent

9. If users nev er loc k after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID

mode again (the programmed “0” bits cannot be reversed to “1”).

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

TABLE 7: CFI QUERY IDENTIFICATION STRING1

Address Data Data

10H 51H Query Unique ASCII string “QRY”

11H 52H

12H 59H

13H 01H Primary OEM command set

14H 07H

15H 00H Address for Primary Extended Table

16H 00H

17H 00H Alternate OEM command set (00H = none exists)

18H 00H

19H 00H Address for Alternate OEM extended Table (00H = none exits)

1AH 00H T7.1 1243

1. Refer to CFI publication 100 for more details.

TABLE 8: SYSTEM INTERFACE INFORMATION

Address Data Data

1BH 27H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 36H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 00H VPP min. (00H = no VPP pin)

1EH 00H VPP max. (00H = no VPP pin)

1FH 03H Typical time out for Byte-Prog r a m 2N µs (23 = 8 µs)

20H 00H Typical time out for min. size buffer program 2N µs (00H = not supported)

21H 04H Typical time out for individu al Sec tor/Bl ock-Erase 2N ms (24 = 16 ms)

22H 05H Typic al time out for Chip-Er ase 2N ms (25 = 32 ms)

23H 01H Maximum time out for Byte-Program 2N times typical (21 x 23 = 16 µs)

24H 00H Maximum time out for buffer program 2N times typical

25H 01H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H 01H Maximum time out for Chip-Erase 2N times typ ical (21 x 25 = 64 ms)

T8.1 1243

TABLE 9: DEVICE GEOMETRY INFORMATION

Address Data Data

27H 15H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)

28H 00H Flash Device Interface description; 00H = x8-only asynchronous interface

29H 00H

2AH 00H Maximum number of byte in multi-byte write = 2N (00H = not s upported)

2BH 00H

2CH 02H Number of Erase Sector/Block sizes supported by device

2DH FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 01H y = 511 + 1 = 512 sectors (01FF = 511

2FH 10H

30H 00H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 1FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 00H y = 31 + 1 = 32 blocks (1F = 31)

33H 00H

34H 01H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T9.1 1243

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shor ted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial

Industrial 0°C to +70°C

-40°C to +85°C 2.7-3.6V

2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 17 and 18

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address i nput =VILT/VIHT2, at f=5 MHz,

VDD=VDD Max

Read318 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 35 mA CE#=WE#=VIL, OE# =VIH

ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max

IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max

All inputs=VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST# 10 µA WP#=GND to VDD or RST#=GND to VDD

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T10.8 1243

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 3V. Not 100% tested.

2. See Figure 17

3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.

TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T11.0 1243

TABLE 12: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T12.0 1243

TABLE 13: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD m A JEDEC Standard 78

T13.2 1243

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

AC CHARACTERISTICS

TABLE 14: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

Symbol Parameter

SST39VF168x-70 SST39VF168x-90

UnitsMin Max Min Max

TRC Read Cycle Time 70 90 ns

TCE Chip Enable Access Time 70 90 ns

TAA Address Access Time 70 90 ns

TOE Output Enable Access Time 35 45 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 20 30 ns

TOHZ1OE# High to High-Z Output 20 30 ns

TOH1Output Hold from Address Change 0 0 ns

TRP1RST# Pulse Width 500 500 ns

TRHR1RST# High before Read 50 50 ns

TRY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Re ad Mod e 20 20 µs

T14.1 1243

TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Byte-Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hol d Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse W idth 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pu lse Width H igh 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

T15.0 1243

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 3: READ CYCLE TIMING DIAGRAM

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

1243 F02.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most Significant Address

AMS = A20 for SST39VF168x

1243 F03.0

ADDRESS AMS-0

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

AAA AAA555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most Significant Address

AMS = A20 f or SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 6: DATA# POLLING T IMING DIAGRAM

1243 F04.0

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

AAA AAA555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

1243 F05.0

ADDRESS AMS-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most Significant Address

AMS = A20 for SST39VF168x

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 7: TOGGLE BITS TIMING DIAGRAM

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

1243 F06.0

ADDRESS AMS-0

DQ6 and DQ2

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most Significant Address

AMS = A20 for SST39VF168x

1243 F07.0

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

AAA AAA AAA555 AAA

55 1055AA 80 AA

555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or V IH, but no other value.

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

1243 F08.0

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

55 3055AA 80 AA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

AAA AAA555 AAA 555

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

BAX = Block Address

AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or V IH, but no other value.

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

1243 F9.0

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

55 5055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

AAA AAA555 AAA 555

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

SAX = Sector Address

AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 11: SOFTWARE ID ENTRY AND READ

FIGU R E 12: CFI Q UERY ENTRY AND READ

1243 F10.1

ADDRESS AMS-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

AAA AAA555 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

Device ID

55AA 90

Note: Devi ce ID - See Table 3 on page 5

AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, b ut no other value .

1243 F11.1

ADDRESS AMS-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

555 AAAAAA

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

55AA 98

Note: AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, b ut no other value .

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

FIGURE 14: SEC ID ENTRY

1243 F12.1

ADDRESS AMS-0

DQ7-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

AAA AAA555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

Note: AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, b ut no other value .

1243 F13.0

ADDRESS AMS-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

AAA AAA555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

55AA 88

Note: AMS = Most Significant Address

AMS = A20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

1243 F14.0

RST#

CE#/OE#

TRP

TRHR

1243 F15.0

RST#

CE#/OE#

TRP

TRY

End-of-Write Detection

(Toggle-Bit)

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 17: AC I NPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 18: A TEST LOAD EXAMPLE

1243 F16.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

A C test inputs are driven at VIHT (0.9 VDD) f or a logic “1” and VILT (0.1 VDD) f o r a logic “0 ”. Measu rement ref e rence point s

f or inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1243 F17.0

TO TESTER

TO DUT

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 19: BYTE-PROGRAM ALGORITHM

1243 F18.0

Start

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: A0H

Address: AAAH

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

X can be VIL or VIH, but no other value

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 20: WAIT OPTIONS

1243 F19.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS

1243 F20.0

Load data: AAH

Address: AAAH

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 555H

Load data: 90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: AAH

Address: AAAH

CFI Query Entry

Command Sequence

Load data: 55H

Address: 555H

Load data: 98H

Address: AAAH

Wait TIDA

Read CFI data

Load data: AAH

Address: AAAH

Sec ID Query Entry

Command Sequence

Load data: 55H

Address: 555H

Load data: 88H

Address: AAAH

Wait TIDA

Read Sec ID

X can be VIL or VIH, but no other value

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS

1243 F21.0

Load data: AAH

Address: AAAH

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: 55H

Address: 555H

Load data: F0H

Address: AAAH

Load data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

X can be V

or V

IH,

but no other value

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

FIGURE 23: ERASE COMMAND SEQUENCE

1243 F22.0

Load data: AAH

Address: AAAH

Chip-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 10H

Address: AAAH

Load data: AAH

Address: AAAH

Wait TSCE

Chip erased

to FFFFH

Load data: AAH

Address: AAAH

Sector-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 50H

Address: SAX

Load data: AAH

Address: AAAH

Wait TSE

Sector erased

to FFFFH

Load data: AAH

Address: AAAH

Block-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 30H

Address: BAX

Load data: AAH

Address: AAAH

Wait TBE

Block erased

to FFFFH

X can be VIL or VIH, but no other value

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

PRODUCT ORDERING INFORMATION

Valid Combinations for SST39VF1681

SST39VF1681-70-4C-EK SST39VF1681-70-4C-B3K

SST39VF1681-70-4C-EKE SST39VF1681-70-4C-B3KE

SST39VF1681-70-4I-EK SST39VF1681-70-4I-B3K

SST39VF1681-70-4I-EKE SST39VF1681-70-4I-B3KE

SST39VF1681-90-4I-EK

SST39VF1681-90-4I-EKE

Valid Combinations for SST39VF1682

SST39VF1682-70-4C-EK SST39VF1682-70-4C-B3K

SST39VF1682-70-4C-EKE SST39VF1682-70-4C-B3KE

SST39VF1682-70-4I-EK SST39VF1682-70-4I-B3K

SST39VF1682-70-4I-EKE SST39VF1682-70-4I-B3KE

SST39VF1682-90-4I-EK

SST39VF1682-90-4I-EKE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Envi ronmental Attribute

E = non-Pb

Package Modifier

K = 48 leads

Package Type

B3 = TFBGA (6mm x 8mm, 0.8mm pitch)

E = TSOP (type1, die up, 12mm x 20mm)

Temperat ure Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

90 = 90 ns

Hardware Bloc k Protection

1 = Bottom Boot-Block

2 = Top Boot-Block

Device Density

168 = 16 Mbit

Voltage

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

SST 39 VF 1681 - 70 - 4C - B3K E

XX XXXXXX -XXX -XX-XXX X

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

PACKAGING DIAGRAMS

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM

SST PACKAGE CODE: EK

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0˚- 5˚

DETAIL

Pin # 1 Identifier

0.50

BSC

Preliminary Specifications

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM

SST PACKAGE CODE: B3K

TABLE 16: REVISION HISTORY

Number Description Date

00 •Initial release May 2003

01 •Change product number from 166x to 168x Sep 2003

02 •Added B3K package and associated MPNs (See page 27)

•Removed 90 ns Commercial temperature for the EK and EKE packages Oct 2003

03 •2004 Data Book

•Updated B3K package diagram Nov 2003

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

Silicon Stor age Technol ogy, Inc. • 1171 Sonora Court • Sunn yvale, CA 94086 • Telephone 408-73 5-91 10 • Fax 408-735-9036