PLL Frequency Synthesizer
Enhanced Product
ADF4106-EP
FEATURES
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Support defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios
GENERAL DESCRIPTION
The ADF4106-EP frequency synthesizer can be used to
implement local oscillators in the up-conversion and down-
conversion sections of wireless receivers and transmitters. It
consists of a low noise, digital phase frequency detector (PFD),
a precision charge pump, a programmable reference divider,
programmable A counter and B counter, and a dual-modulus
prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in
conjunction with the dual-modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REFIN frequencies at the
PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.
Additional application and technical information can be found
in the ADF4106 data sheet.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
REF
IN
RF
IN
A
RF
IN
B
24-BI T INP UT
REGISTER
SD
OUT
AV
DD
DV
DD
CE AGND DGND
14-BIT
R COUNT E R
R COUNT E R
LATCH
22
14
FUNCTION
LATCH
A, B CO UNTER
LATCH
FROM
FUNCTION
LATCH
PRESCALER
P/P + 1
N = BP + A
LOAD
LOAD
13-BIT
B COUNT E R
6-BIT
A COUNT E R
6
19
13
M3 M2 M1
MUX
SD
OUT
AV
DD
HIG H Z
MUXOUT
CPGND R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF4106-EP
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
CURRENT
SETTING 2
09272-001
Figure 1.
Rev. C Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADF4106-EP Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characterisitics ............................................................... 4
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configurations and Function Descriptions ............................6
Typical Performance Characteristics ..............................................7
PCB Design Guidelines for Chip Scale Package............................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
11/14—Rev. B to Rev. C
Change to Table 1 ............................................................................. 3
Change to Table 2 ............................................................................. 4
Changes to Table 3 ............................................................................ 5
8/12—Rev. A to Rev. B
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 10
Changes to Ordering Guide .......................................................... 10
11/10—Rev. 0 to Rev. A
Changes to Figure 6 .......................................................................... 7
Changes to Figure 11 ........................................................................ 8
Changes to Ordering Guide .......................................................... 10
8/10—Revision 0: Initial Version
Rev. C | Page 2 of 10
Enhanced Product ADF4106-EP
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 1.
Parameter S Version1 Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN) 0.5/6.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/µs
RF Input Sensitivity −10/0 dBm min/max
Maximum Allowable Prescaler Output Frequency2 300 MHz max P = 8
325 MHz P = 16
REFIN CHARACTERISTICS
REFIN Input Frequency 20/300 MHz min/max For f < 20 MHz, ensure SR > 50 V/µs
REFIN Input Sensitivity3 0.8/VDD V p-p min/max Biased at AVDD/24
REFIN Input Capacitance 10 pF max
REFIN Input Current ±100 µA max
PHASE DETECTOR
Phase Detector Frequency
5
104
MHz max
ABP = 0, 0 (2.9 ns antibacklash pulse width)
CHARGE PUMP
ICP Sink/Source
High Value 5 mA typ With RSET = 5.1 kΩ
Low Value 625 µA typ
Absolute Accuracy 2.5 % typ With RSET = 5.1 kΩ
RSET Range 3.0/11 kΩ typ
ICP Three-State Leakage 2 nA max 1 nA typical; TA = 25°C
Sink and Source Current Matching 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. VCP 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 % typ VCP = VP/2
LOGIC INPUTS
VIH, Input High Voltage 1.4 V min
VIL, Input Low Voltage 0.6 V max
IINH, IINL, Input Current ±1 µA max
CIN, Input Capacitance 10 pF max
LOGIC OUTPUTS
VOH, Output High Voltage 1.4 V min Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
VDD − 0.4 V min CMOS output chosen
IOH 100 µA max
VOL, Output Low Voltage 0.4 V max IOL = 500 µA
POWER SUPPLIES
AVDD 2.7/3.3 V min/V max
DVDD AVDD
VP AVDD/5.5 V min/V max AVDD ≤ VP ≤ 5.5 V
IDD6 (AIDD + DIDD) 11 mA max 9.0 mA typical
IDD7 (AIDD + DIDD) 11.5 mA max 9.5 mA typical
I
DD8
(AI
DD
+ DI
DD
)
13
mA max
10.5 mA typical
I
P
0.4
mA max
T
A
= 25°C
Power-Down Mode9 (AIDD + DIDD) 10 µA typ
Rev. C | Page 3 of 10
ADF4106-EP Enhanced Product
Parameter S Version1 Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH)10 −223 dBc/Hz typ PLL loop BW = 500 kHz
Normalized 1/f Noise (PN1_f)11 −122 dBc/Hz typ Measured at 10 kHz offset; normalized to 1 GHz
Phase Noise Performance12 VCO output
900 MHz
13
−92.5
dBc/Hz typ
1 kHz offset and 200 kHz PFD frequency
5800 MHz14 −76.5 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
5800 MHz15 −83.5 dBc/Hz typ 1 kHz offset and 1 MHz PFD frequency
Spurious Signals
900 MHz13 −90/−92 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz14 −65/−70 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz15 −70/−75 dBc typ 1 MHz/2 MHz and 1 MHz PFD frequency
1 Operating temperature range is −55°C to +125°C.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AVDD = DVDD = 3 V.
4 AC coupling ensures AVDD/2 bias.
5 Guaranteed by design. Sample tested to ensure compliance.
6 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.
7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.
8 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.
9 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.
10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
11 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a
frequency offset, f, is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
12 The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.
14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 29,000; loop B/W = 20 kHz.
15 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 5800; loop B/W = 100 kHz.
TIMING CHARACTERISITICS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 2.
Parameter Limit1 (B Version) Unit Test Conditions/Comments
t1 10 ns min DATA to CLOCK Setup Time
t
2
10
ns min
DATA to CLOCK Hold Time
t3 25 ns min CLOCK High Duration
t4 25 ns min CLOCK Low Duration
t5 10 ns min CLOCK to LE Setup Time
t6 20 ns min LE Pulse Width
1 Operating temperature range (S Version) is –55°C to +125°C.
Timing Diagram
CLOCK
DB22 DB2
DATA
LE
t1
LE
DB23 (MS B)
t2
DB1 (CO NTROL
BIT C2) DB0 (L S B)
(CO NTROL BI T C1)
t3t4
t6
t5
09272-002
Figure 2. Timing Diagram
Rev. C | Page 4 of 10
Enhanced Product ADF4106-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to GND1 −0.3 V to + 3.6 V
AVDD to DVDD −0.3 V to + 0.3 V
VP to GND −0.3 V to + 5.8 V
VP to AVDD −0.3 V to + 5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REF
IN
, RF
IN
A, RF
IN
B to GND
−0.3 V to V
DD
+ 0.3 V
RFINA to RFINB ±320 mV
Operating Temperature Range
Industrial (S Version) −55°C to +125°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
θJA Thermal Impedance
16-Lead TSSOP 112°C/W
20-Lead LFCSP (Paddle Soldered) 30.4°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Transistor Count
CMOS 6425
Bipolar 303
1GND = AGND = DGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. C | Page 5 of 10
ADF4106-EP Enhanced Product
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
R
SET
CP
CPGND
AGND
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
AV
DD
REF
IN
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
V
P
DV
DD
TOP VIEW
(No t t o Scal e)
ADF4106-EP
NOTES:
1. T RANS ISTO R COUNT 6425 ( CM OS),
303 (BI POL AR) .
09272-003
Figure 3. 16-Lead TSSOP Pin Configuration
15 MUXO UT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20 CP
11 CE
6
7
8
DGND 9
DGND 10
19
18
17
16
RF
IN
B 4
RF
IN
A 5
R
SET
V
P
DV
DD
DV
DD
PIN 1
INDICATOR
TOP VIEW
(No t t o Scal e)
ADF4106-EP
AV
DD
AV
DD
REF
IN
NOTES
1. T RANS ISTO R COUNT 6425 ( CM OS),
303 (BI POL AR) .
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
09272-004
Figure 4. 20-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
Pin No.
LFCSP Mnemonic Description
1 19 RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAXCP R
I5.25
=
So, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
2 20 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives
the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF.
6 5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7 6, 7 AVDD Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device, depending on the status of the power-
down bit, F2.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input
is a high impedance CMOS input.
13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches with the latch being selected using the control bits.
14 15 MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
15 16, 17 DVDD Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16 18 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP Exposed Pad. The exposed pad must be connected to AGND.
Rev. C | Page 6 of 10
Enhanced Product ADF4106-EP
TYPICAL PERFORMANCE CHARACTERISTICS
FREQ MAGS11 ANGS11
0.500 0.89148 –17.2820
0.600 0.88133 – 20.6919
0.700 0.87152 – 24.5386
0.800 0.85855 –27.3228
0.900 0.84911 –31.0698
1.000 0.83512 – 34.8623
1.100 0.82374 –38.5574
1.200 0.80871 –41.9093
1.300 0.79176 – 45.6990
1.400 0.77205 –49.4185
1.500 0.75696 –52.8898
1.600 0.74234 –56.2923
1.700 0.72239 –60.2584
1.800 0.69419 –63.1446
1.900 0.67288 –65.6464
2.000 0.66227 –68.0742
2.100 0.64758 –71.3530
2.200 0.62454 –75.5658
2.300 0.59466 –79.6404
2.400 0.55932 –82.8246
2.500 0.52256 –85.2795
2.600 0.48754 –85.6298
2.700 0.46411 –86.1854
2.800 0.45776 –86.4997
2.900 0.44859 –88.8080
3.000 0.44588 –91.9737
3.100 0.43810 –95.4087
3.200 0.43269 –99.1282
FREQ MAGS11 ANGS11
3.300 0.42777 –102.748
3.400 0.42859 –107.167
3.500 0.43365 –111.883
3.600 0.43849 –117.548
3.700 0.44475 –123.856
3.800 0.44800 –130.399
3.900 0.45223 –136.744
4.000 0.45555 –142.766
4.100 0.45313 –149.269
4.200 0.45622 –154.884
4.300 0.45555 –159.680
4.400 0.46108 –164.916
4.500 0.45325 –168.452
4.600 0.45054 –173.462
4.700 0.45200 –176.697
4.800 0.45043 178.824
4.900 0.45282 174.947
5.000 0.44287 170.237
5.100 0.44909 166.617
5.200 0.44294 162.786
5.300 0.44558 158.766
5.400 0.45417 153.195
5.500 0.46038 147.721
5.600 0.47128 139.760
5.700 0.47439 132.657
5.800 0.48604 125.782
5.900 0.50637 121.110
6.000 0.52172 115.400
FREQ UNI T GHz KEYWORD R
PARAM TYPE SIMPEDANCE 50Ω
DATA FORM AT MA
09272-005
Figure 5. S-Parameter Data for the RF Input
–40
–35
–30
–25
–20
–15
–10
–5
0
5
0 1 2 3
4 5 6 7 8 9 10
LEVEL (dBm)
FREQUENCY (GHz)
–55°C
+25°C
+125°C
09272-018
Figure 6. Input Sensitivity
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
–2kHz –1kHz 900MHz 1kHz 2kHz
FREQUENCY
OUTPUT POWER (dB)
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 200kHz
LO OP BANDWI DTH = 20kHz
RES BANDW IDT H = 10Hz
VIDE O BANDW IDT H = 10Hz
SWEEP = 1.9 SECONDS
AVERAG E S = 10
–93.0dBc/Hz
REF LEV E L = –14.3dBm
09272-007
Figure 7. Phase Noise (900 MHz, 200 kHz, and 20 kHz)
–40
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
100Hz 1MHz
FREQUENCY OF FSET F ROM 900M Hz CARRIER
OUTPUT POWER (dB)
10dB/DIV
R
L
= –40dBc/Hz
RMS NO ISE = 0.36°
09272-008
Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, and 20 kHz)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
–400kHz –200kHz 900MHz 200kHz 400kHz
FREQUENCY
OUTPUT POWER (dB)
REF LEV E L = –14.0dBm V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 200kHz
LO OP BANDWI DTH = 20kHz
RES BANDW IDT H = 1kHz
VIDE O BANDW IDT H = 1kHz
SWEEP = 2.5 SECONDS
AVERAG E S = 30
–91.0dBc/Hz
09272-009
Figure 9. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)
–83.5dBc/Hz
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
–2kHz –1kHz 5800MHz 1kHz 2kHz
FREQUENCY
OUTPUT POWER (dB)
REF LEV E L = –10dBm V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 1M Hz
LO OP BANDWI DTH = 100kHz
RES BANDW IDT H = 10Hz
VIDE O BANDW IDT H = 10Hz
SWEEP = 1.9 SECONDS
AVERAG E S = 10
09272-010
Figure 10. Phase Noise (5.8 GHz,1 MHz, and 100 kHz)
Rev. C | Page 7 of 10
ADF4106-EP Enhanced Product
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
1k 10k 100k 1M 10M 100M
LEVEL (dBm)
FREQUENCY OFF SET (Hz)
–55°C
+25°C
+125°C
09272-017
Figure 11. Integrated Phase Noise (5.8 GHz,1 MHz, and 100 kHz)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
–2M –1M 5800 1M 2M
FREQUENCY ( Hz )
OUTPUT POWER (dB)
REF LEV E L = –10dBm
–65.0dBc
–66.0dBc
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 1M Hz
LO OP BANDWI DTH = 100kHz
RES BANDW IDT H = 1kHz
VIDE O BANDW IDT H = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
09272-012
Figure 12. Reference Spurs (5.8 GHz,1 MHz, and 100 kHz)
–60
–100
–90
–80
–70
100–40 –20 020 40 60 80
TEMPERATURE (°C)
PHASE NOISE (dBc/Hz)
VDD = 3V
VP = 3V
09272-013
Figure 13. Phase Noise (5.8 GHz,1 MHz, and 100 kHz) vs. Temperature
–5
–105
–95
–85
–75
–65
–55
–45
–35
–25
–15
501234
TUNNING VOLTAGE (V)
FI RS T REFERE NCE S P UR ( dBc)
V
DD
= 3V
V
P
= 5V
09272-014
Figure 14. Reference Spurs vs. VTUNE (5.8 GHz,1 MHz, and 100 kHz)
–120
–180
–170
–160
–150
–140
–130
100M10k 100k 1M 10M
PHASE DE TECTO R FREQ UE NCY ( Hz )
PHASE NOISE (dBc/Hz)
VDD = 3V
VP = 5V
09272-015
Figure 15. Phase Noise (Referred to CP Output) vs. PFD Frequency
–6
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
5.000.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
CP
(V)
I
CP
(mA)
V
PP
= 5V
I
CP
SETTLING = 5mA
09272-016
Figure 16. Charge Pump Output Characteristics
Rev. C | Page 8 of 10
Enhanced Product ADF4106-EP
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the 20-lead LFCSP (CP-20) are rectangular. The
printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized. The
bottom of the LFCSP has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias may be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 oz. copper to plug the via.
The user should connect the PCB thermal pad to AGND.
Rev. C | Page 9 of 10
ADF4106-EP Enhanced Product
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM PLI ANT T O JEDE C S TANDARDS MO-153- AB
Figure 17. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
3.75
BCS SQ
COMPLIANT
TO
JEDEC STANDARDS M O-220- V GG D- 1
1
0.50
BSC
PIN 1
INDICATOR
0.75
0.60
0.50
TOP VIEW
12° M AX 0. 80 M AX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 M AX
0.02 NO M
0.20 REF
2.25
2.10 SQ
1.95
20
6
16
10
11
15
5
0.60 M AX
0.60 M AX
0.25 M IN
FOR PRO P E R CONNECTI O N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
04-09-2012-B
BOTTOM VIEW
EXPOSED
PAD
4.10
4.00 SQ
3.90
Figure 18. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADF4106SRU-EP −55°C to + 125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4106SRU-EP-R7 −55°C to + 125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4106SCPZ-EP −55°C to + 125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
ADF4106SCPZ-EP-R7 −55°C to + 125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
1 Z = RoHS Compliant Part.
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D09272-0-11/14(C)
Rev. C | Page 10 of 10
