[AK5720] AK5720 96kHz 24-Bit ADC 1. General Description The AK5720 is a low voltage 24-bit A/D converter for digital audio systems. The AK5720 includes an Input Gain Amplifier, making it suitable for microphone applications. The analog signal input of the AK5720 is single-ended, eliminating the need for external filters. The AK5720 is housed in a space-saving 16-pin TSSOP package. 2. Features 1. Resolution: 24bits 2. Recording Functions Gain Amplifier (0dB / +15dB) Digital HPF for DC-offset cancellation (fc=1.0Hz@fs=48kHz) 3. ADC Characteristics Single-ended Input Input Level: 1.8Vpp@VA=3.0V (= 0.6 x VA), 3.0Vpp@VA=5.0V (=0.6 x VA) S/(N+D): 94dB DR, S/N: 102dB 4. Master Clock: 256fs/384fs/512fs/768fs 5. Sampling Frequency: 8kHz 96kHz 6. Audio Data Format: MSB First, 2's compliment 24-bit MSB justified, I2S and TDM 7. Power Supply VA, VD: 2.7 5.5V (typ. 3V, 5V) 8. Power Supply Current: 6.1mA(VA-VD=5.0V,fs=48kHz) 9. Operating Temperature: Ta = -40 105C 10. Package: 16-pin TSSOP GSEL DIF/TDMI LIN ADC IIIS/TDM Out HPF LRCK BICK SDTO RIN VD VCOM PDN VA REGO Clock Divider Regulator VSS FSEL MS1641-E-02 CKS MCLK 2014/12 -1- [AK5720] 3. Table of Contents 1. 2. 3. 4. General Description ....................................................................................................................................1 Features .......................................................................................................................................................1 Table of Contents........................................................................................................................................2 Pin Configurations and Functions ..............................................................................................................3 Ordering Guide ..........................................................................................................................................3 Pin Layout .................................................................................................................................................3 Functions ...................................................................................................................................................4 Handling of Unused Pin ............................................................................................................................4 5. Absolute Maximum Ratings .......................................................................................................................5 6. Recommended Operating Conditions .........................................................................................................5 7. Analog Characteristics (VA=VD=5.0V) ....................................................................................................6 8. Analog Characteristics (VA=VD=3.0V) ....................................................................................................7 9. Filter Characteristics (fs=48kHz) ...............................................................................................................8 10. Filter Characteristics (fs=96kHz) ...........................................................................................................9 11. DC Characteristics ..................................................................................................................................9 12. Switching Characteristics .....................................................................................................................10 Timing Diagram ......................................................................................................................................12 13. Functional Descriptions ........................................................................................................................16 System Clock ...........................................................................................................................................16 Audio Interface Format ...........................................................................................................................16 Digital High Pass Filter ...........................................................................................................................18 Power Down ............................................................................................................................................18 System Reset ...........................................................................................................................................19 TDM Cascade Mode ...............................................................................................................................19 14. Recommended External Circuits ..........................................................................................................21 15. Package .................................................................................................................................................23 Outline Dimensions .................................................................................................................................23 Material & Lead Finish ...........................................................................................................................23 Marking ...................................................................................................................................................24 16. Revision History ...................................................................................................................................24 IMPORTANT NOTICE ................................................................................................................................25 MS1641-E-02 2014/12 -2- [AK5720] 4. Pin Configurations and Functions Ordering Guide AK5720 AKD5720 40 +105C 16-pin TSSOP (0.65mm pitch) Evaluation Board for AK5720 Pin Layout VCOM 1 16 CKS RIN 2 15 FSEL LIN 3 14 DIF/TDMI VSS 4 13 PDN VA 5 12 BICK VD 6 11 MCLK GSEL 7 10 LRCK REGO 8 9 SDTO Top View MS1641-E-02 2014/12 -3- [AK5720] Functions No. Pin Name I/O Power Down Status Pull-down to VSS with NMOS (0.5k) Hi-z Hi-z - Function 1 VCOM O ADC Common Voltage Output Pin 2 3 4 5 6 RIN LIN VSS VA VD I I - 7 GSEL I Rch Input Pin Lch Input Pin Ground Pin Analog Power Supply Pin Digital Power Supply Pin Input Gain Select Pin "L": 0dB, "H": +15dB 8 REGO O 9 10 11 12 SDTO LRCK MCLK BICK O I/O I I/O Hi-z Pull-down to VSS with 500 "L" (VSS) Hi-z Hi-z Hi-z Regulator Output Pin Audio Serial Data Output Pin Input/Output Channel Clock Pin Master Clock Input Pin Audio Serial Data Clock Pin Reset & Power Down Pin 13 PDN I Hi-z "L": Reset & Power down, "H" : Normal operation Audio Data Format Select Pin Hi-z "L": MSB justified, "H": I2S 14 DIF/TDMI I TDM Data Input Pin Hi-z Digital Filter select Pin 15 FSEL I Hi-z "L": Sharp Roll-Off, "H": Short Delay Sharp Roll-Off Mode Select Pin 16 CKS I Hi-z Parasitic capacitance of the pin should be less than 20pF. Note: All digital input pins must not be allowed to float. Note: The GSEL pin must be fixed to "H" or "L" when the PDN pin = "H" to avoid starting the test mode. Handling of Unused Pin Unused I/O pins must be connected appropriately. Classification Analog Pin Name RIN, LIN Setting This pin should be open. MS1641-E-02 2014/12 -4- [AK5720] 5. Absolute Maximum Ratings (VSS=0V; Note 1) Parameter Power Supplies: Analog Digital Input Current, Any Pin Except Supplies Analog Input Voltage (LIN, RIN pins) Digital Input Voltage Ambient Temperature Storage Temperature Note 1. All voltages with respect to ground. Symbol VA VD IIN VINA VIND Ta Tstg min 0.3 0.3 0.3 0.3 40 65 max 6.0 6.0 10 VA+0.3 VD+0.3 105 150 Unit V V mA V V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. The AK5720 will be damaged if a voltage higher than 2.5V is input to the REGO pin. 6. Recommended Operating Conditions (VSS=0V; Note 1) Parameter Power Supplies Analog (VA pin) Digital (VD pin) Note 1. All voltages with respect to ground. Symbol VA VD min 2.7 2.7 typ 3 or 5 3 or 5 max 5.5 VA Unit V V WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1641-E-02 2014/12 -5- [AK5720] 7. Analog Characteristics (VA=VD=5.0V) (Ta=25C; VA=VD=5.0V; fs=48kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz 20kHz at fs=48kHz, 40Hz 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Unit ADC Analog Input Characteristics: Resolution 24 Bits 2.7 3.0 3.3 Gain = 0dB Input Voltage Vpp (Note 2) 0.48 0.53 0.58 Gain = +15dB VA=5V fs=48kHz, 84 94 dB S/(N+D) fs=96kHz 92 dB Gain = 0dB (-1.0dBFS) VA=5V fs=48kHz 74 84 dB fs=96kHz 80 dB Gain = +15dB VA=5V fs=48kHz, A-weighted 94 102 dB DR fs=96kHz 99 dB Gain = 0dB (-60dBFS) VA=5V fs=48kHz, A-weighted 83 91 dB fs=96kHz 86 dB Gain = +15dB fs=48kHz, A-weighted 94 102 dB VA=5V S/N fs=96kHz 99 dB Gain = 0dB fs=48kHz, A-weighted 83 91 dB VA=5V fs=96kHz 86 dB Gain = +15dB fs=48kHz 29 41 k Gain = 0dB fs=96kHz 28 k Input Resistance fs=48kHz 15 22 k Gain = +15dB fs=96kHz 13 k Gain = 0dB 90 110 dB Interchannel Isolation (RIN, LIN) Gain = +15dB 90 dB Interchannel Gain Mismatch (RIN, LIN) 0 0.5 dB Gain Drift 100 ppm/C Power Supply Rejection (Note 3) 50 dB Power Supplies Power Supply Current Normal Operation (PDN pin = "H") VA 3.8 5.7 mA VD (fs=48kHz) 2.3 3.5 mA VD (fs=96kHz) 4.4 6.7 mA Power down mode (PDN pin = "L") (Note 4) VA+VD 10 100 A Note 2. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage. Vin = 0.6 x VA (Vpp). Note 3. PSR is applied to VA and VD with 1kHz, 50mVpp. Note 4. All digital input pins and CKS1 pin are held VD or VSS. MS1641-E-02 2014/12 -6- [AK5720] 8. Analog Characteristics (VA=VD=3.0V) (Ta=25C; VA=VD=5.0V; fs=48kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz 20kHz at fs=48kHz, 40Hz 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Unit ADC Analog Input Characteristics: Resolution 24 Bits 1.65 1.8 1.95 Gain = 0dB Input Voltage Vpp (Note 2) 0.29 0.32 0.35 Gain = +15dB VA=3V fs=48kHz, 84 94 dB S/(N+D) fs=96kHz 92 dB Gain = 0dB (-1.0dBFS) VA=3V fs=48kHz 71 81 dB fs=96kHz 77 dB Gain = +15dB VA=3V fs=48kHz, A-weighted 90 98 dB fs=96kHz 95 dB Gain = 0dB DR (-60dBFS) VA=3V fs=48kHz, A-weighted 86 dB 81 dB Gain = +15dB fs=96kHz fs=48kHz, A-weighted 90 98 dB VA=3V S/N fs=96kHz 95 dB Gain = 0dB fs=48kHz, A-weighted 86 dB VA=3V fs=96kHz 81 dB Gain = +15dB fs=48kHz 29 41 k Gain = 0dB fs=96kHz 28 k Input Resistance fs=48kHz 15 22 k Gain = +15dB fs=96kHz 13 k Gain = 0dB 90 110 dB Interchannel Isolation Gain = +15dB 90 dB Interchannel Gain Mismatch 0 0.5 dB Gain Drift 100 ppm/C Power Supply Rejection (Note 3) 50 dB Power Supplies Power Supply Current Normal Operation (PDN pin = "H") VA 3.4 5.1 mA VD (fs=48kHz) 1.9 2.9 mA VD (fs=96kHz) 3.7 5.6 mA Power down mode (PDN pin = "L") (Note 4) VA+VD 10 100 A Note 2. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage. Vin = 0.6 x VA (Vpp). Note 3. PSR is applied to VA and VD with 1kHz, 50mVpp. Note 4. All digital input pins and CKS1 pin are held VD or VSS. MS1641-E-02 2014/12 -7- [AK5720] 9. Filter Characteristics (fs=48kHz) (Ta=25C; VA=VD=2.7 5.5V, fs=48kHz) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): SHARP ROLL-OFF(FSEL pin="L") Passband (Note 5) 0.16dB PB 0 - max Unit 18.8 kHz 0.28dB 3.0dB kHz 20.0 kHz 22.8 Stopband (Note 5) SB 28.4 kHz Stopband Attenuation SA 71 dB Group Delay Distortion 0 ~ 20.0kHz 0 1/fs GD Group Delay (Note 6) GD 1/fs 15.5 ADC Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER(FSEL pin="H") Passband (Note 5) 0.16dB PB 0 18.8 kHz 20.0 kHz 0.28dB 22.8 kHz 3.0dB Stopband (Note 5) SB 28.4 kHz Stopband Attenuation SA 72 dB Group Delay Distortion 0 ~ 20.0kHz 2.4 1/fs GD Group Delay (Note 6) GD 1/fs 5.5 ADC Digital Filter (HPF): Frequency Response FR 1.0 Hz 3.0dB 2.5 Hz 0.5dB (Note 5) 6.5 Hz 0.1dB Note 5. The passband and stopband frequencies scale with fs. For example, PB=0.45 x fs(@0.1dB). Note 6. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the output register. MS1641-E-02 2014/12 -8- [AK5720] 10. Filter Characteristics (fs=96kHz) (Ta=25C; VA=VD=2.7 5.5V; fs=96kHz) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): SHARP ROLL-OFF(FSEL pin="L") Passband (Note 5) 0.16dB PB 0 kHz 37.6 kHz 40.0 0.28dB kHz 45.6 3.0dB Stopband (Note 5) SB 56.8 kHz Stopband Attenuation SA 71 dB Group Delay Distortion 0 ~ 20.0kHz 0 1/fs GD Group Delay (Note 6) GD 1/fs 15.5 ADC Digital Filter (Decimation LPF): SHORT DELAY SHARP ROLL-OFF FILTER(FSEL pin="H") Passband (Note 5) 0.16dB PB 0 37.6 kHz 40.0 kHz 0.28dB 45.6 kHz 3.0dB Stopband (Note 5) SB 56.8 kHz Stopband Attenuation SA 72 dB Group Delay Distortion 0 ~ 20.0kHz 2.4 1/fs GD Group Delay (Note 6) GD 1/fs 5.5 ADC Digital Filter (HPF): Frequency Response FR 2.0 Hz 3.0dB 5.0 Hz 0.5dB (Note 5) 13.0 Hz 0.1dB Note 5. The passband and stopband frequencies scale with fs. For example, PB=0.45 x fs(@0.1dB). Note 6. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the output register. 11. DC Characteristics (Ta=25C, VA=VD=2.7 5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=80A) Low-Level Output Voltage (Iout=80A) Input Leakage Current Symbol VIH VIL VOH VOL Iin MS1641-E-02 min 75%VD VD0.4 - typ - max 25%VD 0.4 10 Unit V V V V A 2014/12 -9- [AK5720] 12. Switching Characteristics (Ta=-40C 105C; VA=VD=2.7 5.5V; CL=20pF, unless otherwise specified) Parameter Symbol min typ Master Clock Timing Master Clock 256fs: fCLK 2.048 12.288 Pulse Width Low tCLKL 16 Pulse Width High tCLKH 16 384fs: fCLK 3.072 18.432 Pulse Width Low tCLKL 11 Pulse Width High tCLKH 11 512fs: fCLK 4.096 24.576 Pulse Width Low tCLKL 16 Pulse Width High tCLKH 16 768fs: fCLK 6.144 36.864 Pulse Width Low tCLKL 11 Pulse Width High tCLKH 11 LRCK Timing (Slave Mode) Normal mode LRCK Frequency fs 8 Duty Cycle Duty 45 TDM256 MODE LRCK Frequency fs 8 "H" time tLRH 1/256fs "L" time tLRL 1/256fs LRCK Timing (Master Mode) Normal mode LRCK Frequency fs 8 Duty Cycle Duty 50 TDM256 MODE LRCK Frequency fs 8 "H" time (Note 7) tLRH 1/8fs Note 7. It will be "L" time in I2S format. MS1641-E-02 max Unit 24.576 MHz ns ns MHz ns ns MHz ns ns MHz ns ns 36.864 24.576 36.864 96 55 kHz % 96 kHz ns ns 96 kHz % 96 kHz ns 2014/12 - 10 - [AK5720] Parameter Symbol min typ max Unit Audio Interface Timing (Slave mode) Normal mode BICK Period tBCK 160 ns BICK Pulse Width Low tBCKL 65 ns Pulse Width High tBCKH 65 ns LRCK Edge to BICK "" (Note 8) tLRB 30 ns BICK "" to LRCK Edge (Note 8) tBLR 30 ns LRCK to SDTO (MSB) (Except I2S tLRS 35 ns mode) tBSD 35 ns BICK "" to SDTO TDM256 mode BICK Period tBCK 40 ns BICK Pulse Width Low tBCKL 16 ns Pulse Width High tBCKH 16 ns LRCK Edge to BICK "" (Note 8) tLRB 10 ns BICK "" to LRCK Edge (Note 8) tBLR 10 ns SDTO Setup time BICK "" tBSS 7 ns SDTO Hold BICK "" tBSH 6 ns TDMI Hold Time tSDH 4 ns TDMI Setup Time tSDS 5 ns Audio Interface Timing (Master mode) Normal mode BICK Frequency fBCK 64fs Hz BICK Duty dBCK 50 % BICK "" to LRCK tMBLR 20 20 ns BICK "" to SDTO tBSD 40 40 ns TDM256 mode BICK Frequency fBCK 256fs Hz BICK Duty (Note 9) dBCK 50 % BICK "" to LRCK tMBLR 10 10 ns SDTO Setup time BICK "" tBSS 7 ns SDTO Hold BICK "" tBSH 6 ns TDMI Hold Time tSDH 4 ns TDMI Setup Time tSDS 5 ns Power-Down & Reset Timing PDN Pulse Width (Note 10) tPD 150 ns 30 PDN Reject Pulse Width (Note 10) tRPD ns 4129 PDN "" to SDTO valid (Note 11) tPDV 1/fs Note 8. BICK rising edge must not occur at the same time as LRCK edge. Note 9. In the case of MCLK duty cycle is 50%. Note 10. The AK5720 can be reset by setting the PDN pin to "L" upon power-up. The PDN pin must held "L" for more han 150ns for a certain reset. The AK5720 is not reset by the "L" pulse less than 30ns. Note 11. This is the count of LRCK "" from the PDN pin = "H". MS1641-E-02 2014/12 - 11 - [AK5720] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRH tLRL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing (Slave mode) 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs LRCK 50%VD tLRH 1/fBCK 50%VD BICK tdBCKH tdBCKL dBCK = tdBCKH (or tdBCKL) x fs x 100 Figure 2. Clock Timing (Master mode) MS1641-E-02 2014/12 - 12 - [AK5720] VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO 50%VD Figure 3. Audio Interface Timing (Normal mode & Slave mode) VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSS tBSH SDTO 50%VD tSDS tSDH VIH TDMI VIL Figure 4. Audio Interface Timing (TDM mode & Slave mode) MS1641-E-02 2014/12 - 13 - [AK5720] LRCK 50%VD tMBLR 50%VD BICK tBSD 50%VD SDTO Figure 5. Audio Interface Timing (Normal mode & Master mode) LRCK 50%VD tMBLR 50%VD BICK tBSS tBSH 50%VD SDTO tSDS tSDH VIH TDMI VIL Figure 6. Audio Interface Timing (TDM mode & Master mode) MS1641-E-02 2014/12 - 14 - [AK5720] tPD VIH PDN VIL tPD V SDT O tRP D 50%V D Figure 7. Power-down & Reset Timing MS1641-E-02 2014/12 - 15 - [AK5720] 13. Functional Descriptions System Clock MCLK, BICK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = "L". If the external clocks are not present, place the AK5720 in power-down mode (PDN pin = "L"). In master mode, the master clock (MCLK) must be provided unless PDN pin = "L". fs 32kHz 44.1kHz 48kHz 96kHz MCLK 128fs N/A N/A N/A N/A 192fs N/A N/A N/A N/A 256fs 384fs 8.192MHz 12.288MHz 11.2896MHz 16.9344MHz 12.288MHz 18.432MHz 24.576MHz 36.864MHz Table 1. System Clock Example 512fs 16.384MHz 22.5792MHz 24.576MHz N/A 768fs 24.576MHz 33.8688MHz 36.864MHz N/A Audio Interface Format MCLK frequency, the relationship of BICK frequency and fs, and master/slave mode are set by external resistance value of the CKS pin and the CKS pin connection as shown in Table 2. When the CKS pin is connected to GND or VA directly, or via an external 4.7k resistor (Normal mode), the DIF/TDMI pin becomes an audio data format select pin. Two kinds of data formats: 24bit MSB justified and I2S formats can be chosen by the DIF pin. The audio data is output on the falling edge of BICK from the SDTO pin. The audio interface supports both master and slave modes. In master mode, BICK and LRCK are output and they are input in slave mode. In master mode, LRCK frequency is fixed to 1fs and the BICK frequency is fixed to 64fs. When the CKS pin is connected to GND or the VA pin via an external resistor of 18k or 82k (TDM mode), the DIF/TDMI pin becomes a TDM data input pin. In TDM mode, the audio data is output on a rising edge of BICK from the SDTO pin. When inputting the SDTO output data to the TDMI pin, this SDTO data has a delay which fills set-up or hold time of BICK rising . Mode 0 1 2 3 4 5 6 7 8 9 10 11 Normal CKS < 10 to GND (Short to GND) < 10 to VA (Short to VA) 4.7k10% to GND 4.7k10% to VA TDM 18k10% to GND 18k10% to VA 82k10% to GND 82k10% to VA DIF Master SDTO MCLK /TDMI /Slave L MSB 256/384fs (8kfs96k) Slave H I2S 512/768fs (8kfs48k) L MSB Master 256fs (8kfs96k) H I2S L MSB Master 384fs (8kfs96k) H I2S L MSB Master 512fs (8kfs48k) H I2S TDMI MSB Master 256fs (8kfs96k) TDMI MSB Slave 256fs (8kfs96k) 2 TDMI IS Master 256fs (8kfs96k) TDMI I2S Slave 256fs (8kfs96k) Table 2. Operation Mode Select LRCK BICK H/L L/H H/L L/H H/L L/H H/L L/H 48fs or 32fs 64fs 64fs 64fs 256fs 256fs 256fs 256fs Note 12. SDTO outputs 16-bit data when BICK=32fs. MS1641-E-02 2014/12 - 16 - [AK5720] LRCK 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO 23 22 12 11 10 0 23 22 12 11 10 0 23 23:MSB, 0:LSB Lch Data Rch Data Figure 8. Mode 0, 2, 4, 6 Timing (Normal mode, MSB justified) LRCK 0 1 2 3 23 24 25 26 29 30 31 0 1 2 3 23 24 25 26 29 30 31 0 1 BICK(64fs) SDTO 23 22 2 1 0 23 22 2 1 0 23:MSB, 0:LSB Lch Data Rch Data 2 Figure 9. Mode 1, 3, 5, 7 Timing (Normal mode, I S Compatible) 256 BICK LRCK (Mode 8) LRCK (Mode 9) BICK (256fs) SDTO 23 22 0 23 22 0 L R 32 BICK 32 BICK 23 22 Figure 10. Mode 8, 9 Timing (TDM256 mode, MSB justified) 256 BICK LRCK (Mode 10) LRCK (Mode 11) 5) BICK (256fs) SDTO 23 0 23 0 L R 32 BICK 32 BICK 23 Figure 11. Mode 10, 11 Timing (TDM256 mode, I2S Compatible) MS1641-E-02 2014/12 - 17 - [AK5720] Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz) and scales with sampling rate (fs). Power Down The AK5720 is placed in the power-down mode by bringing the PDN pin to "L". The digital filter is also reset at the same time. This reset should always be executed upon power-up. In power-down mode, VCOM becomes VSS level. The AK5720 will be in analog initialization cycle after exiting the power-down mode. Therefore, the SDTO output data becomes valid after 4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode when power up the AK5720. During initialization, both L and R channels of ADC digital data outputs are forced to "0" in 2's complement. The ADC outputs settle as a data corresponding to the input signals after the end of initialization (this settling takes approximately group delay time). VA/VD PDN (1) VCOM (2) REGO 3~4/fs (3) Internal PDN 4129/fs ADC Internal State (4) Init Cycle Normal Operation GD (6) Power-down GD ADC In (Analog) ADC Out (Digital) Clock In "0"data (5) Don't care (7) "0"data Don't care MCLK,LRCK,BICK Figure 12. Power-down/up Timing Example Notes: (1) The PDN pin must be "L" when power up the AK5720 and set to "H" after all poweres are supplied. (2) The internal power-down state is released after 147456/ MCLK cycles. (3) There is a delay about 3~4fs from internal power-up to the start of initialization cycle. (4) Digital block of the ADC is initialized after internal power-down is released. When start-up the AK5720, ADC input voltage should be operation common voltage. A charge-up time of DC cut capacitor is necessary to wait until the RIN and LIN pins settle to the common voltage. When the external capacitor is 10F, the status of these pin settles in = 400ms (typ). (5) Click noise occurs at the end of initialization in the digital part. Mute the ADC output externally if the click noise influences system applications. (6) Digital output corresponds to analog input has group delay (GD). (7) ADC outputs "0" data in power-down state. MS1641-E-02 2014/12 - 18 - [AK5720] System Reset The AK5720 should be reset once by bringing the PDN pin to "L" after power-up. In slave mode, reset and power-down are released on the rising edge (falling edge in I2C compatible mode) of LRCK after setting the PDN pin = "H". In master mode, reset and power-down are released by MCLK input after setting the PDN pin = "H". TDM Cascade Mode TDM256mode Four or less devices can be connected in cascades at the TDM256 mode. In Figure 13, the SDTO pin of device #1/#2/#3 is connected with the TDMI pin of device #2/#3/#4. It is possible to output 8 channel TDM data from the SDTO pin of device #4 as shown in Figure 14. AK5720 #1 256fs MCLK 48kHz LRCK 256fs BICK DIF/TDMI GND SDTO AK5720 #2 MCLK DIF/TDMI LRCK BICK SDTO AK5720 #3 MCLK DIF/TDMI LRCK BICK SDTO AK5720 #4 MCLK DIF/TDMI LRCK BICK SDTO 8ch TDM Figure 13. Cascade TDM Connection Diagram MS1641-E-02 2014/12 - 19 - [AK5720] 256 BICK LRCK (Master) LRCK (Slave) BICK(256fs) #1 SDTO(o) #4 TDMIN(i) #4 SDTO(o) 23 22 0 23 22 0 L-#1 R-#1 32 BICK 32 BICK 23 22 0 23 22 0 23 22 23 22 0 23 22 0 23 22 0 23 22 0 L-#3 R-#3 L-#2 R-#2 L-#1 R-#1 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 L-#4 R-#4 L-#3 R-#3 L-#2 R-#2 L-#1 R-#1 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 22 Figure 14. Cascade TDM Timing (TDM256 Mode (Left Justified)) MS1641-E-02 2014/12 - 20 - [AK5720] 14. Recommended External Circuits Figure 15 shows the system connection diagram. An evaluation board (AKD5720) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. + 0.47 10 CKS 16 1 VCOM 2 RIN FSEL 15 3 LIN DIF/TDMI 14 4 VSS 5 VA BICK 12 6 VD MCLK 11 7 GSEL LRCK 10 8 REGO SDTO 9 10 Analog Supply 2.7 5.5V 10 Digital Supply 2.7 5.5V 10 1 + + + AK5720 0.1 PDN 13 0.1 Analog Ground Mode Setting Reset Controller System Ground Note: - All digital input pins should not be left floating. Figure 15. Typical Connection Diagram MS1641-E-02 2014/12 - 21 - [AK5720] 1. Grounding and Power Supply Decoupling The AK5720 requires careful attention to power supply and grounding arrangements. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. VSS of the AK5720 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5720 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference The voltage input to VA sets the analog input range. VCOM is 50%VA and used as the common voltage of analog signals. The VCOM pin is connected to VSS. A 0.47F ceramic capacitor should be connected as close to the VCOM pin as possible between VSS and the VCOM pin. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5720. 3. Analog Inputs The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 41k (typ@fs=48kHz) resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp (typ). The ADC output data format is 2's complement. The internal HPF removes the DC offset (includes the DC offset that is caused by the ADC). The AK5720 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5720 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. 4. External Resistor of the CKS pin The external resistor of the CKS pin should be close as possible to the pin and kept away from the signal lines to prevent noises into the CKS pin. MS1641-E-02 2014/12 - 22 - [AK5720] 15. Package Outline Dimensions 16pin TSSOP (Unit: mm) *5.00.1 9 A 8 1 0.13 M 6.40.2 *4.40.1 16 1.050.05 0.220.1 0.65 0.170.05 Detail A 0.50.2 0.10.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10 Material & Lead Finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS1641-E-02 2014/12 - 23 - [AK5720] Marking AKM 5720VT XXXYY Pin #1 indication Date Code: XXXYY (5 digits) XXX: Week Code YY: Factory Control Code Marketing Code : 5720VT Asahi Kasei Logo 1) 2) 3) 4) 16. Revision History Date (Y/M/D) Revision 14/04/17 00 14/10/17 01 Reason First Edition Error Correction Page Contents 14/12/18 Error Correction 16 Description Change 16 02 22 3. Analog Inputs The AK5720 samples the analog inputs at 64fs(@fs=48kHz). The AK5720 samples the analog inputs at 64fs. Table 2 Mode 8-11 The tolerances of resisters were corrected. 5% 10% Table 2 and Table 3 were combined. MS1641-E-02 2014/12 - 24 - [AK5720] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. 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Though AKM works continually to improve the Product's quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. MS1641-E-02 2014/12 - 25 -