LTC4225IGN-2#PBF - ANALOG DEVICES

LTC4225-1/LTC4225-2

422512f

Typical applicaTion

FeaTures DescripTion

Dual Ideal Diode and

Hot Swap Controller

The LTC

4225 offers ideal diode and Hot Swap™ functions

for two power rails by controlling external series connected

N-channel MOSFETs. MOSFETs acting as ideal diodes

replace two high power Schottky diodes and the associ-

ated heat sinks, saving power and board area. Hot Swap

control MOSFETs allow boards to be safely inserted and

removed from a live backplane by limiting inrush current.

The supply output is also protected against short-circuit

faults with a fast acting current limit and internal timed

circuit breaker.

The LTC4225 regulates the forward voltage drop across

the back-to-back MOSFETs to ensure smooth current

transfer from one supply to the other without oscillation.

The ideal diodes turn on quickly to reduce the load voltage

droop during supply switch-over. If the input supply fails

or is shorted, a fast turn-off minimizes reverse-current

transients.

The LTC4225 allows independent on/off control, and reports

fault and power good status for the supply. The LTC4225-1

features a latch-off circuit breaker, while the LTC4225-2

provides automatic retry after a fault.

µTCA Application

applicaTions

n Power Path and Inrush Current Control for

Redundant Supplies

n Low Loss Replacement for Power Schottky Diodes

n Allows Safe Hot Swapping from a Live Backplane

n 2.9V to 18V Operating Range

n Controls N-Channel MOSFETs

n Limits Peak Fault Current in ≤1µs

n 0.5µs Turn-On and Reverse Turn-Off Time

n Adjustable Current Limit with Circuit Breaker

n Smooth Switchover without Oscillation

n Adjustable Current Limit Fault Delay

n Fault and Power Status Output

n LTC4225-1: Latch Off After Fault

n LTC4225-2: Automatic Retry After Fault

n 24-Lead 4mm × 5mm QFN and SSOP Packages

n Redundant Power Supplies

n Supply Holdup

n MicroTCA Systems and Servers

n Telecom Networks

n Power Prioritizer

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

CPO1

ON1

137k

12V

ON2

INTVCC

GND

0.1µF

47nF 47nF

12V

7.6A

PLUG-IN

CARD 1

PLUG-IN

CARD 2

BACKPLANE 422512 TA01a

IN1 SENSE1 DGATE1

Si7336ADP

LTC4225

0.004Ω Si7336ADP

Si7336ADP

0.004Ω Si7336ADP

HGATE1 OUT1

CPO2 IN2 SENSE2 DGATE2 HGATE2 OUT2

FAULT1

PWRGD1

EN1

TMR1

TMR2

EN2

PWRGD2

FAULT2

20k

137k

12V

7.6A

Power Dissipation vs Load Current

LOAD CURRENT (A)

POWER DISSIPATION (W)

0.5

1.0

1.5

2.0

2.5

3.0

2 4 6 8

422512 TA01

DIODE

(SBG1025L)

MOSFET

(Si7336ADP)

POWER SAVED

LTC4225-1/LTC4225-2

422512f

absoluTe MaxiMuM raTings

Supply Voltages

IN1, IN2 .................................................. –0.3V to 24V

INTVCC ..................................................... –0.3V to 7V

Input Voltages

ON1, ON2, EN1, EN2............................... –0.3V to 24V

TMR1, TMR2 .........................–0.3V to INTVCC + 0.3V

SENSE1, SENSE2 ................................... –0.3V to 24V

Output Voltages

FA U LT1, FA U LT2 , PWRGD1, PWRGD2 ..... –0.3V to 24V

CPO1, CPO2 (Note 3) ............................. –0.3V to 35V

DGATE1, DGATE2 (Note 3) ..................... –0.3V to 35V

HGATE1, HGATE2 (Note 4) ..................... –0.3V to 35V

OUT1, OUT2 ........................................... –0.3V to 24V

(Notes 1, 2)

8 9

TOP VIEW

UFD PACKAGE

24-LEAD (4mm × 5mm) PLASTIC QFN

10 11 12

24 23 22 21 20

SENSE1

IN1

INTVCC

GND

ON2

IN2

SENSE2

FAULT1

ON1

EN1

TMR1

TMR2

EN2

FAULT2

DGATE1

CPO1

HGATE1

OUT1

PWRGD1

DGATE2

CPO2

HGATE2

OUT2

PWRGD2

TJMAX = 125°C, θJA = 34°C/W

EXPOSED PAD (PIN 25) PCB GND CONNECTION OPTIONAL

TOP VIEW

GN PACKAGE

24-LEAD PLASTIC SSOP NARROW

CPO1

DGATE1

SENSE1

IN1

ON1

INTVCC

GND

ON2

IN2

SENSE2

DGATE2

CPO2

HGATE1

OUT1

PWRGD1

FAULT1

EN1

TMR1

TMR2

EN2

FAULT2

PWRGD2

OUT2

HGATE2

TJMAX = 125°C, θJA = 85°C/W

pin conFiguraTion

Average Currents

FA U LT1, FA U LT2 , PWRGD1, PWRGD2 ...................5mA

INTVCC ................................................................. 1mA

Operating Temperature Range

LTC4225C ................................................ 0°C to 70°C

LTC4225I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

GN Package ...................................................... 300°C

LTC4225-1/LTC4225-2

422512f

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4225CUFD-1#PBF LTC4225CUFD-1#TRPBF 42251 24-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C

LTC4225CUFD-2#PBF LTC4225CUFD-2#TRPBF 42252 24-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C

LTC4225IUFD-1#PBF LTC4225IUFD-1#TRPBF 42251 24-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C

LTC4225IUFD-2#PBF LTC4225IUFD-2#TRPBF 42252 24-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C

LTC4225CGN-1#PBF LTC4225CGN-1#TRPBF LTC4225GN-1 24-Lead Plastic SSOP 0°C to 70°C

LTC4225CGN-2#PBF LTC4225CGN-2#TRPBF LTC4225GN-2 24-Lead Plastic SSOP 0°C to 70°C

LTC4225IGN-1#PBF LTC4225IGN-1#TRPBF LTC4225GN-1 24-Lead Plastic SSOP –40°C to 85°C

LTC4225IGN-2#PBF LTC4225IGN-2#TRPBF LTC4225GN-2 24-Lead Plastic SSOP –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = 12V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

VIN Input Supply Range l2.9 18 V

IIN Input Supply Current l2.8 5 mA

VIN(UVL) Input Supply Undervoltage Lockout IN Rising l1.75 1.9 2.05 V

∆VIN(HYST) Input Supply Undervoltage Lockout

Hysteresis

l10 50 90 mV

VINTVCC Internal Regulator Voltage l4.5 5 5.6 V

VINTVCC(UVL) Internal VCC Undervoltage Lockout INTVCC Rising l2.1 2.2 2.3 V

∆VINTVCC(HYST) Internal VCC Undervoltage Lockout

Hysteresis

l30 60 90 mV

Ideal Diode Control

∆VFWD(REG) Forward Regulation Voltage

(VINn – VOUTn)

l10 25 40 mV

∆VDGATE External N-Channel Gate Drive

(VDGATEn – VINn)

IN < 7V, ∆VFWD = 0.1V, I = 0, –1µA

IN = 7V to 18V, ∆VFWD = 0.1V, I = 0, –1µA

ICPO(UP) CPOn Pull-Up Current CPO = IN = 2.9V

CPO = IN = 18V

–60

–50

–95

–85

–120

–110

µA

IDGATE(FPU) DGATEn Fast Pull-Up Current ∆VFWD = 0.2V, ∆VDGATE = 0V, CPO = 17V –1.5 A

IDGATE(FPD) DGATEn Fast Pull-Down Current ∆VFWD = –0.2V, ∆VDGATE = 5V 1.5 A

tON(DGATE) DGATEn Turn-On Delay ∆VFWD = 0.2V, CDGATE = 10nF l0.25 0.5 µs

tOFF(DGATE) DGATEn Turn-Off Delay ∆VFWD = –0.2V, CDGATE = 10nF l0.2 0.5 µs

Hot Swap Control

∆VSENSE(CB) Circuit Breaker Trip Sense Voltage

(VINn – VSENSEn)

l47.5 50 52.5 mV

∆VSENSE(ACL) Active Current Limit Sense Voltage

(VINn – VSENSEn)

l55 65 75 mV

∆VHGATE External N-Channel Gate Drive

(VHGATEn – VOUTn)

IN < 7V, I = 0, –1µA

IN = 7V to 18V, I = 0, –1µA

4.8

∆VHGATE(PG) Gate-Source Voltage for Power Good l3.6 4.2 4.8 V

LTC4225-1/LTC4225-2

422512f

elecTrical characTerisTics

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = 12V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IHGATE(UP) External N-Channel Gate Pull-Up Current Gate Drive On, HGATE = 0V l–7 –10 –13 µA

IHGATE(DN) External N-Channel Gate Pull-Down

Current

Gate Drive Off, OUT = 12V,

HGATE = OUT + 5V

l150 300 500 µA

IHGATE(FPD) External N-Channel Gate Fast

Pull-Down Current

Fast Turn-Off, OUT = 12V,

HGATE = OUT + 5V

l100 200 300 mA

tPHL(SENSE) Sense Voltage (INn – SENSEn)

High to HGATEn Low

∆VSENSE = 300mV, CHGATE = 10nF l 0.5 1 µs

tOFF(HGATE) ENn High to HGATEn Low

ONn Low to HGATEn Low

INn Low to HGATEn Low

µs

tD(HGATE) ONn High, ENn Low to HGATEn

Turn-On Delay

l50 100 150 ms

tP(HGATE) ONn to HGATEn Propagation Delay ON = Step 0.8V to 2V l10 20 µs

Input/Output Pin

ISENSE SENSEn Input Current SENSE = 12V l10 50 100 µA

VON(TH) ONn Threshold Voltage ON Rising l1.21 1.235 1.26 V

∆VON(HYST) ONn Hysteresis l40 80 140 mV

VON(RESET) ONn Fault Reset Threshold Voltage ON Falling l0.55 0.6 0.63 V

ION(LEAK) ONn Input Leakage Current ON = 5V l0 ±1 µA

VEN(TH) ENn Threshold Voltage EN Rising l1.185 1.235 1.284 V

∆VEN(HYST) ENn Hysteresis l40 130 200 mV

IEN(UP) ENn Pull-Up Current EN = 1V l –7 –10 –13 µA

VTMR(TH) TMRn Threshold Voltage TMR Rising

TMR Falling

1.198

0.15

1.235

0.2

1.272

0.25

ITMR(UP) TMRn Pull-Up Current TMR = 1V, In Fault Mode l –75 –100 –125 µA

ITMR(DN) TMRn Pull-Down Current TMR = 2V, No Faults l 1.4 2 2.6 µA

ITMR(RATIO) TMRn Current Ratio ITMR(DN)/ITMR(UP) l 1.4 2 2.7 %

IOUT OUTn Current OUT = 11V, IN = 12V, ON = 2V

OUT = 13V, IN = 12V, ON = 2V

2.2

120

µA

VOL Output Low Voltage (FAULTn, PWRGDn) I = 1mA l0.15 0.4 V

VOH Output High Voltage (FAULTn, PWRGDn) I = –1µA lINTVCC – 1 INTVCC – 0.5 V

IOH Input Leakage Current (FAULTn, PWRGDn) V = 18V l0 ±1 µA

IPU Output Pull-Up Current

(FAULTn, PWRGDn)

V = 1.5V l–7 –10 –13 µA

tRST(ON) ONn Low to FAULTn High l20 40 µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of

the device pins are negative. All voltages are referenced to GND unless

otherwise speciﬁed.

Note 3: An internal clamp limits the DGATE and CPO pins to a minimum of

10V above and a diode below IN. Driving these pins to voltages beyond the

clamp may damage the device.

Note 4: An internal clamp limits the HGATE pin to a minimum of 10V

above and a diode below OUT. Driving this pin to voltages beyond the

clamp may damage the device.

LTC4225-1/LTC4225-2

422512f

Typical perForMance characTerisTics

Diode Gate Voltage vs Current Hot Swap Gate Voltage vs Current OUT Current vs Voltage

Circuit Breaker Trip Voltage

vs Temperature

Active Current Limit Sense

Voltage vs Temperature

Active Current Limit Delay

vs Sense Voltage

IN Supply Current vs Voltage INTVCC Load Regulation CPO Voltage vs Current

TA = 25°C, VIN = 12V, unless otherwise noted.

VIN (V)

IIN (mA)

3 6 9 12

422512 G01

15 18

ILOAD (mA)

INTVCC (V)

–2 –4 –6 –8

422512 G02

–10

VIN = 12V

VIN = 3.3V

ICPO (µA)

–2 –60 –100

422512 G03

–20 –40 –80 –120

VCPO – VIN (∆VCPO) (V)

VIN = 18V

VIN = 2.9V

IDGATE (µA)

–2 –60 –100

422512 G04

–20 –40 –80 –120

VDGATE – VIN (∆VDGATE) (V)

VIN = 18V

VIN = 2.9V

VOUT = VIN – 0.1V

IHGATE (µA)

0–6 –10

422712 G05

–2 –4 –8 –12

GATE DRIVE (∆VHGATE) (V)

VIN = 12V

VOUT = VIN

VIN = 2.9V

TEMPERATURE (°C)

–50

CIRCUIT BREAKER TRIP VOLTAGE (mV)

–25 0 25 50

422512 G07

75 100

TEMPERATURE (°C)

–50

ACTIVE CURRENT LIMIT SENSE VOLTAGE (mV)

–25 0 25 50

422512 G08

75 100

SENSE VOLTAGE (VIN – VSENSE) (mV)

0.1

ACTIVE CURRENT LIMIT DELAY (µs)

100

100 150 200 250 300

422512 G09

CHGATE = 10nF

VOUT (V)

–0.5

OUT

(mA)

0.5

1.0

1.5

2.5

36 9 12

422512 G06

15 18

2.0

VIN = 12V

LTC4225-1/LTC4225-2

422512f

HGATE Pull-Up Current

vs Temperature

TMR Pull-Up Current

vs Temperature

PWRGD, FAULT Output Low

Voltage vs Current

Typical perForMance characTerisTics

TA = 25°C, VIN = 12V, unless otherwise noted.

pin FuncTions

CPO1, CPO2: Charge Pump Output. Connect a capacitor

from CPO1 or CPO2 to the corresponding IN1 or IN2 pin.

The value of this capacitor is approximately 10× the gate

capacitance (CISS) of the external MOSFET for ideal diode

control. The charge stored on this capacitor is used to pull

up the gate during a fast turn-on. Leave this pin open if

fast turn-on is not needed.

DGATE1, DGATE2: Ideal Diode MOSFET Gate Drive Out-

put. Connect this pin to the gate of an external N-channel

MOSFET for ideal diode control. An internal clamp limits

the gate voltage to 12V above and a diode voltage below

IN. During fast turn-on, a 1.5A pull-up charges DGATE from

CPO. During fast turn-off, a 1.5A pull-down discharges

DGATE to IN.

EN1, EN2: Enable Input. Ground this pin to enable Hot

Swap control. If this pin is pulled high, the MOSFET is not

allowed to turn on. A 10µA current source pulls this pin

up to a diode below INTVCC. Upon EN going low when ON

is high, an internal timer provides a 100ms start-up delay

for debounce, after which the fault is cleared.

Exposed Pad (UFD Package): The exposed pad may be

left open or connected to device ground.

FAULT1, FAULT2: Fault Status Output. Open-drain output

that is normally pulled high by a 10µA current source to a

diode below INTVCC. It may be pulled above INTVCC using

an external pull-up. It pulls low when the circuit breaker

is tripped after an overcurrent fault timeout. Leave open

if unused.

GND: Device Ground.

HGATE1, HGATE2: Hot Swap MOSFET Gate Drive Output.

Connect this pin to the gate of the external N-channel

MOSFET for Hot Swap control. An internal 10µA current

source charges the MOSFET gate. An internal clamp limits

the gate voltage to 12V above and a diode below OUT.

During turn-off, a 300µA pull-down discharges HGATE to

ground. During an output short or INTVCC undervoltage

lockout, a fast 200mA pull-down discharges HGATE to OUT.

IN1, IN2: Positive Supply Input and MOSFET Gate Drive

Return. The 5V INTVCC supply is generated from IN1 and

IN2 via an internal diode-OR. The voltage sensed at this

pin is used to control DGATE for forward voltage regulation

and reverse turn-off. It also senses the positive side of

the current sense resistor. The gate fast pull-down current

returns through this pin when DGATE is discharged.

TEMPERATURE (°C)

–50

–9.0

HGATE PULL-UP CURRENT (µA)

–9.5

–10.0

–10.5

–11.0

–25 0 25 50

422512 G10

75 100

TEMPERATURE (°C)

–50

–97

TMR PULL-UP CURRENT (µA)

–98

–99

–100

–101

–103

–25 0 25 50

422512 G11

75 100

–102

CURRENT (mA)

OUTPUT LOW VOLTAGE (V)

0.4

0.6

422512 G12

0.2

01235

0.8

LTC4225-1/LTC4225-2

422512f

pin FuncTions

INTVCC: Internal 5V Supply Decoupling Output. This pin

must have a 0.1µF or larger capacitor. An external load of

less than 500µA can be connected at this pin.

ON1, ON2: On Control Input. A rising edge above 1.235V

turns on the external Hot Swap MOSFET and a falling edge

below 1.155V turns it off. Connect this pin to an external

resistive divider from IN to monitor the supply undervolt-

age condition. Pulling the ON pin below 0.6V resets the

electronic circuit breaker.

OUT1, OUT2: Output Voltage Sense and MOSFET Gate

Drive Return. Connect this pin to the output side of the

external MOSFET. The voltage sensed at this pin is used

to control DGATE. The gate fast pull-down current returns

through this pin when HGATE is discharged.

PWRGD1, PWRGD2: Power Status Output. Open-drain

output that is normally pulled high by a 10µA current

source to a diode below INTVCC. It may be pulled above

INTVCC using an external pull-up. It pulls low when the

MOSFET gate drive between HGATE and OUT exceeds

the gate-to-source voltage of 4.2V. Leave open if unused.

SENSE1, SENSE2: Negative Current Sense Input. Connect

this pin to the output of the current sense resistor. The

current limit circuit controls HGATE to limit the voltage

between IN and SENSE to 65mV. A circuit breaker trips

when the sense voltage exceeds 50mV for more than a

fault ﬁlter delay conﬁgured at the TMR pin.

TMR1, TMR2: Timer Capacitor Terminal. Connect a capaci-

tor between this pin and ground to set a 12ms/µF duration

for current limit before the external Hot Swap MOSFET

is turned off. The duration of the off time is 617ms/µF,

resulting in a 2% duty cycle.

LTC4225-1/LTC4225-2

422512f

block DiagraM

–

GA1

HGATE1

CPO1

DGATE1

OUT1

ON1

HGATE2

CPO2

DGATE2

OUT2

65mV 50mV 65mV50mV

IN1 SENSE1

ECB1

SENSE2 IN2

10µA

–

25mV

HGATE1 ON

1.235V

0.6V

1.235V

0.6V

10µA

INTVCC

10µA

INTVCC

CP1

25mV

2.2V

–

100µA

INTVCC

12V

INTVCC

10µA

100µA

–A2

–

INTVCC

UV3

–

CHARGE

PUMP 1

GATE

DRIVER 1

GATE

DRIVER 2

CHARGE

PUMP 2

5V LDO

GA2

+–

100µA

INTVCC

2µA

10µA

INTVCC INTVCC INTVCC

–

IN1

1.9V

IN2

1.9V

UV1 UV2

–

FAULT1 RESET

CP2

CP5

–

1.235V

0.2V

CP7

–

CP8

100µA

2µA

EXPOSED PAD*

1.235V

0.2V

CP9

CP10

–

1.235V

CARD1 PRESENCE DETECT

HGATE2 ON

FAULT2 RESET

LOGIC

CARD2 PRESENCE DETECT

–

TMR1

GND

*UFD PACKAGE ONLY

FAULT1

EN1

10µA 10µA10µA

INTVCC

PWRGD1

ON2

CP6

CP3

CP4

TMR2

422512 BD

FAULT2

PWRGD2

EN2

INTVCC

–

1.235V

–

ECB2

12V

LTC4225-1/LTC4225-2

422512f

operaTion

The LTC4225 functions as an ideal diode with inrush cur-

rent limiting and overcurrent protection by controlling

two external back-to-back N-channel MOSFETs (MD and

MH) on a supply path. This allows boards to be safely

inserted and removed in systems with a backplane pow-

ered by redundant supplies, such as µTCA applications.

The LTC4225 has two separate ideal diode and Hot Swap

controllers, each providing independent control for the

two input supplies.

When the LTC4225 is ﬁrst powered up, the gates of the

back-to-back MOSFETs are held low, keeping them off.

The gate drive ampliﬁer (GA1, GA2) monitors the voltage

between the IN and OUT pins and drives the DGATE pin.

The ampliﬁer quickly pulls up the DGATE pin, turning

on the MOSFET for ideal diode control, when it senses

a large forward voltage drop. The stored charge in an

external capacitor connected between the CPO and IN

pins provides the charge needed to quickly turn on the

ideal diode MOSFET. An internal charge pump charges up

this capacitor at device power-up. The DGATE pin sources

current from the CPO pin and sinks current into the IN

and GND pins.

Pulling the ON pin high and the EN pin low initiates a

100ms debounce timing cycle. After this timing cycle, a

10µA current source from the charge pump ramps up the

HGATE pin. When the Hot Swap MOSFET turns on, the

inrush current is limited at a level set by an external sense

resistor (RS) connected between the IN and SENSE pins.

An active current limit ampliﬁer (A1, A2) servos the gate

of the MOSFET to 65mV across the current sense resistor.

Inrush current can be further reduced, if desired, by add-

ing a capacitor from HGATE to GND. When the MOSFET ’s

gate overdrive (HGATE to OUT voltage) exceeds 4.2V, the

PWRGD pin pulls low.

When both of the MOSFETs are turned on, the gate drive

ampliﬁer controls DGATE to servo the forward voltage drop

(VIN – VOUT) across the sense resistor and the back-to-back

MOSFETs to 25mV. If the load current causes more than

25mV of voltage drop, the gate voltage rises to enhance

the MOSFET used for ideal diode control. For large output

currents, the MOSFET ’s gate is driven fully on and the

voltage drop across the MOSFETs is equal to the sum of

the ILOAD • RDS(ON) of the two MOSFETs in series.

In the case of an input supply short circuit when the

MOSFETs are conducting, a large reverse current starts

ﬂowing from the load towards the input. The gate drive

ampliﬁer detects this failure condition as soon as it ap-

pears and turns off the ideal diode MOSFET by pulling

down the DGATE pin.

In the case where an overcurrent fault occurs on the sup-

ply output, the current is limited to 65mV/RS. After a fault

ﬁlter delay set by 100µA charging the TMR pin capacitor,

the circuit breaker trips and pulls the HGATE pin low, turn-

ing off the Hot Swap MOSFET. Only the supply at fault is

affected, with the corresponding FAULT pin latched low.

At this point, the DGATE pin continues to pull high and

keeps the ideal diode MOSFET on.

Internal clamps limit both the DGATE to IN and CPO to IN

voltages to 12V. The same clamp also limits the CPO and

DGATE pins to a diode voltage below the IN pin. Another

internal clamp limits the HGATE to OUT voltage to 12V

and also clamps the HGATE pin to a diode voltage below

the OUT pin.

Power to the LTC4225 is supplied from either the IN or

OUT pins, through an internal diode-OR circuit to a low

dropout regulator (LDO). That LDO generates a 5V supply

at the INTVCC pin and powers the LTC4225’s internal low

voltage circuitry.

LTC4225-1/LTC4225-2

422512f

applicaTions inForMaTion

High availability systems often employ parallel-connected

power supplies or battery feeds to achieve redundancy

and enhance system reliability. Power ORing diodes are

commonly used to connect these supplies at the point of

load, but at the expense of power loss due to signiﬁcant

diode forward voltage drop. The LTC4225 minimizes this

power loss by using external N-channel MOSFETs for the

pass elements, allowing for a low voltage drop from the

supply to the load when the MOSFETs are turned on. When

an input source voltage drops below the output common

supply voltage, the appropriate MOSFET is turned off,

thereby matching the function and performance of an ideal

diode. By adding a current sense resistor and conﬁguring

two MOSFETs back-to-back with separate gate control, the

LTC4225 enhances the ideal diode performance with inrush

current limiting and overcurrent protection (see Figure 1).

This allows the boards to be safely inserted and removed

from a live backplane without damaging the connector.

Internal VCC Supply

The LTC4225 can operate with input supplies from 2.9V

to 18V at the IN pins. The power supply to the device is

internally regulated at 5V by a low dropout regulator (LDO)

with an output at the INTVCC pin. An internal diode-OR

circuit selects the highest of the supplies at the IN and OUT

pins to power the device through the LDO. The diode-OR

scheme permits the device’s power to be temporarily kept

alive by the OUT load capacitance when the IN supplies

have collapsed or shut off.

An undervoltage lockout circuit prevents all of the MOSFETs

from turning on until the INTVCC voltage exceeds 2.2V. A

0.1µF capacitor is recommended between the INTVCC and

GND pins, close to the device for bypassing. No external

supply should be connected at the INTVCC pin so as not

to affect the LDO’s operation.

A small external load of less

than 500µA can be connected at the INTVCC pin.

Turn-On Sequence

The board power supply at the OUT pin is controlled with

two external back-to-back N-channel MOSFETs (MD, MH).

The MOSFET MD on the supply side functions as an ideal

diode, while MH on the load side acts as a Hot Swap con-

trolling the power supplied to the output load. The sense

resistor, RS, monitors the load current for overcurrent

detection. The HGATE capacitor, CHG, controls the gate

slew rate to limit the inrush current. Resistor RHG with CHG

compensates the current control loop, while RH prevents

high frequency oscillations in the Hot Swap MOSFET.

CPO1

ON1

137k

VIN1

12V

VIN2

12V

ON2

INTVCC

GND

0.1µF

CF1

10nF

CF2

10nF

CCP1

0.1µF

CCP2

0.1µF

CT2

47nF

CHG1

15nF

BULK

SUPPLY

BYPASS

CAPACITOR

BULK

SUPPLY

BYPASS

CAPACITOR

CT1

47nF

12V

7.6A

PLUG-IN

CARD 1

PLUG-IN

CARD 2

BACKPLANE 422512 F01

IN1 SENSE1 DGATE1

MD1

Si7336ADP

MH1

Si7336ADP

LTC4225

RS1

0.004Ω

MD2

Si7336ADP

MH2

Si7336ADP

RS2

0.004Ω

HGATE1 OUT1

CPO2 IN2 SENSE2 DGATE2 HGATE2 OUT2

FAULT1

PWRGD1

EN1

TMR1

TMR2

EN2

PWRGD2

FAULT2

RH1

10Ω

RHG1

47Ω

CHG2

15nF

RH2

10Ω

RHG2

47Ω

100k

VIN1

VIN2

100k

20k

12V

7.6A

CL1

1600µF

CL2

1600µF

Figure 1. µTCA Application Supplying 12V Power to Two µTCA Slots

LTC4225-1/LTC4225-2

422512f

applicaTions inForMaTion

During a normal power-up, the ideal diode MOSFET turns

on ﬁrst. As soon as the internally generated supply, INTVCC,

rises above its 2.2V undervoltage lockout threshold, the

internal charge pump is allowed to charge up the CPO

pins. Because the Hot Swap MOSFET is turned off at

power-up, OUT remains low. As a result, the ideal diode

gate drive ampliﬁer senses a large forward drop between

the IN and OUT pins, causing it to pull up DGATE to the

CPO pin voltage.

Before the Hot Swap MOSFET can be turned on, EN must

remain low and ON must remain high for a 100ms debounce

cycle to ensure that any contact bounces during the inser-

tion have ceased. At the end of the debounce cycle, the

internal fault latches are cleared. The Hot Swap MOSFET

is then allowed to turn on by charging up HGATE with a

10µA current source from the charge pump. The voltage

at the HGATE pin rises with a slope equal to 10µA/CHG and

the supply inrush current ﬂowing into the load capacitor,

CL, is limited to:

IINRUSH =CL

CHG

•10µA

The OUT voltage follows the HGATE voltage when the

Hot Swap MOSFET turns on. If the voltage across the

current sense resistor, RS, becomes too high, the inrush

current will be limited by the internal current limiting

circuitry. Once the MOSFET gate overdrive exceeds 4.2V,

the corresponding PWRGD pin pulls low to indicate that

the power is good. Once OUT reaches the input supply

voltage, HGATE continues to ramp up. An internal 12V

clamp limits the HGATE voltage above OUT.

When both of the MOSFETs are turned on, the gate drive

ampliﬁer controls the gate of the ideal diode MOSFET, to

servo its forward voltage drop across RS, MD and MH to

25mV. If the load current causes more than 25mV of drop,

the MOSFET gate is driven fully on and the voltage drop

across the MOSFET is equal to ILOAD • RDS(ON).

Turn-Off Sequence

The external MOSFETs can be turned off by a variety of

conditions. A normal turn-off for the Hot Swap MOSFET is

initiated by pulling the ON pin below its 1.155V threshold

(80mV ON pin hysteresis), or pulling the EN pin above

its 1.235V threshold. Additionally, an overcurrent fault

of sufﬁcient duration to trip the circuit breaker also turns

off the Hot Swap MOSFET. Normally, the LTC4225 turns

off the MOSFET by pulling the HGATE pin to ground with

a 300µA current sink.

All of the MOSFETs turn off when INTVCC falls below its

undervoltage lockout threshold (2.2V). The DGATE pin is

pulled down with a 100µA current to one diode voltage

below the IN pin, while the HGATE pin is pulled down to

the OUT pin by a 200mA current.

The gate drive ampliﬁer controls the ideal diode MOSFET

to prevent reverse current when the input supply falls

below OUT. If the input supply collapses quickly, the gate

drive ampliﬁer turns off the ideal diode MOSFET with a

fast pull-down circuit as soon as it detects that IN is 20mV

below OUT. If the input supply falls at a more modest rate,

the gate drive ampliﬁer controls the MOSFET to maintain

OUT at 25mV below IN.

Figure 2. Ideal Diode Controller Start-Up Waveforms

Figure 3. Hot Swap Controller Power-Up Sequence

10V/DIV

CPO

10V/DIV

DGATE

10V/DIV

OUT

10V/DIV

20ms/DIV 422512 F02

5V/DIV

HGATE

10V/DIV

OUT

10V/DIV

PWRGD

10V/DIV

50ms/DIV 422512 F03

LTC4225-1/LTC4225-2

422512f

Board Presence Detect with EN

If ON is high when the EN pin goes low, indicating a board

presence, the LTC4225 initiates a 100ms timing cycle for

contact debounce. Upon board insertion, any bounces

on the EN pin restart the timing cycle. When the 100ms

timing cycle is done, the internal fault latches are cleared.

If the EN pin remains low at the end of the timing cycle,

HGATE is charged up with a 10µA current source to turn

on the Hot Swap MOSFET.

If the EN pin goes high, indicating a board removal, the

HGATE pin is pulled low with a 300µA current sink after

a 20µs delay, turning off the Hot Swap MOSFET without

clearing any latched faults.

Overcurrent Fault

The LTC4225 features an adjustable current limit with circuit

breaker function that protects the external MOSFETs against

short circuits or excessive load current. The voltage across

the external sense resistor (RS1, RS2) is monitored by an

electronic circuit breaker (ECB) and active current limit

(ACL) ampliﬁer. The electronic circuit breaker will turn off

the Hot Swap MOSFET with a 200mA current from HGATE

to OUT if the voltage across the sense resistor exceeds

∆VSENSE(CB) (50mV) for longer than the fault ﬁlter delay

conﬁgured at the TMR pin.

Active current limiting begins when the sense voltage

exceeds the ACL threshold ∆VSENSE(ACL) (65mV), which

is 1.3× the ECB threshold ∆VSENSE(CB). The gate of the

Hot Swap MOSFET is brought under control by the ACL

ampliﬁer and the output current is regulated to maintain

the ACL threshold across the sense resistor. At this point,

the fault ﬁlter starts the timeout with a 100µA current

charging the TMR pin capacitor. If the TMR pin voltage

exceeds its threshold (1.235V), the external MOSFET

turns off with HGATE pulled to ground by 300µA, and its

associated FAULT pulls low.

After the Hot Swap MOSFET turns off, the TMR pin ca-

pacitor is discharged with a 2µA pull-down current until

its threshold reaches 0.2V. This is followed by a cool-off

period of 14 timing cycles at the TMR pin. For the latch-off

part (LTC4225-1), the HGATE pin voltage does not restart

at the end of the cool-off period, unless the latched fault

is cleared by pulling the ON pin low or toggling the EN

pin from high to low. For the auto-retry part (LTC4225-2),

the latched fault is cleared automatically at the end of the

cool-off period, and the HGATE pin restarts charging up

to turn on the MOSFET. Figure 4 shows an overcurrent

fault on the 12V output.

In the event of a severe short-circuit fault on the 12V output

as shown in Figure 5, the output current can surge to tens

of amperes. The LTC4225 responds within 1µs to bring

the current under control by pulling the HGATE to OUT

voltage down to zero volts. Almost immediately, the gate

of the Hot Swap MOSFET recovers rapidly due to the RHG

and CHG network, and current is actively limited until the

electronic circuit breaker times out. Due to parasitic sup-

ply lead inductance, an input supply without any bypass

capacitor may collapse during the high current surge

and then spike upwards when the current is interrupted.

Figure11 shows the input supply transient suppressors

consisting of Z1, RSNUB1, CSNUB1 and Z2, RSNUB2, CSNUB2

for the two supplies if there is no input capacitance.

applicaTions inForMaTion

Figure 4. Overcurrent Fault on 12V Output

Figure 5. Severe Short-Circuit on 12V Output

OUT

10V/DIV

HGATE

10V/DIV

ILOAD

40A/DIV

100µs/DIV 422512 F04

OUT

10V/DIV

HGATE

10V/DIV

ILOAD

40A/DIV

2µs/DIV 422512 F05

LTC4225-1/LTC4225-2

422512f

Active Current Loop Stability

The active current loop on the HGATE pin is compensated

by the parasitic gate capacitance of the external N-channel

MOSFET. No further compensation components are nor-

mally required. In the case when a MOSFET with CISS ≤

2nF is chosen, an RHG and CHG compensation network

connected at the HGATE pin may be required. The value

of CHG is selected based on the inrush current allowed for

the output load capacitance. The resistor, RHG, connected

in series with CHG accelerates the MOSFET gate recovery

for active current limiting after a fast gate pull-down due

to an output short. The value of CHG should be ≤100nF

and RHG should be between 10Ω and 100Ω for optimum

performance.

TMR Pin Functions

An external capacitor, CT

, connected from the TMR pin to

GND serves as fault ﬁltering when the supply output is in

active current limit. When the voltage across the sense

resistor exceeds the circuit breaker trip threshold (50mV),

TMR pulls up with 100µA. Otherwise, it pulls down with 2µA.

The fault ﬁlter times out when the 1.235V TMR threshold

is exceeded, causing the corresponding FAULT pin to pull

low. The fault ﬁlter delay or circuit breaker time delay is:

tCB = CT • 12[ms/µF]

After the circuit breaker timeout, the TMR pin capacitor

pulls down with 2µA from the 1.235V TMR threshold

until it reaches 0.2V. Then, it completes 14 cooling cycles

consisting of the TMR pin capacitor charging to 1.235V

with a 100µA current and discharging to 0.2V with a 2µA

current. At that point, the HGATE pin voltage is allowed to

start up if the fault has been cleared as described in the

Resetting Faults section. When the latched fault is cleared

during the cool-off period, the corresponding FAULT pin

pulls high. The total cool-off time for the MOSFET after

an overcurrent fault is:

tCOOL = CT • 11[s/µF]

If the latched fault is not cleared after the cool-off period,

the cooling cycles continue until the fault is cleared.

After the cool-off period, the HGATE pin is only allowed to

pull up if the fault has been cleared for the latch-off part

(LTC4225-1). For the auto-retry part (LTC4225-2), the

latched fault is cleared automatically following the cool-off

period and the HGATE pin voltage is allowed to restart.

Resetting Faults (LTC4225-1)

For the latch-off part (LTC4225-1), an overcurrent fault

is latched after tripping the circuit breaker, and the cor-

responding FAULT pin is asserted low. If the LTC4225

controls the MOSFETs on two supplies, only the Hot Swap

MOSFET on the supply at fault is turned off and the other

is not affected.

To reset a latched fault and restart the output, pull the

corresponding ON pin below 0.6V for more than 100µs

and then high above 1.235V. The fault latches reset and

the FAULT pin deasserts on the falling edge of the ON pin.

When ON goes high again, a 100ms debounce cycle is

initiated before the HGATE pin voltage restarts. Toggling

the EN pin high and then low again also resets a fault,

but the FAULT pin pulls high at the end of the 100ms

debounce cycle before the HGATE pin voltage starts up.

Bringing all the supplies below the INTVCC undervoltage

lockout threshold (2.2V) shuts off all the MOSFETs and

resets all the fault latches. A 100ms debounce cycle is

initiated before a normal start-up when any of the supplies

is restored above the INTVCC UVLO threshold.

Auto-Retry after a Fault (LTC4225-2)

For the auto-retry part (LTC4225-2), the latched fault is reset

automatically after a cool-off timing cycle as described in

the TMR Pin Functions section. At the end of the cool-off

period, the fault latch is cleared and FAULT pulls high. The

HGATE pin voltage is allowed to start up and turn on the

Hot Swap MOSFET. If the output short persists, the supply

powers up into a short with active current limiting until

the circuit breaker times out and FAULT again pulls low. A

new cool-off cycle begins with TMR ramping down with

a 2µA current. The whole process repeats itself until the

output short is removed. Since tCB and tCOOL are a func-

tion of TMR capacitance, CT, the auto-retry duty cycle is

equal to 0.1%, irrespective of CT.

Figure 6 shows an auto-retry sequence after an overcurrent

fault.

applicaTions inForMaTion

LTC4225-1/LTC4225-2

422512f

Supply Undervoltage Monitor

The ON pin functions as a turn-on control and an input

supply monitor. A resistive divider connected between

the input supply (IN1, IN2) and GND at the respective

ON pin monitors the supply undervoltage condition. The

undervoltage threshold is set by proper selection of the

resistors and is given by:

VIN(UVTH) =1+RTOP

RBOTTOM









•VON(TH)

where VON(TH) is the ON rising threshold (1.235V).

An undervoltage fault occurs if the input supply falls below

its undervoltage threshold for longer than 20µs. The FAULT

pin will not be pulled low. If the ON pin voltage falls below

1.155V but remains above 0.6V, the Hot Swap MOSFET is

turned off by a 300µA pull-down from HGATE to ground.

The Hot Swap MOSFET turns back on instantly without

the 100ms debounce cycle when the input supply rises

above its undervoltage threshold.

However, if the ON pin voltage drops below 0.6V, it turns

off the Hot Swap MOSFET and clears the associated fault

latches. The Hot Swap MOSFET turns back on only after a

100ms debounce cycle when the input supply is restored

above its undervoltage threshold. An undervoltage fault on

one supply does not affect the operation of the other sup-

ply. The ideal diode function controlled by the ideal diode

MOSFET is unaffected by undervoltage fault conditions.

If both IN supplies fall until the internally generated sup-

ply, INTVCC, drops below its 2.2V UVLO threshold, all the

MOSFETs are turned off and the fault latches are cleared.

Operation resumes from a fresh start-up cycle when the

input supplies are restored and INTVCC exceeds its UVLO

threshold.

There is a 10µs glitch ﬁlter on the ON pin to reject supply

glitches. By placing a ﬁlter capacitor, CF

, with the resistive

divider at the ON pin, the glitch ﬁlter delay is further extended

by the RC time constant to prevent any false fault.

Power Good Monitor

Internal circuitry monitors the MOSFET gate overdrive

between the HGATE and OUT pins. The power good status

for each supply is reported via its respective open-drain

output, PWRGD1 or PWRGD2. They are normally pulled

high by an external pull-up resistor or the internal 10µA

pull-up. The power good output asserts low when the gate

overdrive exceeds 4.2V during the HGATE start-up. Once

asserted low, the power good status is latched and can only

be cleared by pulling the ON pin low, toggling the EN pin

from low to high, or INTVCC entering undervoltage lockout.

The power good output continues to pull low while HGATE

is regulating in active current limit, but pulls high when

the circuit breaker times out and pulls the HGATE pin low.

CPO and DGATE Start-Up

The CPO and DGATE pin voltages are initially pulled up to a

diode below the IN pin when ﬁrst powered up. CPO starts

ramping up 7µs after INTVCC clears its undervoltage lockout

level. Another 40µs later, DGATE also starts ramping up

with CPO. The CPO ramp rate is determined by the CPO

pull-up current into the combined CPO and DGATE pin

capacitances. An internal clamp limits the CPO pin voltage

to 12V above the IN pin, while the ﬁnal DGATE pin voltage

is determined by the gate drive ampliﬁer. An internal 12V

clamp limits the DGATE pin voltage above IN.

applicaTions inForMaTion

Figure 6. Auto-Retry Sequence After a Fault

TMR

1V/DIV

HGATE

5V/DIV

FAULT

10V/DIV

ILOAD

20A/DIV

50ms/DIV 422512 F06

LTC4225-1/LTC4225-2

422512f

MOSFET Selection

The LTC4225 drives N-channel MOSFETs to conduct the

load current. The important features of the MOSFETs are

on-resistance, RDS(ON), the maximum drain-source volt-

age, BVDSS, and the threshold voltage.

The gate drive for the ideal diode MOSFET and Hot Swap

MOSFET is guaranteed to be greater than 5V and 4.8V

respectively when the supply voltages at IN1 and IN2 are

between 2.9V and 7V. When the supply voltages at IN1 and

IN2 are greater than 7V, the gate drive is guaranteed to be

greater than 10V. The gate drive is limited to not more than

14V. This allows the use of logic-level threshold N-channel

MOSFETs and standard N-channel MOSFETs above 7V. An

external Zener diode can be used to clamp the potential

from the MOSFET’s gate to source if the rated breakdown

voltage is less than 14V.

The maximum allowable drain-source voltage, BVDSS,

must be higher than the supply voltages as the full sup-

ply voltage can appear across the MOSFET. If an input or

output is connected to ground, the full supply voltage will

appear across the MOSFET. The RDS(ON) should be small

enough to conduct the maximum load current, and also

stay within the MOSFET ’s power rating.

CPO Capacitor Selection

The recommended value of the capacitor, CCP

, between the

CPO and IN pins is approximately 10× the input capaci-

tance, CISS, of the ideal diode MOSFET. A larger capacitor

takes a correspondingly longer time to charge up by the

internal charge pump. A smaller capacitor suffers more

voltage drop during a fast gate turn-on event as it shares

charge with the MOSFET gate capacitance.

Supply Transient Protection

When the capacitances at the input and output are very

small, rapid changes in current during input or output short-

circuit events can cause transients that exceed the 24V

absolute maximum ratings of the IN and OUT pins. To mini-

mize such spikes, use wider traces or heavier trace plating

to reduce the power trace inductance. Also, bypass locally

with a 10µF electrolytic and 0.1µF ceramic, or alternatively

clamp the input with a transient voltage suppressor (Z1, Z2).

A 10Ω, 0.1µF snubber damps the response and eliminates

ringing (See Figure 11).

Design Example

As a design example for selecting components, consider

a 12V system with a 7.6A maximum load current for the

two supplies (see Figure 1).

First, select the appropriate value of the current sense

resistors (RS1 and RS2) for the 12V supply. Calculate

the sense resistor value based on the maximum load

current ILOAD(MAX), the minimum circuit breaker trip cur-

rent ITRIP(MIN) and the lower limit for the circuit breaker

threshold ∆VSENSE(CB)(MIN). A load current margin given

as a ratio of ITRIP(MIN)/ILOAD(MAX) is provided for allowing

backfeeding current to ﬂow through the sense resistor

momentarily, without false tripping the circuit breaker on

the higher supply before the reverse turn-off is activated on

the lower supply. Assuming a load current margin of 1.5×,

ITRIP(MIN) = 1.5 • ILOAD(MAX) = 1.5 • 7.6A = 11.4A

RS=∆VSENSE(CB)(MIN)

ITRIP(MIN)

=47.5mV

11.4A =4.16mΩ

Choose a 4mΩ sense resistor with a 1% tolerance.

Next, calculate the RDS(ON) of the MOSFET to achieve

the desired forward drop at maximum load. Assuming a

forward drop, ∆VFWD of 60mV across the two MOSFETs

connected back-to-back:

RDS(ON,TOTAL) ≤∆VFWD

ILOAD(MAX)

=60mV

7.6A =7.9mΩ

The Si7336ADP offers a good choice with a maximum

RDS(ON) of 3mΩ at VGS = 10V, thereby giving a total of

6mΩ for two MOSFETs in the supply path. The input ca-

pacitance, CISS, of the Si7336ADP is about 5600pF. Slightly

exceeding the 10× recommendation, a 0.1µF capacitor is

selected for CCP1 and CCP2 at the CPO pins.

applicaTions inForMaTion

LTC4225-1/LTC4225-2

422512f

Next, verify that the thermal ratings of the selected

MOSFET, Si7336ADP, are not exceeded during power-up

or an output short.

Assuming the MOSFET dissipates power due to inrush

current charging the load capacitor, CL, at power-up, the

energy dissipated in the MOSFET is the same as the energy

stored in the load capacitor, and is given by:

ECL =1

•CL•VIN2

For CL = 1600µF, the time it takes to charge up CL is

calculated as:

tCHARGE =CL•VIN

IINRUSH

=1600µF •12V

1A =19ms

The inrush current is set to 1A by adding capacitance,

CHG, at the gate of the Hot Swap MOSFET.

CHG =CL•IHGATE(UP)

IINRUSH

=1600µF •10µA

1A =16nF

Choose a practical value of 15nF for CHG.

The average power dissipated in the MOSFET is calculated

as:

PAVG =ECL

tCHARGE

2•1600µF •12V

( )

19ms =6W

The MOSFET selected must be able to tolerate 6W for

19ms during power-up. The SOA curves of the Si7336ADP

provide for 1.5A at 30V (45W) for 100ms. This is sufﬁ-

cient to satisfy the requirement. The increase in junction

temperature due to the power dissipated in the MOSFET

is ∆T = PAVG • ZthJC where ZthJC is the junction-to-case

thermal impedance. Under this condition, the Si7336ADP

data sheet indicates that the junction temperature will

increase by 4.8°C using ZthJC = 0.8°C/W (single pulse).

The duration and magnitude of the power pulse during an

output short is a function of the TMR capacitance, CT

, and

the LTC4225’s active current limit. The short-circuit dura-

tion is given as CT • 12[ms/µF] = 0.56ms for CT = 0.047µF.

The maximum short-circuit current is calculated using the

maximum active current limit threshold ∆VSENSE(ACL)(MAX)

and minimum RS value.

ISHORT(MAX) =∆VSENSE(ACL)(MAX)

RS(MIN)

=75mV

3.96mΩ=18.9A

So, the maximum power dissipated in the MOSFET is

18.9A • 12V = 227W for 0.56ms. The Si7336ADP data

sheet indicates that the worst-case increase in junction

temperature during this short-circuit condition is 22.7°C

using ZthJC = 0.1°C/W (single pulse). Choosing CT =

0.047µF will not cause the maximum junction temperature

of the MOSFET to be exceeded. The SOA curves of the

Si7336ADP provide for 15A at 30V (450W) for 1ms. This

also satisﬁes the requirement.

Next, select the resistive divider at the ON1 and ON2 pins

to provide an undervoltage threshold of 9.6V for the 12V

supply. First, choose the bottom resistors, R1 and R3, to be

20k. Then, calculate the top resistor value for R2 and R4:

RTOP =VIN(UVTH)

VON(TH)

– 1









•RBOTTOM

RTOP =9.6V

1.235V – 1









•20k =135k

Choose the nearest 1% resistor value of 137k for R2

and R4. In addition, there is a 0.1µF bypass (C1) at the

INTVCC pin and a 10nF ﬁlter capacitor (CF) at the ON pin

to prevent the supply glitches from turning off the Hot

Swap MOSFET.

PCB Layout Considerations

For proper operation of the LTC4225’s circuit breaker, Kelvin

connection to the sense resistor is strongly recommended.

The PCB layout should be balanced and symmetrical to

minimize wiring errors. In addition, the PCB layout for the

sense resistor and the power MOSFET should include good

thermal management techniques for optimal device power

dissipation. A recommended PCB layout is illustrated in

Figure 7.

applicaTions inForMaTion

LTC4225-1/LTC4225-2

422512f

Connect the IN and OUT pin traces as close as possible to

the MOSFETs’ terminals. Keep the traces to the MOSFETs

wide and short to minimize resistive losses. The PCB traces

associated with the power path through the MOSFETs

should have low resistance. The suggested trace width for

1oz copper foil is 0.03" for each ampere of DC current to

keep PCB trace resistance, voltage drop and temperature

rise to a minimum. Note that the sheet resistance of 1oz

copper foil is approximately 0.5mΩ/square, and voltage

24 23 22 21 20

9 10 11 12

LTC4225UFD

RH1

CCP1

CCP2

RH2

VIAS TO GND PLANE

RS1

IN1 OUT1

OUT2

422512 F07

CURRENT FLOW

TO LOAD

•

MD1

PowerPAK SO-8

MH1

PowerPAK SO-8

MD2

PowerPAK SO-8

MH2

PowerPAK SO-8

S D

G D

D G

D S

S D

G D

D G

D S

•

•• •

• •

CURRENT FLOW

TO LOAD

CURRENT FLOW

TO LOAD

CURRENT FLOW

TO LOAD

TRACK WIDTH W:

0.03" PER AMPERE

ON 1oz Cu FOIL

IN2 W W

RS2

drops due to trace resistance add up quickly in high cur-

rent applications.

It is also important to place the bypass capacitor, C1, for

the INTVCC pin, as close as possible between INTVCC and

GND. Also place CCP1 near the CPO1 and IN1 pins, and

CCP2 near the CPO2 and IN2 pins. The transient voltage

suppressors, Z1 and Z2, when used, should be mounted

close to the LTC4225 using short lead lengths.

Figure 7. Recommended PCB Layout for Power MOSFETs and Sense Resistors

applicaTions inForMaTion

LTC4225-1/LTC4225-2

422512f

applicaTions inForMaTion

Power Prioritizer

Figure 8 shows an application where either of two supplies

is passed to the output on the basis of priority, rather than

simply allowing the highest voltage to prevail. The 5V pri-

mary supply (INPUT 1) is passed to the output whenever

it is available; power is drawn from the 12V backup supply

(INPUT 2) only when the primary supply is unavailable. As

long as INPUT 1 is above the 4.3V UV threshold set by the

R1-R2 divider at the ON1 pin, MH1 is turned on connecting

INPUT 1 to the output. When MH1 is on, PWRGD1 goes

low, which in turn pulls ON2 low and disables the IN2

path by turning MH2 off. If the primary supply fails and

INPUT1 drops below 4.3V, ON1 turns off MH1 and PWRGD1

goes high, allowing ON2 to turn on MH2 and connect the

INPUT 2 to the output. Diode D1 ensures that ON2 remains

above 0.6V while in the off state so that when ON2 goes

high, MH2 is turned on immediately without invoking the

100ms turn-on delay. When INPUT 1 returns to a viable

voltage, MH1 turns on and MH2 turns off. The ideal diode

MOSFETs MD1 and MD2 prevent backfeeding of one input

to the other under any condition.

Additional Applications

In most applications, the back-to-back MOSFETs are con-

ﬁgured with the MOSFET on the supply side as the ideal

diode and the MOSFET on the load side as the Hot Swap

control. But for some applications, the arrangement of the

MOSFETs for the ideal diode and the Hot Swap control may

reversed as shown in Figure 9. The Hot Swap MOSFET is

placed on the supply side and the ideal diode MOSFET on

the load side with the source terminals connected together.

If this conﬁguration is operated with 12V supplies, the

gate-to-source breakdown voltage of the MOSFETs can

be exceeded when the input or output is connected to

ground as the LTC4225’s internal 12V clamps only limit

the DGATE-to-IN and HGATE-to-OUT pin voltages. Choose

a MOSFET whose gate-to-source breakdown voltage is

rated for 25V or more as 24V voltage can appear across

the GATE and SOURCE pins of the MOSFET during an

input or output short. As shown in Figure 9, if a MOSFET

with a lower rated gate-to-source breakdown voltage is

chosen, an external Zener diode clamp is required between

the GATE and SOURCE pins of the MOSFET to prevent it

from breaking down.

Figure 8. 2-Channel Power Prioritizer

CPO1

ON1

EN1

ON2

EN2

INTVCC

GND

CCP1

0.1µF

CF1

0.1µF

CHG1

33nF

470µF

CT2

47nF

SMAJ13A

INPUT 1

INPUT 2

PRIMARY

SUPPLY

12V

BACKUP

SUPPLY

CCP2

0.1µF

CT1

47nF

IN1 SENSE1 DGATE1

MD1

SiR466DP

MH1

SiR466DP

LTC4225

0.006Ω

MD2

SiR466DP

MH2

SiR466DP

RS2

0.006Ω

3.92k

LS4148

HGATE1

RH1

10Ω

RHG1

47Ω

VOUT

OUT1

CPO2 IN2 SENSE2 DGATE2 HGATE2 OUT2

422512 F08

FAULT1

PWRGD2

FAULT2

SMAJ13A

41.2k

49.9k

20k

PWRGD1

TMR1

TMR2

LTC4225-1/LTC4225-2

422512f

applicaTions inForMaTion

Figure 9. An Application with the Hot Swap MOSFET on the Supply Side and the Ideal Diode MOSFET on the Load Side

CPO1

ON1

VIN1

12V

PWREN1

VIN2

12V

ON2

INTVCC

GND

0.1µF

CCP1

0.1µF

CCP2

0.1µF

CT2

47nF

CHG1

15nF

BULK

SUPPLY

BYPASS

CAPACITOR

BULK

SUPPLY

BYPASS

CAPACITOR

CT1

47nF

12V

PLUG-IN

CARD 1

PLUG-IN

CARD 2

BACKPLANE

422512 F09

IN1 SENSE1 HGATE1

MD1

SiR466DP

MH1

SiR466DP

LTC4225

RS1

0.006Ω

MH2

SiR466DP

MD2

SiR466DP

ZH1, ZD1, ZH2, ZD2: CMHZ4706

RS2

0.006Ω

DGATE1 OUT1

CPO2 IN2 SENSE2 HGATE2 DGATE2 OUT2

FAULT1

PWRGD1

EN1

TMR1

TMR2

EN2

PWRGD2

FAULT2

RH1

10Ω

ZH1 ZD1

RHG1

47Ω

CHG2

15nF

RH2

10Ω

RHG2

47Ω

12V

CL1

1000µF

PWREN2

CL2

1000µF

ZH2 ZD2

Figure 10. Plug-In Card Supply Holdup Using Ideal Diode at 12V and 3.3V Input Supplies

CPO1

ON1

EN1

137k

28k

VIN2

3.3V

ON2

EN2

INTVCC

GND

0.1µF

CF1

0.1µF

CF2

0.1µF

CCP1

0.1µF

SMAJ13A

CCP2

0.1µF

CT2

0.1µF

CHG1

15nF

CL1

1000µF

12V

10A

CT1

22nF

BACKPLANE

CONNECTOR

CARD

CONNECTOR 422512 F10

IN1 SENSE1 DGATE1

MD1

SiR158DP

MH1

SiR158DP

LTC4225

0.003Ω

MD2

SiR468DP

MH2

SiR468DP

RS2

0.015Ω

HGATE1 OUT1

CPO2 IN2 SENSE2 DGATE2 HGATE2 OUT2

FAULT1

PWRGD1

TMR1

TMR2

PWRGD2

FAULT2

RH1

10Ω

RHG1

47Ω

2.7k

D2 D1

2.7k

VIN1

20k

SMAJ13A

VIN1

12V

2.7k

D1 D2

2.7k

VIN2

CL2

100µF

3.3V

D1: GREEN LED LN1351C

D2: RED LED LN1261CAL

LTC4225-1/LTC4225-2

422512f

applicaTions inForMaTion

Figure 11. Card Resident Application with the Output Diode-ORed

137k

VIN2

12V

CF1

0.1µF

CF2

0.1µF

BACKPLANE

CONNECTOR

CARD

CONNECTOR

20k

VIN1

12V

CPO1

ON1

EN1

ON2

EN2

INTVCC

GND

0.1µF

CCP1

0.1µF

SMAJ13A

CCP2

0.1µF

CT2

47nF

1000µF

12V

CT1

47nF

422512 F11

IN1 SENSE1 DGATE1

MD1

SiR466DP

MH1

SiR466DP

LTC4225

RS1

0.006Ω

MD2

SiR466DP

MH2

SiR466DP

RS2

0.006Ω

HGATE1 OUT1

CPO2 IN2 SENSE2 DGATE2 HGATE2 OUT2

FAULT1

PWRGD1

TMR1

TMR2

PWRGD2

FAULT2

100k

VIN1

SMAJ13A

100k

VIN2

CHG1

15nF

RH1

10Ω

RHG1

47Ω

CHG2

15nF

RH2

10Ω

RHG2

47Ω

CSNUB2

0.1µF

RSNUB2

10Ω

CSNUB1

0.1µF

RSNUB1

10Ω

LTC4225-1/LTC4225-2

422512f

applicaTions inForMaTion

IN1

12V

OUT1

BACKPLANE

POWER MODULE #1

SENSE1 DGATE1

LTC4225*

•

HGATE1

IN2 OUT2SENSE2 DGATE2

8x •

•

•16x(12 AMCs, 2 CUs, 2 MCHs)

HGATE2

AMC #1

AMC #2

IN1

12V

OUT1SENSE1 DGATE1

LTC4225*

HGATE1

IN2 OUT2SENSE2 DGATE2 HGATE2

MCH #1

MCH #2

IN1

12V

OUT1

POWER MODULE #2

SENSE1 DGATE1

LTC4225*

•

HGATE1

IN2 OUT2SENSE2 DGATE2

HGATE2

IN1

12V

*ADDITIONAL DETAILS OMITTED FOR CLARITY

OUT1SENSE1 DGATE1

LTC4225*

HGATE1

IN2 OUT2

422512 F12

SENSE2 DGATE2 HGATE2

Figure 12. 12V Distribution in µTCA Redundant Power Subsystem

LTC4225-1/LTC4225-2

422512f

package DescripTion

UFD Package

24-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1696 Rev A)

4.00 ± 0.10

(2 SIDES)

5.00 ± 0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

23 24

BOTTOM VIEW—EXPOSED PAD

0.75 ± 0.05 R = 0.115

TYP

R = 0.05 TYP PIN 1 NOTCH

R = 0.20 OR C = 0.35

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UFD24) QFN 0506 REV A

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.65 ± 0.05

2.00 REF

3.00 REF

4.10 ± 0.05

5.50 ± 0.05

3.10 ± 0.05

4.50 ± 0.05

PACKAGE OUTLINE

2.65 ± 0.10

2.00 REF

3.00 REF

3.65 ± 0.10

3.65 ± 0.05

LTC4225-1/LTC4225-2

422512f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.337 – .344*

(8.560 – 8.738)

GN24 (SSOP) 0204

1 2 345678 9 10 11 12

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

161718192021222324 15 1413

.016 – .050

(0.406 – 1.270)

.015 ± .004

(0.38 ± 0.10) × 45°

0° – 8° TYP

.0075 – .0098

(0.19 – 0.25)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.033

(0.838)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC4225-1/LTC4225-2

422512f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2011

LT 0211 • PRINTED IN USA

relaTeD parTs

Typical applicaTion

Plug-In Card Diode-OR Application with Hot Swap First Followed by Ideal Diode Control

CPO1

ON1

EN1

VIN2

ON2

EN2

INTVCC

GND

0.1µF

CCP1

0.1µF

SMAJ7A

CCP2

0.1µF

CT2

0.1µF

100µF

CT1

0.1µF

BACKPLANE

CONNECTOR

CARD

CONNECTOR

422512 TA02

IN1 SENSE1 HGATE1

MH1

Si7790DP

MD1

Si7790DP

LTC4225

RS1

0.006Ω

MH2

Si7790DP

MD2

Si7790DP

RS2

0.006Ω

DGATE1 OUT1

CPO2 IN2 SENSE2 HGATE2 DGATE2 OUT2

FAULT1

PWRGD1

TMR1

TMR2

PWRGD2

FAULT2

SMAJ7A

VIN1

PWREN

10k

PART NUMBER DESCRIPTION COMMENTS

LTC1421 Dual Channel, Hot Swap Controller Operates from 3V to 12V, Supports –12V, SSOP-24

LTC1645 Dual Channel, Hot Swap Controller Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14

LTC1647-1/LTC1647-2/

LTC1647-3

Dual Channel, Hot Swap Controller Operates from 2.7V to 16.5V, SO-8 or SSOP-16

LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6

LTC4211 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10

LTC4215 Single Channel, Hot Swap Controller Operates from 2.9V to 15V, I2C Compatible Monitoring, SSOP-16 or QFN-24

LTC4216 Single Channel, Hot Swap Controller Operates from 0V to 6V, Active Current Limiting, MSOP-10 or DFN-12

LTC4218 Single Channel, Hot Swap Controller Operates from 2.9V to 26.5V, Active Current Limiting, SSOP-16 or DFN-16

LTC4221 Dual Channel, Hot Swap Controller Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16

LTC4222 Dual Channel, Hot Swap Controller Operates from 2.9V to 29V, I2C Compatible Monitoring, SSOP-36 or QFN-32

LTC4223 Dual Supply Hot Swap Controller Controls 12V and 3.3V, Active Current Limiting, SSOP-16 or DFN-16

LTC4224 Dual Channel, Hot Swap Controller Operates from 2.7V to 6V, Active Current Limiting, MSOP-10 or DFN-10

LTC4352 Low Voltage Ideal Diode Controller Operates from 2.9V to 18V, Controls N-Channel, MSOP-12 or DFN-12

LTC4354 Negative Voltage Diode-OR Controller

and Monitor

80V Operation, Controls Two N-Channels, SO-8 or DFN-8

LTC4355 Positive High Voltage Ideal Diode-OR

and Monitor

Operates from 9V to 80V, Controls Two N-Channels, S0-16 or DFN-14

LTC4357 Positive High Voltage Ideal Diode

Controller

Operates from 9V to 80V, Controls N-Channel, MSOP-8 or DFN-6

LTC4358 5A Ideal Diode Operates from 9V to 26.5V, On-Chip N-Channel, TSSOP-16 or DFN-14