ANALOG DEVICES > AN-325 APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 e 617/329-4700 12-Bit Analog I/O Port Uses AD7549 and 8051 Microcomputer by Mike Curtin INTRODUCTION In the process contro! industry, many slowly varying ana- log signals need to be measured and controlled. Exam- ples of these are temperature, pressure, position, etc. This application note describes the design of an analog Input/ Output port based on the AD7549 dual DAC and the 8051 microcomputer which will meet this requirement. The I/O port measures analog signals and also provides an ana- Jog output voltage which may be used in various system control loops (e.g., control voltage on a hydraulic servo valve). HARDWARE DESCRIPTION The two main components in the I/O port are the AD7549 dual DAC and the 8051 microcomputer. The AD7549 is a dual 12-bit DAC. Figure 1 illustrates the biock diagram. For further information consult the AD7549 Data Sheet, avail- able from Analog Devices. One DAC of the AD7549 pro- vides the analog output voltage while the other performs the D/A function in a Successive Approximation ADC. The 8051 provides the interfacing signals to load DACB with the data for the analog output. It also performs the succes- sive approximation routine with DACA to measure the an- alog input, Ai. Vop (o0 lS 5 s2 | AD7549 LOW MiD HIGH 5 NIBBLE NIBBLE NIBBLE DACA DACA DACA 4 4 | 4 SF s Zz ull DAC A REGISTER | UPD (5) J 2 L 17) 1 a2 (s) DACA OUTA Al (7) Ld 18) Resa L on 19) Vaca Ao (8) CONTRO LOGIC = 13) Veere cs (9) ree 14) Rres Wr 15) | WR (10) DAC B 4 IOUTB cir (11) 4 12 r 16) AGND Lol DAC B REGISTER | z 2 4 4 4 LOW MID L HIGH | NIBBLE NIBBLE NIBBLE DACB DACB DACB 3 z O) DGND DB3-DB0 Figure 1. AD7549 Functional Block Diagram+5V 3 Voe 8051 4.7 pF 5 Vss_P1.7 P16 P15 P14 P13 P12 P11 P1.0 P3.1 P33 P34 P30 +15V 10uF + AD7549 BD ~~ A2 6 louta (Tas 10v) t aa -15V 4 04pF t Aout . (0TO +10V) +15V + 0.01 nF ove fiz T Te fons Cf : AD OP-27 [7o A3: -15V Aa: ae) 3 IMO AD OP-27 AD544 TL311 Figure 2. Analog V/O Port Circuit Diagram The I/O port circuit diagram of Figure 2 also incorporates the AD584 voltage reference, an input buffer for Ajy, com- parator circuit for the ADC and output amplifier for Aout: The AD584 is connected to give a voltage reference of 10V to both DACs. This means that the Aun range is 0V to +10V and the Aour range is also OV to +10V. A1(AD OP-27) buffers the analog input. Since the currents in the DAC are being switched at something less than 100kHz, it is important that the buffer amplifier have a high loop gain at this frequency. The loop gain deter- mines the output impedance and so the ability of the am- plifier to maintain Ay at a 12-bit level. The AD OP-27 open loop gain at 100kHz is 40dB (100). This means that the buf- fer output impedance is 0.70 (Open Loop Output Imped- ance divided by loop gain) which is driving a 10kQ load. Error due to this is 0.007% and is well below the 12-bit level, The ADC comparator section has two stages. A3 is an AD544 with a gain resistor of 33kQ and back-to-back diodes (HSCH-1001) to reduce settling time constraints. It is possible to trim the AD544 Vos (input Offset Voltage} to take out offset in the ADC. The deciding factor in the choice of the AD544 is its extremely low input bias and offset currents. Currents of more than 100nA can contri- bute errors of 1/2LSB to the answer. Ad is a TL311 com- parator with some hysteresis. Note that there is no pull-up resistor at the output of A4 even though it is an open col- lector type output. This is because P3.0, when configured as an input, provides an internal pull-up resistor. A2 (AD OP-27) is the output amplifier for DACB and is con- nected to perform the current-to-voltage conversion for the DAC.0100 Aout: CLR P3.3 Disable the CLR line 102 SETB P3.4 Set UPD high 104 CLR P3.1 Bring CS low and select the AD7549 106 MOV R2,#04 Load Register R2 with 04. This will be used to set the device address lines 108 ACALL ADDRS Register address loadedto AD7549 10A MOV RO, #21 10C MOV A,@RO Load data (W) into DAC Blow nibble 10D ACALL DATA register : 10F INC R2 Set up next register address and 110 ACALL ADDRS loadto the AD7549 112 MOV A,@RO 113 SWAP A Load data (V) into DACB mid nibble 114 ACALL DATA register 116 INC R2 Set up next register address and 117 ACALL ADDRS load tothe AD7549 119 DEC Ro WA MOV = A,@RO__Load data (U) into DACB high nibble 118 ACALL DATA register 11D INC R2 Set up DACB Register address and load TIE ACALL ADDRS tothe AD7549 120 CLR PL? Strobe the WR line to load data 122 SETB P1.7 (UVW) to DACB 124 SETB P3.1 Bring CS high to deselect AD7549 126 RET Return to main program 0140 ADDRS: MOV A,R2 This subroutine takes the register 141 SWAP A address in R2, formats it and loads 142 ORL A, #80 itoutto the AD7549. It then returns 144 MOV P1,A to Agut routine 146 RET 0150 DATA: ANL 4,#0OF This subroutine transfers the data 226 SETB P13 Set DAC 1st (5th,9th} MSB 228 CLR P17 Bring WR low ; 224A CLR P3.4 ' 22c SETB P3.4 Strobe UPD pin 22E SETB P1.7 Bring WR high 230 JNB P3.0,290 Test comparator Ad output. If 0, jump to routine to clear bit 233 SETB P1.2 , SetDAC 2nd (6th,10th) MSB 235 CLR P17 Bring WR low 237 CLR P3.4 239 SETB P34 Strobe UPD pin 23B SETB P1.7 Bring WR back high 23D JNB P3.0,294 Test comparator Ad output. If0, jump to routine to clear bit 240 SETB P1.1 Set DAC 3rd (7th, 11th) MSB 242 CLR P17 Bring WR low 244 CLR P3.4 246 SETB P3.4 Strobe UPD pin 248 SETB P17 Bring WR back high 24A JNB P3.0,298 Test Ad output. If0, jump to routine to clear bit 24D SETB P1.0 Set DAC 4th (8th,12th) MSB 24F CLR P17 Bring WR low 251 CLR P3.4 253 SETB P3.4 Strobe UPD pin 255 SETB P1.7 Bring WR back high 257 JNB P3.0,29C Test Ad output. If0, jump to routine to clear bit 25A CLR P1,7 Bring WRiow 25C CLR P3.4 25E SETB P3.4 Strobe UPD pin 260 SETB) P1.7 Bring WR back high 262 INC Ro 263 MOV A, #0F 265 ANL A,P1 Read nibble from port, and place 267 MOV @RO0,A_resultinaddress specified by RO 268 JNB P1.5,271 26B CLR P15 Set up address for DAC Amid nibble 26D SETB P14 26F AJMP 226 271 JNB P1.4,278 274 CLR P14 Set up address for DAC A low nibble 276 AJMP 226 278 MOV A,23 Take the 2 least significant nibbles and 274 SWAP A combine them in data memory location 278 ORL A,24 23 27D MOV 23,4 27F SETB P3.1 Bring C5 high to deselect AD7549 281 RET Return to main program 290 CLR P1.3 These instructions clear the AD7549 292 AJMP 233 data bits and return to the 294 CLR P1.2 successive approximation routine 296 AJMP 240 298 CLR P1.1 29A AJMP 24D 29C CLR P1.0 29E AJMP 25A Table |. 8051 Routines for Programming the I/O Port 152 ORL PLA nibble in the lower half of Ato 154 CLR P1.7 the AD7549 data bus and strobes the 156 SETB) P1.7 WR line low to oad the appropriate 158 RET register, before returning to Aguty 0200 Aw: MOV RO, #21 202 SETB P3.0 Set up port line P3.0 as an input 204 CLR P3.3 Disable the CLR line 206 SETB P3.4 Set UPD high 208 CLR P3.1 Bring CS low and select the AD7549 20A MOV P1,#00 Load DACA low nibble register with 20D SETB P1.7 all0s 20F SETB P1.4 211 CLR P1.7 Load DAC A mid nibble register with 213 SETB P1.7 all0s 215 CLR P1.4 217 SETB P1.5 219 CLR P1.7 Load DAC A high nibble register with 21B SETB P1.7 all 0s 21D SETB P1.4 21F CLR P1.7 221 SETB P1.7 DAC A is now loaded with all 0's 223 MOV P1, #0A0 Set up address for DAC Ahigh nibble SOFTWARE DESCRIPTION Table | lists the complete analog I/O port software sub- routines. The I/O port should be considered as Part of a larger control system. Whenever an analog input is to be measured or an analog output to be delivered, the pro- gram jumps to the appropriate subroutine. These sub- routines are Agur and Ain. Aout takes the 12 bits of data UVW contained in data memory locations 20, 21 and loads this data to DACB. So, the output of A2 (Aout), is the analog value of the digital word, UVW. Ain is the successive approximation routine for convert- ing the analog signal, Ain, into its digital value XYZ and placing the result in data memory locations 22 and 23. The routine initializes port outputs, clears the contents of DACA and then proceeds into the successive approxima- tion routine proper. In this, it makes extensive use of the bit-handling instructions available on the 8051. Individual port bits may be cleared or set with a single instruction (CLR or SETB). Also, a single instruction (JNB) can test the state of port bits and jump to another location depending on the bit state. The use of these instructions simplifies the complete successive approximation routine. Table II shows the memory organization forthe Analog I/O Port.DATAMEMORY | CONTENTS 020 ou . ck 021 vw 022 0x 023 YZ Table Il. Memory Organization for Analog I/O Port PERFORMANCE To perform the Analog Output function, the user jumps from the main program to subroutine Aout. This occupies 55 bytes of memory and has an execution time of 74s. This means that within 74s of jumping to the subroutine, Aout has reached the analog equivalent of UVW (Data in 20, 21). Since A2 (AD OP-27) has excellent input offset voltage characteristics, Aour specifications will match those on the AD7549 data sheet. When the AD7549KN (BD, TD) is used, the integral linearity error is 1/2LSB. oe aa | rt. Zl | a ae Pe 00m = ae i | oo i I ; ; ' H Differential linearity is less than 1LS8, ensuring guaran- teed monotonicity over temperature. Full-scale error (gain error) is 3LSBs max which corresponds to 0.073% F.S.R. Aww is contained in 145 bytes of memory, and has an : execution time which varies between 140us and 180u<s, depending on the value of Ay. This is the ADC conversion time. For the slowly varying signals which occur in proc- ess control systems, this speed is adequate. However, for a user who needs to measure higher frequency signals, increased bandwidth can be obtained by using an AD585 Sample/Hold amplifier instead of the input buffer, A1. This allows sampling of signals up to 2.7kHz. Figure 3 shows how the output of A3 (top trace) varies during the A/D conversion cycle. At the end of the cycle, DACA is loaded with the digital value of Ajj, causing the currents flowing into A3 inverting terminal to balance and bringing the voltage at the output of A3 to zero. The bot- tom trace is the start of conversion signal. This particular conversion is completed in approximately 160s. ~@- 0 VOLTS zl START CONVERSION Figure 3. Voltage at A3 Output During the Conversion Cycle