Applications
1
Features
nIndustrial controllers
Alarm systems with periodic wake up
PABX and telephone systems
Point of sale terminals
Automotive electronics
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nDigital trimming and temperature compensation
facilities
Can be synchronized to 50 Hz or nearest s/min
50 ns access time with 50 pF load capacitance
Standby on power down typically 1.2 mA
Universal interface compatible with both Intel and Motorola
Simple 8 bit interface with no delays or busy flags
16 bytes of user RAM
Power fail input disables during power up / down or reset
Bus can be tri-state in power fail mode
Wide voltage range, 2.0 V to 5.5 V
12 or 24 hour data formats
Time to 1/100 of a second
Leap year correction and week number calculation
Alarm and timer interrupts
Programmable interrupts: 10 ms, 100 ms, s or min
Sleep mode capability
Alarm programmable up to one month
Timer measures elapsed time up to 24 hours
O
Temperature range -40 to +85 C
Packages DIP20 and SO220
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Description
The A3024 is a low power CMOS real time clock. Standby
current is typically 1.2 mA and the access time is 50 ns. The
interface is 8 bits with multiplexed address and data bus.
Multiplexing of address and data is handled by the input line
A/D. There are no busy flags in the A3024, internal time update
cycles are invisible to the user’s software. Time data can be
read from the A3024 in 12 or 24 hour data formats. An external
signal puts the A3024 in standby mode. Even in standby, the
A3024 pulls the IRQ pin active low on an internal alarm interrupt.
Calendar functions include leap year correction and week
number calculation. Time precision can be achieved by digital
triming. The A3024 can be synchronized to an external 50 Hz
signal or to the nearest second or minute.
Very Low Power 8-Bit 32 kHz RTC with
Digital Trimming, User RAM and High Level Integration
Pin Assignment
DIP20 / SO20
Fig. 2
SYNC
PF
AD0
AD1
AD2
AD3
A/D
IRQ
VSS
XIN
NC
AD7
AD6
AD5
AD4
RD
WR
CS
VDD
XOUT
A3024
Typical Operating Configuration
Fig. 1
CPU
Address
Decoder
Address Bus
Data Bus
WR or R/W
RD or DS
IRQ
CS
RD
WR
RAM
AD0 to AD7
A3024
X in
X out
CS
IRQ
RD
WR
A/D
EM MICROELECTRONIC-MARIN SA A3024
R
Absolute Maximum Ratings
Operating Conditions
Handling Procedures
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond specified
operating conditions may affect device reliability or cause
malfunction.
This device has built-in protection against high static voltages
2
Table 1
Parameter
Maximum voltage at VDD
Max. voltage at remaining pins
Min. voltage on all pins
Maximum storage temperature
Minimum storage temperature
Maximum electrostatic discharge
to MIL-STD-883C method 3015
Maximum soldering conditions
VDDmax
Vmax
Vmin
TSTOmin
TSTOmax
VSmax
TSmax
V + 7.0V
SS
V + 0.3V
DD
V - 0.3V
SS
-55 C
O
O
+125 C
1000V
O
250 C x 10s
Symbol Conditions
or electric fields; however, it is advised that normal precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when all
terminal voltages are kept within the supply voltage range.
Unused inputs must always be tied to a defined logic voltage
level.
TA-40
2.0 5.0
+85 OC
V
V/ms
nF
kHz
pF
kW
5.5
6
30
50
100
32.768
8.2
35
7
VDD
CL
RS
f
dv/dt
Table 2
Parameter Symbol Min. Typ. Max. Units
Operating temperature
Logic supply voltage
Supply voltage dv/dt
(power-up & down)
Decoupling capacitor
Crystal Characteristics
Frequency
Load Capacitance
Series resistance
Electrical Characteristics
O
V = 5.0V ± 10%, V = 0 V, T = -40 to +85 C, unless otherwise specified
DD S AS
1) With PFO = 0 (V ) all I/O pads can be tri-state, tested.
SS
With PFO = 1 (V ), CS = 1 (V ) and all other I/O pads fixed to V or to V : same standby current, not tested.
DD DD DD SS
2) All other inputs to V and all outputs open.
DD
3) At a given temperature.
4) See Fig. 4
Table 3
1)
Standby current
2)
Dynamic current
IRQ (open drain)
Inputs and Outputs
Output low voltage
Input logic low
Output low voltage
Input logic high
Output logic low
Output logic high
PF activation voltage
PF hysteresis
Pullup on SYNC
Input leakage
Output tri-state leakage
Oscillator Characteristics
Starting voltage
Frequency tolerance
Frequency stability
Temperature stability
Start-up time
Frequency Characteristics
IDD
IDD
VOL
VOL
VIL
VIH
VOL
VOH
VH
VPFL
IIN
ILS
ITS
VSTA
VSTA
TSTA
Df/f
fsta
tsta
ppm/V
ppm
O
T ³ +25 C
A
O
T = +25 C addr. 10 hex = 00 hex
A
4)
210 251 ppm
3)
2.0£V£5.5V
DD 15
addr. 10 hex = 00 hex see Fig. 5
Parameter Symbol Test Conditions Min. Typ. Max. Units
0
T = +25 C
A
V = 0.8 V
ILS
V <V <V
SSINDD
CS = 1
0
T = +25 C
A0
T = +25 C
A
I = 6 mA
OL
I = 6 mA
OH
0.2 × VDD V
V
V
V
V
0.8 × VDD 0.4
2.4
0.5 × VDD
100 mV
mA
nA
nA
20
10 1000
10 1000
2
V
V
s
2.5
1
I = 8 mA
OL
I = 1 mA, V = 2 V
OH DD
0.4
0.4
V
V
V = 3 V, PF = 0
DD
V = 5 V, PF = 0
DD
1.2
2
10
15
1.5
mA
mA
mA
CS = 4 MHz, RD = V ,
SS
WR = VDD
A3024
R
3
Typical Frequency on IRQ
DF
F0
ppm
0
T [C]
A
Address 10 hex = 00 hex
Quartz recommended
32.768 Hz ± 30 ppm
with 8.2 pF load capacitance
250
200
150
100
50
0-50 -30 -10 10 30 50 70 90 Fig. 4
Typical Standby Current at V = 5 V
DD
5
4
3
2
1
0-50 25 50 80 95 0
T [C]
A
I [mA]
DD Typical standby current range at V = 5 V
DD
Fig. 3
Characteristic of a Quartz
Fig. 5
= the ratio of the change in frequency to the nominal value
expressed in ppm (It can be thought of as the frequency
deviation at any temperature.)
= the temperature of interest in C
O
= the turnover temperature (25 ±5 C)
O
To determine the clock error (accuracy) at a given temperature, add
O
the frequency tolerance at 25 C to the value obtained from the
formula above.
[ppm]
Frequency ratio [ppm]
-100
-200
-300
-400
T -100
OT - 50
O
O
Temperature [ C]
O
T [ C]
TOT +50
OT +100
O
DF
F0
DF
FO
ppm
2
OC
= - 0.038 2
(T - T ) ±10%
O
DF/FO
T
TO
min.
max.
A3024
R
4
Fig. 6a
tCS
tACC
tW
tA/Dt
tR
tA/Ds
tF
DATA VALID
tDF
CS
A/D
RD/DS
DATA
Read Timing for Intel (RD and WR pulse) and Motorola (DS or RD pin tied to CS, and R/W)
Timing Waveforms
0
V = 5.0 ± 10%, V = 0 V, and T = -40 to +85 C
DD SS A
Timing Characteristics
1) t starts from RD (DS) or CS, whichever activates last
ACC
Typically, t = 5 + 0.9 C in ns; where C (external parasitic capacitance) is in pF
ACC EXT EXT
2) t starts from RD (DS) or CS, whichever deactivates first
DF
3) t ends at WR (R/W) or CS, whichever deactivates first
DW
4) t starts from WR (R/W) or CS, whichever deactivates first
DH
5) A/D must come before a CS and RD or a CS and WR combination. The user has to guarantee this.
Table 4
Parameter
Chip select duration, write cycle
Write pulse duration
Time between two transfers
1)
RAM access time
2)
Data valid to Hi-impedance
3)
Write data settle time
4)
Data hold time
Advance write time
PF response delay
Rise time (all timing waveform signals)
Fall time (all timing waveform signals)
5)
delay after A/D
CS delay to A/D
CS
tCS
tWR
tW
tACC
tDF
tDW
tDH
tADW
tPF
tR
tF
tA/Ds
tA/Dt
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
100
10
50
10
10
5
10
60
40
100
200
200
50
30
C = 50 pF
LOAD
Symbol Test Conditions Min. Typ. Max. Units
A3024
R
5
Fig. 6d
CS
A/D
RD
WR
Data Bus
D0 to D7
Valid Address Valid Data
Read
Intel Interface
Write Timing
tCS tW
tA/Dt
tA/Ds
tWR
tDW
DATA VALID
Fig. 6b
tDH
CS
A/D
RD
WR
DATA
Write
Fig. 6c
CS
A/D
RD
WR
Data Bus
D0 to D7
Valid Address Valid Data
A3024
R
6
Fig. 6g
CS
A/D
DS
R/W
Data Bus
D0 to D7
Valid Address Valid Data
Read
Fig. 6f
CS
A/D
DS
R/W
Data Bus
D0 to D7
Valid Address Valid Data
Write
tCS tW
tA/Dt
tA/Ds
tADW
tDW
DATA VALID
Fig. 6e
tDH
CS
A/D
DS
R/W
DATA
Motorola Write
Motorola Interface
A3024
R
7
General Block Diagram
A3024
R
Oscillator and
Divider Chain
100 Hz 8 Trim Bus
Reserved clock
and timer area
RAM
(data space)
RAM
(address command space)
Address / Data
Address / Data
A/D
CS
WR
RD
IRQ
Power Fail
IRQ + PF
Logic
Control Block and
Output Buffers
Control Bus
Trimming and Alarm
Logic
Clock
and
Timer
10
status 0
status 1
status 2
00
01
02
F0
F1
F2
clock and timer command
clock command
timer command
clock
alarm
timer
digital trimming
20
28
30
34
40
43
Digital Trimming
Oscillator :42/43
:31
:32 :10 Timer
Timer RAM
Alarm RAM
IRQ
Reg.
INIB.
INIB.RAM
Reset INIT
Reset WR F2
100 Hz
1 Hz
Clock
Clock RAM
COMP
8
Reset WR F0 F1
Reset WR F1
INIT. Bit
Reset Logic
Write F0, F1, F2
:10
32768 Hz 1kHz
100 Hz
1/100 Sec. Min. Hour
1/100 Sec. Min. Hour Day Month Year W/D W #
Fig. 7
SYNC
50
5F 16 bytes of user RAM
Xin
Xout
Hex Address
Functional Description
Power Supply, Data Retention and Standby
The A3024 is put in standby mode by activating the PF input.
When pulled logic low, PF will disable the input lines, and
immediately take to high impedance the lines AD 0-7. Input
states must be under control whenever PF is deactivated. If no
specific power fail signal can be provided, PF can be tied to the
system RESET. Even in standby the interrupt request pin IRQ
will pull to ground upon an unmasked alarm interrupt
occurring.
Initialisation
When power is first applied to the A3024 all registers have a
random value.
To initialise the A3024, software must first write a 1 to the
8
Pin Description
Table 5
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYNC
PF
AD0
AD1
AD2
AD3
A/D
IRQ
VSS
XIN
XOUT
VDD
CS
WR
RD
AD4
AD5
AD6
AD7
NC
Time synchronization
Power fail
Bit 0 from MUX address / data bus
Bit 1 from MUX address / data bus
Bit 2 from MUX address / data bus
Bit 3 from MUX address / data bus
Address / data decode
Interrupt request
Supply ground (substrate)
Oscillator input
Oscillator output
Positive supply terminal
Chip select
WR (Intel) or R/W (Motorola)
RD (Intel) or DS (Motorola)
Bit 4 from MUX address / data bus
Bit 5 from MUX address / data bus
Bit 6 from MUX address / data bus
Bit 7 from MUX address / data bus
No connection
I
I
I/O
I/O
I/O
I/O
I
O
GND
I
O
PWR
I
I
I
I/O
I/O
I/O
I/O
-
Name Description
initialisation bit (addr. 2 bit 4) and then a 0. This sets the
Frequency Tuning bit and clears all other status bits.
The time and date parameters should then be loaded into the
RAM (addr. 20 to 28 hex) and then transferred to the reserved
clock area using the clock command followed by a write.
The digital trimming register must then be initialised by
writing 210 (D2 hex) to it, if Frequency Tuning is not
required. After having written a value to the digital
trimming register the frequency tuning mode bit can be
cleared.
RAM Configuration
The RAM area of the A 3024 has a reserved clock and time area,
a data space, user RAM and an address command space (see
Table 9 or Fig. 7). The reserved clock and timer area is not
directly accessible to the user, it is used for internal time
keeping and contains the current time and date plus the timer
parameters.
Data Space
All locations in the data space are Read/Write. The data space
is directly accessible to the user and is divided into five areas :
Status Registers - three registers used for status and control
data for the device (see Tables 6, 7 and 8).
Digital Trimming Register - a special function described
under “Frequency Tuning”.
Time and Date Registers - 9 time and date locations which are
loaded with, either the current time and date parameters from
the reserved clock area or the time and date parameters to be
transferred to the reserved clock area.
Alarm Registers - 5 locations used for setting the alarm
parameters.
Timer Registers - 4 locations which are loaded with either the
timer parameters from the reserved timer area or the timer
parameters to be transferred to the reserved time area.
User RAM
The A3024 has 16 bytes of general purpose RAM available for
the users applications. This RAM block is located at addresses
50 to 5F hex and is maintained even in the standby mode (PF
active). The commands, or the time set lock bit, have no effect
on the user RAM block. Reading or writing to the user RAM is
DIP20 and SO20 Packages
A3024
R
9
Address Command Space
This space contains the three commands used for carrying out
the transfers between the Time and Date Register and / or the
Timer Registers and the reserved clock and timer area.
1) The MSB (bit 7) of the hours byte (addr. 23 hex for the clock
and 33 hex for the alarm) are used as AM/PM indicators in the
12 hour time data format and reading of the hours
bytemust be preceded by masking of the AM/PM bit. A set
AM/PM bit indicates PM. In the 24 hour time data format the bit
will always be zero.
2) The alarm hours, addr. 33 hex, must always be rewritten after a
change between 12 and 24 hour modes.
Status Words
Table 6
Status 0 - Address 00 Hex
Read / Write bits
frequency tuning mode
pulse enable / disable
alarm enable / disable
timer enable / disable
1)
24 hour / 12 hour
time set lock
test bit 0
test bit 1
0 - disabled / 24 hour
1 - enabled / 12 hour
7 6 5 4 3 2 1 0
Table 7
Status 1 - Address 01 Hex
Read / Write bits
pulse mask
alarm mask
timer mask
reserved
pulse flag
alarm flag
timer flag
reserved
0 - masked / no event
1 - unmasked / event
7 6 5 4 3 2 1 0
Table 8
Status 2 - Address 02 Hex
Read / Write bits
pulse every 10 ms
pulse every 100 ms
pulse every second
pulse every minute
initialisation bit
SYNC 50 Hz
SYNC second
SYNC minute
0 - disabled
1 - enabled
7 6 5 4 3 2 1 0
RAM Map
Address Comand Space
Address Parameter Range
Dec Hex
Data Space
Status
Special purpose
Alarm
Timer
User RAM
Clock
00
01
02
16
48
49
50
51
52
64
65
66
67
240
241
242
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
32
33
34
35
36
37
38
39
40
00
01
02
10
30
31
32
33
34
40
41
42
43
F0
F1
F2
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
20
21
22
23
24
25
26
27
28
0-255
status 0
status 1
status 2
digital trimming
1/100 second
seconds
minutes
1)
hours
date
month
year
week day
week number
1/100 second
seconds
minutes
1) 2)
hours
date
1/100 second
seconds
minutes
hours
clock and timer transfer
clock transfer
timer transfer
user RAM, byte 0
user RAM, byte 1
user RAM, byte 2
user RAM, byte 3
user RAM, byte 4
user RAM, byte 5
user RAM, byte 6
user RAM, byte 7
user RAM, byte 8
user RAM, byte 9
user RAM, byte 10
user RAM, byte 11
user RAM, byte 12
user RAM, byte 13
user RAM, byte 14
user RAM, byte 15
00-99
00-59
00-59
00-23
01-31
01-12
00-99
01-07
00-53
00-99
00-59
00-59
00-23
01-31
00-99
00-59
00-59
00-23
Table 9
A3024
R
Communication
Data transfer is in 8 bit parallel form. All time data is in packed
BCD format with tens data on lines AD 7 - 4 and units on lines
AD 3 - 0. To access information within the RAM (see Fig. 7) first
write the RAM address, then read or write from or to this
location. Fig 8 shows the two steps needed.
The lines AD 0 - 7 will be treated as an address when pin A/D is
low, and as data when /D is high. Pin /D must not change
state during any single read or write access. One line of the
address bus (e.g. A0) can be used to implement the /D signal
(see "Typical Operating Configuration", Fig. 1). Until a new
address is written, data accesses ( /D high) will always be to
the same RAM address.
Communication Sequence
AA
A
A
10
Access Considerations
The communication sequence shown in Fig. 8 is re-entrant.
When the address is written to the A3024 (ie. first step of the
communication sequence) it is stored in an internal address
latch. Software can read the internal address latch at any time
by holding the A/D line low during a read from the A3024. So, for
example, an interrupt routine can read the address latch and
push it onto a stack, popping it when finished to restore the
A3024.
NB. Alarm and timer interrupt routines can reprogram the alarm
and timer without it being necessary to read or reprogram the
clock.
Commands
The commands allow software to transfer the clock and timer
parameters in a sequence (eg. seconds, minutes, hours, etc.)
without any danger of an internal time update with carry over
corrupting the data. They also avoid delaying internal time
updates while using the A3024, as updates occuring in the
reserved clock and timer area are invisible to software. Software
writes or reads parameters to or from the RAM only.
There are three commands that occupy the command address
space in the RAM. The function of these commands is to
transfer data from the reserved clock and timer area to the RAM
or to transfer data in the opposite direction, from the RAM to the
reserved clock and timer area.
The commands take place in two steps as do all other
communications. The command address is sent with /D low.
This is followed by either a read (RD) or a write (WR), with A/D
high, to determine the direction of the transfer. If the second
step is a read then the data is transferred from the reserved
clock and timer area to the RAM and if the second step is a write
then the data that has already been loaded into the RAM clock
and/or timer locations is transferred to the reserved clock
and/or timer area.
Clock and Calendar
The time and date locations in RAM (see Table 9) provide
access to the 1/100 seconds, seconds, minutes, hours, date,
month, year, week day, and week number. These parameters
have the ranges indicated in Table 9. The A3024 may be
programmed for 12 or 24 hour time format (see section "12/24
Data Format"). If a parameter is found to be out of range, it will
be cleared when the units value on its being next incremented is
equal to or greater than 9 eg. B2 will be set to 00 after the units
have incremented to 9 (ie. B9 to 00). The device incorporates
leap year correction and week number calculation at the
beginning of a year. If the first day of the year is day 05, 06 or 07
of the week, then it is given a zero week number, otherwise it
becomes week one. Week days are numbered from 1 to 7 with
Monday as day 1.
Reading of the current time and date must be preceded by a
clock command. The time and date from the last clock
command is held unchanged in RAM.
When transferring data to the reserved clock and timer area
remember to clear the time set lock bit first.
Timer
The timer can be used either for counting elapsed time, or for
giving an interrupt (IRQ) on being incremented from
23:59:59:99 to 00:00:00:00. The timer counts up with a
resolution of 1/100 second in the timer reserved areas. The
timer enable / disable bit (addr. 00 hex, bit 3) must be set by
software to allow the timer to be incremented. The timer is
incremented in the reserved timer area, every internal time
update (10 ms). The timer flag (addr. 01 hex, bit 6) is set when
the timer rolls over from 23:59:59:99 to 00:00:00:00 and the
becomes active if the timer mask bit (addr. 01, bit 2) is set. The
will remain active until software acknowledges the interrupt
by clearing the timer flag. The timer is incremented in the
standby mode, however it will not cause to become active
until power (V ) has been restored.
DD
Note: The user should ensure that a time lapse of at least 60
microseconds exists between the falling edge of the and
the clearing of the timer flag.
A
IRQ
IRQ
IRQ
IRQ
Write RAM address
to the A3024
A/D = 0
A/D = 1 Read or write data from or to
the above address
Fig. 8
A3024
R
11
Reading the Clock
Fig. 9
Start[Pin 7 = A/D]
A/D = 0
A/D = 0
A/D = 0
A/D = 0
A/D = 1
A/D = 1
A/D = 1
A/D = 1
End
Write clock command
(addr. F1 hex) to the A3024
Read min. data from the RAM
Write 1/100 sec. address (20 hex)
to the A3024
Write sec. address (21 hex) to the
A3024
Write min. address (22 hex) to
the A3024
Read sec. data from the RAM
Read 1/100 sec. data from the
RAM
Read data from the A3024 to
copy the timer parameters from
the reversed clock area to the RAM.
A data read has no significance
Setting the Timer ( Time Set Lock Bit = 0)
Note : Commands are only valid as commands when the A/D
line is low. Writing F2 hex with the A/D line high, as in the last box
of Fig. 8, serves only to activate the A3024 write pin which
determines the direction of transfer.
Fig. 10
Start[Pin 7 = A/D]
A/D = 0
A/D = 0
A/D = 0
A/D = 0
A/D = 0
A/D = 1
A/D = 1
A/D = 1
A/D = 1
A/D = 1
End
Write 1/100 sec. address (40 hex)
to the A3024
Write F2 hex to the A3024 to
copy the timer parameters from
RAM to the reversed timer area
Write sec. address (41 hex) to the
A3024
Write hours address (43 hex) to
the A3024
Write timer command (addr. F2 hex)
to the A3024
Write hours data to the RAM
Write min. address (42 hex) to
the A3024
Write 1/100 sec. data to the RAM
Write sec. data to the RAM
Write min. data to the RAM
A3024
R
Alarm
An alarm date and time may be preset in RAM addresses 30 to
34 hex. The alarm function can be activated by setting the alarm
enable / disable bit (addr. 00 hex, bit 2). Once enabled the
preset alarm time and date are compared, every internal time
update cycle (10 ms), with the clock parameters in the reserved
clock area. When the clock parameters equal the alarm
parameters the alarm flag (addr. 01 hex, bit 5) is set. If the alarm
mask bit (addr. 01 hex, bit 1) is set, the IRQ pin goes active. The
alarm flag indicates to software the source of the interrupt. IRQ
will remain active until software acknowledges the interrupt by
clearing the alarm flag. If the alarm is enabled, and an alarm
address set to FF hex, this parameter is not compared with the
associated clock parameter. Thus it is possible to achieve a
repeat feature where an alarm occurs every programmed
number of seconds, or seconds and minutes, or seconds,
minutes and hours. The A3024 pulls the open drain IRQ line
active low during standby when an alarm interrupt occurs.
If the 12/24 hour mode is changed then the alarm hours
must be re-initialised.
Note: The user should ensure that a time lapse of at least 60
microseconds exists between the falling edge of the IRQ and
the clearing of the alarm flag.
IRQ
The IRQ output is used by 4 of the A3024's features.
These are:
1) Pulse, to provide periodic interrupts to the microprocessor
at preprogrammed intervals;
2) Alarm to provide an interrupt to the microprocessor at a
preprogrammed time and date;
3) Timer, to provide an interrupt to the microprocessor when
the timer rolls over from 23:59:59:99 to 00:00:00:00; and
4) Frequency trimming (see section "Frequency Trimming").
The first 3 features listed are similar in the way they provide
interrupts to the microprocessor. Each of the 3 has an enable /
disable bit, a flag bit, and an interrupt mask bit. The enable /
disable bit allows software to select a feature or not. A set flag bit
indicates that an enable feature has reached its interrupt
condition. Software must clear the flag bit. The interrupt mask
bit allows or disallows the IRQ output to become active when
the flag bit is set. The output becomes active whenever any
interrupt flag is set which also has its mask bit set. For all
sources of maskable interrupts within the A3024, the output
will remain active until software clears the interrupt flag. The
output is the logical OR of all the unmasked interrupt flags. The
output is open drain so an external pullup to V is needed.
DD
In standby (PF active) the output will be active if the alarm
mask bit (addr. 01 hex, bit 1) is set and the alarm flag is also set.
The timer or the pulse feature cannot cause the output to
become active while in standby.
Synchronization
There are 3 ways to synchronize the A3024. It can be
synchronized to 50 Hz, the nearest second, or the nearest
minute. Synchronization mode is selected by setting one of the
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
12
bits 5 to 7 at addr. 02 hex, in accordance with Table 8. If more
than one bit is set then all the synchronization bits are disabled.
If the SYNC input is set low for longer than 200 ms, while in the
synchronization mode, the clock will synchronize to the falling
edge of the signal. Synchronization to the nearest second
implies that the 1/100 seconds are cleared to zero and if the
contents were > 50, the seconds register is incremented.
Synchronization to the nearest minute implies that the seconds
are cleared to zero and if the contents were > 30, the minutes
register is incremented. Fractions of seconds are cleared.
Pulse
There are 4 programmable pulse frequencies available on the
A3024, these are every 10 ms, 100 ms, second or minute. The
pulse feature is activated by setting the pulse enable / disable
bit at address 00, bit 1. The pulse frequency is selected by
setting one of the bits 0 to 3 at address 02 hex (see Table 8). If
more than one of the pulse bits are set then the feature is
disabled. At the selected interval the pulse flag bit (addr. 01 hex,
bit 4) is set. If the pulse mask bit (addr. 01 hex, bit 0) is set then
the pin goes active. The pulse flag indicates to software the
source of the interrupt. will remain active until software
acknowledges the interrupt by clearing the pulse flag. The
pulse feature is disabled while in standby. Upon power
restoration the pulse feature is enabled if enabled prior to
standby. See also the section "Frequency Tuning".
Note: The user should ensure that a time lapse of at least 60
microseconds exists between the falling edge of the and
the clearing of the pulse flag.
Time Set Lock
The time set lock control bit is located at address 00 hex, bit 5
(see Table 6). When set by software, this bit disables any
transfer from the RAM to the reserved clock and timer area as
well as inhibiting any write to the digital trimming register at
address 10 hex. When the time set lock bit is set the following
transfer operations are disabled:
The clock command followed by write,
the timer command followed by write,
the clock and timer command followed by write, and
writing to the digital trimming register.
A set bit prevents unauthorized overwriting of the reserved
clock and timer area. Reading of the reserved clock and timer
area, using the commands, is not affected by the time set lock
bit. Clearing the time set lock bit by software will re-enable the
above listed commands. On initialisation the time set lock bit is
cleared. The time set lock bit does not affect the user RAM (addr.
50 to 5F hex).
Frequency Tuning
The A3024 offers a key feature called "Digital Trimming", which
is used for the clock accuracy adjustment. Unlike the traditional
capacitor trimming method, which tunes the crystal oscillator,
the digital trimming acts on the divider chain, allowing the clock
adjustment by software. The oscillator frequency itself is not
affected.
IRQ
IRQ
IRQ
A3024
R
The Principle of Digital Trimming
With the digital trimming disabled (i.e. digital trimming register
set to 00 hex), the oscillator and the first stages of the divider
chain will run slightly too fast (typ. 210 ppm: ppm = parts per
million), and will generate a 100 Hz signal with a frequency of
typically 100.021 Hz. To correct this frequency, the digital
trimming logic will inhibit every 31 seconds, a number of clock
pulses, as set in the digital trimming register. Since the duration
of 31 seconds corresponds to 1'015'808 oscillator cycles, the
digital trimming has a resolution of 0.984 ppm. In other words,
every increment by1 of the digital trimming value will slow down
the clock by 0.984 ppm, which permits the accuray of ±0.5 ppm
to be reached. Note that a 1 ppm error will result in a 1 second
difference after 11.5 days, or a 1 minute difference after 694
days! The trimming range of the A3024 is from 0 to 251 ppm.
The 251 ppm correction is obtained by writing 255 (FFhex) into
the digital trimming register.
How to Determine the Digital Trimming Value
The value to write into the digital trimming register has to be
determined by the following procedure:
1. Initialise the A3024 by writing a 1 and then a 0 into the
"Initialisation Bit" of the status register 2 (addr. 02 hex, bit 4).
This activates the frequency tuning mode in status register 0
(addr. 00 hex, bit 1) and clears the other status bits.
2. Write the value 00 hex into the digital trimming register
(addr. 10 hex). From now, the IRQ output (open drain) will
deliver the 100 Hz signal, which has a 20% duty cycle.
3. Measure the duration of 21 pulses at the IRQ output, with the
trigger set for the falling edge. It is possible also to divide the
IRQ frequency by 21, using a TTL or CMOS external circuit.
4. Compute the frequency error in ppm:
freq. error =
5. Compute the corrective value to write into the digital
trimming register.
Digital trimming value = frequency error / 0.984
6. Write this value into the digital trimming register.
7. Switch off the frequency tuning mode in status 0 (addr. 00
hex, bit 0 set to 0).
The Real Time Clock circuit will now run accurately at an
operating temperature equal to the calibration temperature. If
the operating temperature differs from the one at calibration
time, the graphs shown on Fig. 4 and 5 will help in determining
the definitive value. If the mean operating temperature of the
equipment is not known at calibration time, the equipment user
will do the final correction with a software provided by the
system designer. To avoid the calibration procedure, it is
possible also to set the digital trimming register to 210 (D2 hex)
as a standard starting value, and let the final equipment user
perform the final adjustment on site, which will take the real
temperature into account.
Time Correction at Room Temperature
Let us consider that the duration of 21 pulses of the IRQ signal is
209.97 ms at room temperature.
The frequency error is:
13
(210 - 209.97) / 210 x 1E + 06 = 142.857 ppm.
The value for the digital trimming register is:
142.857 / 0.984 = 145.18, rounded to 145 ppm (91 hex).
Time Correction with Change of Temperature
If the mean temperature on site is known to be 45 °C, the
frequency error determined at room temperature has to be
modified, using the graphs or the equation on Fig. 5.
2
Df/f = -0.038 x (45 - 25) = 15.2 ppm
O
The trimming value for 45 C will be:
(142.857 ppm - 15.2 ppm) / 0.984 = 129.73, rounded to 130 (82 hex).
12 / 24 Hour Data Format
The A3024 can run in 12 hour or 24 hour data format. On
initialisation the 12/24 hour bit ad addr. 00 bit 4 is cleared putting
the A 3024 in 24 hour data format. If the 12 hour data format is
required then bit 4 at addr. 00 must be set. In the 12 hour data
format the AM/PM indicator is the MSB of the hours register
addr. 23 bit 7. A set bit indicates PM. When reading the hours in
the 12 hour data format software should mask the MSB of the
hours register. In the 24 hour data format the MSB is always
zero.
The internal clock registers change automatically between 12
and 24 hour mode when the 24/12 hour bit is changed. The
alarm hours however must be rewritten.
Test
From the various test features added to the A3024 some may be
activated by the user. Table 6 shows the test bits. Table 10
shows the three available modes and how they may be
activated.
The first accelerates the incrementing of the parameters in the
reserved clock and timer area by 32.
The second causes all clock and timer parameters, in the
reserved clock and timer area, to be incremented in parallel at
100 Hz with no carry over, ie. independently of each other.
The third test mode combines the previous two resulting in
parallel incrementing at 3.2 kHz.
While test bit 1 is set (addr. 00 hex, bit 7) the digital trimming
action is disabled and no pulses are removed from the divider
chain. Test bit 0 (addr. 00 hex, bit 6) can be combined with digital
trimming (see section "Frequency Tuning"). To leave test, the
test bits (addr. 00 hex, bits 6 and 7) must be cleared by software.
Test corrupts the clock and timer parameters and so all
parameters should be re-initialised after a test session.
Test Modes
210 ms - measured value in ms
210 ms
6
x 10
Table 10
Normal Operation
Acceleration by 32
Parallel increment of all clock and timer
parameters at 100 Hz with no carry over;
dependent on the status of bit 3 at
address 00 hex
Parallel increment of all clock and timer
parameters at 3.2 kHz with no carry
over; dependent on the status of bit 3 at
address 00 hex
0
1
0
1
0
0
1
1
Addr.
00hex bit 7 Addr.
00hex bit 6 Function
A3024
R
14
Battery or Supercap Connection
Note : The diodes must have a
forward voltage drop of less than
0.3 V. BAT 85 s are recommended.
Fig. 11
Power fail
(low for standby)
A3024
PF VDD
VDD
VSS
VSS
Battery Supercap
or+ +
CPU
Decoder
A0
Data Bus
Address Bus to other
peripherals
and
memory
AD 0-7
A3024
WRA/DRD CS
R/W
DS
Fig. 13
A 3024 Interfaced with Motorola CPU (DS or RD pin tied to CS, and R/W)
CPU
Decoder
Address
Latch
to other
peripherals
and
memory
Address Bus A8 - A15
D 0-7
A3024
A/D Bus 0 - 7 Address Bus 0 - 7
A0
WR
WR A/DRDCS
RD
Fig. 12
A 3024 Interfaced with Intel CPU (RD and WR pulse)
Typical Applications
A3024
R
15
- The formula in Fig. 5 is used by software to continually
update the digital trimming register and so compensate
the A3024 for the ambient temperature.
- The timer is used to measure the duration the valve is
on.
- The alarm feature is used to turn the controller power on
and off at the time programmed by software. The A3024
pulls IRQ active low on an alarm even in standby and
thus can control the power on/off switch for the
controller.
- The user RAM provides the controller with non volatile
RAM for vital parameters. For example :
1) the total on time for the valve to enable software to
compute energy usage and also to identify when
service is needed - 3 bytes
Solenoid
valve
Controller
Fig. 14
Temperature
sensor
Process Application
2) average on time for the valve - 2 bytes
3) maximum temperature ever encountered together
with the time and date - 6 bytes
4) date of last service and service man’s ID - 4 bytes
5) identification code for the controller - 1 byte
Crystal Layout
In order to ensure proper oscillator operation we
recommend the following standard practices:
- Keep traces as short as possible.
- Use a guard ring around the crystal.
Fig. 15 shows the recommended layout.
Oscillator Layout
A3024
R
Fig. 15
VDD
VSS
XIN XOUT
16
Note : The peak value of the signal provided by the signal
generator should not exceed 2 V on X .
OUT
Note : The peak value of the signal provided by the signal
generator should not exceed 2 V on X .
OUT
External Clock
An external signal generator can be used to drive the divider
chain of the A 3024. Fig. 16a and 16b show how to connect the
signal generator.
VSS
0 - 5.5 V 1)
100 kW
1)
56 kW
1)indicative values Fig. 16b
XIN
XOUT
A3024
Fig. 16a
VSS
1- 2 V peak to peak
XIN
XOUT
A3024
Signal Generator
Ordering Information
The A3024 is available in the following packages:
DIP20 pin plastic package A3024 20P
SO20 pin plastic package A3024 20S
When ordering, please specify the complete part number and
package.
A3024
R
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in
an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change circuitry and specifications
without notice at any time. You are strongly urged to ensure that the information given has not been superthe seded by a more up-to-
Ó 2000 EM Microelectronic-Marin SA, 10/00, Rev. C/321
