ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 1/48
DDR SDRAM 1M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2, 2.5, 3
z Burst Type : Sequential a nd Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V
z Auto & Self refresh
z 64ms refresh period, 4K cycle
z SSTL-2 I/O interface
z 66pin TSOPII and 60 ball BGA package
Ordering Information:
PRODUCT NO. MAX FREQ VDD PACKAGE COMMENTS
M13S64164A -5TG 200MHz
M13S64164A -6TG 166MHz 2.5V 66TSOPII Pb-free
M13S64164A -5BG 200MHz
M13S64164A -6BG 166MHz 2.5V BGA Pb-free
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 2/48
Control Logic
Functional Block Diagram
Pin Arrangement
60-Ball BGA Assignment (Top View)
Bank A
Command Decoder
Bank D
Latch Circuit
Bank B
Bank C
DM
DQ
Mode Register &
Extended Mode
Register
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Sense Amplifier
Column Decoder
Data Control Circuit
Input & Output
Buffer
Address
Clock
Generator
CLK
CLK
CKE
CS
RAS
CAS
WE
DLL DQS
CLK, CLK DQS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16 x1 6
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
A
B
C
D
E
F
G
H
J
K
L
M
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
NC
A11
A8
A6
A4
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CLK
CKE
A9
A7
A5
VSS
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
VDD
DQ2
DQ4
DQ6
LDQS
LDM
WE
RAS
BA1
A0
A2
VDD
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
123 789
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 3/48
Pin Description
(M13S64164A)
Pin Name Function Pin Name Function
A0~A11,
BA0,BA1
Address inputs
- Row address A0~A11
- Column address A0~A7
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
LDM, UDM
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
DQ0~DQ15 Data-in/Data-out CLK, CLK Clock input
RAS Row address strobe CKE Clock enable
CAS Column address strobe CS Chip select
WE Write enable VDDQ Supply Voltage for GDQ
VSS Ground VSSQ Ground for DQ
VDD Power VREF Reference Voltage for SSTL-2
LDQS, UDQS
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
NC No connection
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 4/48
Absolute Maximum Rating
Parameter Symbol Value Unit
Voltage on any pin relative to VSS V
IN, VOUT -0.5 ~ 3.6 V
Voltage on VDD supply relative to VSS V
DD -1.0 ~ 3.6 V
Voltage on VDDQ supply relative to VSS V
DDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 C°
Power dissipation PD 1 W
Short circuit current IOS 50 mA
Note: Permanent device damage m ay occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation conditio n.
Exposure to higher than recommende d voltage for extende d periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 C°)
Parameter Symbol Min Max Unit Note
Supply voltage VDD 2.3 2.7 V
I/O Supply voltage VDDQ 2.3 2.7 V
I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1
I/O Termination voltage (system) VTT V
REF - 0.04 VREF + 0.04 V 2
Input logic high voltage VIH (DC) VREF + 0.15 VDDQ + 0.3 V
Input logic low voltage VIL (DC) -0.3 VREF - 0.15 V
Input Voltage Level, CLK and CLK inputs VIN (DC) -0.3 VDDQ + 0.3 V
Input Differential Voltage, CLK and CLK inputs VID (DC) 0.36 VDDQ + 0.6 V 3
Input leakage current II -2 2
μA 4
Output leakage current IOZ -5 5
μA
Output High Current (Normal strength driver)
(VOUT =VDDQ-0.373V, min VREF, min VTT) IOH -16.8 mA
Output Low Current (Normal strength driver)
(VOUT = 0.373V) IOL +16.8 mA
Output High Current (Weak strength driver)
(VOUT =VDDQ-0.763V, min VREF, min VTT) IOH -9 mA
Output Low Current (Weak strength driver)
(VOUT = 0.763V) IOL +9 mA
Notes: 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the dev ice. VTT is system supply for signal termination resistors, is expected to be set equa l
to VREF, and must track variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CLK and the in put level on CLK .
4. VIN = 0V to VDD, All other pins are not tested under VIN = 0V.
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 5/48
DC Specifications
Version
Parameter Symbol Test Condition
-5 -6
Unit Note
Operation Current
(One Bank Active) IDD0 tRC = tRC (min), tCK = tCK (min),
Active – Precharge 110 100 mA
Operation Current
(One Bank Active) IDD1 Burst Length = 2, tRC = tRC (min),
CL= 2.5, IOUT = 0mA,
Active-Read-Precharge 130 110 mA
Precharge Power-down
Standby Current IDD2P CKE
≤
VIL(max), tCK = tCK (min),
All banks idle 10 10 mA
Idle Standby Current IDD2N CKE≥VIH(min), CS ≥ V
IH(min),
tCK = tCK (min) 70 70 mA
Active Power-down Standby
Current IDD3P All banks ACT, CKE
≤
VIL(max),
tCK = tCK (min) 20 15 mA
Active Standby Current IDD3N One bank; Active-Precharge,
tRC = tRAS(max), tCK = tCK (min) 90 80 mA
Operation Current (Read) IDD4R Burst Length = 2, CL= 2.5 ,
tCK = tCK (min), IOUT = 0mA 180 160 mA
Operation Current (Write) IDD4W Burst Length = 2, CL= 2.5 ,
tCK = tCK (min) 180 160 mA
Auto Refresh Current IDD5 tRC ≥ t
RFC(min) 140 120 mA
Self Refresh Current IDD6 CKE
≤
0.2V 5 5 mA 1
Operation Current
(4 bank interleaving) IDD7 Burst Length = 4, tRC = tRC (min),
IOUT = 0mA 235 215 mA
Note: 1. Enable on-chip refresh and addres s counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter Symbol Min Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V
Input Different Voltage, CLK and CLK inputs VID(AC) 0.7 VDDQ+0.6 V 1
Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2
Note1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(VDD = 2.3V~2.7V, VDDQ=2.3V~2.7V, TA = 25 C° , f = 1MHz)
Parameter Symbol Min Max Unit
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) CIN1 2.5 3.5 pF
Input capacitance (CLK, CLK ) CIN2 2.5 3.5 pF
Data & DQS input/output capacitance COUT 4.0 5.5 pF
Input capacitance (DM) CIN3 4.0 5.5 pF
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 6/48
AC Operating Test Conditions
Parameter Value Unit
Input reference voltage for clock (VREF) 0.5*VDDQ V
Input signal maximum peak swing 1.5 V
Input signal minimum slew rate 1.0 V/ns
Input levels (VIH/VIL) VREF+0.31/VREF-0.31 V
Input timing measurement reference level VREF V
Output timing reference level VTT V
AC Timing Parameter & Specifications
(VDD = 2.3V~2.7V, VDDQ=2.3V~2.7V, TA =0 C° to 70 C°)
-5 -6
Parameter Symbol
min max min max
Unit
CL2 7.5 12 7.5 12
CL2.5 6.0 12 6.0 12
Clock Period
CL3
tCK
5.0 8 6.0 10
ns
Access time from CLK/CLK tAC -0.7 +0.7 -0.7 +0.7 ns
CLK high-level width tCH 0.45 0.55 0.45 0.55 tCK
CLK low-level width tCL 0.45 0.55 0.45 0.55 tCK
Data strobe edge to clock edge tDQSCK -0.6 +0.6 -0.6 +0.6 ns
Clock to first rising edge of DQS delay tDQSS 0.75 1.25 0.75 1.25
tCK
Data-in and DM setup time (to DQS) tDS 0.45 - 0.45 -
ns
Data-in and DM hold time (to DQS) tDH 0.45 - 0.45 -
ns
DQ and DM input pulse width (for each input) tDIPW 1.75 - 1.75 -
ns
Input setup time (fast slew rate) tIS 0.75 - 0.75 -
ns
Input hold time (fast slew rate) tIH 0.75 - 0.75 -
ns
Input setup time (slow slew rate) tIS 0.8 - 0.8 -
ns
Input hold time (slow slew rate) tIH 0.8 - 0.8 -
ns
Control and Address input pulse width tIPW 2.2 - 2.2 -
ns
DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6
tCK
DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6
tCK
DQS falling edge to CLK rising-setup time tDSS 0.2 - 0.2 -
tCK
DQS falling edge from CLK rising-hold time tDSH 0.2 - 0.2 -
tCK
Data strobe edge to output data edge tDQSQ - 0.45 - 0.45 ns
Data-out high-impedance window from
CLK/CLK tHZ -0.7 +0.7 -0.7 +0.7 ns
Data-out low-impedance window from
CLK/CLK tLZ -0.7 +0.7 -0.7 +0.7 ns
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 7/48
AC Timing Parameter & Specifications-continued
-5 -6
Parameter Symbol
min max min max
Unit
Half Clock Period tHP tCLmin or
tCHmin - tCLmin or
tCHmin - ns
DQ-DQS output hold time tQH tHP- tQHS - tHP- tQHS - ns
Data hold skew factor tQHS - 0.45 - 0.5 ns
ACTIVE to PRECHARGE command tRAS 40 120K 42 120K ns
Row Cycle Time tRC 60 - 60 - ns
AUTO REFRESH Row Cycle Time tRFC 70 - 72 - ns
ACTIVE to READ,WRITE delay tRCD 15 - 18 - ns
PRECHARGE command period t RP 15 - 18 - ns
ACTIVE to READ with AUTOPRECHARGE
command tRAP 15 120K 18 120K ns
ACTIVE bank A to ACTI VE bank B command tRRD 10 - 12 - ns
Write recovery time tWR 15 - 18 - ns
Write data in to READ command delay tWTR 2 - 2 - tCK
Col. Address to Col. Address delay tCCD 1 - 1 - tCK
Average periodic refresh interval tREFI - 15.6 - 15.6 us
Write preamble tWPRE 0.25 - 0.25 - tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK
Clock to DQS write preamble setup time tWPRES 0 - 0 - ns
Load Mode Register / Extended Mode
register cycle time tMRD 2 - 1 - tCK
Exit self refresh to READ command tXSRD 200 - 200 - tCK
Exit self refresh to non-READ command tXSNR 75 - 75 - ns
Autoprecharge write recovery+Precharge
time tDAL (tWR/tCK)
+
(tRP/tCK) (tWR/tCK)
+
(tRP/tCK) t
CK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 8/48
Command Truth Table
COMMAND CKEn-1 CKEn CS RAS CAS WE DM BA0,1 A10/AP A11,
A9~A0 Note
Register Extended MRS H X L L L L X OP CODE 1,2
Register Mode Register Set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry H L L L L H X X 3
L H H H 3
Refresh Self
Refresh Exit L H
H X X X
XX 3
Bank Active & Row Addr . H X L L H H X V Row Address
Auto Precharge Disable L 4
Read &
Column
Address Auto Precharge Enable H X L H L H X V H
Column
Address 4
Auto Precharge Disable L 4
Write &
Column
Address Auto Precharge Enable H X L H L L X V H
Column
Address 4,6
Burst Stop H X L H H L X X 7
Bank Selection V L
Precharge All Banks H X L L H L X X H X 5
H X X X
Entry H L
L V V V
X
Active Power Down Exit L H X X X X X X
H X X X
Entry H L
L H H H
X
H X X X
Precharge Power Down
Mode Exit L H
L V V V
XX
DM H X V X 8
H X X X
No Operation Command H X L H H H
XX
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~ BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected .
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issue d at tRP after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 9/48
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is req uired for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & VREF).
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1 5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the
rest address pins, A1~A11 and BA1)
*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock inp ut is required to lock the DLL.
(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
*2 7. Issue precharge commands for al l banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional
200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
CLK
CLK
Command
21 345678910
11 12 13 14 15 16 17 18 19
0
tRP
p rechar ge
All Banks EMRS MRS
Dll Res et
tRP
pr echar ge
All Banks 1st A uto
Refresh
tRFC
2nd Auto
Refre sh
tRFC
Mode
Re gis ter Se t Any
Comman d
min. 200 Cycle
Power up & Initialization Sequence
tMRD tMRD tMRD
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 10/48
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst lengt h, test mode, DLL reset and various ven dor specific options to make DDR SDRAM useful for vari ety
of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS
setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS , CAS, WE and BA0
(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of
address pins A0~A11 in the same c ycle as CS , RAS , CAS, WE and BA0 goin g low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields de pending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal
MRS operation. Refer to the table for specific codes for various burst length, address ing modes and CAS latencies.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0 0 RFU DLL TM CAS Latency BT Burst Length Mode Register
A8 DLL Reset A7 Mode A3 Burst Type
0 No 0 Normal 0 Sequential
1 Yes 1 Test 1 Interleave
Burst Length
CAS Latency Latency
A6 A5 A4 Latency
A2 A1 A0
Sequential Interleave
BA1 BA0 Operating Mode 0 0 0 Reserve 0 0 0 Reserve Reserve
0 0 MRS Cycle 0 0 1 Reserve 0 0 1 2 2
0 1 EMRS Cycle 0 1 0 2 0 1 0 4 4
0 1 1 3 0 1 1 8 8
1 0 0 Reserve 1 0 0 Reserve Reserve
1 1 0 2.5 1 0 1 Reserve Reserve
1 1 1 Reserve 1 1 0 Reserve Reserve
1 1 1 Reserve Reserve
Note: RFU (Reserved for future use) must stay “0” during MRS cycle
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 11/48
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address (A2, A1,A0) Sequential Mode Interleave Mode
xx0 0, 1 0, 1
2 xx1 1, 0 1, 0
x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
4
x11 3, 0, 1, 2 3, 2, 1, 0
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
8
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disa bled the DLL for the purpose of debug or evaluation (upon exitin g Self Refresh Mode, the D LL is
enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S64164A also support a weak drive strength
option, intended for lighter load and/or point-to-point environments.
Mode Register Set
*1: MRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS command.
01 234 5678
COMMAND
tCK
Precharge
All Banks Mode
Register Set Any
Command
tRP
*2
*1
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 12/48
Extended Mode Register Set (EMRS)
The extended mode r egister stores the data enabling or disabling DLL. T he default value of the extended mode register is not
defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode
register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). T he state of address pins A0~A11 and BA1 i n
the same cycle as CS, RAS , CAS and WE going low is written in the extended mode register. The mode register contents
can be changed using the same command and clock c ycle requirement s during operatio n as long as all banks are in the idle state .
A0 is used for DLL enable or disable. “High” on BA0 is used fo r EMRS. All the other address pins except A0 and BA0 must be set
to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 RFU : Must be set “0” D.I.C DLL
Output Driver Strength Control A0 DLL Enable
0 Normal 0 Enable
1 Weak 1 Disable
BA1 BA0 Operaing Mode
0 0 MRS Cycle
0 1 EMRS Cycle
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 13/48
Precharge
The precharge command is us ed to prec harg e or close a ba nk that has activat ed. T he precharg e command is issu ed when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initi ated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued.
After tRP from the precharge, an active command to the same bank ca n be initiated.
Burst Selection for Precharge by Bank address bits
A10/AP BA1 BA0 Precharge
0 0 0 Bank A Only
0 0 1 Bank B Only
0 1 0 Bank C Only
0 1 1 Bank D Only
1 X X All Banks
NOP & Device Deselect
The device should be des elected b y deactivating the CS signal. In this mode DDR SDRAM shoul d ignore all the co ntrol input s.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP the device should finish the current oper ation when this command is issued.
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 14/48
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank
Activation command to the first read or write command must meet or exceed the mi nimum of RAS to CAS delay time (tRCD min).
Once a bank has been activated, it must be precharged before another Bank Activation c ommand can be applied to the same bank.
The minimum time interval bet ween interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank
delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
Address
01 2
Command
Bank A
Row Addr. Bank A
Col. Addr. Bank A
Row. Addr.
Bank B
Row Addr.
Bank A
Activate NOP Write A
with Auto
Precharge
Bank B
Activate NOP Bank A
Activate
RAS-CAS delay (tRCD) RAS-RAS delay (tRRD)
ROW Cycle Time (tRC)
: Don't Care
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 15/48
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from
the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are pre sented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
Burst Write Operation
The Burst Write command is issued by having CS, CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting colu mn address. There is no write latenc y rel ativ e to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge
enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
NOP WRITE NOP NOP NOP NOP NOP NOP
tDQSS tWPST
Din0 Din1 Din2 Din3
tWPRES
CLK
CLK
tDSH tDSS
NOP
01 234 5678
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP
CLK
CLK
CAS Latency=3
DQS
DQ's Dout0 Dout1 Dout2 Dout3
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 16/48
Read Interrupted by a Read
A Burst Read can be interrupted before com pletion of the burst by ne w Read command of any bank. When the prev ious burst i s
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appe ar on the out puts until the CAS latency from the interrupting Rea d command is satisfied. At this poin t
the data from the interrupting Read command app ears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4, CAS Latency = 3>
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) cl ocks ［RU mean round up to the n earest integer］ before
the Write command.
<Burst Length = 4, CAS Latency = 3>
tCCD
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
READ A NOP NOP NOP NOP NOP NOP NOP
Dout A0
READ B
Dou t A1Dout B2Dou t B3
Dout B0Dout B1
CLK
CLK
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
READ NOP WRITENOP NOP NOP NOP NOP
Dout 0
Burst Stop
Din 0
Dou t 1 Din 1 Din 2 Din 3
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 17/48
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
When a burst Read comma nd is issued to a DDR SDRAM, a Prec harge command may be issued to the same bank b efore the
Read burst is complete. The follo wing functionalit y determines when a Precharge command ma y be giv en during a Read burst an d
when a new Bank Activate command may be issued to the same ba nk.
1. F or the earliest possible Precharge comman d without interrupting a Read burst, the Precharge comman d may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Prec h arge comm and interrupts a Read b urst oper ation, the Pr ec harg e comma nd ma y be given on the ris ing c lock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after tRP.
3. F or a Read with autoprecharge command, a ne w Bank Acti vate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read b urst as describ ed in 1 above.
4. For all cases above, tRP is an analog dela y that needs to be converte d into clock cycles. T he number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with
autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
READ NOP NOP NOP NOP NOP NOP
Dou t 0
Precharge
Dout 1
1tCK
NOP
Dou t 2 Dou t 3 Dou t 4 Dout 5
Interrupted by precharge
Dout 6 Dout 7
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 18/48
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst len gth i s satisfied.
<Burst Length = 4>
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst
and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum
delay to a Write command = RU (CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
01 234 5678
COMMAND
DQS
DQ's
NOP NOP NOP NOP NOP NOP
Din A0
WRITE A
Din A1Din B0Din B1Din B2Din B3
1tCK
NOP WRITEB
CLK
CLK
tCCD
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 19/48
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoi d data contention. When the read comma nd is registered,
any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is
required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated
will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write
command.
<Burst Length = 8, CAS Latency = 3>
The following functionalit y established how a Read command may interrupt a Write burst and which input data is not written into
the memory.
1. F or Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case wher e
the Write to Read delay is 1 clock cycle is disallo wed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the SDRAM.
5. It is illegal for a Read command interrupt a Write with autoprecharge command.
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
CAS Latency=3
DQS
DQ's
NOP NOP NOP NOP Read NOP NOP NOP
tDQSSmax
Din 0 Din 1
WRITE
tWPRES
tWTR
Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dout 1
tDQSSmin
Din 0 Din 1
tWPRES
tWTR
Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dou t 0 Dou t 1
DM
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 20/48
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column
access is allowed. A write recovery time (tWR) is require d from the last data to precharge command. When precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
Precharge timing for Write operations in DRAMs requir es enough time to allow “Write recovery” which is the time required b y a
DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used
to indicate the required of tim e between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is
sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by s wit ching clock
domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery
parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock
edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during the
time between the last valid write data and the rising clock edge in which the Precharge command is given. Duri ng this time, the
DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
3. For a Wr ite with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where
tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobe s in the
Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as
the earliest possible externa l Precharge command without interrupting the Write burst as described i n 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with
autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command
which does not interrupt the burst.
01 234 5678
COMMAND
DQS
DQ's
DQS
DQ's
NOP NOP NOP NOP NOP Precharge NOP
tDQSSmax
Dina0 Dina1
WRITE A
Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
tDQSSmin
DM
WRITE B
Dinb0
tWR
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1
CLK
CLK
tWR
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 21/48
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
burst stop command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
01 234 5678
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP
Burst Stop
CLK
CLK
CAS Latency=3
DQS
DQ's Dout 0 Dout 1
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issue d on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a W r ite burst is undefined and shall not be use d.
4. BST applies to all burst lengths.
5. BST is an undefine d comma nd during Read with autoprecharg e and sh all not be used.
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 22/48
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, D DR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
01 2345678
COMMAND
tDQSS
DQS
DQ's
DM
WRITE NOP NOP NOP NOP NOP NOP NOP
Din 0
NOP
Din 1 Din 2 Din 3 Din 4 Din 6 Din 7
Din 5
mask ed by DM = H
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 23/48
Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be
delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied.
<Burst Length = 4, CAS Latency = 3>
01234 5678
COMMAND Bank A
ACTIVE NOP NOP NOP NOP NOP NOP NOP
ReadA
Auto Precharge
CLK
CLK
CAS Latency=3
DQS
DQ's Dout 0 Dout 1 Dout 2 Dout 3
tRAP
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
Bank A
ACTIVE NOP NOP NOP NOP NOP NOP NOP
Dout 0 Dout 1
Write A
Auto Pr echar ge
Dout 2 Dout 3
*Bank can be reactivated at
completion of tRP
tWR tRP
Inte
r
nal
p
r
echa
r
g
e sta
r
t
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 24/48
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held lo w with CKE and WE high at the rising edge of
the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the tRFC(min).
A maximum of eight consecutive AUTO REFRSH commands (with tRFC(min)) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH co mmand is 8x15.6μm.
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. Durin g the
self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce
power consumption. The self refresh is exited by suppl ying stable clock input before returning CKE hi gh, asserting deselect or NOP
command and then asserting CKE high for longer than tXSRD for locking of DLL.
Note: After self refresh exit, input an auto refresh command immediate ly.
COMMAND
CKE
tXSNR
Self
Refresh Auto
Refresh Read
tXSRD
CLK
CLK
COMMAND
CKE = High
tRP
PRE Auto
Refresh CMD
tRFC
CLK
CLK
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 25/48
Power down
Power down is entered when CKE is registered lo w (no accesses can be in progress). If po wer-down occurs when all banks ar e
idle, this mode is referred to as prech arge power-down; if power-down occurs when there is a row active in a ny bank, this mode is
referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE.
For maximum power savings, the user has the opti on of dis abli ng the DLL prior to enteri n g po wer-do wn. In that case, the DLL mus t
be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,
power-down duration is limited by the refresh requireme nts of the device, so in most applications, the self-refresh mode is preferred
over the DLL disable po wer-down mode. In the p ower-down, CKE LOW and a sta ble clock signal must be maintained at the in puts
of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is
registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
COMMAND
CKE
CLK
CLK
VALID NOP NOP VALID
Enter power -down
mode
No column
acess
in program
tIS tIS
Exit power-down
mode
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 26/48
Functional Truth Table:
Current CS RAS CAS WE Address Command Action
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA Active Bank Active, Latch RA
L L H L BA, A10 PRE / PREA NOP*4
L L L H X Refresh AUTO-Refresh*5
IDLE
L L L L Op-Code Mode-Add MRS Mode Register Set*5
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop NOP
L H L H BA, CA, A10 READ / READA Begin Read, Latch CA,
Determine Auto -precharge
L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA,
Determine Auto -precharge
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Precharge/Precharge All
L L L H X Refresh ILLEGAL
ROW ACTIVE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA Burst Stop Terminate Burs t
L H L H BA, CA, A10 READ / READA Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X Refresh ILLEGAL
READ
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 27/48
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Continue Burst to end)
L H H H X NOP NOP (Continue Burst to end)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ/READA Terminate Burst With DM=High,
Latch CA, Begin Read, Determine
Auto-Precharge*3
L H L L BA, CA, A10 WRITE/WRITEA Terminate Burst, Latch CA,
Begin new Write, Determine
Auto-Precharge*3
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminal Burst With DM=High,
Precharge
L L L H X Refresh ILLEGAL
WRITE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to end)
L H H H X NOP NOP (Continue Burst to end)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ READ*7
L H L L BA, CA, A10 WRITE ILLEGAL
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
READ with
AUTO
PRECHARGE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ ILLEGAL
L H L L BA, CA, A10 WRITE Write
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
WRITE with
AUTO
PRECHARGE
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 28/48
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ/WRITE ILLEGAL*2
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP)
L L L H X Refresh ILLEGAL
PRE-CHARGIN
G
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (ROW Active after tRCD)
L H H H X NOP NOP (ROW Active after tRCD)
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
ROW
ACTIVATING
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop ILLEGAL*2
L H L H BA, CA, A10 READ ILLEGAL*2
L H L L BA, CA, A10 WRITE WRITE
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
WRITE
RECOVERING
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 29/48
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL
L H L X BA, CA, A10 READ/WRITE ILLEGAL
L L H H BA, RA Active ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X Refresh ILLEGAL
RE-FRESHING
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA Active ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X Refresh ILLEGAL
MODE
REGISTER
SETTING
L L L L Op-Code Mode-Add MRS ILLEGAL
ABBREVIATIONS:
H = High Level, L = Low level, V = Valid, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
Note: 1. All entries assume that CKE was High during the preceding clock cycle and the current clo ck cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL of any bank is not idle.
6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be
performed.
7. Refer to “Read with Auto Precharge: for more detailed information.
ILLEGAL = Device op eration and / or data integrity are not guaranteed.
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Current State CKE
n-1
CKE
n CS RAS CAS WE Add Action
H X X X X X X INVALID
L H H X X X X Exit Self-Refresh
L H L H H H X Exit Self-Refresh
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
SELF-REFRESHING*
1
L L X X X X X NOP (Maintain Self-Refresh)
H X X X X X X INVALID
L H X X X X X Exit Power Down (Idle after tPDEX)
POWER DOWN
L L X X X X X NOP (Maintain Power Down)
H H X X X X X Refer to Function True Table
H L L L L H X Enter Self-Refresh
H L H X X X X Exit Power Down
H L L H H H X Exit Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
ALL BANKS IDLE*2
L L L X X X X Refer to Current State = Power Down
H H X X X X X Refer to Function True Table
ANY STATE other
than listed above
ABBREVIATIONS:
H = High Level, L = Low level, V = Valid, X = Don’t Care
Note: 1. CKE Low to High transition will re-enable CL K, CLK and other i nputs asynchronously. A minimum setup time must be
satisfied before issuing any command oth er than EXIT.
2. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
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M13S64164A
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Revision : 1.4 31/48
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
Note: 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
CKE
CS
RAS
CAS
BA0,BA1
ADDR
(A0~An)
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A10/AP
BAa BAb
Cb
Db0 Db1 Db3
Db2
tCK
tIS
tIH
tDQSCK
tRPRE
tLZ
tDQSQ
tDQSCK
Da0 Da1 Da2 Da3
tRPST
Hi-Z
Hi-Z
tDQSS
tWPREStDQSH
tDQSL
tDS tDH tDS tDH
tWPST Hi-Z
Hi-Z
READ WRITE
CLK
CLK
tCL
tWPRE
BAa
tHP Note1
tHZ
tAC
tQH
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Multi Bank Interleaving READ (@ BL=4, CL=3)
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Revision : 1.4 33/48
Multi Bank Interleaving WRITE (@ BL=4)
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Read with Auto Precharge (@ BL=8)
Note: 1. T he row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=3)
DQ(CL=3)
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa
Qa4 Qa5 Qa7
Qa6
BAa
tRP
Qa0 Qa1 Qa3
Qa2
ACTIVE
READ
Ca
Auto precharge start
Note1
CLK
CLK
Ra
Ra
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Revision : 1.4 35/48
Write with Auto Precharge (@ BL=8)
Note: 1. T he row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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Revision : 1.4 36/48
Read Interrupted by Precharge (@ BL=8)
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Read Interrupted by a Read (@ BL=8, CL=3)
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Revision : 1.4 38/48
Read Interrupted by a Write & Burst stop (@ BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
BAa
Qa0 Qa1
READ
Qb0 Qb5
Qb1 Qb4
Qb3Qb2 Qb6
BAb
Cb
Burst
Stop WRITE
Qb7
CLK
CLK
A10/AP
ADDR
(A0~An) Ca
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Write followed by Precharge (@ BL=4)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa BAa
tWR
Da0 Da1 Da3
Da2
PRE
CHARGE
WRITE
Ca
CLK
CLK
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Write Interrupted by Precharge & DM (@ BL=8)
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Write Interrupted by a Read (@ BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
BAa
tWTR
Da0 Da1 Da3
Da2
WRITE READ
Ca
CLK
CLK
BAb
Cb
Da5
Da4 Qb0 Qb1 Qb3
Qb2 Qb4 Qb5
Maskecd by DM
A10/AP
ADDR
(A0~An)
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DM Function (@ BL=8) only for write
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=3)
DQ(CL=3)
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa
Qa4 Qa5 Qa7
Qa6
Qa0 Qa1 Qa3
Qa2
WRITE
Ca
CLK
CLK
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Power up & Initialization Sequence
CKE
CS
RAS
CAS
A10/AP
Precharge
All Bank
A7
213
4567891011 12 13 14 15 16 17 18 19 20
0
DQ
Precharge
All Bank
BA0
WE
DQS
High-Z
High-Z
High level is required
BA1,A9,A11
A1~A6
A0
ADDRESS KEY
Minimum 200 Cycle
t
RP
t
RC
t
RC
Minimum of 2 Refresh Cycles are required
EMRS
DLL Enable
MRS
DLL Reset
1st Auto Refresh 2nd Auto Refresh Mode Resister Set
Any
Command
:Don'tCare
CLK
CLK
A8
(Power & Clock must be
stablefor200us
before precharge
All Bank)
t
MRD
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M13S64164A
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Revision : 1.4 44/48
Mode Register Set
CKE
CS
RAS
CAS
ADDR
(A0~An)
Precharge
Command
All Bank
DM
DQ
Mode Register Set
Command
Any
Command
BA0,BA1
A10/AP
tCK
WE
DQS
ADDRESS KEY
High-Z
High-Z
tRP
CLK
CLK
tMRD
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
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M13S64164A
Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2009
Revision : 1.4 45/48
PACKING DIMENSIONS
66-LEAD TSOP(II) DRAM(400mil)
Symbol Dimension in inch Dimension in mm
Min Norm Max Min Norm Max
A
0.047
1.2
A1 0.002 0.004 0.006 0.05 0.1 0.15
A2 0.037 0.039 0.041 0.95 1 1.05
b 0.009
0.015 0.22
0.38
b1 0.009 0.012 0.013 0.22 0.3 0.33
c 0.005
0.008 0.12
0.21
c1 0.0047 0.005 0.006 0.12 0.127 0.16
D 0.875 BSC 22.22 BSC
ZD 0.028 REF 0.71 REF
E 0.455 0.463 0.471 11.56 11.76 11.96
E1 0.400 BSC 10.16 BSC
e 0.026 BSC 0.65 BSC
L 0.016 0.02 0.024 0.4 0.5 0.6
L1 0.031 REF 0.80 REF
°θ °0 °8 °0 °8
°θ1 °10 °15 °20 °10 °15 °20
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M13S64164A
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Revision : 1.4 46/48
PACKING DIMENSIONS
60-BALL DDR SDRAM ( 8x13 mm )
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A
1.20
0.047
A1 0.30 0.35 0.40 0.012 0.014 0.016
A2
0.80
0.031
Φb 0.40 0.45 0.50 0.016 0.018 0.020
D 7.90 8.00 8.10 0.311 0.315 0.319
E 12.90 13.00 13.10 0.508 0.512 0.516
D1
6.40
0.252
E1
11.0
0.433
e
0.80
0.031
e1
1.00
0.039
Controlling dimension : Millimeter.
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Revision : 1.4 47/48
Revision History
Revision Date Description
0.1 2006.10.23 Original
0.2 2007.06.06 Add BGA type spec
0.3 2007.07.20 Modify BGA as signment
0.4 2007.10.01 Modify IDD spec
1.0 2007.11.20 Delete “Preliminary”
1.1 2007.12.06 Modif y type err or of tQHS
1.2 2008.02.21 Modify 66-Lead TSOP(II) packing dimension
1.3 2008.09.04
1. Move Revision History to the last
2. Modify tWR and tWTR
1.4 2009.06.10
1. Modify the specification of II
2. Add the specification of IDD0, IDD1, IDD2P, IDD2N,
IDD3P, IDD3N, IDD4R, IDD4W, IDD5, IDD7
3. Add a note of self refresh operation
4. Correct the chart of Power up & Initialization Sequence
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M13S64164A
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Revision : 1.4 48/48
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time
of publication. ESMT assumes no responsibility for any error in this document,
and reserves the right to change the products or specification in this document
without notice.
The information contained herein is presented only as a guide or examples for
the application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but
not limited to, life support devices or system, where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage. If
products described here are to be used for such kinds of application, purchaser
must do its own quality assurance test ing appropriate to such applications.
