Features
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
123 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Non-volatile Program and Data Memories
2/4/8K Byte of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
128/256/512 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
128/256/512 Bytes Internal SRAM
Data retention: 20 years at 85°C / 100 years at 25°C
Programming Lock for Self-Programming Flash Program & EEPROM Data Security
Peripheral Features
8/16-bit Timer/Counter with Prescaler
8/10-bit High Speed Timer/Counter with Separate Prescaler
3 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
10-bit ADC
11 Single-Ended Channels
16 Differential ADC Channel Pairs
15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)
On-chip Analog Comparator
Programmable Watchdog Timer with Separate On-chip Oscillator
Universal Serial Interface with Start Condition Detector
Special Microcontroller Features
debugWIRE On-chip Debug System
In-System Programmable via SPI Port
External and Internal Interrupt Sources
Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes
Enhanced Power-on Reset Circuit
Programmable Brown-out Detection Circuit
Internal Calibrated Oscillator
On-chip Temperature Sensor
I/O and Packages
16 Programmable I/O Lines
Available in 20-pin PDIP, 20-pin SOIC and 32-pad MLF
Operating Voltage:
1.8 – 5.5V for ATtiny261V/461V/861V
2.7 – 5.5V for ATtiny261/461/861
Speed Grade:
ATtiny261V/461V/861V: 0 – 4 MHz @ 1.8 – 5.5V, 0 – 10 MHz @ 2.7 – 5.5V
ATtiny261/461/861: 0 – 10 MHz @ 2.7 – 5.5V, 0 – 20 MHz @ 4.5 – 5.5V
Industrial Temperature Range
Low Power Consumption
Active Mode (1 MHz System Clock): 300 µA @ 1.8V
Power-Down Mode: 0.1 µA at 1.8V
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny261/V
ATtiny461/V
ATtiny861/V
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1. Pin Configurations
Figure 1-1. Pinout ATtiny261/461/861 and ATtiny261V/461V/861V
Note: To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
(MOSI/DI/SDA/OC1A/PCINT8) PB0
(MISO/DO/OC1A/PCINT9) PB1
(SCK/USCK/SCL/OC1B/PCINT10) PB2
(OC1B/PCINT11) PB3
VCC
GND
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
AVCC
PA4 (ADC3/ICP0/PCINT4)
PA5 (ADC4/AIN2/PCINT5)
PA6 (ADC5/AIN0/PCINT6)
PA7 (ADC6/AIN1/PCINT7)
PDIP/SOIC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
NC
(OC1B/PCINT11) PB3
NC
VCC
GND
NC
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
NC
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
NC
NC
AVCC
PA4 (ADC3/ICP0/PCINT4)
NC
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
NC
(ADC6/AIN1/PCINT7) PA7
(ADC5/AIN0/PCINT6) PA6
(ADC4/AIN2/PCINT5) PA5
NC
PB2 (SCK/USCK/SCL/OC1B/PCINT10)
PB1 (MISO/DO/OC1A/PCINT9)
PB0 (MOSI/DI/SDA/OC1A/PCINT8)
NC
NC
NC
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
QFN/MLF
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1.1 Pin Descriptions
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 AVCC
Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC),
the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port
A. It should be externally connected to VCC, even if some peripherals such as the ADC are not
used. If the ADC is used AVCC should be connected to VCC through a low-pass filter.
1.1.4 AGND
Analog ground.
1.1.5 Port A (PA7:PA0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port A also serves the functions of various special features of the device, as listed on page 63.
1.1.6 Port B (PB7:PB0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port B also serves the functions of various special features of the device, as listed on page 66.
1.1.7 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in Table 19-4 on page 190. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
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2. Overview
ATtiny261/461/861 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
PORT A (8)PORT B (8)
USI
Timer/Counter1
Timer/Counter0 A/D Conv.
Internal
Bandgap
Analog Comp.
SRAMFlash
EEPROM
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
VCC
GND
PROGRAM
LOGIC
debugWIRE
AGND
AREF
AVCC
D ATA BU S
PA[0..7]PB[0..7]
11
RESET
XTAL[1..2]
CPU
3
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The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purpose I/O lines, 32
general purpose working registers, an 8-bit Timer/Counter with compare modes, an 8-bit high
speed Timer/Counter, a Universal Serial Interface, Internal and External Interrupts, an 11-chan-
nel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, and four software
selectable power saving modes. Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Power-
down mode saves the register contents, disabling all chip functions until the next Interrupt or
Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined
with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny261/461/861 AVR is supported by a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation
kits.
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3. About
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.
3.3 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
3.4 Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology.
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4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
4.1 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera-
tion, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
directly addressing the whole address space. Most AVR instructions have a single 16-bit word
format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices
only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-
tion. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
4.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
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The Status Register is neither automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt. This must be handled by software.
4.3.1 SREG – AVR Status Register
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
Bit 76543210
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
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4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
4.4.1 The X-register, Y-register, and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These regis-
ters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4-3.
Figure 4-3. The X-, Y-, and Z-registers
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
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In different addressing modes these address registers function as automatic increment and
automatic decrement (see the instruction set reference for details).
4.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present
4.5.1 SPH and SPL — Stack Pointer Register
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
Bit 1514131211109 8
0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
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Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-5. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 50. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
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to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Note: See “Code Examples” on page 6.
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in the following examples.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
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Note: See “Code Examples” on page 6.
4.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clock cycles the Program Vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
C Code Example
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
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5. Memories
This section describes the different memories in the ATtiny261/461/861. The AVR architecture
has two main memory spaces, the Data memory and the Program memory space. In addition,
the ATtiny261/461/861 features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
5.1 In-System Re-programmable Flash Program Memory
The ATtiny261/461/861 contains 2/4/8K byte On-chip In-System Reprogrammable Flash mem-
ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized
as 1024/2048/4096 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATtiny261/461/861 Program Counter (PC) is 10/11/12 bits wide, thus capable of addressing the
1024/2048/4096 Program memory locations. “Memory Programming” on page 170 contains a
detailed description on Flash data serial downloading using the SPI pins.
Constant tables can be allocated within the entire address space of program memory (see the
LPM – Load Program memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 11.
Figure 5-1. Program Memory Map
5.2 SRAM Data Memory
Figure 5-2 on page 16 shows how the ATtiny261/461/861 SRAM Memory is organized.
The lower data memory locations address both the Register File, the I/O memory and the inter-
nal data SRAM. The first 32 locations address the Register File, the next 64 locations the
standard I/O memory, and the last 128/256/512 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
0x0000
0x03FF/0x07FF/0x0FFF
Program Memory
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When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny261/461/861 are all accessible through all these addressing modes.
The Register File is described in “General Purpose Register File” on page 10.
Figure 5-2. Data Memory Map
5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as illustrated in Figure 5-3.
Figure 5-3. On-chip Data SRAM Access Cycles
5.3 EEPROM Data Memory
The ATtiny261/461/861 contains 128/256/512 bytes of data EEPROM memory. It is organized
as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register. For a detailed description of Serial data
downloading to the EEPROM, see “Electrical Characteristics” on page 187.
32 Registers
64 I/O Registers
Internal SRAM
(128/256/512 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x0DF/0x15F/0x25F
0x0060
Data Memory
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Read Write
CPU
Memory Access Instruction Next Instruction
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5.3.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in Table 5-1 on page 22. A self-timing func-
tion, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-
tered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the
device for some period of time to run at a voltage lower than specified as minimum for the clock
frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
5.3.2 Atomic Byte Programming
Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the
user must write the address into the EEARL Register and data into EEDR Register. If the
EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the
erase/write operation. Both the erase and write cycle are done in one operation and the total
programming time is given in Table 5-1 on page 22. The EEPE bit remains set until the erase
and write operations are completed. While the device is busy with programming, it is not possi-
ble to do any other EEPROM operations.
5.3.3 Split Byte Programming
It is possible to split the erase and write cycle in two different operations. This may be useful if
the system requires short access time for some limited period of time (typically if the power sup-
ply voltage falls). In order to take advantage of this method, it is required that the locations to be
written have been erased before the write operation. But since the erase and write operations
are split, it is possible to do the erase operations when the system allows doing time-critical
operations (typically after Power-up).
5.3.4 Erase
To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the
EEPE within four cycles after EEMPE is written will trigger the erase operation only (program-
ming time is given in Table 5-1 on page 22). The EEPE bit remains set until the erase operation
completes. While the device is busy programming, it is not possible to do any other EEPROM
operations.
5.3.5 Write
To write a location, the user must write the address into EEAR and the data into EEDR. If the
EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger
the write operation only (programming time is given in Table 5-1 on page 22). The EEPE bit
remains set until the write operation completes. If the location to be written has not been erased
before write, the data that is stored must be considered as lost. While the device is busy with
programming, it is not possible to do any other EEPROM operations.
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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre-
quency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on
page 32.
5.3.6 Program Examples
The following code examples show one assembly and one C function for erase, write, or atomic
write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling
interrupts globally) so that no interrupts will occur during execution of these functions.
Note: See “Code Examples” on page 6.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set Programming mode
ldi r16, (0<<EEPM1)|(0<<EEPM0)
out EECR, r16
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r19) to data register
out EEDR, r19
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned char ucAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set Programming mode */
EECR = (0<<EEPM1)|(0<<EEPM0);
/* Set up address and data registers */
EEAR = ucAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
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The next code examples show assembly and C functions for reading the EEPROM. The exam-
ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
Note: See “Code Examples” on page 6.
5.3.7 Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low VCC reset protection circuit can
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned char ucAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = ucAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
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be used. If a reset occurs while a write operation is in progress, the write operation will be com-
pleted provided that the power supply voltage is sufficient.
5.4 I/O Memory
The I/O space definition of the ATtiny261/461/861 is shown in “Register Summary” on page 223.
All ATtiny261/461/861 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed using the LD/LDS/LDD and ST/STS/STD instructions, enabling data transfer between
the 32 general purpose working registers and the I/O space. I/O Registers within the address
range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis-
ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O specific commands IN and OUT,
the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space
using LD and ST instructions, 0x20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, the CBI and
SBI instructions will only operate on the specified bit, and can therefore be used on registers
containing such Status Flags. The CBI and SBI instructions work on registers in the address
range 0x00 to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
5.4.1 General Purpose I/O Registers
The ATtiny261/461/861 contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and
Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
5.5 Register Description
5.5.1 EEARH – EEPROM Address Register
Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 0 – EEAR8: EEPROM Address
This is the most significant EEPROM address bit of ATtiny861. In devices with less EEPROM,
i.e. ATtiny261/ATtiny461, this bit is reserved and will always read zero. The initial value of the
EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written
before the EEPROM is accessed.
Bit 76543210
0x1F (0x3F) –––––––EEAR8EEARH
Read/Write RRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 X/0
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5.5.2 EEARL – EEPROM Address Register
Bit 7 – EEAR7: EEPROM Address
This is the most significant EEPROM address bit of ATtiny461. In devices with less EEPROM,
i.e. ATtiny261, this bit is reserved and will always read zero. The initial value of the EEPROM
Address Register (EEAR) is undefined and a proper value must therefore be written before the
EEPROM is accessed.
Bits 6:0 – EEAR6:0: EEPROM Address
These are the (low) bits of the EEPROM Address Register. The EEPROM data bytes are
addressed linearly in the range 0...128/256/512. The initial value of EEAR is undefined and a
proper value must be therefore be written before the EEPROM may be accessed.
5.5.3 EEDR – EEPROM Data Register
Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
5.5.4 EECR – EEPROM Control Register
Bit 7 – Res: Reserved Bit
This bit is reserved for future use and will always read as 0 in ATtiny261/461/861. For compati-
bility with future AVR devices, always write this bit to zero. After reading, mask out this bit.
Bit 6 – Res: Reserved Bit
This bit is reserved in the ATtiny261/461/861 and will always read as zero.
Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
Bit 76543210
0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X/0 X X X X X X X
Bit 76543210
0x1D (0x3D) EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x1C (0x3C) EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 X X 0 0 X 0
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old value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 5-1.
When EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be
reset to 0b00 unless the EEPROM is busy programming.
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when Non-volatile memory is ready for programming.
Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the
selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles.
Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.
The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no
EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared
by hardware. When EEPE has been set, the CPU is halted for two cycles before the next
instruction is executed.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be written to one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed. The user should poll the EEPE bit before starting the read opera-
tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change
the EEAR Register.
5.5.5 GPIOR2 – General Purpose I/O Register 2
Table 5-1. EEPROM Mode Bits
EEPM1 EEPM0
Programming
Time Operation
0 0 3.4 ms Erase and Write in one operation (Atomic Operation)
0 1 1.8 ms Erase Only
1 0 1.8 ms Write Only
1 1 Reserved for future use
Bit 76543210
0x0C (0x2C) MSB LSB GPIOR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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5.5.6 GPIOR1 – General Purpose I/O Register 1
5.5.7 GPIOR0 – General Purpose I/O Register 0
Bit 76543210
0x0B (0x2B) MSB LSB GPIOR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x0A (0x2A) MSB LSB GPIOR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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6. Clock System
Figure 6-1 presents the principal clock systems and their distribution in ATtiny261/461/861. All of
the clocks need not be active at a given time. In order to reduce power consumption, the clocks
to modules not being used can be halted by using different sleep modes, as described in “Power
Management and Sleep Modes” on page 36.
Figure 6-1. Clock Distribution
6.1 Clock Subsystems
The clock subsystems are detailed in the sections below.
6.1.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
6.1.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
General I/O
Modules CPU Core RAM
clkI/O AVR Clock
Control Unit
clkCPU
Flash and
EEPROM
clkFLASH
Source clock
Watchdog Timer
Watchdog
Oscillator
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
Calibrated RC
Oscillator
ADC
clkADC
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
System Clock
Prescaler
PLL
Oscillator
clkPCK
General I/O
Modules
External Clock
clkPLL
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6.1.3 Flash Clock – clkFLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
6.1.4 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
6.1.5 Fast Peripheral Clock – clkPCK
Selected peripherals can be clocked at a frequency higher than the CPU core. The fast periph-
eral clock is generated by an on-chip PLL circuit.
6.1.6 PLL System Clock – clkADC
The PLL can also be used to generate a system clock. The clock signal can be prescaled to
avoid overclocking the CPU.
6.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Note: 1. For all fuses “1” means unprogrammed and “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before com-
Table 6-1. Device Clocking Options Select(1) vs. PB4 and PB5 Functionality
Device Clocking Option CKSEL3:0 PB4 PB5
External Clock (see page 26) 0000 XTAL1 I/O
High-Frequency PLL Clock (see page 26) 0001 I/O I/O
Calibrated Internal 8 MHz Oscillator (see page 28) 0010 I/O I/O
Internal 128 kHz Oscillator (see page 29) 0011 I/O I/O
Low-Frequency Crystal Oscillator (see page 29) 01xx XTAL1 XTAL2
Crystal Oscillator / Ceramic Resonator
0.4...0.9 MHz (see page 30)
1000
1001 XTAL1 XTAL2
Crystal Oscillator / Ceramic Resonator
0.9...3.0 MHz (see page 30)
1010
1011 XTAL1 XTAL2
Crystal Oscillator / Ceramic Resonator
3...8 MHz (see page 30)
1100
1101 XTAL1 XTAL2
Crystal Oscillator / Ceramic Resonator
8...20 MHz (see page 30)
1110
1111 XTAL1 XTAL2
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mencing normal operation. The watchdog oscillator is used for timing this real-time part of the
start-up time. The number of WD oscillator cycles used for each time-out is shown in Table 6-2.
6.2.1 External Clock
To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-
2. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 6-2. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-3.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the system clock prescaler can be used to implement run-time changes of the internal
clock frequency. See “System Clock Prescaler” on page 31 for details.
6.2.2 High-Frequency PLL Clock
The internal PLL generates a clock signal with a frequency eight times higher than the source
input. The PLL uses the output of the internal 8 MHz oscillator as source and the default setting
generates a fast peripheral clock signal of 64 MHz.
Table 6-2. Number of Watchdog Oscillator Cycles
Typ Time-out Number of Cycles
4 ms 512
64 ms 8K (8,192)
Table 6-3. Start-up Times for the External Clock Selection
SUT1:0
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset Recommended Usage
00 6 CK 14CK BOD enabled
01 6 CK 14CK + 4 ms Fast rising power
10 6 CK 14CK + 64 ms Slowly rising power
11 Reserved
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The fast peripheral clock, clkPCK, can be selected as the clock source for Timer/Counter1 and a
prescaled version of the PLL output, clkPLL, can be selected as system clock. See Figure 6-3 for
a detailed illustration on the PLL clock system.
Figure 6-3. PCK Clocking System
The internal PLL is enabled when CKSEL fuse bits are programmed to ‘0001’and the PLLE bit of
PLLCSR is set. The internal oscillator and the PLL are switched off in power down and stand-by
sleep modes.
When the LSM bit of PLLCSR is set, the PLL switches from using the output of the internal 8
MHz oscillator to using the output divided by two. The frequency of the fast peripheral clock is
effectively divided by two, resulting in a clock frequency of 32 MHz. The LSM bit can not be set if
PLLCLK is used as a system clock.
Since the PLL is locked to the output of the internal 8 MHz oscillator, adjusting the oscillator fre-
quency via the OSCCAL register also changes the frequency of the fast peripheral clock. It is
possible to adjust the frequency of the internal oscillator to well above 8 MHz but the fast periph-
eral clock will saturate and remain oscillating at about 85 MHz. In this case the PLL is no longer
locked to the internal oscillator clock signal. Therefore, in order to keep the PLL in the correct
operating range, it is recommended to program the OSCCAL registers such that the oscillator
frequency does not exceed 8 MHz.
The PLOCK bit in PLLCSR is set when PLL is locked.
Programming CKSEL fuse bits to ‘0001’, the PLL output divided by four will be used as a system
clock, as shown in Table 6-4.
Table 6-4. PLLCK Operating Modes
CKSEL3:0 Nominal Frequency
0001 16 MHz
1/2
8 MHz
LSM
8 MHz
OSCILLATOR PLL
8x
CKSEL3:0PLLEOSCCAL
4 MHz
1/4
LOCK
DETECTOR
PRESCALER
CLKPS3:0
clkPLL
PLOCK
clkPCK
OSCILLATORS
XTAL1
XTAL2
64 / 32 MHz
8 MHz
16 MHz
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When the PLL output is selected as clock source, the start-up times are determined by SUT fuse
bits as shown in Table 6-5.
6.2.3 Calibrated Internal 8 MHz Oscillator
By default, the Internal Oscillator provides an approximately 8 MHz clock signal. Though voltage
and temperature dependent, this clock can be very accurately calibrated by the user. See Table
19-2 on page 189 and “Internal Oscillator Speed” on page 216 for more details. The device is
shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 31 for
more details.
This clock may be selected as the system clock by programming the CKSEL Fuses as shown in
Table 6-6. If selected, it will operate with no external components. During reset, hardware loads
the pre-programmed calibration value into the OSCCAL Register and thereby automatically cal-
ibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in
Table 19-2 on page 189.
Notes: 1. The device is shipped with this option selected.
2. If the oscillator frequency exceeds the specification of the device (depends on VCC), the
CKDIV8 Fuse can be programmed to divide the internal frequency by 8.
When this oscillator is selected, start-up times are determined by SUT fuses as shown in Table
6-7.
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
2. The device is shipped with this option selected.
Table 6-5. Start-up Times for the PLLCK
SUT1:0
Start-up Time from
Power Down
Additional Delay from
Power-On-Reset (VCC = 5.0V)
Recommended
usage
00 14CK + 1K (1024) + 4 ms 4 ms BOD enabled
01 14CK + 16K (16384) + 4 ms 4 ms Fast rising power
10 14CK + 1K (1024) + 64 ms 4 ms Slowly rising power
11 14CK + 16K (16384) + 64 ms 4 ms Slowly rising power
Table 6-6. Internal Calibrated RC Oscillator Operating Modes
CKSEL3:0 Nominal Frequency
0010 (1) 8.0 MHz (2)
Table 6-7. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
SUT1:0
Start-up Time
from Power-down
Additional Delay from
Reset (VCC = 5.0V)
Recommended
Usage
00 6 CK 14CK(1) BOD enabled
01 6 CK 14CK + 4 ms Fast rising power
10(2) 6 CK 14CK + 64 ms Slowly rising power
11 Reserved
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It is possible to reach a higher accuracy than factory calibration by changing the OSCCAL regis-
ter from software. See “OSCCAL – Oscillator Calibration Register” on page 32. The accuracy of
this calibration is shown as User calibration in Table 19-2 on page 189.
When this oscillator is used as device clock, the Watchdog Oscillator will still be used for the
Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-
bration value, see section “Calibration Byte” on page 173.
6.2.4 Internal 128 kHz Oscillator
The 128 kHz internal oscillator is a low power oscillator providing a clock of 128 kHz. The fre-
quency depends on supply voltage, temperature and batch variations. This clock may be select
as the system clock by programming the CKSEL Fuses to “0011”.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-8.
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
6.2.5 Low-Frequency Crystal Oscillator
To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal
oscillator must be selected by setting CKSEL fuses to ‘0100’. The crystal should be connected
as shown in Figure 6-4. To find suitable capacitors please consult the manufacturer’s datasheet.
When this oscillator is selected, start-up times are determined by the SUT fuses as shown in
Table 6-9.
Notes: 1. These options should be used only if frequency stability at start-up is not important.
The Low-frequency Crystal Oscillator provides an internal load capacitance, see Table 6-10 at
each TOSC pin.
Table 6-8. Start-up Times for the 128 kHz Internal Oscillator
SUT1:0
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset Recommended Usage
00 6 CK 14CK(1) BOD enabled
01 6 CK 14CK + 4 ms Fast rising power
10 6 CK 14CK + 64 ms Slowly rising power
11 Reserved
Table 6-9. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
SUT1:0
Start-up Time
from Power Down
Additional Delay
from Reset Recommended usage
00 1K (1024) CK(1) 4 ms Fast rising power or BOD enabled
01 1K (1024) CK(1) 64 ms Slowly rising power
10 32K (32768) CK 64 ms Stable frequency at start-up
11 Reserved
Table 6-10. Capacitance for Low-Frequency Crystal Oscillator
Device 32 kHz Osc. Type Cap (Xtal1/Tosc1) Cap (Xtal2/Tosc2)
ATtiny261/461/861 System Osc. 16 pF 6 pF
30
2588E–AVR–08/10
ATtiny261/461/861
6.2.6 Crystal Oscillator / Ceramic Resonator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-
figured for use as an On-chip Oscillator, as shown in Figure 6-4. Either a quartz crystal or a
ceramic resonator may be used.
Figure 6-4. Crystal Oscillator Connections
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 6-11. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Notes: 1. This option should not be used with crystals, only with ceramic resonators.
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by fuses CKSEL3:1 as shown in Table 6-11.
The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in Table
6-12.
Table 6-11. Crystal Oscillator Operating Modes
CKSEL3:1 Frequency Range (MHz) Recommended C1 and C2 Value (pF)
100(1) 0.4 - 0.9
101 0.9 - 3.0 12 - 22
110 3.0 - 8.0 12 - 22
111 8.0 - 12 - 22
Table 6-12. Start-up Times for the Crystal Oscillator Clock Selection
CKSEL0 SUT1:0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
0 00 258 CK(1) 14CK + 4 ms Ceramic resonator,
fast rising power
0 01 258 CK(1) 14CK + 64 ms Ceramic resonator,
slowly rising power
0 10 1K (1024) CK(2) 14CK Ceramic resonator,
BOD enabled
XTAL2
XTAL1
GND
C2
C1
31
2588E–AVR–08/10
ATtiny261/461/861
Notes: 1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
6.2.7 Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal Oscillator running at 8 MHz with longest start-up
time and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or High-voltage Programmer.
For low-voltage devices (ATtiny261V/461V/861V) it should be noted that unprogramming the
CKDIV8 fuse may result in overclocking. At low voltages (below 2.7V) the devices are rated for
maximum 4 MHz operation (see Section 19.3 on page 188), but routing the clock signal from the
internal oscillator directly to the system clock line will run the device at 8 MHz.
6.3 System Clock Prescaler
The ATtiny261/461/861 system clock can be divided by setting the “CLKPR – Clock Prescale
Register” on page 32. This feature can be used to decrease power consumption when the
requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU,
and clkFLASH are divided by a factor as shown in Table 6-13 on page 34.
6.3.1 Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
0 11 1K (1024)CK(2) 14CK + 4 ms Ceramic resonator,
fast rising power
1 00 1K (1024)CK(2) 14CK + 64 ms Ceramic resonator,
slowly rising power
1 01 16K (16384) CK 14CK Crystal Oscillator,
BOD enabled
1 10 16K (16384) CK 14CK + 4 ms Crystal Oscillator,
fast rising power
1 11 16K (16384) CK 14CK + 64 ms Crystal Oscillator,
slowly rising power
Table 6-12. Start-up Times for the Crystal Oscillator Clock Selection (Continued)
CKSEL0 SUT1:0
Start-up Time from
Power-down and
Power-save
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage