CD74LPT827 S E M I C O N D U C T O R Fast CMOS 3.3V 10-Bit Buffer December 1996 Features Description * Advanced 0.6 micron CMOS Technology The CD74LPT827 is a 10-bit wide non-inverting bus driver providing high-performance bus interface buffering for wide address/data paths or buses carrying parity. The 10-bit buffers have NAND-ed output enables for maximum control flexibility. They are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. * Compatible with LCXTM Families of Products * Supports 5V Tolerant Mixed Signal Mode Operation - Input Can Be 3V or 5V - Output Can Be 3V or Connected to 5V Bus * Advanced Low Power CMOS Operation The CD74LPT827 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system. * Excellent Output Drive Capability: - Balanced Drives (24mA Sink and Source) * Low Ground Bounce Outputs Ordering Information * Hysteresis on All Inputs TEMP. RANGE (oC) PACKAGE CD74LPT827AQM -40 to 85 24 Ld QSOP M24.15-P CD74LPT827BQM -40 to 85 24 Ld QSOP M24.15-P CD74LPT827CQM -40 to 85 24 Ld QSOP M24.15-P CD74LPT827AM -40 to 85 24 Ld SOIC M24.3-P CD74LPT827BM -40 to 85 24 Ld SOIC M24.3-P CD74LPT827CM -40 to 85 24 Ld SOIC M24.3-P PART NUMBER PKG. NO. NOTE: QSOP is commonly known as SSOP. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. Pinout CD74LPT827 (QSOP, SOIC) TOP VIEW 24 VCC OE1 1 D0 2 23 Y0 D1 3 22 Y1 D2 4 21 Y2 D3 5 20 Y3 D4 6 19 Y4 D5 7 18 Y5 D6 8 17 Y6 D7 9 16 Y7 D8 10 15 Y8 D9 11 14 Y9 13 OE2 DQ1 12 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1996 3-123 File Number 4258 CD74LPT827 Functional Block Diagram Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OE1 OE2 TRUTH TABLE (NOTE 1) INPUTS FUNCTION OE1 OE2 DN YN L L L L L L H H H X X Z X H X Z Transparent Three-State NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care Z = High Impedance Pin Description PIN NAME OUTPUT DESCRIPTION OEN Output Enable Input (Active LOW) D 0 - D9 10-Bit Data Inputs Y 0 - Y9 10-Bit Data Outputs GND Ground VCC Power 3-124 CD74LPT827 Absolute Maximum Ratings Thermal Information DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120mA Thermal Resistance (Typical, Note 2) JA (oC/W) QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage to Ground Potential Inputs and VCC Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V Supply Voltage to Ground Potential Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER (NOTE 3) TEST CONDITIONS SYMBOL MIN (NOTE 4) TYP MAX UNITS DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40oC to 85oC, VCC = 2.7V to 3.6V Input HIGH Voltage (Input Pins) VIH Guaranteed Logic HIGH Level 2.2 - 5.5 V Input HIGH Voltage (I/O Pins) VIH Guaranteed Logic HIGH Level 2.0 - 5.5 V Input LOW Voltage (Input and I/O Pins) VIL Guaranteed Logic LOW Level -0.5 - 0.8 V Input HIGH Current (Input Pins) IIH VCC = Max VIN = 5.5V - - 5 A Input HIGH Current (I/O Pins) IIH VCC = Max VIN = VCC - - 5 A Input LOW Current (Input Pins) IIL VCC = Max VIN = GND - - 5 A Input LOW Current (I/O Pins) IIL VCC = Max VIN = GND - - 5 A High Impedance Output Current (Three-State Output Pins) IOZH VCC = Max VOUT = 5.5V - - 5 A IOZL VCC = Max VOUT = GND - - 5 A Clamp Diode Voltage VIK VCC = Min, IIN = -18mA - -0.7 -1.2 V Output HIGH Current IODH VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (Note 5) -36 -60 -110 mA Output LOW Current IODL VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (Note 5) 50 90 200 mA Output HIGH Voltage VOH VCC = Min, VIN = VIH or VIL VCC - 0.2 - - V IOH = -3mA 2.4 3.0 - V IOH = -8mA 2.4 (Note 7) 3.0 - V IOH = -24mA 2.0 - - V IOL = 0.1mA - - 0.2 V IOL = 16mA - 0.2 0.4 V IOL = 24mA - 0.3 0.5 V IOH = -0.1mA VCC = 3.0V, VIN = VIH or VIL Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL 3-125 CD74LPT827 Electrical Specifications PARAMETER (Continued) (NOTE 3) TEST CONDITIONS MIN (NOTE 4) TYP MAX UNITS -60 -85 -240 mA - - 100 A - 150 - mV VIN = 0V - 4.5 6 pF VOUT = 0V - 5.5 8 pF SYMBOL Short Circuit Current (Note 6) IOS VCC = Max (Note 5), VOUT = GND Power Down Disable IOFF VCC = 0V, VIN or VOUT 4.5V Input Hysteresis VH CAPACITANCE TA = 25oC, f = 1MHz Input Capacitance (Note 8) Output Capacitance (Note 8) CIN COUT POWER SUPPLY SPECIFICATIONS ICC VCC = Max VIN = GND or VCC - 0.1 10 A Quiescent Power Supply Current TTL Inputs HIGH ICC VCC = Max VIN = VCC - 0.6V (Note 9) - 2.0 30 A Dynamic Power Supply (Note 10) ICCD VCC = Max, Outputs Open OEX = GND One Bit Toggling 50% Duty Cycle VIN = VCC VIN = GND - 50 75 A/ MHz VCC = Max, Outputs Open fI = 10MHz, 50% Duty Cycle OEX = GND One Bit Toggling VIN = VCC - 0.6V VIN = GND - 0.6 2.3 mA VCC = Max, Outputs Open fI = 2.5MHz, 50% Duty Cycle OEX = GND 10 Bits Toggling VIN = VCC - 0.6V VIN = GND - 2.1 4.7 (Note 11) mA Quiescent Power Supply Current Total Power Supply Current (Note 12) IC 3-126 CD74LPT827 Switching Specifications Over Operating Range (NOTE 13) PARAMETER SYMBOL Propagation Delay DXX to YX tPLH, tPHL Output Enable Time OEX to YX Output Disable Time (Note 16) OEX to YX CD74LPT16827A (NOTE 14) TEST (NOTE 15) CONDITIONS MIN MAX CL = 50pF RL = 500 CD74LPT16827B CD74LPT16827C (NOTE 15) MIN MAX (NOTE 15) MIN MAX UNITS 1.5 6.5 1.5 5.0 1.5 4.4 ns tPZH, tPZL 1.5 9.5 1.5 8.0 1.5 7.0 ns tPHZ, tPLZ 1.5 8.5 1.5 6.0 1.5 5.7 ns NOTES: 3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type. 4. Typical values are at VCC = 3.3V, 25oC ambient and maximum loading. 5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 6. This parameter is guaranteed but not tested. 7. VOH = VCC - 0.6V at rated current. 8. This parameter is determined by device characterization but is not production tested. 9. Per TTL driven input; all other inputs at VCC or GND. 10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current (ICCL,ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 13. Propagation Delays and Enable/Disable times are with VCC = 3.3V 0.3V, normal range. For VCC = 2.7V, extended range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 14. See test circuit and wave forms. 15. Minimum limits are guaranteed but not tested on Propagation Delays. 16. This parameter is guaranteed but not production tested. 3-127 CD74LPT827 Test Circuits and Waveforms 6V VCC SWITCH POSITION OPEN GND 500 PULSE GENERATOR VIN TEST SWITCH tPLZ, tPZL, Open Drain 6V tPHZ, tPZH GND tPLH, tPHL Open VOUT DUT 50pF CL RT 500 DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. NOTE: 17. Pulse Generator for All Pulses: Rate 1.0MHz; ZOUT 50; tf, tr 2.5ns. FIGURE 1. TEST CIRCUIT ENABLE DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 0V tPLZ tPZL tPLH 3V OUTPUT NORMALLY LOW SWITCH 6V OUTPUT NORMALLY HIGH SWITCH GND tPHL 3V VOH 1.5V 0.3V tPZH 1.5V tPHZ 0.3V 1.5V VOL OUTPUT VOL tPLH VOH tPHL 3V 1.5V OPPOSITE PHASE INPUT TRANSITION 0V 0V 0V 1.5V 0V FIGURE 3. PROPAGATION DELAY FIGURE 2. ENABLE AND DISABLE TIMING All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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