SEMICONDUCTOR
3-123
December 1996
CD74LPT827
Fast CMOS 3.3V 10-Bit Buffer
Features
• Advanced 0.6 micron CMOS Technology
• Compatible with LCX™ Families of Products
• Supports 5V Tolerant Mixed Signal Mode Operation
- Input Can Be 3V or 5V
- Output Can Be 3V or Connected to 5V Bus
• Advanced Low Power CMOS Operation
• Excellent Output Drive Capability:
- Balanced Drives (24mA Sink and Source)
• Low Ground Bounce Outputs
• Hysteresis on All Inputs
Description
The CD74LPT827 is a 10-bit wide non-inverting bus driver
providing high-performance bus interface buffering for wide
address/data paths or buses carrying parity. The 10-bit buff-
ers have NAND-ed output enables for maximum control flex-
ibility. They are designed for high-capacitance load drive
capability, while providing low-capacitance bus loading at
both inputs and outputs.
The CD74LPT827 can be driven from either 3.3V or 5.0V
devices allowing this device to be used as a translator in a
mixed 3.3/5.0V system.
Pinout
Ordering Information
PART NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG.
NO.
CD74LPT827AQM -40 to 85 24 Ld QSOP M24.15-P
CD74LPT827BQM -40 to 85 24 Ld QSOP M24.15-P
CD74LPT827CQM -40 to 85 24 Ld QSOP M24.15-P
CD74LPT827AM -40 to 85 24 Ld SOIC M24.3-P
CD74LPT827BM -40 to 85 24 Ld SOIC M24.3-P
CD74LPT827CM -40 to 85 24 Ld SOIC M24.3-P
NOTE: QSOP is commonly known as SSOP.
When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CD74LPT827
(QSOP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
OE1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DQ1
16
17
18
19
20
21
22
23
24
15
14
13
VCC
Y1
Y2
Y3
Y4
Y6
Y8
Y9
OE2
Y0
Y5
Y7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996 File Number 4258
3-124
Functional Block Diagram
TRUTH TABLE (NOTE 1)
Pin Description
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OE1OE2
FUNCTION
INPUTS OUTPUT
OE1OE2DNYN
Transparent LLLL
LLHH
Three-State H X X Z
XHXZ
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
Z = High Impedance
PIN NAME DESCRIPTION
OENOutput Enable Input (Active LOW)
D0 - D910-Bit Data Inputs
Y0 - Y910-Bit Data Outputs
GND Ground
VCC Power
CD74LPT827
3-125
Absolute Maximum Ratings Thermal Information
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120mA
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage to Ground Potential
Inputs and VCC Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Thermal Resistance (Typical, Note 2) θJA (oC/W)
QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYMBOL (NOTE 3)
TEST CONDITIONS MIN (NOTE 4)
TYP MAX UNITS
DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40oC to 85oC, VCC = 2.7V to 3.6V
Input HIGH Voltage
(Input Pins) VIH Guaranteed Logic HIGH Level 2.2 - 5.5 V
Input HIGH Voltage
(I/O Pins) VIH Guaranteed Logic HIGH Level 2.0 - 5.5 V
Input LOW Voltage
(Input and I/O Pins) VIL Guaranteed Logic LOW Level -0.5 - 0.8 V
Input HIGH Current
(Input Pins) IIH VCC = Max VIN = 5.5V - - ±5µA
Input HIGH Current
(I/O Pins) IIH VCC = Max VIN = VCC --±5µA
Input LOW Current
(Input Pins) IIL VCC = Max VIN = GND - - ±5µA
Input LOW Current
(I/O Pins) IIL VCC = Max VIN = GND - - ±5µA
High Impedance
Output Current
(Three-State Output
Pins)
IOZH VCC = Max VOUT = 5.5V - - ±5µA
IOZL VCC = Max VOUT = GND - - ±5µA
Clamp Diode Voltage VIK VCC = Min, IIN = -18mA - -0.7 -1.2 V
Output HIGH Current IODH VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (Note 5) -36 -60 -110 mA
Output LOW Current IODL VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (Note 5) 50 90 200 mA
Output HIGH Voltage VOH VCC = Min, VIN = VIH or VIL IOH = -0.1mA VCC - 0.2 - - V
IOH = -3mA 2.4 3.0 - V
VCC = 3.0V, VIN = VIH or VIL IOH = -8mA 2.4
(Note 7) 3.0 - V
IOH = -24mA 2.0 - - V
Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 0.1mA - - 0.2 V
IOL = 16mA - 0.2 0.4 V
IOL = 24mA - 0.3 0.5 V
CD74LPT827
3-126
Short Circuit Current
(Note 6) IOS VCC = Max (Note 5), VOUT = GND -60 -85 -240 mA
Power Down Disable IOFF VCC = 0V, VIN or VOUT ≤4.5V - - ±100 µA
Input Hysteresis VH- 150 - mV
CAPACITANCE TA = 25oC, f = 1MHz
Input Capacitance
(Note 8) CIN VIN = 0V - 4.5 6 pF
Output Capacitance
(Note 8) COUT VOUT = 0V - 5.5 8 pF
POWER SUPPLY SPECIFICATIONS
Quiescent Power
Supply Current ICC VCC = Max VIN = GND
or VCC - 0.1 10 µA
Quiescent Power
Supply Current TTL
Inputs HIGH
∆ICC VCC = Max VIN = VCC - 0.6V
(Note 9) - 2.0 30 µA
Dynamic Power
Supply
(Note 10)
ICCD VCC = Max, Outputs Open
OEX = GND
One Bit Toggling
50% Duty Cycle
VIN = VCC
VIN = GND -5075µA/
MHz
Total Power Supply
Current (Note 12) ICVCC = Max, Outputs Open
fI = 10MHz, 50% Duty Cycle
OEX = GND
One Bit Toggling
VIN = VCC - 0.6V
VIN = GND - 0.6 2.3 mA
VCC = Max, Outputs Open
fI = 2.5MHz, 50% Duty Cycle
OEX = GND
10 Bits Toggling
VIN = VCC - 0.6V
VIN = GND - 2.1 4.7
(Note 11) mA
Electrical Specifications (Continued)
PARAMETER SYMBOL (NOTE 3)
TEST CONDITIONS MIN (NOTE 4)
TYP MAX UNITS
CD74LPT827
3-127
Switching Specifications Over Operating Range (NOTE 13)
PARAMETER SYMBOL
(NOTE 14)
TEST
CONDITIONS
CD74LPT16827A CD74LPT16827B CD74LPT16827C
UNITS
(NOTE 15)
MIN MAX (NOTE 15)
MIN MAX (NOTE 15)
MIN MAX
Propagation Delay
DXX to YXtPLH,
tPHL CL = 50pF
RL = 500Ω1.5 6.5 1.5 5.0 1.5 4.4 ns
Output Enable Time
OEX to YXtPZH,
tPZL 1.5 9.5 1.5 8.0 1.5 7.0 ns
Output Disable Time
(Note 16)
OEX to YX
tPHZ,
tPLZ 1.5 8.5 1.5 6.0 1.5 5.7 ns
NOTES:
3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.
4. Typical values are at VCC = 3.3V, 25oC ambient and maximum loading.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
6. This parameter is guaranteed but not tested.
7. VOH = VCC - 0.6V at rated current.
8. This parameter is determined by device characterization but is not production tested.
9. Per TTL driven input; all other inputs at VCC or GND.
10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
12. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current (ICCL,ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
13. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, normal range. For VCC = 2.7V, extended range, all Propaga-
tion Delays and Enable/Disable times should be degraded by 20%.
14. See test circuit and wave forms.
15. Minimum limits are guaranteed but not tested on Propagation Delays.
16. This parameter is guaranteed but not production tested.
CD74LPT827
3-128
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems cer tification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which ma y result from its use . No license is g r anted b y implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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FAX: (65) 748-0400
SEMICONDUCTOR
Test Circuits and Waveforms
NOTE:
17. Pulse Generator for All Pulses: Rate ≤1.0MHz; ZOUT ≤50Ω;
tf, tr≤ 2.5ns. FIGURE 1. TEST CIRCUIT
FIGURE 2. ENABLE AND DISABLE TIMING FIGURE 3. PROPAGATION DELAY
DUT
PULSE
GENERATOR
RTCL
50pF
VCC
VOUT
6V
500Ω
VIN 500Ω
OPEN
GND
SWITCH POSITION
TEST SWITCH
tPLZ, tPZL, Open Drain 6V
tPHZ, tPZH GND
tPLH, tPHL Open
DEFINITIONS:
CL = Load capacitance, includes jig and probe capacitance.
RT = Termination resistance, should be equal to Z OUT of the
Pulse Generator.
3V
1.5V
0V
CONTROL INPUT
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH SWITCH
GND
tPZL 3V
1.5V
1.5V
0V
tPLZ
tPHZ
tPZH
0V
3V
0.3V
0.3V
VOL
VOH
SWITCH
6V
ENABLE DISABLE
1.5V
3V
0V
1.5V
3V
0V
tPLH
SAME PHASE
INPUT TRANSITION
tPHL
tPLH tPHL
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT 1.5V
VOH
VOL
CD74LPT827
