800 MHz, Linear-in-dB
VGA with AGC Detector
Data Sheet
AD8368
Rev. C Document Feedback
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FEATURES
Analog variable gain range: −12 dB to +22 dB
Linear-in-dB scaling: 37.5 dB/V
3 dB bandwidth: 800 MHz @ VGAIN = 0.5 V
Integrated rms detector
P1dB: 16 dBm @ 140 MHz
Output IP3: 33 dBm @ 140 MHz
Noise figure at maximum gain: 9.5 dB @ 140 MHz
Input and output impedances: 50 Ω
Single-supply voltage from 4.5 V to 5.5 V
RoHS-compliant, 24-lead LFCSP
APPLICATIONS
Complete IF AGC amplifiers
Gain trimming and leveling
Cellular base stations
Point-to-point radio links
RF instrumentation
FUNCTIONAL BLOCK DIAGRAM
05907-001
9
VPSO
11
VPSI
12
VPSI
22
VPSI
23
VPSI
13
VPSI
24 ENBL
8OUTP
3HPFL
4DECL
14 DECL
15 DECL
20
ICOM
18
ICOM
17
ICOM
19
INPT
7
OCOM
1
GAIN
6
OCOM
16
ICOM
10
VPSO
21
MODE
2
DETO
5
DETI
REF
X2
–
+
AD8368
ATTENUATOR LADDER
DECL
50Ω
0dB –2dB –4dB –36dB
GAIN INTERPOLATOR
gmSTAGES
FIXED-GAIN
AMPLIFIER
OUTPUT
BUFFER
Figure 1.
GENERAL DESCRIPTION
The AD8368 is a variable gain amplifier (VGA) with analog
linear-in-dB gain control that can be used from low frequencies
to 800 MHz. Its excellent gain range, conformance, and flatness
are attributed to the Analog Devices, Inc., X-AMP® architecture,
an innovative technique for implementing high performance
variable gain control.
The gain range of −12 dB to +22 dB is scaled accurately to
37.5 dB/V with excellent conformance error. The AD8368 has
a 3 dB bandwidth of 800 MHz that is nominally independent
of gain setting. At 140 MHz, the OIP3 is 33 dBm at maximum
gain. The output noise floor is −143 dBm/Hz, which corresponds
to a 9.5 dB noise figure at maximum gain. The single-ended
input and output impedances are nominally 50 Ω.
The gain of the AD8368 can be configured to be an increasing
or decreasing function of the gain control voltage depending
on whether the MODE pin is pulled to the positive supply or
to ground, respectively. When MODE is pulled high, the
AD8368 operates as a typical VGA with increasing gain.
By connecting MODE to ground and using the on-board rms
detector, the AD8368 can be configured as a complete
automatic gain control (AGC) system with RSSI. The output
power is accurately leveled to the internal default setpoint of
63 mV rms (−11 dBm referenced to 50 Ω), independent of the
waveform crest factor. Because the uncommitted detector
input is available at DETI, the AGC loop can level the signal at
the AD8368 output or at any other point in the signal chain
over a maximum input power range of 34 dB. Furthermore, the
setpoint level can be raised by dividing down the output signal
before applying it to the detector.
The AD8368 operates from a supply voltage of 4.5 V to 5.5 V
and consumes 60 mA of current. It can be fully powered down
to <3 mA by grounding the ENBL pin. The AD8368 is fabricated
using the Analog Devices proprietary SiGe SOI complementary
bipolar IC process. It is available in a 24-lead LFCSP and
operates over the industrial temperature range of −40°C to
+85°C. Application boards are available upon request.
AD8368 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features ............................................................................................ 1
Applications ..................................................................................... 1
Functional Block Diagram ............................................................ 1
General Description ....................................................................... 1
Revision History ............................................................................. 2
Specifications ................................................................................... 3
Absolute Maximum Ratings .......................................................... 5
ESD Caution ................................................................................ 5
Pin Configuration and Function Descriptions ........................... 6
Typical Performance Characteristics ........................................... 7
Circuit Description ....................................................................... 12
Input Attenuator and Interpolator ......................................... 12
Fixed-Gain Stage and Output Buffer ..................................... 12
Output Offset Correction........................................................ 12
Input and Output Impedances ............................................... 12
Gain Control Interface ............................................................ 13
Applications Information ............................................................ 14
VGA Operation ........................................................................ 14
AGC Operation ........................................................................ 14
Stability and Layout Considerations ...................................... 16
Evaluation Board .......................................................................... 17
Outline Dimensions ..................................................................... 19
Ordering Guide ........................................................................ 19
REVISION HISTORY
9/2017—Rev. B to Rev. C
Changed CP-24-3 to CP-24-7 ...................................... Throughout
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
9/2008—Rev. A to Rev. B
Added Stability and Layout Considerations Section ................. 16
Changes to Evaluation Board Section, Figure 40, and
Table 6 .............................................................................................. 17
Added Figure 41, Figure 42, Figure 43, and Figure 44;
Renumbered Sequentially .............................................................. 18
Added Exposed Pad Notation to Outline Dimensions ............. 19
10/2007—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Figure 4 to Figure 6 ...................................................... 7
Changes to Figure 16 ........................................................................ 9
Changes to Figure 31 ...................................................................... 12
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
4/2006—Revision 0: Initial Version
Data Sheet AD8368
Rev. C | Page 3 of 20
SPECIFICATIONS
VS = 5 V, TA = 25°C, system impedance Z0 = 50 Ω, VMODE = 5 V, RF input = 140 MHz, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
OVERALL FUNCTION
Frequency Range LF 800 MHz 3 dB bandwidth
Maximum Input 3 VP To avoid input overload
Maximum Output
1
2
V
P
To avoid clipping
AC Input Impedance
50
Ω
From INPT to ICOM
AC Output Impedance 50 Ω From OUTP to OCOM
GAIN CONTROL INTERFACE (GAIN)
Gain Span 34 dB
Gain Scaling 37.5 dB/V VMODE = 5 V, 50 mV ≤ VGAIN ≤ 950 mV
−38 dB/V VMODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV
Gain Accuracy ±0.4 dB 100 mV ≤ VGAIN ≤ 900 mV
Maximum Gain 22 dB VGAIN = 1 V
Minimum Gain −12 dB VGAIN = 0 V
VGAIN Range 0 1 V
Gain Step Response 100 ns For 6 dB gain step
Gain Input Bias Current −2 µA
f = 70 MHz
Noise Figure 9.5 dB Maximum gain
Output IP3 34 dBm f1 = 70 MHz, f2 = 71 MHz, VGAIN = 1 V, 0 dBm per output tone
Output P1dB1 16 dBm VGAIN = 0 V, VMODE = 0 V
f = 140 MHz
Noise Figure 9.5 dB Maximum gain
Output IP3
33
dBm
f
1
= 140 MHz, f
2
= 141 MHz, V
GAIN
= 1 V, 0 dBm per output tone
Output P1dB1 16 dBm VGAIN = 0 V, VMODE = 0 V
f = 240 MHz
Noise Figure 9.7 dB Maximum gain
Output IP3 33 dBm f1 = 240 MHz, f2 = 241 MHz, VGAIN = 1 V, 0 dBm per output tone
Output P1dB1 15 dBm VGAIN = 0 V, VMODE = 0 V
f = 380 MHz
Noise Figure 10 dB Maximum gain
Output IP3 29 dBm f1 = 380 MHz, f2 = 381 MHz, VGAIN = 1 V, 0 dBm per output tone
Output P1dB1 13 dBm VGAIN = 0 V, VMODE = 0 V
1 Operation at compression is not recommended due to adverse distortion components.
AD8368 Data Sheet
Rev. C | Page 4 of 20
VS = 5 V, TA = 25°C, system impedance Z0 = 50 Ω, VMODE = 5 V, RF input = 140 MHz, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Conditions
SQUARE LAW DETECTOR (DETI, DETO)
Output Setpoint
−11
dBm
OUTP connected to DETI
DETI DC Bias Level to ICOM VS/2 V
DETI Impedance 710 Ω
0.6 pF
DETO Output Range1 0.1 VS/2 V
AGC Step Response
30
µs
For −6 dB input power step (C
DETO
= 1 nF)
MODE CONTROL INTERFACE (MODE)
MODE Threshold 3.5 V
MODE Input Bias Current 50 µA
POWER INTERFACE (VPSI, VPSO)
Supply Voltage 4.5 5 5.5 V
Total Supply Current
60
mA
ENBL high
Disable Current 2 mA ENBL low
ENABLE INTERFACE (ENBL)
Enable Threshold 2.5 V
Enable Response Time 1.5 µs Time delay following off-to-on transition until output
reaches 90% of final value
3 µs Time delay following on-to-off transition until supply
current is less than 5 mA
ENBL Input Bias Current
150
µA
V
ENBL
= 5 V
1 Refer to AGC Operation section.
Data Sheet AD8368
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage (VPSO, VPSI) 5.5 V
ENBL and MODE Select Voltage
5.5 V
RF Input Level 20 dBm
Internal Power Dissipation 440 mW
θJA 52°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD8368 Data Sheet
Rev. C | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05907-002
ICOM
GAIN
ENBL
VPSI
VPSI
MODE
ICOM
INPT
OCOM
OUTP
VPSO
VPSO
VPSI
VPSI
ICOM
DETO
ICOM
HPFL
DECL
DECL
DECL
DETI
VPSI
OCOM
NOTES
1. EXPOSED PAD. CONNECT EPAD TO LOW
IMPEDANCE GROUND.
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
11
7
12
20
19
21
22
23
24
AD8368
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 GAIN Gain Control.
2 DETO Detector Output. Provides an output error current for the AGC function.
3 HPFL
High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the internal output offset
control loop that controls the minimum usable input frequency.
4, 14, 15 DECL Decoupling Pin. Nominally ~VS/2. Decoupling capacitance may need to be adjusted for AGC operation
(see the Applications Information section).
5 DETI Detector Input. DC level referenced to DECL pin.
6, 7 OCOM Connect OCOM to low impedance ground.
8 OUTP Signal Output. Must be ac-coupled.
9, 10 VPSO Positive Supply Voltage, 4.5 V to 5.5 V. VPSO and VPSI must be connected together externally and
properly bypassed.
11, 12, 13, 22, 23 VPSI Positive Supply Voltage, 4.5 V to 5.5 V. VPSO and VPSI must be connected together externally and
properly bypassed.
16, 17, 18, 20 ICOM Connect ICOM to low impedance ground.
19 INPT Signal Input. Must be ac-coupled.
21 MODE Gain Direction Control. High for positive slope. Low for negative slope.
24 ENBL
Apply a Positive Voltage (2.5 V VENBL VPSI) to Activate Device.
EPAD Exposed Pad. Connect the exposed pad to low impedance ground.
Data Sheet AD8368
Rev. C | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, T = 25°C, system impedance Z0 = 50 Ω, MODE = 5 V, unless otherwise noted.
25
–20
–15
–10
–5
0
5
10
15
20
10 100 1000
S21 (dB)
FREQUENCY (MHz)
05907-003
0V
0.25V
0.5V
0.75V
1V
Figure 3. S21 vs. Frequency by VGAIN
25
–15
–10
–5
0
5
10
15
20
4
–4
–3
–2
–1
0
1
2
3
0 0.2 0.4 0.6 0.8 1.0
GAIN (dB)
CONFORMANCE ERROR (dB)
V
GAIN
(V)
05907-004
70MHz
+85°C
–40°C
+25°C
Figure 4. Gain and Conformance Error vs. VGAIN (f = 70 MHz)
25
–15
–10
–5
0
5
10
15
20
4
–4
–3
–2
–1
0
1
2
3
0 0.2 0.4 0.6 0.8 1.0
GAIN (dB)
CONFORMANCE ERROR (dB)
V
GAIN
(V)
05907-005
140MHz
+85°C
–40°C
+25°C
Figure 5. Gain and Conformance Error vs. VGAIN (f = 140 MHz)
25
–15
–10
–5
0
5
10
15
20
4
–4
–3
–2
–1
0
1
2
3
0 0.2 0.4 0.6 0.8 1.0
GAIN (dB)
CONFORMANCE ERROR (dB)
V
GAIN
(V)
05907-006
240MHz
+85°C
–40°C
+25°C
Figure 6. Gain and Conformance Error vs. VGAIN (f = 240 MHz)
25
–15
–10
–5
0
5
10
15
20
4
–4
–3
–2
–1
0
1
2
3
0 0.2 0.4 0.6 0.8 1.0
GAIN (dB)
CONFORMANCE ERROR (dB)
V
GAIN
(V)
05907-007
380MHz
+85°C
–40°C
+25°C
Figure 7. Gain and Conformance Error vs. VGAIN (f = 380 MHz)
0.7
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
AMPLITUDE (V)
TIME (µs)
05907-008
V
GAIN
V
OUTP
Figure 8. Gain Step Time Domain Response (6 dB Gain Step)
AD8368 Data Sheet
Rev. C | Page 8 of 20
40
0
5
10
15
20
25
30
35
OUTPUT THIRD-ORDER INTERCEPT (dBm)
RF INPUT (MHz)
05907-009
–40°C
+25°C
70 110 150 190 230 270 310 350 380
+85°C
Figure 9. Output Third-Order Intercept vs. RF Input Frequency at
Maximum Gain (VMODE = 0 V)
40
0
5
10
15
20
25
30
35
0 0.2 0.4 0.6 0.8 1.0
OUTPUT THIRD-ORDER INTERCEPT (dBm)
V
GAIN
(V)
05907-010
70MHz 140MHz
240MHz 380MHz
Figure 10. Output Third-Order Intercept vs. VGAIN (VMODE = 0 V)
0
–80
–70
–60
–50
–40
–30
–20
–10
0 0.2 0.4 0.6 0.8 1.0
THIRD-ORDER IMD (dBc)
V
GAIN
(V)
05907-011
140MHz
240MHz 380MHz
70MHz
Figure 11. Third-Order IMD vs. VGAIN
(Output Power = 0 dBm per Tone, VMODE = 0 V)
20
18
16
14
12
10
8
6
4
2
0
OUTPUT 1dB COMPRESSION (dBm)
RF INPUT (MHz)
05907-012
–40°C
+25°C
+85°C
70 110 150 190 230 270 310 350 380
Figure 12. Output 1dB Compression Point vs. RF Input Frequency at
Maximum Gain (VMODE = 0 V)
20
18
16
14
12
10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1.0
OUTPUT 1dB COMPRESSION (dBm)
V
GAIN
(V)
05907-013
70MHz 140MHz
240MHz
380MHz
Figure 13. Output 1dB Compression Point vs. VGAIN (VMODE = 0 V)
20
4.5V
5.0V
5.5V
18
16
14
12
10
8
6
4
2
0
70 350 380310270230190150110
OUTPUT 1dB COMPRESSION (dBm)
RF INPUT (MHz)
05907-014
Figure 14. Output 1dB Compression Point vs. RF Input Frequency by
Supply Voltage at Maximum Gain (VMODE = 0 V)
Data Sheet AD8368
Rev. C | Page 9 of 20
50
40
45
0
5
10
15
20
25
30
35
10 100 1000
NOISE FIGURE (dB)
FREQUENCY (MHz)
05907-015
Figure 15. Noise Figure vs. Frequency at Maximum Gain (VMODE = 0 V)
50
45
40
35
30
25
20
15
10
5
0
01.00.80.60.40.2
NOISE FIGURE (dB)
V
GAIN
(V)
05907-016
70MHz
140MHz
240MHz
380MHz
Figure 16. Noise Figure vs. VGAIN (VMODE = 0 V)
0
–40
–35
–30
–25
–20
–15
–10
–5
10 100 1000
INPUT RETURN LOSS (dB)
FREQUENCY (MHz)
05907-017
VGAIN = 0.5V
VGAIN = 0V
VGAIN = 0.25V
VGAIN = 0.75V
VGAIN = 1V
Figure 17. Input Return Loss vs. Frequency
05907-018
V
GAIN
= 1V
V
GAIN
= 0.75V
V
GAIN
= 0.5V
V
GAIN
= 0.25V
V
GAIN
= 0V
Figure 18. Input Reflection Coefficient vs. Frequency
0
–40
–35
–30
–25
–20
–15
–10
–5
10 100 1000
OUTPUT RETURN LOSS (dB)
FREQUENCY (MHz)
05907-019
VGAIN = 1V
VGAIN = 0V
Figure 19. Output Return Loss vs. Frequency
05907-020
VGAIN = 1V
VGAIN = 0V
Figure 20. Output Reflection Coefficient vs. Frequency
AD8368 Data Sheet
Rev. C | Page 10 of 20
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–40 –35 –30 –25 –20 –15 –10 –5 0 5
RSSI (V)
CONFORMANCE ERROR (dB)
RF INPUT (dBm)
05907-021
+85°C
+85°C
–40°C
–40°C
+25°C
+25°C
Figure 21. RSSI (VDETO) and Conformance Error vs. Input Power (f = 70 MHz)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–40 –35 –30 –25 –20 –15 –10 –5 0 5
RSSI (V)
CONFORMANCE ERROR (dB)
RF INPUT (dBm)
05907-022
+85°C
+85°C
–40°C
–40°C
+25°C
+25°C
Figure 22. RSSI (VDETO) and Conformance Error vs. Input Power (f = 140 MHz)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–40 –35 –30 –25 –20 –15 –10 –5 0 5
RSSI (V)
CONFORMANCE ERROR (dB)
RF INPUT (dBm)
05907-023
+85°C
+85°C
–40°C
–40°C
+25°C
+25°C
Figure 23. RSSI (VDETO) and Conformance Error vs. Input Power (f = 240 MHz)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–40 –35 –30 –25 –20 –15 –10 –5 0 5
RSSI (V)
CONFORMANCE ERROR (dB)
RF INPUT (dBm)
05907-024
+85°C
+85°C
–40°C
–40°C
+25°C
+25°C
Figure 24. RSSI (VDETO) and Conformance Error vs. Input Power (f = 380 MHz)
05907-025
CH2 50mV Ω CH3 100mV Ω M20µs 500MS/s
2.0ns/PT
A CH1 410mV
V
RSSI
V
OUTP
AMPLITUDE (V)
Figure 25. AGC Time Domain Response (3 dB Power Step, CDETO = 1 nF)
DISABLE CURRENT (mA)
80
70
60
50
40
30
20
10
0
8
7
6
5
4
3
2
1
0
–40 –20 020 6040 80
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
05907-026
4.5V
5.0V 5.5V
4.5V
5.0V
5.5V
Figure 26. Supply Current and Disable Current vs. Temperature
Data Sheet AD8368
Rev. C | Page 11 of 20
05907-027
CH2 500mV ΩCH3 5V ΩM2.0µs 250MS/s
4.0ns/PT
A CH3 0.0V
AMPLITUDE (V)
V
ENBL
V
OUTP
Figure 27. ENBL Response Time
50
40
0
10
20
30
36.8 37.0 37.2 37.4 37.6 37.8 38.0 38.2
PERCENTAGE (%)
SLOPE (dB/V)
05907-028
Figure 28. Gain Scaling Distribution (140 MHz)
50
40
0
10
20
30
–15.0 –13.5–13.8–14.1–14.4–14.7
PERCENTAGE (%)
INTERCEPT (dB)
05907-029
Figure 29. Gain Intercept Distribution (140 MHz)
AD8368 Data Sheet
Rev. C | Page 12 of 20
CIRCUIT DESCRIPTION
The AD8368 is a single-ended VGA with a bandwidth of 800 MHz
and a gain control span of 34 dB ranging from −12 dB to +22 dB.
It incorporates an uncommitted square law detector that can be
used to form a tight AGC loop around the VGA. Using the
Analog Devices patented X-AMP architecture, the AD8368
achieves accurate linear-in-dB gain control with excellent linearity
(OIP3) and noise figure (NF). The part also features 50 Ω input
and output impedances for ease of use.
The main signal path, shown in Figure 30, consists of a variable
input attenuator followed by a fixed-gain amplifier and output
buffer. This architecture allows for a constant OIP3 and output
noise floor as a function of gain setting. As a result, NF and IIP3
increase 1 dB for every 1 dB decrease in gain, resulting in a part
with constant dynamic range over gain setting.
05907-033
ATTENUATOR LADDER
DECL
50Ω
0dB –2dB –4dB –36dB
V
OU
T
INPT
GAIN
MODE
GAIN INTERPOLATOR
g
m
STAGES
FIXED-GAIN
AMPLIFIER
OUTPUT
BUFFER
Figure 30. Simplified Block Diagram
INPUT ATTENUATOR AND INTERPOLATOR
The input attenuator is built from an 18-section resistor ladder,
providing 2 dB of attenuation at each successive tap point. The
resistor ladder acts as a linear input attenuator, in addition to
providing an accurate 50 Ω input impedance. The variable
transconductance (gm) stages are used to select the attenuated
signal from the appropriate tap point along the ladder and feed
this signal to the fixed-gain amplifier. To realize a continuous gain
control function from discrete tap points, the gain interpolator
creates a weighted sum of signals appearing on adjacent tap
points by carefully controlling the variable gm stages.
FIXED-GAIN STAGE AND OUTPUT BUFFER
The weighted sum of the different tap points is fed into the
fixed-gain stage that drives the output buffer. Because the
resistive input attenuator is linear and contributes minimal
noise as a passive termination, the dynamic range as a function
of gain is determined primarily by the noise and the distortion
of the fixed-gain amplifier. This architecture explains the constant
OIP3 and constant output noise floor with gain setting and the
corresponding dB-for-dB increase in IIP3 and NF with decreasing
gain. The output buffer has 6 dB of gain and provides a broadband
50 Ω single-ended output impedance.
OUTPUT OFFSET CORRECTION
The dc level at the input, INPT, is driven by an internal reference to
VS/2. The reference is made available at the DECL pin for external
decoupling with CDECL. The dc level at the output, OUTP, is
regulated to the same midsupply reference by an offset correction
loop independent of gain setting, temperature, and process. The
low-pass response of this loop creates a high-pass corner frequency
in the signal path transfer function, which can be set by choosing
CDECL and CHPFL.
05907-034
VOUT
g
m
FIXED-GAIN
AMPLIFIER
FROM
INTERPOLATOR
g
m
STAGES
OUTPUT
BUFFER
×1 V
MID
DECL
C
DECL
HPFL
C
HPFL
Figure 31. Output Centering Control Loop
The input and output coupling capacitors should be selected to
provide low impedances at the frequencies of interest relative to
50 Ω so as not to affect the high-pass corner. In this case, the
high-pass corner frequency can be set by either CHPFL or CDECL,
which form independent poles in the feedback path of the offset
correction loop. The high-pass corner is determined by the highest
of these poles, which are given by
)005.0(
8.0
)kHz(
,
HPFL
HPFLHP C
f
)005.0(
5700
)kHz(
,
DECL
DECLHP C
f
where CHPFL and CDECL are in nF.
When using this method to set the high-pass frequency, the
other capacitor should be sized such that its pole is at least 30×
lower in frequency. In addition, note that CDECL represents the
total decoupling capacitance at the DECL pins.
INPUT AND OUTPUT IMPEDANCES
The AD8368 offers single-ended broadband 50 Ω input and
output impedances. The excellent match to 50 Ω is maintained
from part to part, over frequency, and over gain setting. Both
the input and output pins must be externally ac-coupled to
prevent disruption of the internal dc levels. Sufficiently large
coupling capacitors should be used so that their impedance is
negligible relative to the 50 Ω presented by the ladder at the
input and by the output buffer at the output.
Data Sheet AD8368
Rev. C | Page 13 of 20
GAIN CONTROL INTERFACE
The AD8368 has a linear-in-dB gain control interface that can
be operated in either a gain-up mode or gain-down mode. In
the gain-up mode with the MODE pin pulled high, the gain
increases with increasing gain voltages. In the gain-down mode,
with the MODE pin pulled low, the gain decreases with increasing
gain voltages. In both modes of operation, the gain control
slope is maintained at +37.5 dB/V or −38 dB/V (depending
on mode selection) over temperature, supply, and process as
VGAIN varies from 100 mV to 900 mV. To form an AGC loop
with the on-board detector around the VGA, the MODE pin
has to be pulled low.
The gain functions for MODE pulled high and low are given
respectively by
GainHIGH (dB) = 37.5 × VGAIN − 14
GainLOW (dB) = −38 × VGAIN + 24.8
where VGAIN is expressed in volts.
25
–15
–10
–5
0
5
10
15
20
4
–4
–3
–2
–1
0
1
2
3
01.00.80.60.40.2
GAIN (dB)
V
GAIN
(V)
05907-035
GAIN_H
GAIN_L
ERROR_H
ERROR_L
CONFORMANCE ERROR (dB)
Figure 32. Gain and Conformance Error vs. VGAIN
As shown in Figure 32, the gain function can be either an
increasing or decreasing function of VGAIN, depending on the
MODE pin.
AD8368 Data Sheet
Rev. C | Page 14 of 20
APPLICATIONS INFORMATION
VGA OPERATION
The AD8368 is a general-purpose VGA suitable for use in a wide
variety of applications where accurate, continuous, linear-in-dB
gain control over a broad range of frequencies is important. Its
stability over temperature and supply in comparison to other
variable gain techniques can be traced back to the X-AMP
architecture. While having an 800 MHz bandwidth, its low
frequency operation can be extended by properly selecting
CHPFL and CDECL.
The typical connections for using the AD8368 in VGA mode are
illustrated in Figure 33. The input (INPT) and output (OUTP) of
the AD8368 should be externally ac-coupled to prevent disrupting
the dc levels on the chip. Therefore, a sufficiently large coupling
capacitor should be used such that the series impedance of the
capacitor is negligible at the frequencies of interest.
05907-036
ICOMGAIN
ENBL
VPSI
VPSI
MODE
ICOM
INPT
OCOM
OUTP
VPSO
VPSO
VPSI
VPSI
ICOMDETO
ICOMHPFL
DECLDECL
DECLDETI
VPSIOCOM
AD8368
V
GAIN
0V TO 1V
V
POS
V
IN
REF
X
2
–
+
V
POS
V
OUT
Figure 33. Typical Connections for VGA Mode for
Increasing Gain with Increasing VGAIN (MODE High)
The gain control voltage ranging from 0 V to 1 V is applied to
the GAIN pin. The MODE pin controls whether the gain of the
part is an increasing or decreasing function of the gain voltage.
When the MODE pin is pulled high, the gain increases with
increasing gain voltages. When the MODE pin is pulled low, the
gain decreases with increasing gain voltages. The ENBL pin is
used to enable or disable the part. ENBL is active high; when
ENBL is pulled low, the part is disabled and draws a fraction of
the normal supply current.
The DECL pin provides the internal midsupply dc reference
for the AD8368. It should be well decoupled to ground using a
large capacitor with low ESR. The capacitors connected to the
HPFL pin and DECL pin are used to control the low-pass
corner frequency of the output offset correction loop. The
resulting high-pass corner frequency is inversely proportional
to their values.
AGC OPERATION
The AD8368 can be configured as a standalone AGC amplifier
by using the on-board rms detector, as shown in Figure 34. The
detector output, DETO, is an error current representing the
difference of squares between the root-mean-square (rms) of
the sensed signal and an internal reference of 63 mV rms. This
error current is integrated on CDETO and connected to the GAIN
pin to form the AGC loop.
The 63 mV rms reference corresponds to 178 mV p-p for a sine
wave but the detector accuracy is maintained for more complex
signals, such as Gaussian noise, complex envelopes, and multi-
carrier signals with high peak-to-average ratios.
05907-037
ICOMGAIN
ENBL
VPSI
VPSI
MODE
ICOM
INPT
OCOM
OUTP
VPSO
VPSO
VPSI
VPSI
ICOMDETO
ICOMHPFL
DECLDECL
DECLDETI
VPSIOCOM
AD8368
RSSI
CDETO
VPOS
VIN
REF
X2
–
+
VPOS
VOUT
R2
R1
Figure 34. AGC Mode of Operation
The AGC mode of operation requires a specific gain direction.
The gain must fall as VDETO increases to restore the needed
balance against the setpoint. Therefore, the MODE pin must be
pulled low. By connecting the signal at OUTP directly to the
detector input (DETI), the output level is driven to the 63 mV
rms reference setpoint.
Data Sheet AD8368
Rev. C | Page 15 of 20
The output setpoint can be increased using an external resistive
divider network between OUTP and DETI, referenced to DECL
as depicted in Figure 34. In this configuration, the rms output
voltage is forced to (1 + R1/R2) 63 mV rms by the AGC loop.
For a 0 dBm (224 mV rms referenced to 50 Ω) output setpoint,
this ratio is 3.5. After correcting for the input impedance of
DETI, the choice of R1 = 226 Ω and R2 = 100 Ω yields a setpoint of
roughly 0 dBm. This very accurate leveling function is shown in
Figure 35, where the rms output is held to within 0.2 dB of the
0 dBm setpoint for >30 dB range of input levels.
10
–30
–25
–20
–15
–10
–5
0
5
–40 –30 –20 –10 010 20
POWER OUT (dBm)
POWER IN (dBm)
05907-038
Figure 35. Output Power vs. Input Power in AGC Mode at 140 MHz
Note that to achieve the accurate level of AGC output power,
the DECL capacitor must be adjusted for the corresponding RF
frequency. The DECL capacitor value varies depending on board
parasitics. Table 5 shows the DECL capacitor value based on the
evaluation board parasitics.
Table 5. DECL Capacitor Value
IF Frequency (MHz) C4 (pF) C20 (pF)
70 1000 2200
140 270 560
240 68 150
380 33 68
480 15 39
A valuable feature of using a square law detector in AGC mode
is that the RSSI voltage is a true reflection of signal power and
can be converted to an absolute power measurement for any
given source impedance. The RSSI in units of dBm referenced
to 50 Ω and based on the voltage available on the DETO pin is
given by
RSSI = −11 + 20 log10(1 + R1/R2) + 38 × VDETO − 24.8
Figure 36 shows a plot of the RSSI voltage at DETO as input
power is swept.
3.0
0
0.5
1.0
1.5
2.0
2.5
–40 –30 –20 –10 010 20
RSSI (V)
POWER IN (dBm)
05907-039
Figure 36. Monitoring the GAIN/DETO RSSI Voltage vs. Input Power
In some cases, it can be found that, if driven into AGC overload,
the AD8368 requires unusually long times to recover; that is, the
voltage at DETO remains at an abnormally high value, and the
gain is at its lowest value. To avoid this situation, it is recommended
that a clamp be placed on the DETO pin, as shown in Figure 37.
05907-042
ICOMGAIN
ENBL
VPSI
VPSI
MODE
ICOM
INPT
OCOM
OUTP
VPSO
VPSO
VPSI
VPSI
ICOMDETO
ICOMHPFL
DECLDECL
DECLDETI
VPSIOCOM
AD8368
C
AGC
0.1µF
V
AGC
Q1
2N2907
RB
0.5V
RA
+V
S
Figure 37. External Clamp to Prevent AGC Overload
The resistive divider network, RA and RB, should be designed
such that the base of Q1 is driven to 0.5 V.
AD8368 Data Sheet
Rev. C | Page 16 of 20
The choice of CDETO is a compromise of averaging time constant,
response time, and carrier leakage. If CDETO is selected to be too
small to speed up the response time, the AGC loop could start
tracking and leveling any amplitude envelope and corrupt the
constellation. Figure 38 illustrates a 16 QAM, 100 ksymbols per
second constellation with a degraded error vector magnitude
(EVM) of 5%. By increasing CDETO to 0.01 µF, the EVM is
improved to 1.1%.
REF –4.9dBm CF 100MHz
SR 10kHz
CONST DIAG
MEAS SIGNAL
16 QAM
1U
–1U
–1.31289U 262.578mU/ 1.31289U
05907-040
Figure 38. Degraded Error Vector Magnitude Performance for 16 QAM at
100 ksymbols per second (CDETO Too Small)
Figure 39 illustrates the measured EVM performance for a 16 QAM
modulation at 10 Msymbols per second using CDETO = 1 nF.
10
0
1
2
3
4
5
6
7
8
9
–40 –30 –20 –10 010 20
EVM (%)
POWER IN (dBm)
05907-041
Figure 39. Error Vector Magnitude Performance for
16 QAM 10 Msymbols per second
STABILITY AND LAYOUT CONSIDERATIONS
In some applications, the printed circuit board (PCB) parasitic, in
combination with the source impedance presented by the driving
stage, can present some troublesome impedance at high frequency
and can potentially unstablize the amplifier under certain extreme
conditions, such as high gain and high temperature. To avoid such
scenarios, it is recommended to include a simple parallel RL
snubbing network directly at the input terminal of the AD8368.
Figure 40 depicts an example of this network. The RL network
formed by R3 and L1 is used to minimize the negative impact
due to reflective source conditions at high RF frequencies and
ensures the amplifier operates unconditionally stable and
maintains the typical device performance.
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
ground of the chip. Solder the paddle to the low impedance ground
plane on the PCB to ensure specified electrical performance and to
provide thermal relief. It is also recommended that the ground
planes on all layers under the paddle be stitched together with
vias to reduce thermal impedance.
Data Sheet AD8368
Rev. C | Page 17 of 20
EVALUATION BOARD
The standard evaluation board schematic and layout artwork is
presented in Figure 41 through Figure 44. The evaluation board
is fabricated on a multilayer FR-4 board, with 50 Ω-controlled
impedance transmission lines for the RF input and output traces.
The board is powered by a single supply in the 4.5 V to 5.5 V
range. The power supply is decoupled by 0.1 µF and 1 nF capacitors
at each power supply pin. Additional decoupling, in the form
of a series resistor or inductor at the supply pins, can also be added.
Table 6 details the various configuration options of the
evaluation board.
05907-043
VPOS
VPOS1 VPOS2 VPOS3
ICOMGAIN
ENBL
VPSI
VPSI
MODE
ICOM
INPT
OCOM
OUTP
VPSO
VPSO
VPSI
VPSI
ICOMDETO
ICOMHPFL
DECLDECL
DECLDETI
VPSIOCOM
AD8368
C20
1nF
C2
5.6pF
C11
1nF
C14
0.1µF
R11
0Ω
VPOS2
C12
1nF
C15
0.1µF
R12
0Ω
VPOS3
C
OUT
10nF OUTPUT
R31
OPEN
R32
OPEN
R30
OPEN
DET_IN
C1
OPEN
GAIN
C23
10nF
C4
1nF
C6
1nF
JP4
GAIN
C13
0.1µF
DET_OUT_TP
R35
OPEN
R3
215Ω
L1
10nH
C
IN
10nF
INPUT
SW1
SW2
LOW
HI
ON
OFF C10
1nF
R1
10kΩ
R2
10kΩ
ENABLE
R10
0Ω
VPOS1
Figure 40. Evaluation Board
Table 6. Evaluation Board Configuration Options
Component Function Default Conditions
R1, R2, R3, L1 Pull-Down Resistors for MODE and ENBL. RL network. Prevent potential instability impact
due to PCB parasitics and/or certain extreme conditions (see the Stability and Layout
Considerations section).
R1 = R2 = 10 kΩ
R3 = 215 Ω
L1 = 10 nH
R10, R11, R12,
C10, C11, C12,
C13, C14, C15
Supply Decoupling. Jumpers, power supply decoupling resistors, and filter capacitors. R10 = R11 = R12 = 0 Ω
C10 = C11 = C12 = 1 nF
C13 = C14 = C15 = 0.1 µF
CIN RF Input. CIN provides dc block for RF input. CIN = 10 nF
COUT RF Output. COUT provides dc block for RF output. COUT = 10 nF
R31, R32
Feedback Path for AGC Operation. For a default setpoint of 63 mV rms, set R31 = 0 Ω and
remove R32. For other AGC setpoints, rms voltage = (1 + n) × 63 mV rms, where n = R31/R32.
R31 = R32 = Open
(VGA mode)
R35 Populate with 0 Ω to feed detector output RSSI voltage to DET_OUT_TP. R35 = Open
C23 Sets the corner frequency of the output offset control loop high-pass filter. C23 = 10 nF
C1, R30 Used for driving the detector externally. Set R30 to 50 Ω for matching. Set C1 to be a large
ac coupling capacitor.
C1 = Open
R30 = Open
C6 DETO Capacitor. Needs to be made larger for lower data rates (see the AGC Operation section). C6 = 1 nF
C20, C2, C4 DECL Capacitor. Needs to be adjusted based on RF frequency in AGC operation (see the
AGC Operation section).
C20 = C4 = 1 nF
C2 = 5.6 pF
JP4 Jumper for AGC Mode of Operation. Provides feedback from the detector output to the
gain pin.
JP4 = not populated
(VGA mode)
SW1 Mode Switch. Low mode puts the part in gain-down mode. High mode puts the part in
gain-up mode. AGC operation requires gain-down mode.
SW1 = JP2
SW2 Power-Down. The part is disabled when the enable pin is tied to ground. SW2 = JP3
AD8368 Data Sheet
Rev. C | Page 18 of 20
05907-044
Figure 41. Component Side Silkscreen
05907-045
Figure 42. Circuit Side Silkscreen
05907-046
Figure 43. Component Side Layout
05907-047
Figure 44. Circuit Side Layout
Data Sheet AD8368
Rev. C | Page 19 of 20
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD.
BOTTOM VIEWTOP VIEW
SIDE VIEW
EXPOSED
PAD
4.10
4.00 SQ
3.90
0.80
0.75
0.70
0.20 REF
0.25 MIN
3.16 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.45
1
24
7
12
13
18
19
6
0.05 MAX
0.02 NOM
PKG-004462
08-10-2017-A
SEATING
PLANE
PIN 1
INDIC AT OR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 45. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
Ordering
Quantity
AD8368ACPZ-REEL7
−40°C to +85°C
24-Lead Lead Frame Chip Scale Package (LFCSP)
CP-24-7
1,500
AD8368ACPZ-WP −40°C to +85°C 24-Lead Lead Frame Chip Scale Package (LFCSP) CP-24-7 64
AD8368-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
2 WP = Waffle Pack.
