1
40V Precision Single Supply Rail-Rail Output Low
Power Operational Amplifiers
ISL28108, ISL28208, ISL28408
The ISL28108, ISL28208 and ISL28408 are single, dual and
quad low power precision amplifiers optimized for single
supply applications. These devices feature a common mode
input voltage range extending to 0.5V below the V- rail, a
rail-to-rail differential input voltage range for use as a
comparator, and rail-to-rail output voltage swing, which make
them ideal for single supply applications where input
operation at ground is important.
Added features include low offset voltage, and low
temperature drift making them the ideal choice for
applications requiring high DC accuracy. The output stage is
capable of driving large capacitive loads from rail to rail for
excellent ADC driving performance. The devices can operate
for single or dual supply from 3V (±1.5V) to 40V (±20V) and are
fully characterized at ±5V and ±15V. The combination of
precision, low power, and small footprint provides the user with
outstanding value and flexibility relative to similar competitive
parts.
Applications for these amplifiers include precision
instrumentation, data acquisition, precision power supply
control, and industrial control.
The ISL28108 single is offered in 8 Ld TDFN, SOIC and MSOP
packages. The ISL28208 dual amplifier is offered in 8 Ld
TDFN, MSOP, and SOIC packages. The ISL28408 is offered in
14 Ld SOIC package. All devices are offered in standard pin
configurations and operate over the extended temperature
range to -40°C to +125°C.
Features
• Single or Dual Supply, Rail-to-Rail Output and Below Ground
(V-) input capability
• Rail-to-rail Input Differential Voltage Range for Comparator
Applications
• Single Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
• Low Current Consumption (VS = ±5V) . . . . . . . . . . . . . . 165µA
• Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 15.8nV/√Hz
• Low Noise Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 80fA/√Hz
• Low Input Offset Voltage (ISL28108) . . . . . . . . . . . . . . 150µV
• Superb Temperature Drift
- Voltage Offset TC . . . . . . . . . . . . . . . . . . . . . . 0.1µV/°C, Typ
• Low Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . -13nA Typ
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
• No Phase Reversal
Applications
• Precision Instruments
• Medical Instrumentation
• Data Acquisition
• Power Supply Control
• Industrial Process Control
Related Literature
•AN1658, “ISL28208SOICEVAL2Z Evaluation Board User
Guide”
FIGURE 1. TYPICAL APPLICATION CIRCUIT FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
IN-
IN+
RF
RREF+
ISL28108
+3V
V-
V+
RIN-
10kΩ
RIN+
10kΩ
-
+
100kΩ
VREF
100kΩ
VOUT
LOAD
RSENSE
SINGLE-SUPPLY, LOW-SIDE
GAIN = 10
to 40V
CURRENT SENSE AMPLIFIER
VOS (µV)
INPUT COMMON MODE VOLTAGE (V)
-500
-400
-300
-200
-100
0
100
200
300
400
500
13 13.5 14 14.5 15
-16 -15.5 -15 -14.5 -14
+25°C
+125°C
VS = ±15V
-40°C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
November 1, 2011
FN6935.3
ISL28108, ISL28208, ISL28408
2FN6935.3
November 1, 2011
Pin Configurations
Ordering Information
PART NUMBER
(Notes 1, 2, 3) PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28108FBZ 28108 FBZ -40 to +125 8 Ld SOIC M8.15E
ISL28108FRTZ 108Z -40 to +125 8 Ld TDFN L8.3x3K
Coming soon
ISL28108FUZ 8108Z -40 to +125 8 Ld MSOP M8.118B
ISL28208FBZ 28208 FBZ -40 to +125 8 Ld SOIC M8.15E
ISL28208FRTZ 208F -40 to +125 8 Ld TDFN L8.3x3K
Coming soon
ISL28208FUZ 8208Z -40 to +125 8 Ld MSOP M8.118B
ISL28408FBZ 28408 FBZ -40 to +125 14 Ld SOIC M14.15
ISL28208SOICEVAL2Z Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to Tech Brief TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28108, ISL28208, ISL28408. For more information on MSL please
see Tech Brief TB363.
ISL28108
(8 LD TDFN)
TOP VIEW
ISL28108
(8 LD MSOP, SOIC)
TOP VIEW
ISL28208
(8 LD TDFN)
TOP VIEW
ISL28208
(8 LD MSOP, SOIC)
TOP VIEW
ISL28408
(14 LD SOIC)
TOP VIEW
2
3
4
1
7
6
5
8
NC
-IN
+IN
V-
NC
V+
VOUT
NC
+-
PAD
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC
V+
VOUT
NC
+-
2
3
4
1
7
6
5
8
V
OUT
_A
-IN_A
+IN_A
V-
V+
V
OUT
_B
-IN_B
+IN_B
+-
+-
PAD
VOUT _A
-IN_A
+IN_A
V-
1
2
3
4
8
7
6
5
V+
VOUT_B
-IN_B
+IN_B
+-
+-
-+ -+
-+ -+
BC
AD
VOUT_A
-IN_A
+IN_A
V +
1
2
3
4
5
6
7
10
9
8
11
12
13
14
+IN_B
-IN_B
VOUT_B
V -
+IN_C
-IN_C
VOUT_C
VOUT_D
-IN_D
+IN_D
ISL28108, ISL28208, ISL28408
3FN6935.3
November 1, 2011
Pin Descriptions
ISL28108
(8 Ld SOIC,
MSOP, TDFN)
ISL28208
(8 Ld SOIC,
TDFN)
ISL28408
(14 Ld SOIC)
PIN
NAME
EQUIVALENT
CIRCUIT DESCRIPTION
3 - - +IN Circuit 1 Amplifier non-inverting input
-3 3+IN_A
-5 5+IN_B
- - 10 +IN_C
- - 12 +IN_D
4 4 11 V- Circuit 3 Negative power supply
2 - - -IN Circuit 1 Amplifier inverting input
-2 2-IN_A
-6 6-IN_B
-- 9-IN_C
--13-IN_D
7 8 4 V+ Circuit 3 Positive power supply
6- -V
OUT Circuit 2 Amplifier output
-1 1V
OUT_A
-7 7V
OUT_B
-- 8V
OUT_C
--14V
OUT_D
1, 5, 8 - - NC - No internal connection
PAD PAD - PAD - Thermal Pad - TDFN and QFN packages only. Connect
thermal pad to ground or most negative potential.
CIRCUIT 2
CIRCUIT 1
V+
V-
CIRCUIT 3
CAPACITIVELY
TRIGGERED
ESD CLAMP
IN-
V+
V-
IN+
V+
V-
OUT
ISL28108, ISL28208, ISL28408
4FN6935.3
November 1, 2011
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications, VS ±15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications, VS ±5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input Stage Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Output Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
ISL28108, ISL28208, ISL28408 SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Characterization vs Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package Outline Drawing, M8.15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing, L8.3x3K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package Outline Drawing, M8.118B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package Outline Drawing, M14.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ISL28108, ISL28208, ISL28408
5FN6935.3
November 1, 2011
Absolute Maximum Ratings Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . .42V or V- - 0.5V to V+ + 0.5V
Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . Indefinite
ESD Tolerance (ISL28208, ISL28408)
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 6kV
Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV
ESD Tolerance (ISL28108)
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .5.5kV
Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
8 Ld SOIC Package (208, Notes 4, 7) . . . . . . . 120 55
8 Ld SOIC Package (108, Notes 4, 7) . . . . . . . 120 60
8 Ld TDFN Package (208, Notes 5, 6) . . . . . . 47 6
8 Ld TDFN Package (108, Notes 5, 6) . . . . . . 45 3.5
8 Ld MSOP Package (208, Notes 4, 7). . . . . . 150 50
8 Ld MSOP Package (108, Notes 4, 7). . . . . . 165 57
14 Ld SOIC Package (408, Notes 4, 7). . . . . . 71 37
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature Range. . . . . . . . . . . . . . -40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V (±1.5V) to 40V (±20V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
VOS Input Offset Voltage ISL28208 SOIC, TDFN
ISL28408 SOIC
-230 25 230 µV
-330 330 µV
ISL28108 SOIC, TDFN -150 10 150 µV
-270 270 µV
TCVOS Input Offset Voltage Temperature
Coefficient
ISL28208 SOIC
-40°C to +125°C
0.1 1.1 µV/°C
ISL28208 TDFN
ISL28408 SOIC
-40°C to +125°C
0.2 1.4 µV/°C
ISL28108 SOIC, TDFN
-40°C to +125°C
0.2 1.2 µV/°C
ΔVOS Input Offset Voltage Match
(ISL28208 only)
-300 5 300 µV
-400 400 µV
IBInput Bias Current -43 -13 nA
-63 nA
TCIBInput Bias Current
Temperature Coefficient
0.07 nA/°C
ISL28108, ISL28208, ISL28408
6FN6935.3
November 1, 2011
IOS Input Offset Current ISL28208 SOIC, TDFN -3 0 3 nA
-4 4 nA
ISL28108 SOIC, TDFN
ISL28408 SOIC
-4 0 4 nA
-5 5 nA
CMRR Common-Mode Rejection Ratio VCM = V- -0.5V to V+ -1.8V 119 dB
VCM = V- -0.2V to V+ -1.8V 123 dB
102 dB
VCM = V- to V+ -1.8V 105 123 dB
102 115 dB
VCMIR Common Mode Input Voltage
Range
Guaranteed by CMRR test V- - 0.5 V+ - 1.8 V
V-V+ - 1.8 V
PSRR Power Supply Rejection Ratio VS = 3V to 40V, VCMIR = Valid Input Voltage 110 128 dB
109 124 dB
AVOL Open-Loop Gain VO = -13V to +13V, RL = 10kΩ to ground 117 126 dB
100 dB
VOL Output Voltage Low,
VOUT to V-
RL = 10kΩ52 85 mV
145 mV
VOH Output Voltage High,
V+ to VOUT
RL = 10kΩ70 110 mV
150 mV
ISSupply Current/Amplifier RL = Open 185 250 µA
270 350 µA
ISC+ Output Short Circuit Source
Current
RL = 10Ω to V-19 mA
ISC- Output Short Circuit Sink Current RL = 10Ω to V+30 mA
VSUPPLY Supply Voltage Range Guaranteed by PSRR 3 40 V
AC SPECIFICATIONS
GBWP Gain Bandwidth Product ACL = 101, VO = 100mVP-P, RL = 2kΩ 1.2 MHz
enp-p Noise Voltage 0.1Hz to 10Hz; VS = +18V 580 nVP-P
enNoise Voltage Density f = 10Hz; VS = +18V 18 nV/√Hz
enNoise Voltage Density f = 100Hz; VS = +18V 16 nV/√Hz
enNoise Voltage Density f = 1kHz; VS = +18V 15.8 nV/√Hz
enNoise Voltage Density f = 10kHz; VS = +18V 15.8 nV/√Hz
inNoise Current Density f = 10kHz; VS = +18V 80 fA/√Hz
THD + N Total Harmonic Distortion + Noise 1kHz, AV = 1, VO = 3.5VRMS, RL =10kΩ 0.00042 %
TRANSIENT RESPONSE
SR Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩ, VO = 10VP-P 0.45 V/µs
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
ISL28108, ISL28208, ISL28408
7FN6935.3
November 1, 2011
tr, tf, Small
Signal
Rise Time, VOUT 10% to 90% AV
= 1,
VOUT = 100mVP-P, Rf = 0Ω, R
L
=2k
Ω to
VCM
264 ns
Fall Time, VOUT 90% to 10% AV
= 1,
VOUT = 100mVP-P
, Rf = 0Ω, R
L
= 2k
Ω to
VCM
254 ns
tsSettling Time to 0.01%
10V Step; 10% to VOUT
AV
= -1,
VOUT = 10VP-P
, Rg = Rf =10k, R
L
=2k
Ω to
VCM
27 µs
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +125°C. Temperature data established by characterization.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
VOS Input Offset Voltage ISL28208 SOIC, TDFN
ISL28408 SOIC
-230 25 230 µV
-330 330 µV
ISL28108 SOIC, TDFN -150 10 150 µV
-270 270 µV
TCVOS Input Offset Voltage Temperature
Coefficient
ISL28208 SOIC
-40°C to +125°C
0.1 1.1 µV/°C
ISL28208 TDFN
ISL28408 SOIC
-40°C to +125°C
0.2 1.4 µV/°C
ISL28108 SOIC, TDFN
-40°C to +125°C
0.2 1.2 µV/°C
ΔVOS Input Offset Voltage Match
(ISL28208 only)
-300 3 300 µV
-400 400 µV
IBInput Bias Current -43 -15 nA
-63 nA
TCIBInput Bias Current
Temperature Coefficient
-40°C to +125°C -0.067 nA/°C
IOS Input Offset Current ISL28208 SOIC, TDFN -303nA
-4 4 nA
ISL28108 SOIC, TDFN
ISL28408 SOIC
-404nA
-5 5 nA
CMRR Common-Mode Rejection Ratio VCM = V- -0.5V to V+ -1.8V 101 dB
VCM = V- -0.2V to V+ -1.8V 123 dB
89 dB
VCM = V- to V+ -1.8V 105 123 dB
100 112 dB
VCM = V- to V+ -1.8V
ISL28408 SOIC
105 123 dB
97 112 dB
VCMIR Common Mode Input Voltage
Range
Guaranteed by CMRR test V- - 0.5 V+ - 1.8 V
V- V
+ - 1.8 V
PSRR Power Supply Rejection Ratio VS = 3V to 10V, VCMIR = Valid Input Voltage 110 126 dB
109 123 dB
ISL28108, ISL28208, ISL28408
8FN6935.3
November 1, 2011
AVOL Open-Loop Gain VO = -3V to +3V, RL = 10kΩ to ground 117 124 dB
99 dB
VOL Output Voltage Low,
VOUT to V-
RL = 10kΩ23 38 mV
48 mV
VOH Output Voltage High,
V+ to VOUT
RL = 10kΩ30 65 mV
70 mV
ISSupply Current/Amplifier RL = Open 165 250 µA
240 350 µA
ISC+ Output Short Circuit Source Current RL = 10Ω to V-14 mA
ISC- Output Short Circuit Sink Current RL = 10Ω to V+22 mA
AC SPECIFICATIONS
GBW Gain Bandwidth Product ACL = 101, VO = 100mVP-P
, RL = 2kΩ 1.2 MHz
enp-p Noise Voltage 0.1Hz to 10Hz 600 nVP-P
enNoise Voltage Density f = 10Hz 18 nV/√Hz
enNoise Voltage Density f = 100Hz 16 nV/√Hz
enNoise Voltage Density f = 1kHz 15.8 nV/√Hz
enNoise Voltage Density f = 10kHz 15.8 nV/√Hz
inNoise Current Density f = 10kHz 90 fA/√Hz
TRANSIENT RESPONSE
SR Slew Rate, VOUT 20% to 80% AV = 1, RL = 2kΩ, VO = 4VP-P 0.4 V/µs
tr, tf, Small
Signal
Rise Time, VOUT 10% to 90% AV
= 1,
VOUT = 100mVP-P
, Rf = 0Ω, R
L
=2k
Ω to
VCM
264 ns
Fall Time, VOUT 90% to 10% AV
= 1,
VOUT = 100mVP-P, Rf = 0Ω, R
L
= 2k
Ω to
VCM
254 ns
tsSettling Time to 0.01%
4V Step; 10% to VOUT
AV
= -1,
VOUT = 4VP-P, Rg = Rf =10k, R
L
=2k
Ω to
VCM
14.4 µs
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNIT
ISL28108, ISL28208, ISL28408
9FN6935.3
November 1, 2011
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
FIGURE 3. ISL28408 SOIC INPUT OFFSET VOLTAGE
DISTRIBUTION, VS= ±15V
FIGURE 4. ISL28408 SOIC INPUT OFFSET VOLTAGE
DISTRIBUTION, VS= ±5V
FIGURE 5. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION,
VS= ±15V
FIGURE 6. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION,
VS= ±5V
FIGURE 7. ISL28108 SOIC INPUT OFFSET VOLTAGE
DISTRIBUTION, VS= ±15V
FIGURE 8. ISL28108 SOIC INPUT OFFSET VOLTAGE
DISTRIBUTION, VS= ±5V
VOS (µV)
NUMBER OF AMPLIFIERS
0
50
100
150
200
250
300
350
400
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
VS = ±15V
VOS (µV)
NUMBER OF AMPLIFIERS
0
50
100
150
200
250
300
350
400
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
VS = ±5V
VOS (µV)
NUMBER OF AMPLIFIERS
0
50
100
150
200
250
300
VS = ±15V
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
VS = ±5V
VOS (µV)
NUMBER OF AMPLIFIERS
0
50
100
150
200
250
300
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
VOS (µV)
NUMBER OF AMPLIFIERS
0
50
100
150
200
VS = ±15V
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
VOS (µV)
NUMBER OF AMPLIFIERS
VS = ±5V
0
50
100
150
200
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
ISL28108, ISL28208, ISL28408
10 FN6935.3
November 1, 2011
FIGURE 9. ISL28108 TDFN INPUT OFFSET VOLTAGE
DISTRIBUTION, VS= ±15V
FIGURE 10. ISL28108 TDFN INPUT OFFSET VOLTAGE
DISTRIBUTION, VS= ±5V
FIGURE 11. ISL28408 SOIC TCVOS vs NUMBER OF AMPLIFIERS,
VS= ±15V
FIGURE 12. ISL28408 SOIC TCVOS vs NUMBER OF AMPLIFIERS,
VS= ±5V
FIGURE 13. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS,
VS= ±15V
FIGURE 14. ISL28208 SOIC TCVOS vs NUMBER OF AMPLIFIERS,
VS= ±5V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
VOS (µV)
NUMBER OF AMPLIFIERS
0
5
10
15
20
25
VS = ±15V
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
VOS (µV)
NUMBER OF AMPLIFIERS
0
5
10
15
20
25
VS = ±5V
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
VS = ±15V
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0
5
10
15
20
25
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0
5
10
15
20
25
30
VS = ±5V
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
0
2
4
6
8
10
12
14
16
18
20
22
24
VS = ±15V
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
0
2
4
6
8
10
12
14
16
18
20
22
24
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VS = ±5V
ISL28108, ISL28208, ISL28408
11 FN6935.3
November 1, 2011
FIGURE 15. ISL28208 TDFN TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±15V
FIGURE 16. ISL28208 TDFN TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±5V
FIGURE 17. ISL28108 SOIC TCVOS vs NUMBER OF AMPLIFIERS,
VS= ±15V
FIGURE 18. ISL28108 SOIC TCVOS vs NUMBER OF AMPLIFIERS,
VS= ±5V
FIGURE 19. ISL28108 TDFN TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±15V
FIGURE 20. ISL28108 TDFN TCVOS vs NUMBER OF AMPLIFIERS,
VS = ±5V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
0
2
4
6
8
10
12
14
16
18
20
22
24
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VS = ±15V
NUMBER OF AMPLIFIERS
TCVOS (µV/C)
0
2
4
6
8
10
12
14
16
18
20
22
24
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VS = ±5V
NUMBER OF AMPLIFIERS
0
5
10
15
20
25
30
35
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VS = ±15V
TCVOS (µV/C)
NUMBER OF AMPLIFIERS
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
TCVOS (µV/C)
0
5
10
15
20
25
30
VS = ±5V
NUMBER OF AMPLIFIERS
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
TCVOS (µV/C)
0
2
4
6
8
10
12
14
VS = ±15V
NUMBER OF AMPLIFIERS
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
TCVOS (µV/C)
0
2
4
6
8
10
12
14
VS = ±5V
ISL28108, ISL28208, ISL28408
12 FN6935.3
November 1, 2011
FIGURE 21. VOS vs TEMPERATURE FIGURE 22. IBIAS vs TEMPERATURE vs SUPPLY
FIGURE 23. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
FIGURE 24. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±5V
FIGURE 25. CMRR vs TEMPERATURE, VS = ±15V FIGURE 26. CMRR vs TEMPERATURE, VS = ±5V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
VOS (µV)
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
VS = ±5V
VS = ±2.25V
VS = ±20V
VS = ±15V
TEMPERATURE (°C)
-40-20 0 20406080100120
IBIAS (nA)
-25
-20
-15
-10
-5
0
VS = ±5V
VS = ± 15V
VS = ±21V
VS = ±1.5V
VS = ±2.25V
VOS (µV)
INPUT COMMON MODE VOLTAGE (V)
-500
-400
-300
-200
-100
0
100
200
300
400
500
13 13.5 14 14.5 15
-16 -15.5 -15 -14.5 -14
+25°C
+125°C
VS = ±15V
-40°C
VOS (µV)
INPUT COMMON MODE VOLTAGE (V)
-500
-400
-300
-200
-100
0
100
200
300
400
500
3 3.5 4 4.5 5
-6 -5.5 -5 -4.5 -4
+25°C
+125°C
VS = ±5V
-40°C
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CMRR (dB)
100
105
110
115
120
125
130 VS = ±15V
CHANNEL-A
CHANNEL-B
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
CMRR (dB)
100
105
110
115
120
125
130 VS = ±5V
CHANNEL-A
CHANNEL-B
ISL28108, ISL28208, ISL28408
13 FN6935.3
November 1, 2011
FIGURE 27. CMRR vs FREQUENCY, VS = ±15V FIGURE 28. PSRR vs FREQUENCY, VS = ±5V & ±15V
FIGURE 29. PSRR (DC) vs TEMPERATURE, VS = ±15V FIGURE 30. PSRR (DC) vs TEMPERATURE, VS = ±5V
FIGURE 31. OUTP UT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT,
VS = ±5V and ±15V
FIGURE 32. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT,
VS = ±5V and ±15V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
CMRR (dB)
FREQUENCY (Hz)
1m 1 10 100 1k 10k 100k 1M 10M100M 1G0.10.01
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
VS = ±15V
SIMULATION
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
120
CL = 4pF
VSOURCE = 1VP-P
RL = 10k
AV = 1
VS = ±5V, ±15V
PSRR+
PSRR-
TEMPERATURE (°C)
PSRR (dB)
120
125
130
135
140
-40 -20 0 20 40 60 80 100 120
VS = ±15V
TEMPERATURE (°C)
PSRR (dB)
120
125
130
135
140
-40 -20 0 20 40 60 80 100 120
VS = ±5V
V
+
- VOH (V)
LOAD CURRENT (mA)
0.001
0.01
0.1
1
0.001 0.01 0.1 1 10
VS = ±5V and ±15V
-40°C
+25°C
125°C
VOL - V
-
(V)
LOAD CURRENT (mA)
0.001
0.01
0.1
1
0.001 0.01 0.1 1 10
-40°C
+25°C
125°C
V
S
= ±5V and ±15V
ISL28108, ISL28208, ISL28408
14 FN6935.3
November 1, 2011
FIGURE 33. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT
VS = ±15V
FIGURE 34. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT
VS = ±5V
FIGURE 35. VOUT HIGH AND LOW vs TEMPERATURE,
VS=±15V,R
L=10k
FIGURE 36. VOUT HIGH AND LOW vs TEMPERATURE,
VS= ±5V, RL= 10k
FIGURE 37. SHORT CIRCUIT CURRENT vs TEMPERATURE,
VS=±15V
FIGURE 38. SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±5V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
-15
-14
-13
-12
-11
-10
V
OH
(V)
VOL(V)
I-FORCE (mA)
11
12
13
14
15
10
VS = ±15V
AV = 2
VIN = ±7.5V-DC
RF = RG = 100k
0 2 4 6 8 10 12 14 16 18 20 22 24
-40°C
0°C
+25°C
+75°C
125°C
1
2
3
4
5
-5
-4
-3
-2
-1
V
OH
(V)
VOL(V)
I-FORCE (mA)
VS = ±5V
AV = 2
VIN = ±2.5V-DC
RF = RG = 100k
0 2 4 6 8 10 12 14 16 18 20 22 24
-40°C
0°C
+25°C
125°C
+75°C
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
VOH AND VOL (mV)
0
10
20
30
40
50
60
70
80
90
100 VS = ±15V
RL = 10k V
OH
(V
+
TO V
OUT
)
VOL (VOUT TO V-)
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
VOH AND VOL (mV)
0
10
20
30
40
50
60
70
80
90
100 VS = ±5V
RL = 10k
V
OH
(V
+
TO V
OUT
)
VOL (VOUT TO V-)
Isc (mA)
0
5
10
15
20
25
30
35
40
45
50
TEMPERATURE (°C)
-40-20 0 20406080100120
VS = ±15V
RL = 10k
ISC-SINK
ISC-SOURCE
Isc (mA)
0
5
10
15
20
25
30
35
40
45
50 VS = ±5V
RL = 10k
TEMPERATURE (°C)
-40-20 0 20406080100120
ISC-SINK
ISC-SOURCE
ISL28108, ISL28208, ISL28408
15 FN6935.3
November 1, 2011
FIGURE 39. MAX OUTPUT VOLTAGE vs FREQUENCY FIGURE 40. NO PHASE REVERSAL
FIGURE 41. AVOL vs TEMPERATURE FIGURE 42. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V
FIGURE 43. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 44. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1k 10k 100k 1M
VOUT (VP-P)
FREQUENCY (Hz)
VS = ±15V
AV = 1
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
INPUT AND OUTPUT (V)
TIME (ms)
010202 4 6 8 12141618
VS = ±5V
VIN = ±5.9V
INPUT
OUTPUT
-60 -40 -20 0 20 40 60 80 100 120 140 160
TEMPERATURE (°C)
100
110
120
130
140
AVOL (dB)
VS = ± 15V
VS = ±5V
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
1 10 100 1k 10k 100k 1M 10M 100M 1G
GAIN (dB), PHASE (°)
FREQUENCY (Hz)
0.1
VS = ±15V
RL = 1MΩ
SIMULATION
GAIN
PHASE
ISUPPLY PER AMPLIFIER (µA)
VSUPPLY (V)
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
0 2 4 6 8 1012141618202224262830323436384042
-10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
100
ACL = 1
ACL = 10
ACL = 1001
VS = ±5V, ±15V
CL = 4pF
VOUT = 100mVP-P
RL = 2k
ACL = 101
RF = 0, RG = ∞
RF = 10kΩ, RG = 10Ω
RF = 10kΩ, RG = 100Ω
RF = 10kΩ, RG = 1.1kΩ
ISL28108, ISL28208, ISL28408
16 FN6935.3
November 1, 2011
FIGURE 45. GAIN vs FREQUENCY vs RL, VS = ±15V FIGURE 46. GAIN vs FREQUENCY vs RL, VS = ±5V
FIGURE 47. GAIN vs FREQUENCY vs OUTPUT VOLTAGE FIGURE 48. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 49. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V FIGURE 50. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±5V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
RL = 100
RL = 49.9
RL = 499
VS = ±15V
AV = +1
VOUT = 100mVP-P
CL = 4pF
100
RL = OPEN, 100k, 10k
RL = 1k
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100
VS = ±5V
AV = +1
VOUT = 100mVp-p
CL = 4pF RL = 100
RL = 49.9
RL = 499
RL = OPEN, 100k, 10k
RL = 1k
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100
VS = ±5V
AV = +1
RL = INF
CL = 4pF
VOUT = 50mVP-P
VOUT = 10mVP-P
VOUT = 100mVP-P
VOUT = 500mVP-P
VOUT = 1VP-P
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100 1k 10k 100k 1M 10M
CL = 4pF
RL = 10k
AV = +1
VOUT = 100mVP-P
VS = ±15V
VS = ±5V
VS = ±20V
VS = ±2.5V
0.01
0.10
1
10
100
10 100 1k 10k 100k 1M 10M
Z
OUT
(Ω)
FREQUENCY (Hz)
1
VS = ±15V
G = 1
G = 10
G = 100
0.01
0.10
1
10
100
10 100 1k 10k 100k 1M 10M
Z
OUT
(Ω)
FREQUENCY (Hz)
1
VS = ±5V
G = 100
G = 10
G = 1
ISL28108, ISL28208, ISL28408
17 FN6935.3
November 1, 2011
FIGURE 51. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±18V
FIGURE 52. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±5V
FIGURE 53. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS= ±18V FIGURE 54. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS= ±5V
FIGURE 55. ISL28208 CHANNEL SEPARATION vs FREQUENCY, VS =
±5V, ±15V
FIGURE 56. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS=±15V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (pA/√Hz)
0.01
0.1
1
10
100
0.01
0.1
1
10
100
VS = ±18V
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
INPUT NOISE CURRENT (pA/√Hz)
0.01
0.1
1
10
100
VS = ±5V
0.01
0.1
1
10
100
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
INPUT NOISE VOLTAGE (nV)
012345678910
TIME (s)
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
VS = ±18V
AV = 10k
INPUT NOISE VOLTAGE (nV)
012345678910
TIME (s)
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
VS = ±5V
AV = 10k
10 100 1k 10k 100k 1M 10M
CROSSTALK (dB)
FREQUENCY (Hz)
0
20
40
60
80
100
120
140
160 VS = ±15V
CL = 4pF
VTX = 1VP-P
RL_TRANSMIT = ∞
RL_RECEIVE = 10k
RL_TRANSMIT = 2k
RL_RECEIVE = 10k
OUTPUT (V)
INPUT (mV)
TIME (µs)
0
4
8
12
16
20
0
40
80
120
160
200
0 20 40 60 80 100 120 140 160 180 200
VS = ±15V
AV = 100
VIN = 100mVP-P
OVERDRIVE = 1V
RL = 10k
OUTPUT
INPUT
ISL28108, ISL28208, ISL28408
18 FN6935.3
November 1, 2011
FIGURE 57. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS=±15V
FIGURE 58. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS=±5V
FIGURE 59. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS= ±5V
FIGURE 60. OVERSHOOT vs CAPACITIVE LOAD, VS=±15V
FIGURE 61. OVERSHOOT vs CAPACITIVE LOAD, VS= ±5V FIGURE 62. LARGE SIGNAL 10V STEP RESPONSE, VS= ±15V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
OUTPUT (V)
INPUT (mV)
TIME (µs)
0 20 40 60 80 100 120 140 160 180 200
VS = ±15V
AV = 100
VIN = 100mVP-P
OVERDRIVE = 1V
RL = 10k
-20
-16
-12
-8
-4
0
-200
-160
-120
-80
-40
0
INPUT
OUTPUT
OUTPUT (V)
INPUT (mV)
TIME (µs)
0
1
2
3
4
5
6
0
10
20
30
40
50
60
VS = ±5V
AV = 100
VIN = 50mVP-P
OVERDRIVE = 1V
RL = 10k
0 20 40 60 80 100 120 140 160 180 200
OUTPUT
INPUT
OUTPUT (V)
INPUT (mV)
TIME (µs)
-6
-5
-4
-3
-2
-1
0
-60
-50
-40
-30
-20
-10
0
VS = ±5V
AV = 100
VIN = 50mVP-P
OVERDRIVE = 1V
RL = 10k
0 20 40 60 80 100 120 140 160 180 200
INPUT
OUTPUT
OVERSHOOT (%)
LOAD CAPACITANCE (nF)
0
10
20
30
40
50
60
0.001 0.010 0.100 1 10 100
V
S
= ±15V
V
OUT
= 100mV
P-P
AV = 10
AV = 1
AV = -1
OVERSHOOT (%)
LOAD CAPACITANCE (nF)
0
10
20
30
40
50
60
0.001 0.010 0.100 1 10 100
V
S
= ±5V
V
OUT
= 100mV
P-P
AV = 10
AV = 1
AV = -1
-6
-4
-2
0
2
4
6
V
OUT
(V)
TIME (µs)
0 100 200 300 400
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
ISL28108, ISL28208, ISL28408
19 FN6935.3
November 1, 2011
FIGURE 63. LARGE SIGNAL 4V STEP RESPONSE, VS= ±5V FIGURE 64. SMALL SIGNAL TRANSIENT RESPONSE VS = ±5V, ±15V
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
0
V
OUT
(V)
TIME (µs)
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
2.4
100 200 300 400
VS = ±5V
AV = 1
RL = 2k
CL = 4pF
V
OUT
(mV)
TIME (µs)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
VS = ±5V
AND
ISL28108, ISL28208, ISL28408
20 FN6935.3
November 1, 2011
Applications Information
Functional Description
The ISL28108, ISL28208, and ISL28408 are single, dual and
quad, 1.2MHz, single supply rail-to-rail output amplifiers with a
common mode input voltage range extending to a range of 0.5V
below the V- rail. Their input stages are optimized for precision
sensing of ground referenced signals in low voltage, single supply
applications. The input stage has the capability of handling large
input differential voltages without phase inversion making them
suitable for high voltage comparator applications. Their bipolar
design features high open loop gain and excellent DC input and
output temperature stability. These op amps feature low
quiescent current of 165µA, and a maximum temperature drift
ranging from 1.1µV/°C for the ISL28208 and ISL28408 in the
SOIC package to 1.4µV/°C for the ISL28208 in the TDFN
package and the ISL28408 in the SOIC package (see Figures 11
through 20. All devices are fabricated in a new precision 40V
complementary bipolar DI process and immune from latch-up.
Operating Voltage Range
The devices are designed to operate over the 3V (±1.5V) to 40V
(±20V) range and are fully characterized at ±5V and ±15V. Both DC
and AC performance remain virtually unchanged over the ±5V to
±15V operating voltage range. Parameter variation with operating
voltage is shown in the “Typical Performance Curves” beginning on
page 9.
Input Stage Performance
The PNP input stage has a common mode input range extending
up to 0.5V below ground at +25°C (see Figures 23 and 24). Full
amplifier performance is guaranteed down to ground (V-) over the -
40°C to +125°C temperature range. For common mode voltages
down to -0.5V the amplifiers are fully functional, but performance
degrades slightly over the full temperature range. This feature
provides excellent CMRR, AC performance and DC accuracy when
amplifying low level ground referenced signals.
The input stage has a maximum input differential voltage equal
to a diode drop greater than the supply voltage (max 42V) and
does not contain the back-to-back input protection diodes found
on many similar amplifiers. This feature enables the device to
function as a precision comparator by maintaining very high
input impedance for high voltage differential input comparator
voltages. The high differential input impedance also enables the
device to operate reliably in large signal pulse applications
without the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. Thus, input
signal distortion caused by nonlinear clamps under high slew
rate conditions are avoided.
In applications where one or both amplifier input terminals are at
risk of exposure to voltages beyond the supply rails, current
limiting resistors may be needed at each input terminal (see
Figure 65 RIN+, RIN-) to limit current through the power supply
ESD diodes to 20mA.
Output Drive Capability
The bipolar rail-to-rail output stage features low saturation levels
that enable an output voltage swing to less than 10mV when the
total output load (including feedback resistance) is held below
50µA (Figures 31 and 32). With ±15V supplies this can be
achieved by using feedback resistor values >300kΩ. The low input
bias and offset currents (-43nA and ±3nA +25°C max
respectively) minimize DC offset errors at these high resistance
values. For example, a balanced 4 resistor gain circuit (Figure 65)
with 1MΩ feedback resistors (RF, RG) generates a worst case
input offset error of only ±3mV. Furthermore, the low noise
current reduces the added noise associated with high feedback
resistance.
The output stage is internally current limited. Output current limit
over-temperature is shown in Figures 37 and 38. The amplifiers
can withstand a short circuit to either rail as long as the power
dissipation limits are not exceeded. This applies to only one
amplifier at a time for the dual op amp. Continuous operation
under these conditions may degrade long-term reliability.
The amplifiers perform well driving capacitive loads (Figures 60
and 61). The unity gain, voltage follower (buffer) configuration
provides the highest bandwidth, but is also the most sensitive to
ringing produced by load capacitance found in BNC cables. Unity
gain overshoot is limited to 30% at capacitance values to 0.33nF.
At gains of 10 and higher, the device is capable of driving more
than 10nF without significant overshoot.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. These devices are immune to output phase reversal, out
to 0.5V beyond the rail (VABS MAX) limit (see Figure 40).
FIGURE 65. INPUT ESD DIODE CURRENT LIMITING
-
+
RIN-
RL
VIN-
V+
V-
RIN+
VIN+
RF
RG
ISL28108, ISL28208, ISL28408
21 FN6935.3
November 1, 2011
Unused Channels
If the application requires only one channel, the user must
configure any unused channel to prevent it from oscillating.
Unused channels can oscillate if the input and output pins are
floating. This will result in higher-than-expected supply currents
and possible noise injection into the channel being used. The
proper way to prevent oscillation is to short the output to the
inverting input, and ground the positive input (Figure 66).
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
•P
DMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
•PD
MAX for each amplifier can be calculated using Equation 2:
where:
•T
MAX = Maximum ambient temperature
•θJA = Thermal resistance of the package
•PD
MAX = Maximum power dissipation of 1 amplifier
•V
S = Total supply voltage
•I
qMAX = Maximum quiescent supply current of 1 amplifier
•V
OUTMAX = Maximum output voltage swing of the application
•R
L = Load resistance
ISL28108, ISL28208, ISL28408 SPICE Model
Figure 67 shows the SPICE model schematic and Figure 68 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The
DC parameters are IOS, total supply current and output voltage
swing. The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 5. The AVOL is adjusted
for 122dB with the dominant pole at 1Hz. The CMRR is set 128dB,
f = 6kHz. The input stage models the actual device to present an
accurate AC representation. The model is configured for ambient
temperature of +25°C.
Figures 69 through 83 show the characterization vs simulation
results for the Noise Voltage, Open Loop Gain Phase, Closed Loop
Gain vs Frequency, Gain vs Frequency vs RL, CMRR, Large Signal
10V Step Response, Small Signal 0.05V Step and Output Voltage
Swing ±15V supplies.
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the macro-
model, in whole, in part, or in modified form, to anyone outside
the Licensee’s company. The Licensee may modify the macro-
model to suit his/her specific applications, and the Licensee may
make copies of this macro-model for use within their company
only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FIGURE 66. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
TJMAX TMAX θJAxPDMAXTOTAL
+= (EQ. 1)
PDMAX VSIqMAX VS
( - VOUTMAX)VOUTMAX
RL
------------------------
×+×=(EQ. 2)
ISL28108, ISL28208, ISL28408
22 FN6935.3
November 1, 2011
Common Mode
Gain Stage
with Zero
Correction Current SourcesOutput Stage
Input Stage 1st Gain Stage
Mid Supply ref V2nd Gain Stage
Vc
Vmid
Vmid
Vmid
13
26
V-
2
15
20
V++
V--
19
27
V++
VOUT
5
14
23
Vmid
V--
V++
V--
6
17
V+
Vg
16
11
Vin+
8
V--
107
9
22
21
24
18
Vc
25
1
28
V++
12
Vin-
0
0
0
0
+
-
G1
GAIN = 0.477
-
+
+
-
EOS
E
GAIN = 1
EOS
E
GAIN = 1
+
-
G15
GAIN = 314.15e-6
CinDif
1.21e-12
Q8
PNP_LATERAL Q8
+
-
G8
GAIN = 0.6
C6
10e-12
R11
1e-3
IOS
3e-9
R5 11
DX
D11
R13
3.183e3
R13
C2
2.31e-11
D1DBREAKD1DBREAK
R7
7.62e9
DX
D3
V2
-6.76
-
+
+
-
E4
GAIN = 0.5
+
-
G7
GAIN = 0.6GAIN = 0.6
+
-
G5
GAIN = 0.6
I2
6E-6
C3
10e-12
C3
10e-12
V4
-6.76
DX
D8
+
-
G16
GAIN = 314.15e-6
DY
D12
+
-
G13
GAIN = 12.5e-3
R19
3.183e3
Q9
PNP_LATERAL
Q9
PNP_LATERAL
+
-
G11
GAIN = 12.5e-3
+
-
G2
GAIN = 0.477
+
-
G3
GAIN = 261.74e-6
R4
6250
DX
D10
DN
D14
R15
80
R8
7.62e9
L1
1.59E-08
C5
10e-12
C5
10e-12
V5
-0.4
V5
-0.4
R9
1e-3
DN
D13
V3
-6.74
-
+
+
-
E3
GAIN = 1
+
-
G9
GAIN = 314.15e-6
L3
1.59E-08
R3
6250
V6
-0.4
V6
Cin2
4.19e-12
DX
D4
+
-
G12
GAIN = 12.5e-3
Q7
PNP_input
Q7
I3
6E-6
+
-
G6
GAIN = 0.6
DX
R1
5e11
R14
3.183e3
R12
1e-3 C4
10e-12
C4
10e-12
DX
D7
-
+
+
-
GAIN = 0.3
DY
D9
Q6
PNP_input
R10
1e-3
-
+
+
-
E2
GAIN = 1
E2
+
-
G4
GAIN = 261.74e-6
1150
I1
12e-6
+
-
G14
GAIN = 12.5e-3
L4
1.59E-08
DX
D5
D2DBREAKD2DBREAK
R6 1
L2
1.59E-08
ISY
185e-6
ISY
R16
80
V1
-6.74
R20
3.183e3
+
-
G10
GAIN = 314.15e-6
C1
2.31e-11
R2
V7
0.10.1
Cin1
4.19e-12
FIGURE 67. SPICE MODEL SCHEMATIC
ISL28108, ISL28208, ISL28408
23 FN6935.3
November 1, 2011
*ISL28108_208 Macromodel - covers following
*products
*ISL28108
*ISL28208
*ISL28408
*
*Revision History:
* Revision A, LaFontaine March 5th 2011
* Model for Noise, supply currents, CMRR
*128dB f=6kHz ,AVOL 122dB f=1Hz
* SR = 0.45V/us, GBWP 1.2MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE STATEMENT"
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance characteristics
*under a wide range of external circuit
*configurations using compatible simulation
*platforms – such as iSim PE.
*
*Device performance features supported by this
*model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate,
*Input and Output Headroom limits to I/O
*voltage swing,
*Supply current at nominal specified supply
*voltages.
*
*Device performance features NOT supported
*by this model:
*Harmonic distortion effects,
*Output current limiting (current will limit at
*40mA),
*Disable operation (if any),
*Thermal effects and/or over temperature
*parameter variation,
*Limited performance variation vs. supply
*voltage is modeled,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging source,
*Load current reflected into the power supply
*current.
*
* Connections: +input
* | -input
* | | +Vsupply
* | | | -Vsupply
* | | | | output
* | | | |
.subckt ISL28108_208 Vin+ Vin-V+ V- VOUT
* source ISL28118_218_subckt_check_0
*
*Voltage Noise
E_En VIN+ 6 2 0 0.3
D_D13 1 2 DN
D_D14 1 2 DN
V_V7 1 0 0.1
R_R17 2 0 1150
*
*Input Stage
Q_Q6 11 10 9 PNP_input
Q_Q7 8 7 9 PNP_input
Q_Q8 V-- VIN- 7 PNP_LATERAL
Q_Q9 V-- 12 10 PNP_LATERAL
I_I1 V++ 9 DC 12e-6
I_I2 V++ 7 DC 6E-6
I_I3 V++ 10 DC 6E-6
I_IOS 6 VIN- DC 3e-9
*D_D1 7 10 DBREAK
*D_D2 10 7 DBREAK
R_R1 5 6 5e11
R_R2 VIN- 5 5e11
R_R3 V-- 8 6250
R_R4 V-- 11 6250
C_Cin1 V-- VIN- 4.19e-12
C_Cin2 V-- 6 4.19e-12
C_CinDif 6 VIN- 1.21E-12
*
*1st Gain Stage
G_G1 V++ 14 8 11 0.4779867
G_G2 V-- 14 8 11 0.4779867
V_V1 13 14 -6.74
V_V2 14 15 -6.76
D_D3 13 V++ DX
D_D4 V-- 15 DX
R_R5 14 V++ 1
R_R6 V-- 14 1
*
*2nd Gain Stage
G_G3 V++ VG 14 VMID 261.748e-6
G_G4 V-- VG 14 VMID 261.748e-6
V_V3 16 VG -6.74
V_V4 VG 17 -6.76
D_D5 16 V++ DX
D_D6 V-- 17 DX
R_R7 VG V++ 7.62283e9
R_R8 V-- VG 7.62283e9
C_C1 VG V++ 2.31e-11
C_C2 V-- VG 2.31e-11
*
*Mid supply Ref
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
E_E4 VMID V-- V++ V-- 0.5
I_ISY V+ V- DC 185E-6
*
*Common Mode Gain Stage with Zero
G_G5 V++ 19 5 VMID 0.6
G_G6 V-- 19 5 VMID 0.6
G_G7 V++ VC 19 VMID 0.6
G_G8 V-- VC 19 VMID 0.6
E_EOS 12 6 VC VMID 1
L_L1 18 V++ 1.59159E-08
L_L2 20 V-- 1.59159E-08
L_L3 21 V++ 1.59159E-08
L_L4 22 V-- 1.59159E-08
R_R9 19 18 1e-3
R_R10 20 19 1e-3
R_R11 VC 21 1e-3
R_R12 22 VC 1e-3
*
*Pole Satge
G_G15 V++ 28 VG VMID 314.15e-6
G_G16 V-- 28 VG VMID 314.15e-6
R_R19 28 V++ 3.18319e3
R_R20 V-- 28 3.18319e3
C_C5 28 V++ 10e-12
C_C6 V-- 28 10e-12
*
G_G9 V++ 23 28 VMID 314.15e-6
G_G10 V-- 23 28 VMID 314.15e-6
R_R13 23 V++ 3.18319e3
R_R14 V-- 23 3.18319e3
C_C3 23 V++ 10e-12
C_C4 V-- 23 10e-12
*
*Output Stage with Correction Current Sources
G_G11 26 V-- VOUT 23 12.5e-3
G_G12 27 V-- 23 VOUT 12.5e-3
G_G13 VOUT V++ V++ 23 12.5e-3
G_G14 V-- VOUT 23 V-- 12.5e-3
D_D7 23 24 DX
D_D8 25 23 DX
D_D9 V-- 26 DY
D_D10 V++ 26 DX
D_D11 V++ 27 DX
D_D12 V-- 27 DY
V_V5 24 VOUT -0.4
V_V6 VOUT 25 -0.4
R_R15 VOUT V++ 80
R_R16 V-- VOUT 80
.model PNP_LATERAL pnp(is=1e-016 bf=250
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1)
.model PNP_input pnp(is=1e-016 bf=100
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1)
.model DBREAK D(bv=43 rs=1)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28108_208
FIGURE 68. SPICE NET LIST
ISL28108, ISL28208, ISL28408
24 FN6935.3
November 1, 2011
Characterization vs Simulation Results
FIGURE 69. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 70. SIMULATED INPUT NOISE VOLTAGE
FIGURE 71. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 72. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
FIGURE 73. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY FIGURE 74. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
10
100
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
100
0.1 1 10 100 1k 10k 100k
INPUT NOISE VOLTAGE (nV/√Hz)
FREQUENCY (Hz)
10
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
1 10 100 1k 10k 100k 1M 10M 100M 1G
GAIN (dB), PHASE (°)
FREQUENCY (Hz)
0.1
VS = ±15V
RL = 1MΩ
SIMULATION
GAIN
PHASE
-100
-50
0
50
100
150
200
1 10 100 1k 10k 100k 1M 10M 100M 1G
GAIN (dB), PHASE (°)
FREQUENCY (Hz)
0.1
VS = ±15V
RL = 1MΩ
SIMULATION
PHASE
GAIN
-10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
100
ACL = 1
ACL = 10
ACL = 1001
VS = ±5V, ±15V
CL = 4pF
VOUT = 100mVP-P
RL = 2k
ACL = 101
RF = 0, RG = ∞
RF = 10kΩ, RG = 10Ω
RF = 10kΩ, RG = 100Ω
RF = 10kΩ, RG = 1.1kΩ
-10
0
10
20
30
40
50
60
70
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
100
VS = ±5V, ±15V
CL = 4pF
VOUT = 100mVP-P
RL = 2k
RF = 0, RG = ∞
RF = 10kΩ, RG = 1.1kΩ
RF = 10kΩ, RG = 100Ω
RF = 10kΩ, RG = 10Ω
ISL28108, ISL28208, ISL28408
25 FN6935.3
November 1, 2011
FIGURE 75. CHARACTERIZED GAIN vs FREQUENCY vs RLFIGURE 76. SIMULATED GAIN vs FREQUENCY vs RL
FIGURE 77. CHARACTERIZED CMRR vs FREQUENCY FIGURE 78. SIMULATED CMRR vs FREQUENCY
FIGURE 79. CHARACTERIZED LARGE SIGNAL 10V STEP RESPONSE FIGURE 80. SIMULATED LARGE SIGNAL 10V STEP RESPONSE
Characterization vs Simulation Results (Continued)
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
RL = 100
RL = 49.9
RL = 499
VS = ±15V
AV = +1
VOUT = 100mVP-P
CL = 4pF
100
RL = OPEN, 100k, 10k
RL = 1k
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
100k 1M 10M10k1k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
VS = ±15V
AV = +1
VOUT = 100mVP-P
CL = 4pF
100
RL = 100
RL = 49.9
RL = 499
R
L
= OPEN, 100k, 10k
RL = 1k
CMRR (dB)
FREQUENCY (Hz)
1m 1 10 100 1k 10k 100k 1M 10M100M 1G0.10.01
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
VS = ±15V
SIMULATION
0
50
100
150
CMRR (dB)
FREQUENCY (Hz)
1m 1 10 100 1k 10k 100k 1M 10M100M 1G0.10.01
VS = ±15V
SIMULATION
-6
-4
-2
0
2
4
6
V
OUT
(V)
TIME (µs)
0 100 200 300 400
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
-6
-4
-2
0
2
4
6
V
OUT
(V)
TIME (µs)
0 100 200 300 400
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
ISL28108, ISL28208, ISL28408
26
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6935.3
November 1, 2011
For additional products, see www.intersil.com/product_tree
FIGURE 81. CHARACTERIZED SMALL SIGNAL TRANSIENT
RESPONSE
FIGURE 82. SIMULATED SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 83. SIMULATED OUTPUT VOLTAGE SWING
Characterization vs Simulation Results (Continued)
V
OUT
(mV)
TIME (µs)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
VS = ±5V
AND
V
OUT
(mV)
TIME (µs)
-100
-80
-60
-40
-20
0
20
40
60
80
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VS = ±15V
AV = 1
RL = 2k
CL = 4pF
VS = ±5V
AND
0 0.5 1.0 1.5 2.0
-20
-10
0
10
20
OUTPUT VOLTAGE SWING (V)
TIME (m s)
VOH = 14.93V
VOL = -14.94V
ISL28108, ISL28208, ISL28408
27 FN6935.3
November 1, 2011
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE REVISION CHANGE
10/19/11 FN6935.3 • On page 1, Features: changed Low Input Offset Voltage from 230µV to (ISL28108)……150µV. Added Related
Literature section with AN1658, "ISL28208SOICEVAL2Z Evaluation Board User Guide".
• On page 2, Ordering Information: added ISL28208SOICEVAL2Z evaluation board. Removed "Coming Soon" from
ISL28408FBZ. Corrected Package Dwg. # for TDFN package from L8.3x3A to L8.3x3K. Corrected Package Dwg. #
for MSOP package from M8.118 to M8.118B.
• On page 5, Absolute Maximum Ratings, changed “ESD Tolerance (ISL28208)” to “ESD Tolerance (ISL28208,
ISL28408)”. Added ESD information for ISL28108 as follows:
ESD Tolerance (ISL28108)
Human Body Model (Tested per JESD22-A114F).....5.5kV
Machine Model (Tested per JESD22-A115-C).....300V
Charged Device Model (Tested per JESD22-C110D).....2kV
• On page 5, Thermal Information, changed package temperatures from:
8 Ld SOIC Package (108, 208, Notes 4, 7), θJA = 120, θJC = 55
8 Ld TDFN Package (108, 208, Notes 5, 6), θJA = 47, θJC = 6
8 Ld MSOP Package (108, 208, Notes 4, 7), θJA = 150, θJC = 45
14 Ld SOIC Package (408, Notes 4, 7), θJA = -, θJA = -
To:
8 Ld SOIC Package (208, Notes 4, 7), θJA = 120, θJC = 55
8 Ld SOIC Package (108, Notes 4, 7), θJA = 120, θJC = 60
8 Ld TDFN Package (208, Notes 5, 6), θJA = 47, θJC = 6
8 Ld TDFN Package (108, Notes 5, 6), θJA = 45, θJC = 3.5
8 Ld MSOP Package (208, Notes 4, 7), θJA = 150, θJC = 50
8 Ld MSOP Package (108, Notes 4, 7), θJA = 165, θJC = 57
14 Ld SOIC Package (408, Notes 4, 7), θJA = 71, θJC = 37
• On page 5, ±15V Electrical Specifications table, added the following parameters:
- VOS ISL28108 SOIC, TDFN
- TCVOS ISL28108 SOIC, TDFN
- IOS ISL28108 SOIC, TDFN
• On page 5 and 6, ±15V Electrical Specifications table, changed the following in Conditions column:
- VOS: changed “ISL28208 SOIC, TDFN” to “ISL28208 SOIC, TDFN; ISL28408 SOIC”
- TCVOS: changed “ISL28208 TDFN” to”ISL28208 TDFN, ISL28408 SOIC”
- IOS: changed “ISL28108 SOIC, TDFN” to “ISL28108 SOIC, TDFN; ISL28408 SOIC”
• On page 7, ±5V Electrical Specifications table, added the following:
- VOS ISL28108 SOIC, TDFN
- TCVOS ISL28108 SOIC, TDFN
- IOS ISL28108 SOIC, TDFN
• On page 7, ±5V Electrical Specifications table, changed the following in Conditions column:
- VOS: changed “ISL28208 SOIC, TDFN” to “ISL28208 SOIC, TDFN; ISL28408 SOIC”
- TCVOS: changed “ISL28208 TDFN” to”ISL28208 TDFN, ISL28408 SOIC”
- IOS: changed “ISL28108 SOIC, TDFN” to “ISL28108 SOIC, TDFN; ISL28408 SOIC”
• On page 9 through page 11, added the following to Typical Performance Curves:
- Figures 3, 4: ISL28408 SOIC Input Offset Distribution Voltage, ±15V and ±5V
- Figures 7, 8: ISL28108 SOIC ±15V VOS distribution, and ±5V VOS distribution
- Figures 9, 10: ISL28108 TDFN ±15V VOS distribution, and ±5V VOS distribution
- Figures 11, 12: ISL28408 SOIC TCVOS vs. number of Amplifiers ±15V and ±5V
- Figures 17, 18: ISL28108 SOIC ±15V TCVOS distribution, and ±5V TCVOS distribution
- Figures 19, 20: ISL28108 TDFN ±15V TCVOS distribution, and ±5V TCVOS distribution
• On page 20, Applications: minor edits to re-align figures with curves
• On page 21: changed heading from “Using Only One Amplifier to “Unused Channels” and edited for clarity.
• On page 30: changed Package Outline Drawing L8.3x3A to L8.3x3K
• On page 31: changed Package Outline Drawing M8.118 to M8.118B
• On page 32: added Package Outline Drawing M14.15
ISL28108, ISL28208, ISL28408
28 FN6935.3
November 1, 2011
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28108, ISL28208, ISL28408.
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
4/20/11 FN6935.2 • Added discussion of ISL28408 throughout datasheet.
• On page 2 in “Ordering Information”: Added new part, “ISL28408FBZ”. Corrected part marking for
ISL28208FRTZ from 208Z to 208F. Added “ISL28408” to Note 3. Under” Pin Configurations,” added
ISL28408 (14 Ld SOIC) pin configuration diagram.
• On page 3: in Pin Descriptions table, added column for ISL28408 14Ld SOIC. Corrected schematic for
Circuit 2.
• On page 5: under “Thermal Information” added "14 Ld SOIC Package (408, Notes 4, 7)" and added
ISL28108 to 8 Ld TDFN and 8 Ld MSOP. Changed θJA and θJC for 8 Ld TDFN Package from 48 and 5.5 to 47
and 6. Added Note 6 regarding θJC “case temp” measurement, and applied it to 8 Ld TDFN Package.
• On page 5: in Electrical Specifications table, changed TYP spec for TCIB from 70 pA/° C to 0.07nA/° C. On
page 7, changed TYP spec for TCIB from -67 pA/° C to -0.067nA/° C. These are not spec changes since the
values are the same.
• On page 13, Figs. 31 and 32: changed y axis units label from (mV) to (V); changed x axis units label from (µA)
to (mA).
• On page 20, under “Output Drive Capability,” para 2, changed "The output stage can swing at moderate
levels of output current (Figures 21 and 22) and the output stage is internally current limited. Output current
limit over-termperature..." to "The output stage is internally current limited. Output current limit over-
temperature..."
3/11/11 FN6935.1 • On page 1, in the first paragraph - added the following after V-rail: "a rail-to-rail differential input voltage
range for use as a comparator,…"
•On page1 in “Features:
- Added bullet - “Rail-to-rail Input Differential Voltage Range for Comparator Applications”
- Changed Low Noise Current from "100fA/sq.root Hz" to "80fA/sq.root Hz"
• On page 2 in “Ordering Information” - Removed "coming soon" from ISL28208FRTZ part since it is
releasing.
• On page 5, changed “ESD Tolerance (ISL28208, ISL28408)” as follows:
- Human Body Model changed from "3kV" to "6kV"
- Machine Model changed from "300V" to "400V"
- Added JEDEC Test information for all ESD ratings
• On page 5 and page 7, added test conditions for SOIC TCVos specs. Added TCVos specs for TDFN.
• On page 6 changed “Noise Current Density” Typical from "100" to "80"
• On page 20, updated Applications Information Functional Description
• On page 20 Updated Input Stage Performance Section
• On page 20 Updated Output Drive Capability Section
• On page 21 Added ISL28108 AND ISL28208 SPICE MODEL and License Agreement section
• On page 22 Added SPICE NET LIST
• On page 24 Added Characterization vs Simulation Results curves
2/16/11 FN6935.0 Initial Release
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev. (Continued)
DATE REVISION CHANGE
ISL28108, ISL28208, ISL28408
29 FN6935.3
November 1, 2011
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”
ISL28108, ISL28208, ISL28408
30 FN6935.3
November 1, 2011
Package Outline Drawing
L8.3x3K
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 9/11
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
C 0 . 203 REF
0 . 05 MAX.
0 . 02 NOM.
5
3.00 A
B
3.00
(4X) 0.15
6
PIN 1
INDEX AREA
PIN #1
6X 0.65
1.50 ±0.10
8
1
0.40 ± 0.05
6
0.75 ±0.05
SEE DETAIL "X"
0.08
0.10 C
C
C
( 2.90 )
(1.50)
( 8 X 0.25)
( 8X 0.50)
( 1.95)
2.30 ±0.10
0.10
8X 0.25 ±0.05
AMC B
4
2X 1.95
(6x 0.65)
INDEX AREA
PIN 1
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.20mm from the terminal tip.
Dimension applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
( 2.30)
ISL28108, ISL28208, ISL28408
31 FN6935.3
November 1, 2011
Package Outline Drawing
M8.118B
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 7/11
DETAIL "X"
SIDE VIEW 2
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
PIN# 1 ID
0.23 - 0.36mm
DETAIL "X"
0.10 ± 0.05mm
(4.40)
(3.00)
(5.80)
H
C
1.10 MAX
3°±3°
GAUGE
PLANE 0.25
0.95 REF
0.53 ± 0.10mm
B
3.0±0.10mm
12
8
0.86±0.05mm
SEATING PLANE
A
0.65mm BSC
3.0±0.10mm
(0.40)
(1.40)
(0.65)
D
5
5
0.15 - 0.05mm
SIDE VIEW 1
0.08 C A-B D
M0.10 C
Dimensioning and tolerancing conform to JEDEC MO-187-AA
Plastic interlead protrusions of 0.15mm max per side are not
Dimensions in ( ) are for reference only.
Dimensions are measured at Datum Plane "H".
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions are in millimeters.
3.
4.
5.
6.
NOTES:
1.
2.
and AMSEY14.5m-1994.
included.
included.
4.9±0.20mm
ISL28108, ISL28208, ISL28408
32 FN6935.3
November 1, 2011
Package Outline Drawing
M14.15
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
A
D
4
0.25 A-BMC
C
0.10 C
5B
D
3
0.10 A-BC
4
0.20 C 2X
2X
0.10 DC 2X
H
0.10 C
6
36
ID MARK
PIN NO.1 (0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
1.27
0.31-0.51
4° ± 4°
DETAIL"A" 0.22±0.03
0.10-0.25
1.25 MIN
1.75 MAX
(1.27) (0.6)
6.0
8.65
3.9
7
14 8
Dimensioning and tolerancing conform to AMSEY14.5m-1994.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Datums A and B to be determined at Datum H.
4.
5.
3.
2.
Dimensions are in millimeters.
NOTES:
1.
The pin #1 indentifier may be either a mold or mark feature.
6. Does not include dambar protrusion. Allowable dambar protrusion
7. Reference to JEDEC MS-012-AB.
shall be 0.10mm total in excess of lead width at maximum condition.
DETAIL "A"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
