INTEGRATED CIRCUITS P87C51RA2/RB2/RC2/RD2 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP, 512B/512B/512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Product data Supersedes data of 2002 Oct 28 2003 Jan 24 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 * CMOS and TTL compatible * Two speed ranges at VCC = 5 V DESCRIPTION The devices are Single-Chip 8-Bit Microcontrollers manufactured in an advanced CMOS process and are derivatives of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set. - 0 to 30 MHz with 6-clock operation - 0 to 33 MHz with 12-clock operation * Parallel programming with 87C51 compatible hardware interface The devices support 6-clock/12-clock mode selection by programming an OTP bit (OX2) using parallel programming. In addition, an SFR bit (X2) in the clock control register (CKCON) also selects between 6-clock/12-clock mode. to programmer * RAM expandable externally to 64 kbytes * Programmable Counter Array (PCA) The devices also have four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. - PWM - Capture/compare * PLCC, LQFP, or DIP package * Extended temperature ranges * Dual Data Pointers * Security bits (3 bits) * Encryption array - 64 bytes * Seven interrupt sources * 4 interrupt priority levels * Four 8-bit I/O ports * Full-duplex enhanced UART The added features of the P87C51RA2/RB2/RC2/RD2 make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. FEATURES * 80C51 Central Processing Unit - 8 kbytes OTP (87C51RA2) - 16 kbytes OTP (87C51RB2) - 32 kbytes OTP (87C51RC2) - 64 kbytes OTP (87C51RD2) - 512 byte RAM (87C51RA2/RB2/RC2) - 1 kbyte RAM (87C51RD2) - Framing error detection - Boolean processor - Automatic address recognition * Three 16-bit timers/counters T0, T1 (standard 80C51) and - Fully static operation additional T2 (capture and compare) - Low voltage (2.7 V to 5.5 V at 16 MHz) operation * Programmable clock-out pin * Asynchronous port reset * Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock * 12-clock operation with selectable 6-clock operation (via software or via parallel programmer) * Memory addressing capability - Up to 64 kbytes ROM and 64 kbytes RAM mode) * Power control modes: * Wake-up from Power Down by an external interrupt - Clock can be stopped and resumed - Idle mode - Power-down mode 2003 Jan 24 2 853-2391 29335 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) SELECTION TABLE Serial Interfaces PWM PCA WD UART I 2C CAN SPI ADC bits/ch. I/O Pins Interrupts (Ext.)/Levels Default Clock Rate Optional Clock Rate Reset active low/high? P87C51RD2 1K - 64K - 4 - - - - 32 7(2)/4 12-clk 6-clk H 30/33 0-16 0-30/33 P87C51RC2 512B - 32K - 4 - - - - 32 7(2)/4 12-clk 6-clk H 30/33 0-16 0-30/33 P87C51RB2 512B - 16K - 4 - - - - 32 7(2)/4 12-clk 6-clk H 30/33 0-16 0-30/33 P87C51RA2 512B - 8K - 4 - - - - 32 7(2)/4 12-clk 6-clk H 30/33 0-16 0-30/33 Program Security # of Timers Max. Freq. at 6-clk / 12-clk (MHz) RAM Flash Timers OTP Memory ROM Type Freq. Range at 3V (MHz) Freq. Range at 5V (MHz) ORDERING INFORMATION PHILIPS ((EXCEPT NORTH AMERICA)) PART ORDER NUMBER PART MARKING MEMORY TEMPERATURE RANGE (C) AND PACKAGE VOLTAGE RANGE DWG # OTP RAM P87C51RA2BA 8 KB 512B 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RA2FA 8 KB 512B -40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RA2BBD 8 KB 512B 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RB2BA 16 KB 512B 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RB2FA 16 KB 512B -40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RB2BBD 16 KB 512B 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RB2BN 16 KB 512B 0 to +70, DIP40 2.7 to 5.5 V SOT129-1 P87C51RB2FN 16 KB 512B -40 to +85, DIP40 2.7 to 5.5 V SOT129-1 P87C51RC2BA 32 KB 512B 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RC2FA 32 KB 512B -40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RC2BBD 32 KB 512B 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RC2BN 32 KB 512B 0 to +70, DIP40 2.7 to 5.5 V SOT129-1 P87C51RC2FN 32 KB 512B -40 to +85, DIP40 2.7 to 5.5 V SOT129-1 P87C51RD2BA 64 KB 1 KB 0 to +70, PLCC 2.7 to 5.5 V SOT187-2 P87C51RD2FA 64 KB 1 KB -40 to +85, PLCC 2.7 to 5.5 V SOT187-2 P87C51RD2BBD 64 KB 1 KB 0 to +70, LQFP 2.7 to 5.5 V SOT389-1 P87C51RD2FBD 64 KB 1 KB -40 to +85, LQFP 2.7 to 5.5 V SOT389-1 P87C51RD2BN 64 KB 1 KB 0 to +70, DIP40 2.7 to 5.5 V SOT129-1 2003 Jan 24 3 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 BLOCK DIAGRAM 1 ACCELERATED 80C51 CPU (12-CLK MODE, 6-CLK MODE) 8K / 16K / 32K / 64 KBYTE CODE OTP FULL-DUPLEX ENHANCED UART 512 / 1024 BYTE DATA RAM TIMER 0 TIMER 1 PORT 3 CONFIGURABLE I/Os TIMER 2 PORT 2 CONFIGURABLE I/Os PROGRAMMABLE COUNTER ARRAY (PCA) PORT 1 CONFIGURABLE I/Os WATCHDOG TIMER PORT 0 CONFIGURABLE I/Os CRYSTAL OR RESONATOR OSCILLATOR su01657 2003 Jan 24 4 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) BLOCK DIAGRAM (CPU-ORIENTED) P0.0-P0.7 P2.0-P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM OTP MEMORY PORT 2 LATCH 8 B REGISTER STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 BUFFER ALU SFRs TIMERS PSW PC INCREMENTER P.C.A. 8 16 PSEN ALE EAVPP TIMING AND CONTROL RST INSTRUCTION REGISTER PROGRAM COUNTER PD DPTR'S MULTIPLE PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS P1.0-P1.7 P3.0-P3.7 OSCILLATOR XTAL1 XTAL2 SU01658 2003 Jan 24 5 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) LOGIC SYMBOL Plastic Leaded Chip Carrier VCC 6 VSS XTAL1 PORT 0 DATA BUS LCC 17 PORT 1 RST EA/VPP PSEN 29 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PORT 2 ALE/PROG PORT 3 39 ADDRESS AND T2 T2EX SECONDARY FUNCTIONS 40 7 XTAL2 RxD TxD INT0 INT1 T0 T1 WR RD 1 ADDRESS BUS SU01672 PINNING Function NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 28 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 * NO INTERNAL CONNECTION Function P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC SU00023 Plastic Dual In-Line Package Plastic Quad Flat Pack T2/P1.0 1 40 VCC T2EX/P1.1 2 39 P0.0/AD0 ECI/P1.2 3 38 P0.1/AD1 CEX0/P1.3 4 37 P0.2/AD2 CEX1/P1.4 5 36 P0.3/AD3 CEX2/P1.5 6 35 P0.4/AD4 CEX3/P1.6 7 34 P0.5/AD5 CEX4/P1.7 8 33 P0.6/AD6 RST 9 32 P0.7/AD7 RxD/P3.0 10 TxD/P3.1 11 DUAL IN-LINE PACKAGE 44 1 11 29 PSEN 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 Function P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 * NO INTERNAL CONNECTION SU00021 2003 Jan 24 23 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 ALE/PROG INT1/P3.3 13 33 LQFP 31 EA/VPP INT0/P3.2 12 34 6 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 22 Function VSS NIC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NIC* EA/VPP P0.7/AD7 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NIC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 SU01400 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 PIN DESCRIPTIONS PIN NUMBER MNEMONIC TYPE NAME AND FUNCTION PDIP PLCC LQFP VSS 20 22 16 I Ground: 0 V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. 1-8 2-9 40-44, 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). 1 2 40 I/O 2 3 4 5 6 7 8 3 4 5 6 7 8 9 41 42 43 44 1 2 3 I I I/O I/O I/O I/O I/O P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the P87C51RA2/RB2/RC2/RD2, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal resistor to VSS permits a power-on reset using only an external capacitor to VCC. ALE 30 33 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted twice every machine cycle, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. P0.0-0.7 P1.0-P1.7 2003 Jan 24 Alternate functions for P87C51RA2/RB2/RC2/RD2 Port 1 include: T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1.2): External Clock Input to the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 7 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) PIN NUMBER MNEMONIC TYPE P87C51RA2/RB2/RC2/RD2 NAME AND FUNCTION PDIP PLCC LQFP PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations. If EA is held high, the device executes from internal program memory. The value on the EA pin is latched when RST is released and any subsequent changes have no effect. This pin also receives the programming supply voltage (VPP) during programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin (other than VPP) must not be higher than VCC + 0.5 V or less than VSS - 0.5 V. 2003 Jan 24 8 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) SPECIAL FUNCTION REGISTERS SYMBOL DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH - - - - - - EXTRAM AO xxxxxx00B AUXR1# Auxiliary 1 A2H - - - - GF2 0 - DPS xxxxxxx0B B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low FAH FBH FCH FDH FEH EAH EBH ECH EDH EEH CCAPM0# Module 0 Mode DAH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM1# Module 1 Mode DBH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM2# Module 2 Mode DCH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM3# Module 3 Mode DDH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM4# Module 4 Mode DEH - ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B DF DE DD DC DB DA D9 D8 CCON*# CH# PCA Counter Control PCA Counter High D8H F9H CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 CKCON# CL# Clock control PCA Counter Low 8FH E9H - - - - - - - X2 CMOD# PCA Counter Mode D9H CIDL WDTE - - - CPS1 CPS0 ECF DPTR: DPH DPL Data Pointer (2 bytes) Data Pointer High Data Pointer Low 83H 82H IE* Interrupt Enable 0 A8H 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB 00x00000B 00H x0000000B 00H 00xxx000B 00H 00H AF AE AD AC AB AA A9 A8 EA EC BF BE ET2 ES ET1 EX1 ET0 EX0 BD BC BB BA B9 B8 - PPC PT2 PS PT1 PX1 PT0 PX0 00H IP* Interrupt Priority B8H B7 B6 B5 B4 B3 B2 B1 B0 IPH# Interrupt Priority High B7H - PPCH PT2H PSH PT1H PX1H PT0H PX0H 87 86 85 84 83 82 81 80 P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 P1* Port 1 90H CEX4 CEX3 CEX2 CEX1 CEX0 ECI T2EX T2 A7 A6 A5 A4 A3 A2 A1 A0 P2* Port 2 A0H AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 B7 B6 B5 B4 B3 B2 B1 B0 RD WR T1 T0 INT1 INT0 TxD RxD FFH SMOD0 - POF GF1 GF0 PD IDL 00xxx000B P3* Port 3 B0H PCON#1 Power Control 87H SMOD1 * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source. 2003 Jan 24 9 x0000000B x0000000B FFH FFH FFH Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) SPECIAL FUNCTION REGISTERS (Continued) BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION DESCRIPTION DIRECT ADDRESS PSW* Program Status Word D0H RCAP2H# RCAP2L# Timer 2 Capture High Timer 2 Capture Low CBH CAH 00H 00H SADDR# SADEN# Slave Address Slave Address Mask A9H B9H 00H 00H SBUF Serial Data Buffer 99H SYMBOL MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 CY AC F0 RS1 RS0 OV F1 P 00000000B xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 SM1 SM2 REN TB8 RB8 TI RI SCON* SP Serial Control Stack Pointer 98H 81H SM0/FE 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 CF CE CD CC CB CA C9 C8 T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2MOD# Timer 2 Mode Control C9H - - - - - - T2OE DCEN TH0 TH1 TH2# TL0 TL1 TL2# Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 8CH 8DH CDH 8AH 8BH CCH TMOD Timer Mode 89H GATE WDTRST Watchdog Timer Reset A6H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 00H 07H 00H 00H xxxxxx00B 00H 00H 00H 00H 00H 00H C/T M1 M0 GATE C/T M1 M0 00H This device is configured at the factory to operate using 12 clock periods per machine cycle, referred to in this datasheet as "12-clock mode". It may be optionally configured on commercially available parallel programming equipment or via software to operate at 6 clocks per machine cycle, referred to in this datasheet as "6-clock mode". (This yields performance equivalent to twice that of standard 80C51 family devices). Also see next page. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. Minimum and maximum high and low times specified in the data sheet must be observed. 2003 Jan 24 RESET VALUE 10 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) OX2, when programmed (6-clock mode), supersedes the X2 bit (CKCON.0). The CKCON register is shown below in Figure 1. CLOCK CONTROL REGISTER (CKCON) This device allows control of the 6-clock/12-clock mode by means of both an SFR bit (X2) and an OTP bit. The OTP clock control bit CKCON Address = 8Fh Reset Value = x0000000B Not Bit Addressable 7 - BIT CKCON.7 CKCON.6 CKCON.5 CKCON.4 CKCON.3 CKCON.2 CKCON.1 CKCON.0 SYMBOL - X2 6 5 4 3 2 1 0 - - - - - - X2 FUNCTION Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle SU01689 Figure 1. Clock control (CKCON) register Also please note that the clock divider applies to the serial port for modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3 (variable baud rate modes) use either Timer 1 or Timer 2. RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator periods in 12-clock mode), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RST. Below is the truth table for the CPU clock mode. Table 1. OX2 clock mode bit (can only be set by parallel programmer) X2 bit (CKCON.0) CPU clock mode erased 0 12-clock mode (default) erased 1 6-clock mode programmed X 6-clock mode 2003 Jan 24 The value on the EA pin is latched when RST is deasserted and has no further effect. 11 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) LOW POWER MODES Stop Clock Mode Design Consideration The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Idle Mode In the idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. ONCE Mode The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Power-Down Mode To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. Programmable Clock-Out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. 2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in 6-clock mode). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. To properly terminate Power Down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. n Oscillator Frequency (65536 * RCAP2H, RCAP2L) n= 2 in 6-clock mode 4 in 12-clock mode POWER-ON FLAG The Power-On Flag (POF) is set by on-chip circuitry when the VCC level on the P87C51RA2/RB2/RC2/RD2 rises from 0 to 5 V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3 V for the POF to remain unaffected by the VCC level. Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. Table 2. External Pin Status During Idle and Power-Down Mode MODE PROGRAM MEMORY ALE PSEN Idle Internal 1 Idle External 1 Power-down Internal Power-down External 2003 Jan 24 PORT 0 PORT 1 1 Data 1 Float 0 0 0 0 12 PORT 2 PORT 3 Data Data Data Data Address Data Data Data Data Data Float Data Data Data Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Timer 0 and Timer 1 Mode 1 Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. The "Timer" or "Counter" function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text. Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 5. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which is preset by software. The reload leaves THn unchanged. TIMER 0 AND TIMER 1 OPERATION Mode 2 operation is the same for Timer 0 as for Timer 1. Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 3 shows the Mode 0 operation. Mode 3 Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The counted input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure 4). Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 6. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, and TF0 as well as pin INT0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the "Timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer 0 in Mode 3, an 80C51 can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). TMOD Address = 89H Reset Value = 00H Not Bit Addressable 7 6 5 4 3 2 1 0 GATE C/T M1 M0 GATE C/T M1 M0 TIMER 1 BIT TMOD.3/ TMOD.7 TMOD.2/ TMOD.6 SYMBOL GATE C/T TIMER 0 FUNCTION Gating control when set. Timer/Counter "n" is enabled only while "INTn" pin is high and "TRn" control pin is set. when cleared Timer "n" is enabled whenever "TRn" control bit is set. Timer or Counter Selector cleared for Timer operation (input from internal system clock.) Set for Counter operation (input from "Tn" input pin). M1 M0 OPERATING 0 0 8048 Timer: "TLn" serves as 5-bit prescaler. 0 1 16-bit Timer/Counter: "THn" and "TLn" are cascaded; there is no prescaler. 1 0 8-bit auto-reload Timer/Counter: "THn" holds a value which is to be reloaded into "TLn" each time it overflows. 1 1 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. 1 1 (Timer 1) Timer/Counter 1 stopped. SU01580 Figure 2. Timer/Counter 0/1 Mode Control (TMOD) Register 2003 Jan 24 13 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) / d* OSC C/T = 0 TLn (5 Bits) THn (8 Bits) TFn Interrupt C/T = 1 Control Tn Pin TRn Timer n Gate bit INTn Pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. SU01618 Figure 3. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter TCON Address = 88H Reset Value = 00H Bit Addressable 7 TF1 BIT TCON.7 SYMBOL TF1 TCON.6 TCON.5 TR1 TF0 TCON.4 TCON.3 TR0 IE1 TCON.2 IT1 TCON.1 IE0 TCON.0 IT0 6 5 4 3 2 1 0 TR1 TF0 TR0 IE1 IT1 IE0 IT0 FUNCTION Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. SU01516 Figure 4. Timer/Counter 0/1 Control (TCON) Register 2003 Jan 24 14 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) / d* OSC C/T = 0 TLn (8 Bits) TFn Interrupt C/T = 1 Control Tn Pin Reload TRn Timer n Gate bit THn (8 Bits) INTn Pin SU01619 *d = 6 in 6-clock mode; d = 12 in 12-clock mode. Figure 5. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload / d* OSC C/T = 0 TL0 (8 Bits) TF0 Interrupt TH0 (8 Bits) TF1 Interrupt C/T = 1 Control T0 Pin TR0 Timer 0 Gate bit INT0 Pin OSC / d* Control TR1 *d = 6 in 6-clock mode; d = 12 in 12-clock mode. SU01620 Figure 6. Timer/Counter 0 Mode 3: Two 8-Bit Counters 2003 Jan 24 15 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 Counter Enable) which is located in the T2MOD register (see Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. TIMER 2 OPERATION Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 3. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/6 pulses (osc/12 in 12-clock mode).). If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. Auto-Reload Mode (Up or Down Counter) The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2 in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down (MSB) TF2 (LSB) EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Symbol Position Name and Significance TF2 T2CON.7 EXF2 T2CON.6 RCLK T2CON.5 TCLK T2CON.4 EXEN2 T2CON.3 TR2 C/T2 T2CON.2 T2CON.1 CP/RL2 T2CON.0 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/6 in 6-clock mode or OSC/12 in 12-clock mode) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. SU01251 Figure 1. Timer/Counter 2 (T2CON) Control Register 2003 Jan 24 16 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Table 3. Timer 2 Operating Modes RCLK + TCLK CP/RL2 TR2 0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud rate generator X X 0 (off) OSC MODE / n* C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2 C/T2 = 1 T2 Pin Control TR2 Capture Transition Detector Timer 2 Interrupt RCAP2L RCAP2H T2EX Pin EXF2 Control EXEN2 SU01252 * n = 6 in 6-clock mode, or 12 in 12-clock mode. Figure 2. Timer 2 in Capture Mode T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable Bit * -- -- -- -- -- -- T2OE DCEN 7 6 5 4 3 2 1 0 Symbol Function -- Not implemented, reserved for future use.* T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00729 Figure 3. Timer 2 Mode (T2MOD) Control Register 2003 Jan 24 17 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 / n* OSC C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) C/T2 = 1 T2 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL SU01253 EXEN2 * n = 6 in 6-clock mode, or 12 in 12-clock mode. Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0) (DOWN COUNTING RELOAD VALUE) FFH FFH TOGGLE EXF2 OSC / n* C/T2 = 0 OVERFLOW TL2 T2 PIN TH2 TF2 INTERRUPT C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L RCAP2H (UP COUNTING RELOAD VALUE) * n = 6 in 6-clock mode, or 12 in 12-clock mode. SU01254 Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) 2003 Jan 24 T2EX PIN 18 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Timer 1 Overflow n = 1 in 6-clock mode n = 2 in 12-clock mode /2 "0" /n OSC "1" C/T2 = 0 SMOD TL2 (8-bits) "1" TH2 (8-bits) "0" RCLK C/T2 = 1 T2 Pin Control / 16 "1" TR2 Reload Transition Detector RCAP2L T2EX Pin EXF2 RX Clock "0" TCLK RCAP2H / 16 TX Clock Timer 2 Interrupt Control EXEN2 Note availability of additional external interrupt. SU01629 Figure 6. Timer 2 in Baud Rate Generator Mode Table 4. The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below: Timer 2 Generated Commonly Used Baud Rates Baud Rate Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 The timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation (C/T2=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Timer 2 12-clock mode 6-clock mode Osc Freq 375 k 9.6 k 4.8 k 2.4 k 1.2 k 300 110 300 110 750 k 19.2 k 9.6 k 4.8 k 2.4 k 600 220 600 220 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz RCAP2H RCAP2L FF FF FF FF FE FB F2 FD F9 FF D9 B2 64 C8 1E AF 8F 57 Usually, as a timer it would increment every machine cycle (i.e., the oscillator frequency in 6-clock mode, 1/12 the oscillator frequency in 12-clock mode). As a baud rate generator, it increments at the oscillator frequency in 6-clock mode (OSC/2 in 12-clock mode). Thus the baud rate formula is as follows: 1/ 6 Modes 1 and 3 Baud Rates = Oscillator Frequency [ n * [65536 * (RCAP2H, RCAP2L)]] Baud Rate Generator Mode *n= Bits TCLK and/or RCLK in T2CON (Table 4) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates - one generated by Timer 1, the other by Timer 2. Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 2003 Jan 24 16 in 6-clock mode 32 in 12-clock mode 19 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) If Timer 2 is being clocked internally, the baud rate is: When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Baud Rate + *n= f OSC [65536 * (RCAP2H, RCAP2L)]] 16 in 6-clock mode 32 in 12-clock mode Where fOSC= Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: Table 4 shows commonly used baud rates and how they can be obtained from Timer 2. RCAP2H, RCAP2L + 65536 * Summary of Baud Rate Equations Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2 (P1.0) the baud rate is: n* f OSC Baud Rate Timer/Counter 2 Set-up Baud Rate + Timer 2 Overflow Rate 16 Table 5. [ n* Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 5 for set-up of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a counter. Timer 2 as a Timer T2CON MODE INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 16-bit Auto-Reload 00H 08H 16-bit Capture 01H 09H Baud rate generator receive and transmit same baud rate 34H 36H Receive only 24H 26H Transmit only 14H 16H Table 6. Timer 2 as a Counter TMOD MODE INTERNAL CONTROL (Note 1) EXTERNAL CONTROL (Note 2) 16-bit 02H 0AH Auto-Reload 03H 0BH NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 2003 Jan 24 20 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. FULL-DUPLEX ENHANCED UART Standard UART operation SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. Serial Port Control Register The serial port control and status register is the Special Function Register SCON, shown in Figure 7. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2: Mode 3: Baud Rates The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency / 12 (12-clock mode) or / 6 (6-clock mode). The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. Mode 2 Baud Rate = 2 SMOD n 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. Where: n = 64 in 12-clock mode, 32 in 6-clock mode The baud rates in Modes 1 and 3 are determined by the Timer 1 or Timer 2 overflow rate. Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator (T2CON.RCLK = 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. Mode 1, 3 Baud Rate = 2 SMOD n (Timer 1 Overflow Rate) Where: In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. n = 32 in 12-clock mode, 16 in 6-clock mode The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either "timer" or "counter" operation, and in any of its 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula: Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: Mode 1, 3 Baud Rate = 2 SMOD n Oscillator Frequency 12 [256-(TH1)] Where: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. 2003 Jan 24 (Oscillator Frequency) n = 32 in 12-clock mode, 16 in 6-clock mode One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Figure 8 lists various commonly used baud rates and how they can be obtained from Timer 1. 21 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) SCON Address = 98H Bit Addressable Reset Value = 00H 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Where SM0, SM1 specify the serial port mode, as follows: SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate fOSC/12 (12-clock mode) or fOSC/6 (6-clock mode) variable fOSC/64 or fOSC/32 (12-clock mode) or fOSC/32 or fOSC/16 (6-clock mode) variable SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. SU01626 Figure 7. Serial Port Control (SCON) Register Timer 1 Baud Rate Mode 12-clock mode 6-clock mode Mode 0 Max Mode 2 Max Mode 1, 3 Max Mode 1, 3 1.67 MHz 625 k 104.2 k 19.2 k 9.6 k 4.8 k 2.4 k 1.2 k 137.5 110 110 3.34 MHz 1250 k 208.4 k 38.4 k 19.2 k 9.6 k 4.8 k 2.4 k 275 220 220 fOSC SMOD 20 MHz 20 MHz 20 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.986 MHz 6 MHz 12 MHz X 1 1 1 0 0 0 0 0 0 0 C/T Mode Reload Value X X 0 0 0 0 0 0 0 0 0 X X 2 2 2 2 2 2 2 2 1 X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH Figure 8. Timer 1 Generated Commonly Used Baud Rates More About Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or 1/6 the oscillator frequency (6-clock mode). S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after "write to SBUF." Figure 9 shows a simplified functional diagram of the serial port in Mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write to SBUF" and activation of SEND. Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are SEND enables the output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At 2003 Jan 24 22 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set. More About Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 or Timer 2 overflow rate. Figures 11 and 12 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Figure 10 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal.) Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SUBF." The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "write to SBUF." Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, 2003 Jan 24 P87C51RA2/RB2/RC2/RD2 23 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) 80C51 Internal Bus Write to SBUF S D Q RxD P3.0 Alt Output Function SBUF CL Zero Detector Start Shift TX Control S6 T1 TX Clock Send Serial Port Interrupt R1 RX Clock Receive RX Control REN RI Start 1 1 1 TxD P3.1 Alt Output Function Shift Clock Shift 1 1 1 1 0 MSB LSB RxD P3.0 Alt Input Function Input Shift Register Shift Load SBUF LSB MSB SBUF Read SBUF 80C51 Internal Bus S4 . . S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 ALE Write to SBUF S6P2 Send Shift Transmit RxD (Data Out) D0 D1 D2 D3 D4 D5 D6 D7 TxD (Shift Clock) S3P1 TI S6P1 Write to SCON (Clear RI) RI Receive Shift RxD (Data In) Receive D0 D1 D2 D3 D4 D5 D6 D7 S5P2 TxD (Shift Clock) SU00539 Figure 9. Serial Port Mode 0 2003 Jan 24 24 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Timer 1 Overflow 80C51 Internal Bus TB8 /2 SMOD = 0 SMOD = 1 Write to SBUF S D Q SBUF TxD CL Zero Detector Start Data Shift TX Control / 16 T1 Send RX Clock RI Load SBUF TX Clock Serial Port Interrupt / 16 Sample RX Control 1-to-0 Transition Detector Shift Start 1FFH Bit Detector Input Shift Register (9 Bits) Shift RxD Load SBUF SBUF Read SBUF 80C51 Internal Bus TX Clock Write to SBUF Send Data S1P1 Transmit Shift TxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit TI / 16 Reset RX Clock RxD Bit Detector Sample Times Start Bit Receive Shift RI SU00540 Figure 10. Serial Port Mode 1 2003 Jan 24 25 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) 80C51 Internal Bus TB8 Write to SBUF S D Q SBUF TxD CL Phase 2 Clock (1/2 fOSC) Zero Detector Mode 2 Start / 16 SMOD = 1 Stop Bit Gen. TX Control TX Clock Shift Data T1 Send R1 Load SBUF Serial Port Interrupt /2 SMOD = 0 (SMOD is PCON.7) / 16 RX Clock Sample RX Control 1-to-0 Transition Detector Shift Start 1FFH Bit Detector Input Shift Register (9 Bits) Shift RxD Load SBUF SBUF Read SBUF 80C51 Internal Bus TX Clock Write to SBUF Send Data S1P1 Transmit Shift TxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit TI Stop Bit Gen. / 16 Reset RX Clock RxD Bit Detector Sample Times Start Bit Stop Bit Receive Shift RI SU00541 Figure 11. Serial Port Mode 2 2003 Jan 24 26 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Timer 1 Overflow 80C51 Internal Bus TB8 Write to SBUF /2 SMOD = 0 SMOD = 1 S D Q SBUF TxD CL Zero Detector Start Data Shift TX Control / 16 TX Clock T1 Send R1 Load SBUF Serial Port Interrupt / 16 RX Clock Sample RX Control 1-to-0 Transition Detector Shift Start 1FFH Bit Detector Input Shift Register (9 Bits) Shift RxD Load SBUF SBUF Read SBUF 80C51 Internal Bus TX Clock Write to SBUF Send Data S1P1 Transmit Shift TxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit TI Stop Bit Gen. RX Clock RxD Bit Detector Sample Times / 16 Reset Start Bit Stop Bit Receive Shift RI SU00542 Figure 12. Serial Port Mode 3 2003 Jan 24 27 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Slave 1 Enhanced Features The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 Slave 1 SADDR = SADEN = Given = 1110 0000 1111 1010 1110 0X0X Slave 2 SADDR = SADEN = Given = 1110 0000 1111 1100 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: 2003 Jan 24 1100 0000 1111 1110 1100 000X In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 14. SADDR = SADEN = Given = SADDR = SADEN = Given = In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 13. Slave 0 P87C51RA2/RB2/RC2/RD2 Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. 1100 0000 1111 1101 1100 00X0 28 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) D0 D1 D2 D3 D4 D5 D6 D7 D8 DATA BYTE START BIT ONLY IN MODE 2, 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN TB8 RB8 TI RI SCON (98H) SMOD1 SMOD0 - POF LVF GF0 GF1 IDL PCON (87H) 0 : SCON.7 = SM0 1 : SCON.7 = FE SU00044 Figure 13. UART Framing Error Detection D0 D1 D2 D3 D4 SM0 SM1 1 1 1 0 D5 SM2 1 D6 D7 D8 REN TB8 RB8 1 X TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 COMPARATOR PROGRAMMED ADDRESS IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. SU00045 Figure 14. UART Multiprocessor Communication, Automatic Address Recognition 2003 Jan 24 29 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. Interrupt Priority Structure The P87C51RA2/RB2/RC2/RD2 has a 7 source four-level interrupt structure (see Table 7). There are 3 SFRs associated with the four-level interrupt. They are the IE, IP, and IPH. (See Figures 15, 16, and 17.) The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown in Figure 17. The function of the IPH SFR, when combined with the IP SFR, determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS INTERRUPT PRIORITY LEVEL IPH.x IP.x 0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority) Table 7. Interrupt Table SOURCE POLLING PRIORITY REQUEST BITS X0 1 IE0 HARDWARE CLEAR? N (L)1 Y (T)2 VECTOR ADDRESS 03H T0 2 TP0 Y 0BH X1 3 IE1 N (L) Y (T) 13H T1 4 TF1 Y 1BH PCA 5 CF, CCFn n = 0-4 N 33H SP 6 RI, TI N 23H T2 7 TF2, EXF2 N 2BH NOTES: 1. L = Level activated 2. T = Transition activated IE (0A8H) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT IE.7 SYMBOL EA IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 EC ET2 ES ET1 EX1 ET0 EX0 FUNCTION Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. PCA interrupt enable bit Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit. SU01290 Figure 15. IE Registers 2003 Jan 24 30 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) IP (0B8H) 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Priority Bit = 1 assigns high priority Priority Bit = 0 assigns low priority BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL - PPC PT2 PS PT1 PX1 PT0 PX0 FUNCTION - PCA interrupt priority bit Timer 2 interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit. SU01291 Figure 16. IP Registers IPH (B7H) 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT IPH.7 IPH.6 IPH.5 IPH.4 IPH.3 IPH.2 IPH.1 IPH.0 SYMBOL - PPCH PT2H PSH PT1H PX1H PT0H PX0H FUNCTION - PCA interrupt priority bit Timer 2 interrupt priority bit high. Serial Port interrupt priority bit high. Timer 1 interrupt priority bit high. External interrupt 1 priority bit high. Timer 0 interrupt priority bit high. External interrupt 0 priority bit high. SU01292 Figure 17. IPH Registers 2003 Jan 24 31 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) The GF2 bit is a general purpose user-defined flag. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. Reduced EMI Mode The AO bit (AUXR.0) in the AUXR register when set disables the ALE output unless the CPU needs to perform an off-chip memory access. Reduced EMI Mode AUXR (8EH) DPS 7 6 5 4 3 2 1 0 - - - - - - EXTRAM AO AUXR.1 AUXR.0 BIT0 AUXR1 DPTR1 DPTR0 EXTRAM AO DPH (83H) DPL (82H) See more detailed description in Figure 32. EXTERNAL DATA MEMORY SU00745A Dual DPTR The dual DPTR structure (see Figure 18) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. Figure 18. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: * New Register Name: AUXR1# * SFR Address: A2H * Reset Value: xxxxxxx0B AUXR1 (A2H) 7 6 5 4 3 2 1 0 - - - - GF2 0 - DPS Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPS DPTR0 0 DPTR1 1 Increments the data pointer by 1 MOV DPTR, #data16 Loads the DPTR with a 16-bit constant MOV A, @ A+DPTR Move code byte relative to DPTR to ACC MOVX A, @ DPTR Move external RAM (16-bit address) to ACC MOVX @ DPTR , A Move ACC to external RAM (16-bit address) JMP @ A + DPTR Jump indirect relative to DPTR The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See Application Note AN458 for more details. The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. 2003 Jan 24 INC DPTR 32 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system shown in Figure 21. Programmable Counter Array (PCA) The Programmable Counter Array available on the P87C51RA2/RB2/RC2/RD2 is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3 (CEX0), module 1 to P1.4 (CEX1), etc. The basic PCA configuration is shown in Figure 19. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Figure 24). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The PCA timer is a common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 22): CPS1 CPS0 PCA Timer Count Source 0 0 1/6 oscillator frequency (6-clock mode); 1/12 oscillator frequency (12-clock mode) 0 1 1/2 oscillator frequency (6-clock mode); 1/4 oscillator frequency (12-clock mode) 1 0 Timer 0 overflow 1 1 External Input at ECI pin The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 25 shows the CCAPMn settings for the various PCA functions. In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 20. The watchdog timer function is implemented in module 4 (see Figure 29). There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 23). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when 16 BITS MODULE 0 P1.3/CEX0 MODULE 1 P1.4/CEX1 MODULE 2 P1.5/CEX2 MODULE 3 P1.6/CEX3 MODULE 4 P1.7/CEX4 16 BITS PCA TIMER/COUNTER TIME BASE FOR PCA MODULES MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) SU00032 Figure 19. Programmable Counter Array (PCA) 2003 Jan 24 33 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) TO PCA MODULES OSC/6 (6 CLOCK MODE) OR OSC/12 (12 CLOCK MODE) OSC/2 (6 CLOCK MODE) OR OSC/4 (12 CLOCK MODE) OVERFLOW CH INTERRUPT CL 16-BIT UP COUNTER TIMER 0 OVERFLOW EXTERNAL INPUT (P1.2/ECI) 00 01 10 11 DECODE IDLE CIDL CF WDTE -- -- -- CPS1 CPS0 ECF CMOD (C1H) CR -- CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0H) SU01256 Figure 20. PCA Timer/Counter CF CR -- CCF4 CCF3 CCF2 CCF1 CCF0 CCON (C0H) PCA TIMER/COUNTER MODULE 0 IE.6 EC IE.7 EA TO INTERRUPT PRIORITY DECODER MODULE 1 MODULE 2 MODULE 3 MODULE 4 CMOD.0 ECF CCAPMn.0 ECCFn SU01097 Figure 21. PCA Interrupt System 2003 Jan 24 34 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) CMOD Address = D9H Reset Value = 00XX X000B CIDL WDTE - - - CPS1 7 6 5 4 3 2 Bit: CPS0 1 ECF 0 Symbol Function CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. - Not implemented, reserved for future use.* CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. CPS1 CPS0 Selected PCA Input** 0 0 1 1 ECF 0 1 0 1 0 1 2 3 Internal clock, fOSC/6 in 6-clock mode (fOSC/12 in 12-clock mode) Internal clock, fOSC/2 in 6-clock mode (fOSC/4 in 12-clock mode) Timer 0 overflow External clock at ECI/P1.2 pin (max. rate = fOSC/4 in 6-clock mode, fOCS/8 in 12-clock mode) PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ** fOSC = oscillator frequency SU01318 Figure 22. CMOD: PCA Counter Mode Register CCON Address = D8H Reset Value = 00X0 0000B Bit Addressable Bit: CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 7 6 5 4 3 2 1 0 Symbol Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. - Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01319 Figure 23. CCON: PCA Counter Control Register 2003 Jan 24 35 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) CCAPMn Address CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 0DAH 0DBH 0DCH 0DDH 0DEH Reset Value = X000 0000B Not Bit Addressable Bit: - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 7 6 5 4 3 2 1 0 Symbol Function - ECOMn CAPPn CAPNn MATn Not implemented, reserved for future use*. Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. TOGn PWMn ECCFn NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01320 Figure 24. CCAPMn: PCA Modules Compare/Capture Registers - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn X 0 0 0 0 0 0 0 No operation MODULE FUNCTION X X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X X 1 1 0 0 0 X 16-bit capture by a transition on CEXn X 1 0 0 1 0 0 X 16-bit Software Timer X 1 0 0 1 1 0 X 16-bit High Speed Output X 1 0 0 0 0 1 0 8-bit PWM X 1 0 0 1 X 0 X Watchdog Timer Figure 25. PCA Module Modes (CCAPMn Register) PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 26. counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see Figure 28). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 29 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 27). High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA 2003 Jan 24 36 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) CF CR -- CCF4 CCF3 CCF2 CCF1 CCON (D8H) CCF0 PCA INTERRUPT (TO CCFn) PCA TIMER/COUNTER CH CL CCAPnH CCAPnL CAPTURE CEXn -- ECOMn CAPPn CAPNn MATn TOGn PWMn 0 0 0 0 ECCFn CCAPMn, n= 0 to 4 (DAH - DEH) SU01608 Figure 26. PCA Capture Mode CF WRITE TO CCAPnH -- CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) RESET CCAPnH WRITE TO CCAPnL 0 CR PCA INTERRUPT CCAPnL (TO CCFn) 1 ENABLE MATCH 16-BIT COMPARATOR CH CL PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn 0 0 MATn TOGn PWMn 0 0 ECCFn CCAPMn, n= 0 to 4 (DAH - DEH) SU01609 Figure 27. PCA Compare Mode 2003 Jan 24 37 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) CF WRITE TO CCAPnH CR CCF4 CCF3 CCF2 CCF1 CCON (D8H) CCF0 RESET CCAPnH WRITE TO CCAPnL 0 -- PCA INTERRUPT CCAPnL (TO CCFn) 1 MATCH ENABLE 16-BIT COMPARATOR TOGGLE CH CEXn CL PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn 0 0 MATn TOGn PWMn 1 CCAPMn, n: 0..4 (DAH - DEH) ECCFn 0 SU01610 Figure 28. PCA High Speed Output Mode CCAPnH CCAPnL 0 CL < CCAPnL ENABLE 8-BIT COMPARATOR CEXn CL >= CCAPnL 1 CL OVERFLOW PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn MATn TOGn 0 0 0 0 PWMn ECCFn CCAPMn, n: 0..4 (DAH - DEH) 0 SU01611 Figure 29. PCA PWM Mode 2003 Jan 24 38 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) CIDL WRITE TO CCAP4L -- -- -- CPS1 CPS0 ECF CMOD (D9H) RESET CCAP4H WRITE TO CCAP4H 1 WDTE CCAP4L MODULE 4 0 ENABLE MATCH 16-BIT COMPARATOR CH RESET CL PCA TIMER/COUNTER -- ECOMn CAPPn CAPNn MATn 0 0 1 TOGn X PWMn ECCFn 0 X CCAPM4 (DEH) SU01612 Figure 30. PCA Watchdog Timer mode (Module 4 only) The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 30 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. Figure 31 shows the code for initializing the watchdog timer. Module 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The user's software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine in Figure 31. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 216 count of the PCA timer. 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. 2003 Jan 24 39 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) INIT_WATCHDOG: MOV CCAPM4, #4CH MOV CCAP4L, #0FFH MOV CCAP4H, #0FFH ORL CMOD, #40H ; ; ; ; ; ; ; ; P87C51RA2/RB2/RC2/RD2 Module 4 in compare mode Write to low byte first Before PCA timer counts up to FFFF Hex, these compare values must be changed Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD ; ;******************************************************************** ; ; Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H, CH ; 255 counts of the current PCA SETB EA ; timer value RET Figure 31. PCA Watchdog Timer Initialization Code 2003 Jan 24 40 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) For example: Expanded Data RAM Addressing The P87C51RA2/RB2/RC2/RD2 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes expanded RAM (ERAM) (768 bytes for the RD2). where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. The ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 256/768 bytes of external data memory in the P87C51RA2/RB2/RC2/RD2. MOV @R0,acc 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external addressing. For example, with EXTRAM = 0, 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The 256/768-bytes expanded RAM (ERAM, 00H - 1FFH/2FFH) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared, see Figure 32. MOVX @R0,acc where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory. An access to external data memory locations higher than the ERAM will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 33. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of DPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H,#data accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM. AUXR Address = 8EH Reset Value = xxxx xx00B Not Bit Addressable -- -- -- -- -- -- EXTRAM AO 7 6 5 4 3 2 1 0 Bit: Symbol Function AO Disable/Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (12-clock mode; 1/3 fOSC in 6-clock mode). 1 ALE is active only during off-chip memory access. EXTRAM Internal/External RAM access using MOVX @Ri/@DPTR EXTRAM Operating Mode 0 Internal ERAM access using MOVX @Ri/@DPTR 1 External data memory access. -- Not implemented, reserved for future use*. NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01613 Figure 32. AUXR: Auxiliary Register 2003 Jan 24 41 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) FF FF UPPER 128 BYTES INTERNAL RAM ERAM 256 or 768 BYTES 80 FFFF SPECIAL FUNCTION REGISTER EXTERNAL DATA MEMORY 80 LOWER 128 BYTES INTERNAL RAM 100 00 00 0000 SU01293 Figure 33. Internal and External Data Memory Address Space with EXTRAM = 0 HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT FOR P87C51RA2/RB2/RC2/RD2) Using the WDT To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When the WDT overflows, it will generate an output RESET pulse at the reset pin (see note below). The RESET pulse duration is 98 x TOSC (6-clock mode; 196 in 12-clock mode), where TOSC = 1/fOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset. To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When the WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When the WDT overflows, it will drive an output reset HIGH pulse at the RST-pin (see the note below). 2003 Jan 24 42 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Operating temperature under bias RATING UNIT 0 to +70 or -40 to +85 C -65 to +150 C 0 to +13.0 V Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS 4 Maximum IOL per I/O pin -0.5 to +6.0 V 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 4. Transient voltage only. AC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or -40C to +85C CLOCK FREQUENCY RANGE SYMBOL 1/tCLCL 2003 Jan 24 FIGURE PARAMETER 38 Oscillator frequency OPERATING MODE POWER SUPPLY VOLTAGE MAX UNIT 6-clock 5V 0 30 MHz 6-clock 2.7 V to 5.5 V 0 16 MHz 12-clock 5V 0 33 MHz 12-clock 2.7 V to 5.5 V 0 16 MHz 43 10% MIN 10% Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 DC ELECTRICAL CHARACTERISTICS Tamb = 0 C to +70 C or -40 C to +85 C; VCC = 2.7 V to 5.5 V; VSS = 0 V (16 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN VIL Input low voltage11 UNIT TYP1 MAX 4.0 V < VCC < 5.5 V -0.5 0.2 VCC-0.1 V 2.7 V < VCC < 4.0 V -0.5 0.7 VCC V VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2 VCC+0.9 VCC+0.5 V VIH1 Input high voltage, XTAL1, RST11 0.7 VCC VCC+0.5 V VOL Output low voltage, ports 1, 2, 8 VCC = 2.7 V; IOL = 1.6 mA2 - 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 2.7 V; IOL = 3.2 mA2 - 0.4 V VCC = 2.7 V; IOH = -20 mA VCC - 0.7 - V VCC = 4.5 V; IOH = -30 mA VCC - 0.7 - V VOH Output high voltage, ports 1, 2, 3 3 VOH1 Output high voltage (port 0 in external bus VCC = 2.7 V; IOH = -3.2 mA mode), ALE9, PSEN3 VCC - 0.7 - V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V -1 -50 mA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V; See note 4 - -650 mA ILI Input leakage current, port 0 0.45 < VIN < VCC - 0.3 - 10 mA ICC Power supply current (see Figure 41 and Source Code): Active mode @ 16 MHz mA Idle mode @ 16 MHz mA Power-down mode or clock stopped (see Figure 37 for conditions) 12 Tamb = 0 C to 70 C 2 30 mA Tamb = -40 C to +85 C 3 50 mA VRAM RAM keep-alive voltage 1.2 RRST Internal reset pull-down resistor 40 225 V k CIO Pin capacitance10 (except EA) - 15 pF NOTES: 1. Typical ratings are not guaranteed. Values listed are based on tests conducted on limited number of samples at room temperature. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC-0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 43 through 46 for ICC test conditions and Figure 41 for ICC vs. Frequency 12-clock mode characteristics: Active mode (operating): ICC = 1.0 mA + 1.1 mA x FREQ.[MHz] Active mode (reset): ICC = 7.0 mA + 0.6 mA FREQ.[MHz] FREQ.[MHz] Idle mode: ICC = 1.0 mA + 0.22 mA 6. This value applies to Tamb = 0 C to +70 C. For Tamb = -40 C to +85 C, ITL = -750 mA. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15 mA (*NOTE: This is 85 C specification.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26 mA 71 mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection. 12. Power down mode for 3 V range: Commercial Temperature Range - typ: 0.5 mA, max. 20 mA; Industrial Temperature Range - typ. 1.0 mA, max. 30 mA; 2003 Jan 24 44 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) DC ELECTRICAL CHARACTERISTICS Tamb = 0 C to +70 C or -40 C to +85 C; VCC = 5 V 10%; VSS = 0 V (30/33 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN VIL Input low voltage11 VIH Input high voltage (ports 0, 1, 2, 3, EA) 4.5 V < VCC < 5.5 V RST11 UNIT TYP1 MAX -0.5 0.2 VCC-0.1 V 0.2 VCC+0.9 VCC+0.5 V VIH1 Input high voltage, XTAL1, 0.7 VCC VCC+0.5 V VOL Output low voltage, ports 1, 2, 3 8 VCC = 4.5 V; IOL = 1.6 mA2 - 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN 7, 8 VCC = 4.5 V; IOL = 3.2 mA2 - 0.4 V VOH Output high voltage, ports 1, 2, 3 3 VCC = 4.5 V; IOH = -30 mA VCC - 0.7 - V VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 VCC = 4.5 V; IOH = -3.2 mA VCC - 0.7 - V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V -1 -50 mA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V; See note 4 - -650 mA ILI Input leakage current, port 0 0.45 < VIN < VCC - 0.3 - 10 mA ICC Power supply current Active mode (see Note 5) Idle mode (see Note 5) Power-down mode or clock stopped (see Figure 46 for conditions) Tamb = 0 C to 70 C 2 30 mA Tamb = -40 C to +85 C 3 50 mA VRAM RAM keep-alive voltage 1.2 RRST Internal reset pull-down resistor 40 225 V k CIO Pin capacitance10 (except EA) - 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC-0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 43 through 46 for ICC test conditions and Figure 41 for ICC vs. Frequency. 12-clock mode characteristics: Active mode (operating): ICC = 1.0 mA + 1.1 mA x FREQ.[MHz] Active mode (reset): ICC = 7.0 mA + 0.6 mA FREQ.[MHz] FREQ.[MHz] Idle mode: ICC = 1.0 mA + 0.22 mA 6. This value applies to Tamb = 0C to +70C. For Tamb = -40C to +85C, ITL = -750 . 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 C specification.) 26 mA Maximum IOL per 8-bit port: Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection. 2003 Jan 24 45 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 5 V 10% OPERATION) Tamb = 0 C to +70 C or -40 C to +85 C ; VCC = 5 V 10%, VSS = 0 V1,2,3,4 Symbol Figure Parameter Limits 16 MHz Clock MIN MAX 33 MIN Unit MAX 1/tCLCL 38 Oscillator frequency 0 tLHLL 34 ALE pulse width 2 tCLCL-8 117 MHz ns tAVLL 34 Address valid to ALE low tCLCL -13 49.5 ns tLLAX 34 Address hold after ALE low tCLCL -20 tLLIV 34 ALE low to valid instruction in tLLPL 34 ALE low to PSEN low tCLCL -10 52.5 ns tPLPH 34 PSEN pulse width 3 tCLCL -10 177.5 ns tPLIV 34 PSEN low to valid instruction in tPXIX 34 Input instruction hold after PSEN tPXIZ 34 Input instruction float after PSEN tCLCL -10 52.5 ns tAVIV 34 Address to valid instruction in 5 tCLCL -35 277.5 ns tPLAZ 34 PSEN low to address float 10 10 ns 42.5 4 tCLCL -35 3 tCLCL -35 0 ns 215 152.5 0 ns ns ns Data Memory tRLRH 35 RD pulse width 6 tCLCL -20 355 tWLWH 36 WR pulse width 6 tCLCL -20 355 tRLDV 35 RD low to valid data in tRHDX 35 Data hold after RD tRHDZ 35 Data float after RD 2 tCLCL -10 115 ns tLLDV 35 ALE low to valid data in 8 tCLCL -35 465 ns tAVDV 35 Address to valid data in 9 tCLCL -35 527.5 ns tLLWL 35, 36 ALE low to RD or WR low 3 tCLCL -15 202.5 ns tAVWL 35, 36 Address valid to WR low or RD low 4 tCLCL -15 235 ns tQVWX 36 Data valid to WR transition tCLCL -25 37.5 ns tWHQX 36 Data hold after WR tCLCL -15 47.5 ns tQVWH 36 Data valid to WR high 7 tCLCL -5 tRLAZ 35 RD low to address float tWHLH 35, 36 RD or WR high to ALE high tCLCL -10 tCLCL +10 5 tCLCL -35 0 ns ns 277.5 0 3 tCLCL +15 172.5 ns 432.5 0 52.5 ns ns 0 ns 72.5 ns External Clock tCHCX 38 High time 0.32 tCLCL tCLCL - tCLCX ns tCLCX 38 Low time 0.32 tCLCL tCLCL - tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Fall time 5 ns Shift register tXLXL 37 Serial port clock cycle time 12 tCLCL 750 ns tQVXH 37 Output data setup to clock rising edge 10 tCLCL -25 600 ns tXHQX 37 Output data hold after clock rising edge 2 tCLCL -15 110 ns tXHDX 37 Input data hold after clock rising edge 0 0 ns tXHDV 37 Clock rising edge to input data valid5 10 tCLCL -133 492 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Below 16 MHz this parameter is 8 tCLCL - 133. 2003 Jan 24 46 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 2.7 V TO 5.5 V OPERATION) Tamb = 0 C to +70 C or -40 C to +85 C ; VCC = 2.7 V to 5.5 V, VSS = 0 V1,2,3,4 Symbol Figure Parameter Limits 16 MHz Clock MIN MAX 16 MIN Unit MAX 1/tCLCL 38 Oscillator frequency 0 tLHLL 34 ALE pulse width 2tCLCL-10 115 MHz ns tAVLL 34 Address valid to ALE low tCLCL -15 47.5 ns tLLAX 34 Address hold after ALE low tCLCL -25 tLLIV 34 ALE low to valid instruction in tLLPL 34 ALE low to PSEN low tCLCL -15 47.5 ns tPLPH 34 PSEN pulse width 3 tCLCL -15 172.5 ns tPLIV 34 PSEN low to valid instruction in tPXIX 34 Input instruction hold after PSEN tPXIZ 34 Input instruction float after PSEN tCLCL -10 52.5 ns tAVIV 34 Address to valid instruction in 5 tCLCL -50 262.5 ns tPLAZ 34 PSEN low to address float 10 10 ns 37.5 4 tCLCL -55 3 tCLCL -55 0 ns 195 132.5 0 ns ns ns Data Memory tRLRH 35 RD pulse width 6 tCLCL -25 350 tWLWH 36 WR pulse width 6 tCLCL -25 350 tRLDV 35 RD low to valid data in tRHDX 35 Data hold after RD tRHDZ 35 Data float after RD 2 tCLCL -20 105 ns tLLDV 35 ALE low to valid data in 8 tCLCL -55 445 ns tAVDV 35 Address to valid data in 9 tCLCL -50 512.5 ns tLLWL 35, 36 ALE low to RD or WR low 3 tCLCL -20 207.5 ns tAVWL 35, 36 Address valid to WR low or RD low 4 tCLCL -20 230 ns tQVWX 36 Data valid to WR transition tCLCL -30 32.5 ns tWHQX 36 Data hold after WR tCLCL -20 42.5 ns tQVWH 36 Data valid to WR high 7 tCLCL -10 tRLAZ 35 RD low to address float tWHLH 35, 36 RD or WR high to ALE high tCLCL -15 tCLCL +15 5 tCLCL -50 0 ns ns 262.5 0 3 tCLCL +20 167.5 ns 427.5 0 47.5 ns ns 0 ns 77.5 ns External Clock tCHCX 38 High time 0.32 tCLCL tCLCL - tCLCX ns tCLCX 38 Low time 0.32 tCLCL tCLCL - tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Fall time 5 ns Shift register tXLXL 37 Serial port clock cycle time 12 tCLCL 750 ns tQVXH 37 Output data setup to clock rising edge 10 tCLCL -25 600 ns tXHQX 37 Output data hold after clock rising edge 2 tCLCL -15 110 ns tXHDX 37 Input data hold after clock rising edge 0 0 ns tXHDV 37 Clock rising edge to input data valid5 10 tCLCL -133 492 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Below 16 MHz this parameter is 8 tCLCL - 133. 2003 Jan 24 47 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 5 V 10% OPERATION) Tamb = 0 C to +70 C or -40 C to +85 C ; VCC = 5 V 10%, VSS = 0 V1,2,3,4,5 Symbol Figure Parameter Limits 16 MHz Clock MIN MAX 30 MIN Unit MAX 1/tCLCL 38 Oscillator frequency 0 tLHLL 34 ALE pulse width tCLCL-8 54.5 MHz ns tAVLL 34 Address valid to ALE low 0.5 tCLCL -13 18.25 ns tLLAX 34 Address hold after ALE low 0.5 tCLCL -20 tLLIV 34 ALE low to valid instruction in tLLPL 34 ALE low to PSEN low 0.5 tCLCL -10 21.25 ns tPLPH 34 PSEN pulse width 1.5 tCLCL -10 83.75 ns tPLIV 34 PSEN low to valid instruction in tPXIX 34 Input instruction hold after PSEN tPXIZ 34 Input instruction float after PSEN 0.5 tCLCL -10 21.25 ns tAVIV 34 Address to valid instruction in 2.5 tCLCL -35 121.25 ns tPLAZ 34 Data Memory PSEN low to address float 10 10 ns tRLRH 35 RD pulse width 3 tCLCL -20 tWLWH 36 WR pulse width 3 tCLCL -20 tRLDV 35 RD low to valid data in tRHDX 35 Data hold after RD tRHDZ 35 Data float after RD tCLCL -10 52.5 ns tLLDV 35 ALE low to valid data in 4 tCLCL -35 215 ns tAVDV 35 Address to valid data in 4.5 tCLCL -35 246.25 ns tLLWL 35, 36 ALE low to RD or WR low 1.5 tCLCL -15 108.75 ns tAVWL 35, 36 Address valid to WR low or RD low 2 tCLCL -15 110 ns tQVWX 36 Data valid to WR transition 0.5 tCLCL -25 6.25 ns tWHQX 36 Data hold after WR 0.5 tCLCL -15 16.25 ns tQVWH 36 Data valid to WR high 3.5 tCLCL -5 213.75 tRLAZ 35 RD low to address float 11.25 2 tCLCL -35 1.5 tCLCL -35 0 ns 90 58.75 0 ns 167.5 0 ns 121.25 0 1.5 tCLCL +15 78.75 0 21.25 ns ns 167.5 2.5 tCLCL -35 ns ns ns ns 0 ns 41.25 ns tWHLH 35, 36 External Clock RD or WR high to ALE high 0.5 tCLCL -10 0.5 tCLCL +10 tCHCX 38 High time 0.4 tCLCL tCLCL - tCLCX ns tCLCX 38 Low time 0.4 tCLCL tCLCL - tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Shift register Fall time 5 ns tXLXL 37 Serial port clock cycle time 6 tCLCL 375 ns tQVXH 37 Output data setup to clock rising edge 5 tCLCL -25 287.5 ns tXHQX 37 Output data hold after clock rising edge tCLCL -15 47.5 ns tXHDX 37 Input data hold after clock rising edge 0 tXHDV 37 Clock rising edge to input data valid6 0 5 tCLCL -133 ns 179.5 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. Below 16 MHz this parameter is 4 tCLCL - 133 2003 Jan 24 48 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 2.7 V TO 5.5 V OPERATION) Tamb = 0 C to +70 C or -40 C to +85 C ; VCC=2.7 V to 5.5 V, VSS = 0 V1,2,3,4,5 Symbol Figure Parameter Limits 16 MHz Clock MIN MAX 16 MIN Unit MAX 1/tCLCL 38 Oscillator frequency 0 tLHLL 34 ALE pulse width tCLCL-10 52.5 MHz ns tAVLL 34 Address valid to ALE low 0.5 tCLCL -15 16.25 ns tLLAX 34 Address hold after ALE low 0.5 tCLCL -25 tLLIV 34 ALE low to valid instruction in tLLPL 34 ALE low to PSEN low 0.5 tCLCL -15 16.25 ns tPLPH 34 PSEN pulse width 1.5 tCLCL -15 78.75 ns tPLIV 34 PSEN low to valid instruction in tPXIX 34 Input instruction hold after PSEN tPXIZ 34 Input instruction float after PSEN 0.5 tCLCL -10 21.25 ns tAVIV 34 Address to valid instruction in 2.5 tCLCL -50 101.25 ns tPLAZ 34 Data Memory PSEN low to address float 10 10 ns tRLRH 35 RD pulse width 3 tCLCL -25 tWLWH 36 WR pulse width 3 tCLCL -25 tRLDV 35 RD low to valid data in tRHDX 35 Data hold after RD tRHDZ 35 Data float after RD tCLCL -20 42.5 ns tLLDV 35 ALE low to valid data in 4 tCLCL -55 195 ns tAVDV 35 Address to valid data in 4.5 tCLCL -50 231.25 ns tLLWL 35, 36 ALE low to RD or WR low 1.5 tCLCL -20 113.75 ns tAVWL 35, 36 Address valid to WR low or RD low 2 tCLCL -20 105 ns tQVWX 36 Data valid to WR transition 0.5 tCLCL -30 1.25 ns tWHQX 36 Data hold after WR 0.5 tCLCL -20 11.25 ns tQVWH 36 Data valid to WR high 3.5 tCLCL -10 208.75 tRLAZ 35 RD low to address float 6.25 2 tCLCL -55 1.5 tCLCL -55 0 ns 70 38.75 0 ns 162.5 0 ns 106.25 0 1.5 tCLCL +20 73.75 0 16.25 ns ns 162.5 2.5 tCLCL -50 ns ns ns ns 0 ns 46.25 ns tWHLH 35, 36 External Clock RD or WR high to ALE high 0.5 tCLCL -15 0.5 tCLCL +15 tCHCX 38 High time 0.4 tCLCL tCLCL - tCLCX ns tCLCX 38 Low time 0.4 tCLCL tCLCL - tCHCX ns tCLCH 38 Rise time 5 ns tCHCL 38 Shift register Fall time 5 ns tXLXL 37 Serial port clock cycle time 6 tCLCL 375 ns tQVXH 37 Output data setup to clock rising edge 5 tCLCL -25 287.5 ns tXHQX 37 Output data hold after clock rising edge tCLCL -15 47.5 ns tXHDX 37 Input data hold after clock rising edge 0 tXHDV 37 Clock rising edge to input data valid6 0 5 tCLCL -133 ns 179.5 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF 3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 4. Parts are guaranteed by design to operate down to 0 Hz. 5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. 6. Below 16 MHz this parameter is 4 tCLCL - 133 2003 Jan 24 49 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) EXPLANATION OF THE AC SYMBOLS P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX INSTR IN A0-A7 PORT 0 tPXIZ tPLAZ tPXIX A0-A7 tAVIV PORT 2 A0-A15 A8-A15 SU00006 Figure 34. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0-A7 FROM RI OR DPL DATA IN A0-A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH SU00025 Figure 35. External Data Memory Read Cycle 2003 Jan 24 50 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) ALE tWHLH PSEN tWLWH tLLWL WR tLLAX tAVLL tWHQX tQVWX tQVWH A0-A7 FROM RI OR DPL PORT 0 DATA OUT A0-A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH SU00026 Figure 36. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 2 WRITE TO SBUF 3 4 5 6 7 tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI SU00027 Figure 37. Shift Register Mode Timing VCC-0.5 0.45V 0.7VCC 0.2VCC-0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 38. External Clock Drive 2003 Jan 24 51 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) VCC-0.5 VLOAD+0.1V 0.2VCC+0.9 0.2VCC-0.1 0.45V VOH-0.1V TIMING REFERENCE POINTS VLOAD VLOAD-0.1V VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA. NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. SU00717 SU00718 Figure 39. AC Testing Input/Output Figure 40. Float Waveform 40 35 MAX ACTIVE MODE ICCMAX = 1.1 FREQ. + 1.0 ICC(mA) 30 25 20 15 TYP ACTIVE MODE 10 MAX IDLE MODE ICCMAX = 0.22 FREQ. + 1.0 5 TYP IDLE MODE 4 8 12 16 20 24 28 32 36 FREQ AT XTAL1 (MHz) SU01684 Figure 41. ICC vs. FREQ for 12-clock operation Valid only within frequency specifications of the specified operating voltage 2003 Jan 24 52 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 /* ## as31 version V2.10 / *js* / ## ## ## source file: idd_ljmp1.asm ## list file: idd_ljmp1.lst created Fri Apr 20 15:51:40 2001 ## ########################################################## #0000 # AUXR equ 08Eh #0000 # CKCON equ 08Fh # # #0000 # org 0 # # LJMP_LABEL: 0000 /75;/8E;/01; # MOV AUXR,#001h ; turn off ALE 0003 /02;/FF;/FD; # LJMP LJMP_LABEL ; jump to end of address space 0005 /00; # NOP # #FFFD # org 0fffdh # # LJMP_LABEL: # FFFD /02;/FD;FF; # LJMP LJMP_LABEL # ; NOP # # */" Figure 42. Source code used in measuring IDD operational 2003 Jan 24 53 SU01499 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) VCC VCC ICC ICC VCC VCC VCC VCC RST RST P0 P0 EA EA (NC) XTAL2 (NC) XTAL2 CLOCK SIGNAL XTAL1 CLOCK SIGNAL XTAL1 VSS VSS SU00719 SU00720 Figure 43. ICC Test Condition, Active Mode All other pins are disconnected VCC-0.5 Figure 44. ICC Test Condition, Idle Mode All other pins are disconnected 0.7VCC 0.2VCC-0.1 0.45V tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 45. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VCC ICC VCC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS SU00016 Figure 46. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2 V to 5.5 V 2003 Jan 24 VCC 54 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Program Verification If security bits 2 and 3 have not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 49. The other pins are held at the `Verify Code Data' levels indicated in Table 8. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. EPROM CHARACTERISTICS All these devices can be programmed by using a modified Improved Quick-Pulse Programming algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The family contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as being manufactured by Philips. If the 64 byte encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Table 8 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 47 and 48. Figure 49 shows the circuit configuration for normal program memory verification. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = CAH indicates 87C51RA2 CBH indicates 87C51RB2 CCH indicates 87C51RC2 CDH indicates 87C51RD2 (060H) = NA Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 47. Note that the device is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 47. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 8 are held at the `Program Code Data' levels indicated in Table 8. The ALE/PROG is pulsed low 5 times as shown in Figure 48. Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 8, and which satisfies the timing specifications, is suitable. To program the encryption table, repeat the 5 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. Security Bits With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 9) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. To program the security bits, repeat the 5 pulse programming sequence using the `Pgm Security Bit' levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bits can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). Trademark phrase of Intel Corporation. 2003 Jan 24 P87C51RA2/RB2/RC2/RD2 55 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Table 8. EPROM Programming Modes RST PSEN ALE/PROG EA/VPP P2.7 P2.6 P3.7 P3.6 P3.3 Read signature MODE 1 0 1 1 0 0 0 0 X Program code data 1 0 0* VPP 1 0 1 1 X Verify code data 1 0 1 1 0 0 1 1 X Pgm encryption table 1 0 0* VPP 1 0 1 0 X Pgm security bit 1 1 0 0* VPP 1 1 1 1 X Pgm security bit 2 1 0 0* VPP 1 1 0 0 X Pgm security bit 3 1 0 0* VPP 0 1 0 1 X Program to 6-clock mode 1 0 0* VPP 0 0 1 0 0 Verify 6-clock4 1 0 1 1 e 0 0 1 1 Verify security bits5 1 0 1 1 e 0 1 0 X NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75 V 0.25 V. 3. VCC = 5 V10% during programming and verification. 4. Bit is output on P0.4 (1 = 12x, 0 = 6x). 5. Security bit one is output on P0.7. Security bit two is output on P0.6. Security bit three is output on P0.3. * ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while VPP is held at 12.75 V. Each programming pulse is low for 100 s (10 s) and high for a minimum of 10 s. Table 9. Program Security Bits for EPROM Devices PROGRAM LOCK BITS1, 2 SB1 SB2 SB3 PROTECTION DESCRIPTION 1 U U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, external execution is disabled. Internal data RAM is not accessible. NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined. 2003 Jan 24 56 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) +5V A0-A7 VCC P1 P0 1 RST 1 P3.6 EA/VPP 1 P3.7 ALE/PROG OTP XTAL2 4-6MHz XTAL1 PGM DATA +12.75V 5 PULSES TO GROUND PSEN 0 P2.7 1 P2.6 0 A8-A13 P2.0-P2.5 VSS A8-A15 are programming addresses (not external memory addresses per device pin out) P3.4 A14 P3.5 A15 (RD2 ONLY) SU01659 Figure 47. Programming Configuration 5 PULSES 1 ALE/PROG: 0 1 2 3 4 5 SEE EXPLODED VIEW BELOW tGHGL = 10s MIN tGLGH = 100s10s 1 ALE/PROG: 1 0 SU00875 Figure 48. PROG Waveform +5V VCC A0-A7 P0 P1 1 RST 1 P3.6 1 P3.7 OTP XTAL2 4-6MHz XTAL1 EA/VPP 1 ALE/PROG 1 PSEN 0 P2.7 0 ENABLE P2.6 0 P2.0-P2.5 VSS P3.4 A8-A15 are programming addresses (not external memory addresses per device pin out) P3.5 A8-A13 A14 A15 (RD2 ONLY) SU01660 Figure 49. Program Verification 2003 Jan 24 PGM DATA 57 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 50) SYMBOL VPP PARAMETER Programming supply voltage MIN MAX UNIT 12.5 13.0 V 50 1 IPP Programming supply current 1/tCLCL Oscillator frequency tAVGL Address setup to PROG low 48tCLCL tGHAX Address hold after PROG 48tCLCL tDVGL Data setup to PROG low 48tCLCL tGHDX Data hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) high to VPP 48tCLCL tSHGL VPP setup to PROG low 10 s tGHSL VPP hold after PROG 10 s tGLGH PROG width 90 tAVQV Address to data valid 48tCLCL tELQZ ENABLE low to data valid 48tCLCL tEHQZ Data float after ENABLE 0 tGHGL PROG high to PROG low 10 4 6 110 mA MHz s 48tCLCL s NOTE: 1. Not tested. PROGRAMMING* VERIFICATION* P1.0-P1.7 P2.0-P2.5 P3.4 (A0 - A14) ADDRESS ADDRESS PORT 0 P0.0 - P0.7 (D0 - D7) DATA IN tAVQV DATA OUT tDVGL tAVGL tGHDX tGHAX ALE/PROG tGLGH tSHGL tGHGL tGHSL LOGIC 1 LOGIC 1 EA/VPP LOGIC 0 tEHSH tELQV tEHQZ P2.7 ** SU00871 NOTES: * FOR PROGRAMMING CONFIGURATION SEE FIGURE 47. FOR VERIFICATION CONDITIONS SEE FIGURE 49. ** SEE TABLE 8. Figure 50. EPROM Programming and Verification 2003 Jan 24 58 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 MASK ROM DEVICES from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. Security Bits With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 10) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes Encryption Array 64 bytes of encryption array are initially unprogrammed (all 1s). Table 10. Program Security Bits PROGRAM LOCK BITS1, 2 SB1 SB2 PROTECTION DESCRIPTION 1 U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) 2 P U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined. ROM CODE SUBMISSION FOR 8K ROM DEVICES (87C51RA2) When submitting ROM code for the 8k ROM devices, the following must be specified: 1. 8 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 1FFFH DATA 7:0 User ROM Data 2000H to 203FH KEY 7:0 ROM Encryption Key FFH = no encryption 2040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 2040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: V Enabled V Disabled Security Bit #2: V Enabled V Disabled Encryption: V No V Yes 2003 Jan 24 If Yes, must send key file. 59 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 ROM CODE SUBMISSION FOR 16K ROM DEVICES (87C51RB2) When submitting ROM code for the 16K ROM devices, the following must be specified: 1. 16 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 3FFFH DATA 7:0 User ROM Data 4000H to 403FH KEY 7:0 ROM Encryption Key FFH = no encryption 4040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 4040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: V Enabled V Disabled Security Bit #2: V Enabled V Disabled Encryption: V No V Yes 2003 Jan 24 If Yes, must send key file. 60 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 ROM CODE SUBMISSION FOR 32K ROM DEVICES (87C51RC2) When submitting ROM code for the 32K ROM devices, the following must be specified: 1. 32 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to 7FFFH DATA 7:0 User ROM Data 8000H to 803FH KEY 7:0 ROM Encryption Key FFH = no encryption 8040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 8040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: V Enabled V Disabled Security Bit #2: V Enabled V Disabled Encryption: V No V Yes 2003 Jan 24 If Yes, must send key file. 61 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 ROM CODE SUBMISSION FOR 64K ROM DEVICE (87C51RD2) When submitting ROM code for the 64K ROM devices, the following must be specified: 1. 64 kbyte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS CONTENT BIT(S) COMMENT 0000H to FFFFH DATA 7:0 User ROM Data 10000H to 1003FH KEY 7:0 ROM Encryption Key FFH = no encryption 10040H SEC 0 ROM Security Bit 1 0 = enable security 1 = disable security 10040H SEC 1 ROM Security Bit 2 0 = enable security 1 = disable security Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: V Enabled V Disabled Security Bit #2: V Enabled V Disabled Encryption: V No V Yes 2003 Jan 24 If Yes, must send 62 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) DIP40: plastic dual in-line package; 40 leads (600 mil) 2003 Jan 24 63 P87C51RA2/RB2/RC2/RD2 SOT129-1 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) PLCC44: plastic leaded chip carrier; 44 leads 2003 Jan 24 P87C51RA2/RB2/RC2/RD2 SOT187-2 64 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm 2003 Jan 24 65 SOT389-1 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) P87C51RA2/RB2/RC2/RD2 REVISION HISTORY Rev Date Description _3 20030124 Product data (9397 750 10994); ECN 853-2391 29335 dated 07 Jan 2003. Modifications: * Updated ordering information table. _2 2003 Jan 24 20021028 Product data (9397 750 10393); ECN 853-2391 29117 dated 28 Oct 2002. 66 Philips Semiconductors Product data 80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP P87C51RA2/RB2/RC2/RD2 with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 01-03 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 2003 Jan 24 67 9397 750 10994