CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
FPGA-EB-02010 Version 1.2
September 2017
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02010-1.2
Contents
Acronyms in This Document ................................................................................................................................................. 3
1. Introduction .................................................................................................................................................................. 4
2. Headers and Test Connections ..................................................................................................................................... 6
3. Programming Circuit ..................................................................................................................................................... 7
3.1. Bridging Circuit .................................................................................................................................................... 7
3.2. I2C Expander ........................................................................................................................................................ 8
4. Power Supply ................................................................................................................................................................ 9
5. Status Indicators ......................................................................................................................................................... 11
6. SMA IO Link Board ...................................................................................................................................................... 12
7. Breakout IO Link Board ............................................................................................................................................... 14
8. Ordering Information .................................................................................................................................................. 17
References .......................................................................................................................................................................... 18
Technical Support Assistance............................................................................................................................................... 18
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics ........................................................................................................... 19
Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials .................................................................................................... 27
Appendix C. SMA-IOL-EVN-BRD Schematics ....................................................................................................................... 33
Appendix D. SMA-IOL-EVN-BRD Bill of Materials................................................................................................................ 34
Appendix E. B-IOL-EVN-BRD Schematics............................................................................................................................. 35
Appendix F. B-IOL-EVN-BRD Bill of Materials ..................................................................................................................... 36
Revision History ................................................................................................................................................................... 37
Figures
Figure 1.1. Top View of Master Link Board and its Key Components ................................................................................... 4
Figure 1.2. Bottom View of Master Link Board ..................................................................................................................... 5
Figure 3.1. Programming Block ............................................................................................................................................. 7
Figure 3.2. Bridging Block ..................................................................................................................................................... 8
Figure 3.3. I2C Expander Block .............................................................................................................................................. 8
Figure 4.1. Power Supply Block ............................................................................................................................................. 9
Figure 6.1. Top View of SMA IO Link Board ........................................................................................................................ 13
Figure 6.2. Bottom View of SMA IO Link Board .................................................................................................................. 13
Figure 7.1. Top View of Breakout IO Link Board ................................................................................................................. 16
Figure 7.2. Bottom View of Breakout IO Link Board ........................................................................................................... 16
Tables
Table 2.1. Headers and Test Connectors .............................................................................................................................. 6
Table 4.1. Power LEDs ........................................................................................................................................................... 9
Table 4.2. Device Power Rail Summary and Test Points ..................................................................................................... 10
Table 5.1. Status LED I/O Map ............................................................................................................................................ 11
Table 6.1. Headers and Test Connectors ............................................................................................................................ 12
Table 6.2. U1 Connector Description .................................................................................................................................. 12
Table 7.1. Headers and Test Connectors ............................................................................................................................ 14
Table 7.2. U1 Connector Description .................................................................................................................................. 14
Table 7.3. J2 Header Description ........................................................................................................................................ 15
Table 8.1. Ordering Information ......................................................................................................................................... 17
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 3
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
Complementary Metal-Oxide Semiconductor
CSI-2
Camera Serial Interface
DSI
Display Serial Interface
FTDI
Future Technology Devices International
I2C
Inter-Integrated Circuit
IO
Input/Output
LVDS
Low-Voltage Differential Signaling
MIPI
Mobile Industry Processor Interface
SPI
Serial Peripheral Interface
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02010-1.2
1. Introduction
This document describes the Lattice Semiconductor CrossLink™ LIF-MD6000 Master Link board that supports a variety
of demos, encompassing different signaling logic standards bridging with MIPI® CSI-2/DSI interface. The board‘s key
component is the CrossLink Family device that features built in MIPI D-PHY hard blocks to support different bridging
solutions.
For the latest information about this board, including optional Tx/Rx Link boards, demo files, further documentation
and more, see the Lattice website at: www.latticesemi.com/masterlink
For details about the CrossLink device, refer to FPGA-DS-02007, CrossLink Family Data Sheet.
The content of this user guide includes descriptions of on-board jumper settings, programming circuit, a complete set
of schematics, and bill of materials for LIF-MD6000 Master Link board.
Refer to Appendix A, B, C, D, E, F for the schematics and BOM of the CrossLink LIF-MD6000 Master Link board and the
schematics and BOMs of the Breakout IO Link and SMA IO Link boards that are included in the demo kit.
Circuits on the development kit board:
Programming Circuit
Mini USB Type-B connector to FTDI
FTDI to CrossLink using SPI
FTDI to XO3LF device using JTAG
CrossLink
MIPI CSI-2/DSI hard block
Bridging of multiple signaling standards
SPI flash configuration
General Purpose Input/Output
LED display
LCMXO3LF-1300E
I2C muxing
Figure 1.1 shows the top view of the LIF-MD6000 Master Link board and its key components. Figure 1.2 on the next
page shows the bottom view of the board.
Tx Connector 1 & 2 (U9, U7)
Power Switch (SW1)
External Power Input
External Power Jack (J3)
LCMXO3L-1300E (U19)
USB 2.0 Mini-B (J2)
JTAG Header (J1)
FTDI Chip (U1)
SPI Flash Device (U14)
Rx Connectors (U11, U12)
Power LEDs
LIF-MD6000-CSFBGA81
Debug Header (J18)
Debug and
Configuration LEDs
Reset and wake-up buttons
Switch (SW2)
Clock Source Selection (J26, J27)
Bank 1, 2 Voltage Selection
Headers (J24, J25)
External Clock SMA Inputs
XO3 Reset (SW3)
Figure 1.1. Top View of Master Link Board and its Key Components
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 5
Figure 1.2. Bottom View of Master Link Board
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02010-1.2
2. Headers and Test Connections
Figure 1.1 shows the top view of the Master Link board. The headers and test connections on the board provide access
to LIF-MD6000 Master Link demo board circuits. Table 2.1 lists the headers and test connectors.
Table 2.1. Headers and Test Connectors
Part
Description
Setting
J1
External JTAG interface - For LCMX03 only
—
J8
External 12 V terminal block
Open
J9
External 5 V terminal block
Open
SW1
External adaptor power ON/OFF
—
J22
External reference clock input for MIPI D-PHY reference clock
—
J21
External or internal reference clock selection
1–2 (External), 2–3 (Internal)
J5
Debug I/O
—
J20
LIF-MD6000 chip select
OPEN-OFF, SHORT-ON
J19
SPI Flash chip select
OPEN-OFF, SHORT-ON
J4
External clock input for MIPI D-PHY reference clock
—
J6
External or internal clock selection
1–2 (External), 2–3 (Internal)
J18
External SP/I2C access
—
SW2
Configuration reset for LIF-MD6000
—
J29
Reset signal voltage selector
1-2 (VCCIO2), 2-3 (VCCIO0)
J28
Reveal analyzer signal connector
—
J26
Internal/External clock and I2C SDA Mux
1-2 (CLK_INT), 2-3 (CLK_EXT), 2-4 (SDA)
J27
Internal/External reference clock and I2C SCL Mux
1-2 (CLK_INT_REF), 2-3 (CLK_EXT_REF), 2-4 (SCL)
J24
VCCIO1 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J25
VCCIO2 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J3
External power jack
—
U7, U9
Tx Connectors for external interface
—
U11, U12
Rx Connectors for external interface
—
SW4
External reset for LIF-MD6000 device
—
SW3
External reset for LCMXO3L device
—
SW5
PMU WAKEUP Switch
—
J23
Debug Header for LCMXO3L device
—
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 7
3. Programming Circuit
The Mini-B USB connector is used for programming the board by using Lattice Diamond® Programmer software.
Figure 3.1 shows the programming block of LIF-MD6000 Master Link board.
The Mini-B USB connector interfaces to the FTDI FT2232H IC. The FTDI IC works with Diamond programmer software to
provide interfaces for:
JTAG – to program MachXO2-1300E
SPI – to program both CrossLink, and SPI Flash Memory
USB Mini-B
(J2) FTDI Chip (U1)
SPI Flash (U14)
LIF-MD6000
CSFBGA81 (U8)
LCMXO3LF-1300E
MG121 (U19)
JTAG
SPI
Figure 3.1. Programming Block
3.1. Bridging Circuit
Figure 3.2 shows the block diagram of bridging of different standard interfaces. The CrossLink device is used as a
bridging device that supports a variety of I/O standards. This demo board supports development of the following
interface bridges:
1:1 MIPI DSI Display Interface Bridge
1:2 MIPI DSI Display Interface Bridge
2:1 MIPI CSI-2 Image Sensor Aggregator Bridge
CMOS to MIPI CSI-2 Image Sensor Interface Bridge
MIPI CSI-2 to CMOS Image Sensor Interface Bridge
MIPI DSI to CMOS Display Interface Bridge
OpenLDI LVDS to MIPI DSI Display Interface Bridge
CMOS to MIPI DSI Display Interface Bridge
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02010-1.2
Figure 3.2. Bridging Block
3.2. I2C Expander
Figure 3.3 shows the block diagram of the I2C expander. The LCMXO3LF-1200E device is used as an I2C expander and it
supports a single master and multiple slave devices connected to the board. The master I2C interface is connected to
the Tx header and the slave device I2C interface is connected to the Rx connectors supporting any slave device access
from the master based on the slave address.
LCMXO3LF-1200E-
MG121 (U19)
Rx Connector 1
Rx Connector 2
LIF-MD6000
CSFBGA81 (U8)
Tx
H
e
a
d
e
r
I2C
2 X I2C
2 X I2C
Figure 3.3. I2C Expander Block
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 9
4. Power Supply
The power supply to the development kit is provided by the Mini-B USB connector or from an external adaptor.
Figure 4.1 shows the power supply block of the CrossLink LIF-MD6000 Master Link board. The Mini-B USB connector is
used only for programming and the onboard power regulator for the successful programming. The external adaptor
provides 12 V power source through voltage regulators on the board to CrossLink and LCMXO3LF-1300E, as well as to
the external boards connected to Tx and Rx Headers. Each I/O and core voltage rail on the board is accessible by a test
point on the board. The current flowing to each rail can be measured using a 1 Ω resistor placed in the path of each
voltage rail.
J3
J2
12 V to 5 V
converter
LDO
LDO
LDO
LDO
Power adaptor
Mini-B USB
5 V
5 V
U15
U5
U6
U17
12 V
U18
1.2 V
3.3 V
2.5 V
1.8 V
Figure 4.1. Power Supply Block
Table 4.1 lists the device power rails. There are five voltage regulators on the board used to supply the 5 V, 3.3 V, 2.5V
1.8 V, and 1.2 V rails. The input to these regulators is either from the Mini-B USB connector or the external 12 V
adaptor that is connected to the board. Switch SW2 is used to connect or disconnect the external adaptor power to the
board.
Table 4.1. Power LEDs
Voltage Rail
LEDs
Color
12
D26
Green
5
D3
Green
3.3
D25
Green
2.5
D29
Green
1.8
D28
Green
1.2
D27
Green
Table 4.2 on the next page lists the board voltage rails, including the rail source voltage, test point number, and current
sense resistor number.
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02010-1.2
Table 4.2. Device Power Rail Summary and Test Points
Voltage Rail
Source Rail
Current Sense Resistor
Test Points
12 V
12_Ext
—
12V
5 V
12 V
—
5V
+3.3 V
5 V
—
3V3
+2.5 V
5 V
—
2V5
+1.8 V
5 V
—
1V8
+1.2 V
5 V
—
1V2
VCCCORE
+1.2 V
R19
VCC_CORE
VCCIO0
+3.3 V
R20
VCCIO0
VCCIO1
+3.3 V
R21
VCCIO1
VCCIO2
+3.3 V
R28
VCCIO2
VCC_DPHY
+1.2 V
R417
VCC_DPHY
1K_VCC_CORE
1.2 V
R190
1K_VCC_CORE
1K_VCCIO0
+3.3 V
R410
1K_VCCIO0
1K_VCCIO1
+3.3 V
R184
1K_VCCIO1
1K_VCCIO2
+3.3 V
R186
1K_VCCIO2
1K_VCCIO3
+3.3 V
R188
1K_VCCIO3
CrossLink LIF-MD6000 Master Link Board
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© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 11
5. Status Indicators
The LED status indicators on the board show power, configuration, and application status. Table 5.1 lists the status LED
I/O map.
Table 5.1. Status LED I/O Map
Device
LED
Net Name
Color
CrossLink
D6
CMOS_IO_1
Blue
CrossLink
D7
CMOS_IO_2
Blue
CrossLink
D8
CMOS_IO_3
Blue
CrossLink
D9
CMOS_IO_4
Blue
CrossLink
D10
CDONE
Green
LCMX03LF-1300E
D23
DONE
Red
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02010-1.2
6. SMA IO Link Board
The SMA IO Link board connects to the CrossLink LIF-MD6000 Master Link board’s Tx or Rx connectors (U7, U9, U11 or
U12) and transfers signals to the respective SMA connectors.
Table 6.1. Headers and Test Connectors
Part
Description
Mapping to U1
J1
SMA connector for DCK_TX_P
Pin 1
J2
SMA connector for DCK_TX_N
Pin 2
J3
SMA connector for DATA0_TX_P
Pin 4
J4
SMA connector for DATA0_TX_N
Pin 5
J5
SMA connector for DATA1_TX_P
Pin 7
J6
SMA connector for DATA1_TX_N
Pin 8
J7
SMA connector for DATA2_TX_P
Pin 13
J8
SMA connector for DATA2_TX_N
Pin 14
J9
SMA connector for DATA3_TX_P
Pin 16
J10
SMA connector for DATA3_TX_N
Pin 17
J11
SMA connector for DATA4_TX_P
Pin 24
J12
SMA connector for DATA4_TX_N
Pin 25
J13
SMA connector for DATA5_TX_P
Pin 27
J14
SMA connector for DATA5_TX_N
Pin 28
U1
Connector to interface to CrossLink Master Link board
N/A
Table 6.2. U1 Connector Description
Pin
Name
1
CH4_DCK_P
2
CH4_DCK_N
3
GND
4
CH4_DATA0_P
5
CH4_DATA0_N
6
GND
7
CH4_DATA1_P
8
CH4_DATA1_N
9
GND
10
SN
11
SCLK
12
GND
13
CH4_DATA2_P
14
CH4_DATA2_N
15
GND
16
CH4_DATA3_P
17
CH4_DATA3_N
18
GND
19
12V
20
12V
Pin
Name
21
TBD
22
RESETN
23
PWR_5-0V
24
GND
25
GND
26
PWR_3-3V
27
GND
28
GND
29
PWR_1-8V
30
MOSI
31
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
GND
37
GND
38
PWR_5-0V
39
SDA
40
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link board
connector this daughter board is connected to.
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 13
Figure 6.1. Top View of SMA IO Link Board
Figure 6.2. Bottom View of SMA IO Link Board
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-EB-02010-1.2
7. Breakout IO Link Board
The Breakout IO Link board connects to the CrossLink LIF-MD6000 Master Link board’s Tx or Rx connectors (U7, U9,
U11 or U12) and transfers signals to the 26-pin header (J2).
Table 7.1. Headers and Test Connectors
Part
Description
Setting
J2
13x2 Header
—
U1
Connector to interface to CrossLink Master Link board
—
Table 7.2. U1 Connector Description
Pin
Name
1
CH4_DCK_P
2
CH4_DCK_N
3
GND
4
CH4_DATA0_P
5
CH4_DATA0_N
6
GND
7
CH4_DATA1_P
8
CH4_DATA1_N
9
GND
10
SN
11
SCLK
12
GND
13
CH4_DATA2_P
14
CH4_DATA2_N
15
GND
16
CH4_DATA3_P
17
CH4_DATA3_N
18
GND
19
12V
20
12V
Pin
Name
21
TBD
22
RESETN
23
PWR_5-0V
24
GND
25
GND
26
PWR_3-3V
27
GND
28
GND
29
PWR_1-8V
30
MOSI
31
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
GND
37
GND
38
PWR_5-0V
39
SDA
40
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link board
connector this daughter board is connected to.
CrossLink LIF-MD6000 Master Link Board
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© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 15
Table 7.3. J2 Header Description
Pin
Name
Mapping to U1
1
+3.3V
N/A
2
+1.8V
N/A
3
RESETN
Pin 22
4
CH4_DCK_TX_P
Pin 1
5
SDA
Pin 39
6
CH4_DCK_TX_N
Pin 2
7
SCL
Pin 40
8
GND
N/A
9
GND
N/A
10
CH4_DATA0_TX_P
Pin 4
11
CH4_DATA3_TX_P
Pin 16
12
CH4_DATA0_TX_N
Pin 5
13
CH4_DATA3_TX_N
Pin 17
14
GND
N/A
15
GND
N/A
16
CH4_DATA1_TX_P
Pin 7
17
CH4_DATA4_TX_P
Pin 24
18
CH4_DATA1_TX_N
Pin 8
19
CH4_DATA4_TX_N
Pin 25
20
GND
N/A
21
GND
N/A
22
CH4_DATA2_TX_P
Pin 13
23
CH4_DATA5_TX_P
Pin 27
24
CH4_DATA2_TX_N
Pin 14
25
CH4_DATA5_TX_N
Pin 28
26
GND
N/A
CrossLink LIF-MD6000 Master Link Board
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© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02010-1.2
Figure 7.1. Top View of Breakout IO Link Board
Figure 7.2. Bottom View of Breakout IO Link Board
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 17
8. Ordering Information
Table 8.1. Ordering Information
Description
Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
CrossLink: LIF-MD6000 Master Link Board
(Includes 1 SMA IO Link Board and 1 Breakout
IO Link Board)
LIF-MD6000-ML-EVN
CrossLink: LIF-MD6000 IO Link Boards
(Includes 1 SMA IO Link Board and 1 Breakout
IO Link Board)
LIFMD-IOL-EVN
CrossLink LIF-MD6000 Master Link Board
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© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02010-1.2
References
For more information, refer to FPGA-DS-02007 (previously DS1055), CrossLink Family Data Sheet
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
EB105-1.1 19
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics
LIF-MD6000 Master Link Board Block Diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB
CONNECTOR
USB to
JTAG / SPI
FTDI
USP Programming only
BANK-1,2
DPHY BLOCK
LIFMD-6000-6MG81I
MIPI TX HEADER1
I2C
MIPI TX I/O
BANK-0
LVDS RX HEADER1
SPI
Ext Power
Adaptor (12V)
OnBoard
LDO'S & Buck
1V2,1V8,2V5,3V3,5V
JTAG_I/F/ SPI
MIPI TX HEADER2
MIPI TX I/O
LVDS RX HEADER1
I2C
LVDS RX In
LVDS RX In
SPI
BANK-3,4
BANK-2
BANK-0
LCMXO3LF-1300-MG121
JTAG
I2C*3
I/O Expander - I2C Switch
Targeted FPGA
SPI FLASH
I2C
SPI
SPI
I2C*2
I2C*1
SPI
SPI
I2C
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888111
BBBLLLOOOCCCKKK DDDiiiaaagggrrraaammm
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 EB105-1.1
FTDI Interface
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROGRAMMING INTERFACE
TDO
TDI
TMS
TCK
FT_EECS
FT_EECLK
FT_EEDATA
VCC1_8FT
VCC1_8FT
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
VBUS_5V
MCLK 4,5,6
SISPI 4,5,6
SPISO 4,5,6
7 12MHZ
CSSPIN 4,5,6
TCK 7
TDI 7
TDO 7
TMS 7
CDONE 6
CRESETB 6
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888222
FFFTTTDDDIII IIINNNTTTEEERRRFFFAAACCCEEE
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
C6 0.1uF
C7
10uF
R4 0
R1712k
C12
0.1uF
R13
10K
R60
R3
4.7k
L3
600ohm 500mA
12
C15
0.1uF
R1
4.7k
C1
4u7
12
C2
0.1uF
93LC56-SO8
U2
CS 1
CLK 2
DI 3
DO 4
VSS
5ORG
6NU
7VCC
8
C13
0.1uF
R11 12k
R12
10K
R2
4.7k
R1800
C8
0.1uF
R9
2k2
C9
0.1uF
R1810
C16
0.1uF
R1670
L2
600ohm 500mA
12
C4
0.1uF
FTDI High-Speed USB
FT2232H
FT2232HL
U1
VREGIN
50
VREGOUT
49
DM
7
DP
8
REF
6
RESET#
14
EECS
63
EECLK
62
EEDATA
61
OSCI
2
OSCO
3
TEST
13
ADBUS0 16
ADBUS1 17
ADBUS2 18
ADBUS3 19
VPHY 4
VPLL 9
VCORE 12
VCORE 37
VCORE 64
VCCIO 20
VCCIO 31
VCCIO 42
VCCIO 56
AGND
10
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
PWREN# 60
SUSPEND# 36
ADBUS4 21
ADBUS5 22
ADBUS6 23
ADBUS7 24
ACBUS0 26
ACBUS1 27
ACBUS2 28
ACBUS3 29
ACBUS4 30
ACBUS5 32
ACBUS6 33
ACBUS7 34
BDBUS0 38
BDBUS1 39
BDBUS2 40
BDBUS3 41
BDBUS4 43
BDBUS5 44
BDBUS6 45
BDBUS7 46
BCBUS0 48
BCBUS1 52
BCBUS2 53
BCBUS3 54
BCBUS4 55
BCBUS5 57
BCBUS6 58
BCBUS7 59
J2
SKT_MINIUSB_B_RA
VCC 1
D- 2
D+ 3
ID 4
GND 5
SHIELD3
8
SHIELD2
7
SHIELD1
6
SHIELD4
9
R160
R50
C11
18pF
X1
12MHZ
1
133
G1
2G2 4
R260
R10 2k2
C10
18pF
0DNI R23
L1
600ohm 500mA
12
R180
DNI
R70
C5
0.1uF
C14
0.1uF
C3
4u7
12
R14
10K R150
J1
header_1x8
11
22
33
44
55
66
77
88
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EB105-1.1 21
Power Regulator Interface
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOTE : INPUT VOLTAGE SHOULD BE 12V AT 3A Max
500mA traces
500mA traces
500mA traces
500mA traces
XO3-1K Voltage
Selection
500mA traces
ON BOARD POWER REGULATORS
NOTE : Place this gnd test point near J3
GLOBAL POWER TEST POINTS
Snow Voltage
Selection
+3.3V
+2.5V
VCC_CORE
VCCIO0 VCCIO1
+1.2V +2.5V
+2.5V
VCC_1.2V
VCC_2.5V
+1.2V
5V
+1.2V VCC_CORE
+3.3VVCC_3.3V
5V
+3.3V 5V
5V
VCCIO2
+3.3V 1K_VCCIO1
+2.5V
+3.3V 1K_VCCIO2
+2.5V
1K_VCCIO1 1K_VCCIO2
+3.3V 1K_VCCIO3
+2.5V
1K_VCCIO3
1K_VCC_CORE
+1.2V 1K_VCC_CORE
+1.8VVCC_1.8V
5V
VBUS_5V
5V_INT
12V_EXT
12V 5V_INT
12V
+3.3V 1K_VCCIO0
+2.5V
1K_VCCIO0
12V
5V_INT
12V12V_EXT
5V
VCC_DPHY
VCCIO0+1.2V VCC_DPHY
+1.2V
+1.2V
+3.3V
+3.3V
+2.5V
+2.5V
VCCIO1
VCCIO2
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888333
PPPOOOWWWEEERRR RRREEEGGGUUULLLAAATTTOOORRR III///FFF
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
VCCIO0
1
L8
4.7uH
R435 1 R449 1
J9
2 Position Terminal Block_0
11
22
R187 1
DNI
C25
0.1uF
J25
Tri-Con
2V5 1
VCCIO1/2 2
3V3 3
1V2
4
1K_VCCIO0
1
C129
47uF
C114
10uF
R190 1
U3
FUSE
1
122
R188 1
R231
536K
12V0
1
D1
SL44-E3/57T
1 2
R28 1
D25
Green
12
C22
0.1uF
U6
NCP1117ST25T3G
GND
1
IN
3OUT 2
TAB 4
R20 1
100E
R22
DNI
R229
15K
R189 1
DNI
R232
100K
C95
0.1u
R21 1
GND5
1
1V2
1
R36
1K
C127
680pF
VCCIO2
1
3V3
1
1K_VCCIO1
1
L5
600ohm 500mA
12
C97
0.1u
D14
SL44-E3/57T
1 2
C112
0.1uF
1K_VCCIO2
1
R230
34K
C94
10u
1K_VCCIO3
1
LT3680
U18
LT3680
Manufacturer = Linear
PART_NUMBER = LT3680EDD#PBF
BD 1
BOOST 2
SW 3
VIN
4
RUN_SS
5
SYNC
6
PG
7
FB 8
VC
9
RT
10
EPAD 11
5V0
1
R19 1
VCC_DPHY1
1
R165 0
GND1
1
R184 1
R434 1
C96
10u
R39 0
L7
600ohm 500mA
12
R37 0
GND3
1
U5
NCP1117ST33T3G
GND
1
IN
3OUT 2
TAB 4
R448 1
C128
0.47uF
SW1
PWR
C130
10uF
C115
10uF
AP7313-12SAG-7
U15
IN
1OUT 2
GND
3
GND2
1
C21
22uF
R417 1
2V5
1
R185 1
DNI
GND4
1
R33 1
C24
22uF
100E
R144
DNI
D3
Green
12
C123
0.1uF
L4
600ohm 500mA
12
VCCIO1
1
R192 0
C29
0.1u
R24 1
DNI
U17
NCP1117ST18T3G
GND
1
IN
3OUT 2
TAB 4
R233
1K
C23
10uF
R25 1
D12
0.3VF
MBRA340T3G
2 1
R410 1
C113
22uF
J8
2 Position Terminal Block_0
11
22
R186 1
C20
10uF
J24
Tri-Con
2V5 1
VCCIO1/2 2
3V3 3
1V2
4
J3
PJ-032A
1
2
3
R411 1
DNI
L6
600ohm 500mA
12
VCC_CORE1
1
1K_VCC_CORE1
1
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22 EB105-1.1
MIPI Block – MIPI Tx
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TX Connector1
TX Connector2
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
4)Place MIPI TX resistor network as close to bank 0 as possible.
Trace match *HS* P & N channels as well as individual pairs.
Minimize routing and trace match *LP* signals to banks 5 and 0.
Piggyback Configuration info:
1.. 0.001uF and 0.1uF is added as the piggyback c
100nF and 470pF is loaded near DUT and 0.001uF and 0.1uF is made piggy back for the following reference designer
C42,C44,C46,C171,C172
CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
RESETN
SDA
SCL
GPIO1
GPIO2
RESETN
SDA
SCL
GPIO1
GPIO2
CH4_DATA3_TX_P
CH4_DATA3_TX_N
CH4_DATA2_TX_P
CH4_DATA2_TX_N
CSSPIN
MCLK
CH5_DATA3_TX_P
CH5_DATA3_TX_N
CH5_DATA2_TX_P
CH5_DATA2_TX_N
CH5_DCK_TX_P
CH5_DCK_TX_N
CH5_DATA0_TX_P
CH5_DATA0_TX_N
CH5_DATA1_TX_P
CH5_DATA1_TX_N
CSSPIN
MCLK
CH5_DCK_TX_P
CH5_DCK_TX_N
CH5_DATA0_TX_P
CH5_DATA0_TX_N
CH5_DATA1_TX_P
CH5_DATA1_TX_N
CH5_DATA2_TX_P
CH5_DATA2_TX_N
CH5_DATA3_TX_P
CH5_DATA3_TX_N
CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
CH4_DATA2_TX_P
CH4_DATA2_TX_N
CH4_DATA3_TX_P
CH4_DATA3_TX_N
5V +3.3V +1.8V
5V +3.3V +1.8V
12V
12V
12V 5V +3.3V +1.8V
12V 5V +3.3V +1.8V
VCC_DPHY
VCC_DPHY
VCC_DPHY 2,5,6 CSSPIN
2,5,6 MCLK
RESETN 5
SDA 6,7
SCL 6,7
SISPI 2,5,6
SPISO 2,5,6
RPI1 5
RPI2 5
XO3_SCL 7
XO3_SDA 7
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888444
MMMiiiPPPiii BBBllloooccckkk --- MMMIIIPPPIII TTTXXX
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
C44
0.01uF
16V
R53
0
R4550
R4530
C155
0.1uF
R4650
R4560
R4540
C171
470pF
16V
C156
0.1uF
U7
Hirose - FX12 - 40 Pos
CH4_DCK_P
1
CH4_DCK_N
2
GND
3
CH4_DATA0_P
4
CH4_DATA0_N
5
GND
6
CH4_DATA1_P
7
CH4_DATA1_N
8
GND
9
SN
10
SCLK
11
GND
12
CH4_DATA2_P
13
CH4_DATA2_N
14
GND
15
CH4_DATA3_P
16
CH4_DATA3_N
17
GND
18
12V
19
12V
20
TBD 21
RESETN 22
PWR_5-0V 23
GND 24
GND 25
PWR_3-3V 26
GND 27
GND 28
PWR_1-8V 29
MOSI 30
MISO 31
PWR_1-8V 32
GND 33
GND 34
PWR_3-3V 35
GND 36
GND 37
PWR_5-0V 38
SDA 39
SCL 40
Shield1
41 Shield2 42
Shield3
43
Shield4
44 Shield5 45
Shield6 46
C42
0.01uF
16V
LIFMD6000-csfBGA81
U8D
DPHY1_DP2 C1
DPHY1_DN2 C2
DPHY1_DP0 B1
DPHY1_DN0 B2
DPHY1_CKP A1
DPHY1_CKN A2
DPHY1_DP1 A3
DPHY1_DN1 B3
DPHY1_DP3 A4
DPHY1_DN3 B4
DPHY0_DP2 B6
DPHY0_DN2 A6
DPHY0_DP0 B7
DPHY0_DN0 A7
DPHY0_CKP A8
DPHY0_CKN A9
DPHY0_DP1 B8
DPHY0_DN1 B9
DPHY0_DP3 C8
DPHY0_DN3 C9
VCCA_DPHY0
D7
VCCA_DPHY1
D3
VCCPLL_DPHY0
C4
C6 VCCPLL_DPHY1
GNDA_DPHY0
C7
GNDA_DPHY1
C3
GNDPLL_DPHYX
B5
VCCA_DPHY1
A5
C159
0.1uF
C41
1uF
4V
C172
470pF
16V
R4660
R4200
C46
470pF
16V
C158
0.1uF
R4210
C160
0.1uF
C45
1uF
16V
R4180 DNI
U9
Hirose - FX12 - 40 Pos
CH5_DCK_P
1
CH5_DCK_N
2
GND
3
CH5_DATA0_P
4
CH5_DATA0_N
5
GND
6
CH5_DATA1_P
7
CH5_DATA1_N
8
GND
9
SN
10
SCLK
11
GND
12
CH5_DATA2_P
13
CH5_DATA2_N
14
GND
15
CH5_DATA3_P
16
CH5_DATA3_N
17
GND
18
12V
19
12V
20
TBD 21
RESETN 22
PWR_5-0V 23
GND 24
GND 25
PWR_3-3V 26
GND 27
GND 28
PWR_1-8V 29
MOSI 30
MISO 31
PWR_1-8V 32
GND 33
GND 34
PWR_3-3V 35
GND 36
GND 37
PWR_5-0V 38
SDA 39
SCL 40
Shield1
41 Shield2 42
Shield3
43
Shield4
44 Shield5 45
Shield6 46
C161
0.1uF
R4810 DNI
R51
0
C43
1uF
4V
C162
0.1uF
R4820 DNI
C157
0.1uF
R52
0
R4190 DNI
C178
0.1uF
16V
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EB105-1.1 23
Bank 1, 2 – LVDS Rx
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U8
LVDS RX TERMINATION RESISTORS
RX Connector1
RX Connector2
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
well as individual pairs. Minimize routing and trace
match *CD* signals to bank 3 pins.
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
All the power rails should be capable of carrying 1A current3)
1. 0.001uF and 1.5nF is added as the piggyback cap
100nF and 1.5nF is loaded near DUT and 0.001uF and 1.5nF is
made piggy back for the following reference designer
C51,C59
DNI
Piggyback Configuration info:
NOTE : PLACE SWITCH IN THE TOP SIDE
EXTERNAL RESET
Default short (J29.2,J29.3)
CSSPIN
MCLK
CH0_DCK_P
CH0_DCK_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA2_P
CH0_DATA2_N
CH0_DATA1_P
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
GPIO3
GPIO4
GPIO3
GPIO4
CSSPIN
MCLK
CH1_DCK_P
CH1_DCK_N
CH1_DATA0_P
CH1_DATA0_N
CH1_DATA2_P
CH1_DATA2_N
CH1_DATA1_P
CH1_DATA1_N
CH1_DATA3_P
CH1_DATA3_N
RESETN
CMOS_IO_7
CMOS_IO_8
CMOS_IO_1
CMOS_IO_1
CMOS_IO_2
CMOS_IO_3
CMOS_IO_4
CMOS_IO_7
CMOS_IO_8
CMOS_IO_2
CMOS_IO_1
CMOS_IO_3
CMOS_IO_4
CMOS_IO_5
CMOS_IO_6
CMOS_IO_1
CMOS_IO_2
GPIO3
GPIO4
CH0_DATA2_P
CH0_DATA2_N
CH0_DCK_N
CH0_DCK_P
CH0_DATA1_P
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA1_P
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
CH1_DATA0_P
CH1_DATA0_N
CH1_DATA3_P
CH1_DATA3_N
CH1_DATA2_P
CH1_DATA2_N
CH1_DATA1_P
CH1_DATA1_N
CH1_DATA0_N
CH1_DATA0_P
CH1_DATA3_P
CH1_DATA3_N
CH1_DATA2_P
CH1_DATA2_N
CH1_DCK_P
CH1_DCK_N
CH0_DATA2_P
CH0_DATA2_N
CH1_DATA1_P
CH1_DATA1_N
CMOS_IO_3
CH0_DCK_P
CH0_DCK_N
CMOS_IO_2
EXT_RST
CH1_DCK_P
CH1_DCK_N
CMOS_IO_5
CMOS_IO_6
CMOS_IO_4 RESETN
EXT_RST
CMOS_IO_5
CMOS_IO_6
CMOS_IO_7
CMOS_IO_8
5V +3.3V +1.8V
5V +3.3V +1.8V
12V
12V
12V
12V
12V 5V +3.3V +1.8V
12V 5V +3.3V +1.8V
VCCIO1
VCCIO2
VCCIO2
VCCIO1
VCCIO2 VCCIO0
SDA2 7
SCL2 7
2,4,6 CSSPIN
2,4,6 MCLK
RESE
R
T
E
N
SETN 4
7 SCL4
7 SDA4
SDA1 7
SCL1 7
7 SCL3
7 SDA3
SISPI 2,4,6
SPISO 2,4,6
RPI1 4
RPI2 4
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888555
BBBAAANNNKKK111,,,222 --- LLLVVVDDDSSS RRRXXX
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
D8 blue
1 2
R4580
R55 680R
NI
SW4
EXT_RST
R4240
R4460
C60
1uF
4V
D9 blue
1 2
J29
CON3
1
2
3
R445
4.7k
R4610
R4250
R110
100
DNI
C167
0.1uF
C163
0.1uF
C58
100nF
16V
R4690
J28
CON6
1
2
3
4
5
6
U11
Hirose - FX12 - 40 Pos
CH1_DCK_P
1
CH1_DCK_N
2
GND
3
CH1_DATA0_P
4
CH1_DATA0_N
5
GND
6
CH1_DATA2_P
7
CH1_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12_0V
12
SDA1
13
SCL1
14
GND
15
CH3_DATA0_P
16
CH3_DATA0_N
17
GND
18
CH3_DCK_P
19
CH3_DCK_N
20
PWR_12V 21
RESETN 22
PWR_5-0V 23
CH1_DATA1_P 24
CH1_DATA1_N 25
PWR_3-3V 26
CH1_DATA3_P 27
CH1_DATA3_N 28
PWR_1-8V 29
MOSI 30
MISO 31
PWR_1-8V 32
GND 33
GND 34
PWR_3-3V 35
CH3_DATA1_P 36
CH3_DATA1_N 37
PWR_5-0V 38
SDA 39
SCL 40
Shield1
41 Shield2 42
Shield3
43
Shield4
44 Shield5 45
Shield6 46
R4720
R4620
D6 blue
1 2
R113
100
DNI
R111
100
DNI
R4700
D7 blue
1 2
R4760
R114
100
DNI
R4730
R600
C164
0.1uF
R117
100
DNI
R4590
C168
0.1uF
R610
R119
100
DNI
C165
0.1uF
C169
0.1uF
R4740
R4670
R4600
C52
6800pF
10V
C166
0.1uF
C170
0.1uF
LIFMD6000-csfBGA81
U8B
PB29A/PCLKT1_0 G7
PB29C/PCLKT1_1
PB29B/PCLKC1_0 J6
G6
PB29D/PCLKC1_1 H6
PB34A/GR_PCLK1_0 D1
PB34C/MIPI_CLKT1_0
PB34B J5
D2
H5
PB34D/MIPI_CLKC1_0
PB38A E1
PB38C
PB38B J4
E2
PB38D H4
PB43C J3
PB43D H3
VCCIO1 F3
VCCIO1 G4
R121
100
DNI
R106
100
DNI
R4220 DNI
C53
1uF
4V
R4500 DNI
U12
Hirose - FX12 - 40 Pos
CH0_DCK_P
1
CH0_DCK_N
2
GND
3
CH0_DATA0_P
4
CH0_DATA0_N
5
GND
6
CH0_DATA2_P
7
CH0_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12V
12
SDA1
13
SCL1
14
GND
15
CH2_DATA0_P
16
CH2_DATA0_N
17
GND
18
CH2_DCK_P
19
CH2_DCK_N
20
PWR_12-0V 21
RESETN 22
PWR_5-0V 23
CH0_DATA1_P 24
CH0_DATA1_N 25
PWR_3-3V 26
CH0_DATA3_P 27
CH0_DATA3_N 28
PWR_1-8V 29
MOSI 30
MISO 31
PWR_1-8V 32
GND 33
GND 34
PWR_3-3V 35
CH2_DATA1_P 36
CH2_DATA1_N 37
PWR_5-0V 38
SDA 39
SCL 40
Shield1
41 Shield2 42
Shield3
43
Shield4
44 Shield5 45
Shield6 46
R4680
R4230 DNI
R4630
R56
4.7k
C51
100nF
16V
R107
100
DNI
C181
0.1uF
R5D
7 680R
DNI
C177
470pF
16V
R4570
R4710
R4640
LIFMD6000-csfBGA81
U8C
PB2A F9
PB2C/MIPI_CLKT2_0
PB2B G9
F8
PB2D/MIPI_CLKC2_0 G8
PB6A/GR_PCLK2_0 E9
PB6C
PB6B H9
E8
PB6D H8
PB12A/GPLLT2_0 F7
PB12C
PB12B/GPLLC2_0 J9
E7
J8
PB12D
PB16A/PCLKT2_0 D9
D8
PB16B/PCLKC2_0 J7
PB16C/PCLKT2_1 H7
PB16D/PCLKC2_1
VCCIO2 E6
VCCIO2 F6
R59 680R
R54 680R
DNI
C59
1.5nF
10V
R4750
R108
100
DNI
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24 EB105-1.1
Bank0, Flash Interface
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLACE DECOUPLING CAPACITORS CLOSE TO THE U8 POWER PINS
J20
NOTE : PLACE SWITCH IN THE TOP SIDE OSCILLATOR
NOTE : PLACE X3 NEAR U8
NOTE : R159 SHUOULD BE PLACED
NEAR X3
SYSTEM RESET
PLACE CLOSE TO U8
SPI FLASH
NOTE : PLACE SPI FLASH IN THE TOP SIDE
IT SUPPORTS 2.5/3.3 V
SPI FLASH
CRESETB
NOTE : PLACE R83 Close to the snow device
1. 0.1uF and 1.5nF is added as the piggyback cap
470pF and 1.5nF is loaded near DUT and 0.1uF and 1.5nF is made piggy back for the following reference designer
C66,C75,C78
Piggyback Configuration info:
2. 0.001uF is added as the piggyback cap
100nF is loaded near DUT and 0.001uF is made piggy back for the following reference designer
C176
3. 1.5nF is added as the piggyback cap
1.5nF is loaded near DUT and 1.5nF is made piggy back for the following reference designer
C175
PLACE CLOSE TO U8
NOTE : PLACE X4 NEAR U8
NOTE : R431 SHUOULD BE PLACED
NEAR X4
OSCILLATOR
SYS_RST
CLK_INT
CLK_EXT
SISPI
SPISO
MCLK
CSSPIN
CDONE
CLK_SDA
CLK_SCL
CRESETB
CRESETB
MCLK
SISPI
SPISO
CSSPIN
SDA
SCL
CLK_INT
CLK_SDA
CLK_EXT
SDA
CLK_INT_REF
CLK_SCL
CLK_EXT_REF
SCL
CLK_EXT_REF
CLK_INT_REF
CDONE
VCC_CORE
VCCIO0 VCCIO2
VCCIO0
VCCIO0
VCCIO0
VCC_CORE
+2.5V
5V
+1.2V
5V
+1.8V
5V
+2.5V
VCCIO0
VCCIO0
VCCIO2
12V_EXT
SPISO 2,4,5,62,4,5,6 SISPI
2,4,5,6 MCLK
2,4,5,6 CSSPIN
SISPI 2,4,5,6
SPISO 2,4,5,6
MCLK 2,4,5,6
CSSPIN 2,4,5,6
CDONE 2
CRESETB 2
4,7 SDA
4,7 SCL
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888666
BBBAAANNNKKK000,,, FFFlllaaassshhh III///FFF
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
C76
330pF
Q10
MMBT2222A
2
1
MH4ThruHole
CON2
2
1
D29
Green
132
KC3225A27.0000C30E0A
X3
GND
2
VDD
4STDBY# 1
OUT 3
R78
10K
C77
5600pF
Q11
MMBT2222A
2
1
J7
CON2
1
2
MH5ThruHole
1K
R441
J4
50 Ohm Clock Route
73391-0060
12
3
4
5
R431
0
R8330E
R123
10K
C78
1.5nF
MH6ThruHole
R76
2K
R395 10K
C176
100nF
16V
C174
1000pF
25V
R124
10K
MH7ThruHole
R4140
1K
R442
R125
10K
C175
1.5nF
J26
Tri-Con
In1 1
Out 2
In2 3
In3
4
C173
2200pF
25V
MH8ThruHole
J19
CON2
2
1
R80
680R
Q9
MMBT2222A
2
1
TP18
1
R77
2K
C179
100nF
10V
R90
0
C66
470pF
16V
C70
100nF
16V
R4150
C49
100nF
10V
1K
R443
R1830
D10
Green
12
R159
0
KC3225A27.0000C30E0A
X4
GND
2
VDD
4STDBY# 1
OUT 3
R412
0
C68
0.1uF
J18
HEADER 5X2
2
4
6
8
10
1
3
5
7
9
C67
1uF
4V
C71
1uF
4V
1K
R166
R4160
R432
100K R4470
LIFMD6000-csfBGA81
U8A
J2
H2
F2
F1
J1
G1
H1
PB47/PCLKT0_0/USER_SDA
CDONE/PB49/PMU_WKUPN
PB48/PCLKT0_1/USER_SCL
PB50/MOSI
PB51/MISO
PB52/SPI_SS/CSN/SCL
PB53/SPI_SCK/MCK/SDA
CRESET_B G2
VCCIO0 G3
R131
4.7k
C74
330pF
R413
0
J22
50 Ohm Clock Route
73391-0060
12
3
4
5
1K
R444
R399 10K
MH9ThruHole
MH1ThruHole
C73
330pF
MH10
ThruHole
SW2
SYS_RST
D26
Green
12
R4330
LIFMD6000-csfBGA81
U8E
VCCGPLL G5
GNDGPLL
F5 GND
D4 GND
C5 GND
E5 GND
F4 GND
D6 VCC E3
VCC E4
VCCAUX25VPP D5
MH2ThruHole
C72
4700pF
R400 10K
D27
Green
132
C98
100nF
10V
SW5
WAKE_UP
MH3ThruHole
C75
1.5nF
U14
M25PX16-VMW6TG
CS
1
SDI
5
SCK
6
WP
3
HOLD 7
VCC 8
GND
4
SDO 2
D28
Green
132
R160
100K
J27
Tri-Con
In1 1
Out 2
In2 3
In3
4
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© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
EB105-1.1 25
I2C Expander
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLACE DECOUPLING CAPACITORS CLOSE TO THE U5 POWER PINS
I/O Expander - I2C Muxing
NOTE : PLACE SWITCH IN THE TOP SIDE
EXTERNAL RESET
DONE
INITN
PROGRAMN
JTAGENB
DONE
LED1
LED2
LED3
LED4
DEBUG1
DEBUG2
DEBUG3
DEBUG4
LED1
LED2
LED3
LED4
DEBUG1
DEBUG2
DEBUG3
DEBUG4
XO3_RESET
XO3_RESET
1K_VCC_CORE
1K_VCCIO2 1K_VCCIO0
1K_VCCIO3
1K_VCCIO0
1K_VCCIO2
1K_VCCIO1
1K_VCC_CORE
1K_VCCIO1
VCCIO0
1K_VCCIO3
SCL 4,6
SDA 4,6 SCL2 5
SCL1 5
SDA2 5
SDA1 5
12MHZ 2
TDO 2
TCK 2
TMS 2
TDI 2
SCL4 5
SCL3 5
SDA4 5
SDA3 5
XO3_SCL 4
XO3_SDA 4
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888777
III222CCC EEExxxpppaaannndddeeerrr
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
C140
0.01uF
C104
0.1uF
C151
0.1uF
R404
4.7k
R436 680R
C105
0.1uF
R440
4.7k
C141
10uF
D23
Red
12
R437 680R
R405
4.7k
SW3
SYS_RST
C106
1uF
R179
650
D30 blue
1 2
BANK2
LCMXO3LF-1200E-MG121
U19C
VCCIO2
H6 H7
H9
J4
J5
J6
J7
J8
J9
K10
K2
K3
K4
K5
K6
K7
K8
K9
L10
L2
L3
L4
L5
L6
L7
L8
PB6D/SO/SPISO
PB4A
PB18D
PB18C
PB15C
PB11D
PB6C/MCLK/CCLK
PB4B
PB4C/CSSPIN
PB20D/SI/SISPI
PB20B
PB18B
PB15B
PB11B/PCLKC2_1
PB9B/PCLKC2_0
PB9C
PB6A
PB4D
PB20C/SN
PB20A
PB18A
PB15A
PB11A/PCLKT2_1
PB9A/PCLKT2_0
PB9D
PB6B L9
C152
0.1uF
C147
0.1uF
LCMXO3LF-1200E-MG121
U19E
VCC
D5
VCC
E5
VCC
F7
VCC
G7
GND A1
GND A11
GND E6
GND E7
GND F5
GND F6
GND G5
GND G6
GND L1
GND L11
D31 blue
1 2
R477
4.7k
TP23
1
R175
4.7k
R478
4.7k
C143
0.1uF
C153
10uF
C142
0.1uF
R176
4.7k
R438 680R
C154
0.01uF
R479
4.7k
TP24
1
D32 blue
1 2
R4510
R480
4.7k
C148
0.1uF
R483
4.7k
TP25
1
C107
10uF
BANK1
LCMXO3LF-1200E-MG121
U19B
VCCIO1
H5 PR2C B1
PR2D C1
PR2A C2
PR3B D1
PR3A D2
PR2B D3
PR4D E1
PR4C E2
PR4B E3
PR4A E4
PR5D/PCLKC1_0 F1
PR5C/PCLKT1_0 F2
PR5A F3
PR5B F4
PR8A G1
PR8B G2
PR8C G3
PR8D G4
PR9A H1
PR9B H2
PR9C H3
PR9D H4
PR10A J1
PR10C J2
PR10D J3
PR10B K1
R439 680R
R177
4.7k
R484
4.7k
C144
0.1uF
C149
0.01uF
C102
0.1uF
R4520
D33 blue
1 2
R178
4.7k
C150
10uF
C145
10uF
C139
0.1uF
C146
0.01uF
C103
0.01uF
R403
4.7k
J23
4 HEADER
1
2
3
4
BANK3
LCMXO3LF-1200E-MG121
U19D
VCCIO3
D8
VCCIO3
F8
VCCIO3
H8
B10
B11
C10
C11
C9
D10
D11
D9
E10
E11
E8
E9
F10
F11
F9
G10
G11
G8
G9
H10
H11
J10
J11
PL2C/L_GPLLT_IN
PL2D/L_GPLLC_IN
PL3A/PCLKT3_2
PL3B/PCLKC3_2
PL2A/L_GPLLT_FB
PL4A
PL4B
PL3C
PL4C
PL4D
PL2B/L_GPLLC_FB
PL3D
PL5B/PCLKC3_1
PL5A/PCLKT3_1
PL5C
PL8B
PL8A
PL8D
PL8C
PL9B/PCLKC3_0
PL9A/PCLKT3_0
PL10D
PL10A
PL10C K11
C180
0.1uF
LCMXO3LF-1200E-MG121
U19A
VCCIO0
D6 A10
A2
A3
A4
A5
A6
A7
A8
A9
B2
B3
B4
B5
B6
B7
B8
B9
C3
C4
C5
C6
C7
C8
D4
PT9A
BANK0
PT17A
PT16A
PT15A
PT12C/SCL/PCLKTO_0
PT12B/PCLKC0_1
PT11A
PT10D/TDI
PT10A
PT17B
PT16B
PT15B
PT12D/SDA/PCLKC0_0
PT12A/PCLKTO_1
PT11B
PT10B
PT9B
PT17C/INITN
PT15D/PROGRAMN
PT15C/JTAGENB
PT11D/TMS
PT11C/TCK
PT9C
PT17D/DONE
PT10C/TDO D7
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26 EB105-1.1
Layout Guidelines
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Routing guidlines for MIPI & LVDS
----------------------------------
1)All differential routes are required to have the same length between the positive (true) and the negative (complimentary) routes.
Spacing between the positive (true) and the negative (complimentary) shall be 2 times trace width.
2)Target differential impedance shall be 100 Ohms
3)Trace length matching to be within 1.0 mm (40 mil) across the entire bus.
4)Use small humps for skew corrections
5)Place signal vias close together and remove copper in between vias.
Traces to be fully shielded with GND stitching terminating at both trace end points
6)Board trace impedance results must be within ±10 percent of target and
Power plane impedance to be within +/- 10 percent of target at operating frequency
MIPI &LVDS Simulation Requirement
----------------------------------
1)MIPI Differential Mode insertion Loss shall be > -1.6dB at 750 MHz
2)MIPI Differential Mode Return Loss shall be < -15dB at 750 MHz
3)MIPI Common Mode Return Loss shall be < -15dB at 750 MHz
4)LVDS differential mode return loss shall be < -16.5db at 600 MHz
5)LVDS common mode return loss shall be < -16.5db at 600 MHz
6)LVDS insertion loss shall be > -1.7db at 600 MHz
7)LVDS Cross coupling shall be < -22 dB for victim IO at 600MHz
8)Power plane impedance to be within +/- 10 percent of target at operating frequency
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888888
LLLaaayyyooouuuttt GGGuuuiiidddeeellliiinnneeesss
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
EB105-1.1 27
Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials
LIF-MD6000 Master Link Board Bill of Materials
Item
Reference
Quantity
Part
PCB
Footprint
Comments
Part_
Number
Manufacturer
Description
1
C1, C3
2
4u7
C0603
—
ECJ-
1VB0J475K
Panasonic
Cap Cer
4.7 µF
6.3 V 10% X5R 0603
2
C2, C4, C5, C6, C8,
C9, C12, C13, C14,
C15, C16, C22, C25,
C68, C112, C180,
C181
17
0.1 µF
C0402
—
C0402C104K4
RACTU
Kemet
CAP CERAMIC
0.1 µF
16 V X7R 0402
3
C7, C20, C23, C107,
C114, C141, C145,
C150, C153
9
10 µF
C0603
—
LMK107BJ10
6MALTD
Taiyo Yuden
CAP CECAP CER 10 µF
10 V X5R 20% 0603
4
C10, C11
2
18 pF
C0402
—
C0402C180K3
GACTU
Kemet
CAP CER 18 pF 25 V
C0G 0402
5
C21, C24, C113
3
22 µF
C0805
—
LMK212BJ22
6MG-T
Taiyo Yuden
CAP CERAMIC
22 µF 10 V X5R 0805
6
C29, C95, C97
3
0.1 µF
C0402
—
CL05A104MP
5NNNC
Samsung
Cap Ceramic 0.1 µF
10 V X5R 20% SMD
0402 85C Paper T/R
7
C41, C43, C53, C60,
C67, C71
6
1 µF
C0306
—
LLR185C70G1
05ME05L
Murata
CAP CER 1µF 4 V X7S
0306
8
C42, C44
2
0.01 µF
C0201
—
GRM033R61C
103KA12D
Murata
CAP CER 10000 pF
16 V X5R 0201
9
C42, C44, C51, C176
4
0.001 µF
C0201
Piggyback
Configuration
GRM033R71C
102KA01D
Murata
CAP CER 1000 pF 16 V
X7R 0201
10
C45
1
1 µF
C0402
—
GRM155R61C
105KA12D
Murata
CAP CER
1 µF 16 V X5R 0402
11
C46, C66, C171,
C172, C177
5
470 pF
C0201
—
GRM033R71C
471KA01D
Murata
CAP CER
470 pF 16 V X7R 0201
12
C46, C66, C171, C172
4
0.1 µF
C0201
Piggyback
Configuration
GRM033R61C
104KE84D
Murata
CAP CER 0.1 µF
16 V X5R 0201
13
C49, C98, C179
3
100 nF
C0402
—
GRM155R61
A104KA01D
Murata
CAP CER 100 nF
10 V 10% X5R 0402
14
C51, C58, C70, C176
4
100 nF
C0201
—
C0603X5R1C1
04K030BC
TDK
CAP CER
0.1 µF 16 V X5R 0201
15
C52
1
6800 pF
C0201
—
GRM033R71A
682KA01D
Murata
CAP CER 6800 pF 10 V
X7R 0201
16
C59, C75, C78, C175
4
1.5 nF
C0201
—
GRM033R71A
152KA01D
Murata
CAP CER 1500 pF 10 V
X7R 0201
17
C75, C78, C59, C175
4
1.5 nF
C0201
Piggyback
Configuration
GRM033R71A
152KA01D
Murata
CAP CER 1500 pF 10 V
X7R 0201
18
C72
1
4700 pF
C0306
—
LLL185R71H4
72MA01L
Murata
CAP CER 4700 pF 50 V
X7R 0306
19
C73, C74, C76
3
330 pF
C0201
—
GRM033R71
H331KA12D
Murata
CAP CER
330 pF 50 V X7R 0201
20
C77
1
5600 pF
C0201
—
GRM033R71A
562KA01D
Murata
CAP CER 5600 pF 10 V
X7R 0201
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28 EB105-1.1
LIF-MD6000 Master Link Board Bill of Materials (Continued)
Item
Reference
Quantity
Part
PCB
Footprint
Comments
Part_
Number
Manufacturer
Description
21
C94, C96
2
10 µF
C0603
—
CL10X106MP
8NRNC
Samsung
CAP CER
10 µF 10 V 20% X6S
0603
22
C102, C104, C105,
C139, C142, C143,
C144, C147, C148,
C151, C152
11
0.1 µF
C0201
-—
C0603X5R1C1
04K030BC
TDK
CAP CER
0.1 µF 16 V 10% X5R
0201
23
C103, C140, C146,
C149, C154
5
0.01 µF
C0201
—
CC0201KRX7R
7BB103
Yageo
CAP CER 10000 pF
16 V 10% X7R 0201
24
C106
1
1 µF
C0402
—
C0402C105K9
PACTU
Kemet
CAP CERAMIC
1 µF 6.3 V X5R 0402
25
C115, C130
2
10 µF
C0603
—
CL10A106MA
8NRNC
Samsung
CAP CER
10 µF 25 V 20% X5R
0603
26
C123
1
0.1 µF
C0603
—
GRM188R71E
104KA01D
Murata
CAP CER
0.1 µF 25 V 10% X7R
0603
27
C127
1
680 pF
C0603
—
C0603C681J3
GACTU
Kemet
CAP CER
680 pF 25 V 5% NP0
0603
28
C128
1
0.47 µF
C0402
—
CL05A474KA5
NNNC
Samsung
CAP CER 0.47 µF 25 V
10% X5R 0402
29
C129
1
47 µF
C0805
—
C2012X5R1A4
76M125AC
TDK
CAP CER
47 µF 10 V 20% X5R
0805
30
C155, C156, C157,
C158, C159, C160,
C161, C162, C163,
C164, C165, C166,
C167, C168, C169,
C170
16
0.1 µF
C0402
—
04023C104KA
T2A
AVX
CAP CER
0.1 µF 25 V 10% X7R
0402
31
C173
1
2200 pF
C0201
—
GRM033R71E
222KA12D
Murata
CAP CER 2200 pF 25 V
X7R 0201
32
C174
1
1000 pF
C0201
—
GRM033R61E
102KA01D
Murata
CAP CER 1000 pF 25 V
X5R 0201
33
C178
1
0.1 µF
C0201
—
GRM033R61C
104KE84D
Murata
CAP CER
0.1 µF 16 V X5R 0201
34
D1, D14
2
SL44-E3/
57T
SL44E357T
—
SL44-E3/57T
Vishay
semiconducto
r
Schottky Diodes &
Rectifiers 4.0 A 40 V
35
D3, D25, D26, D27,
D28, D29
6
Green
led_0603
—
LTST-
C190KGKT
LITE-On INC
LED SUPER GREEN
CLEAR 0603 SMD
36
D6, D7, D8, D9,
D30, D31, D32,
D33
8
blue
led_0603
—
LTST-
C193TBKT-5A
LITE-On INC
Standard LEDs - SMD
Blue 470 nm 28mcd
5 mA
37
D10
1
Green
led_0603
—
LG L29K-
G2J1-24-Z
OSRAM
LED SUPER GREEN
CLEAR 0603 SMD
38
D12
1
0.3 VF
MBRA340T
3G
—
MBRA340T3G
ON Semi
DIODE SCHOTTKY 40 V
3 A SMA
39
D23
1
Red
led_0603
—
LTST-
C193KRKT-5A
LITE-On INC
Standard LEDs - SMD
Red 631 nm 14mcd
5 mA
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
EB105-1.1 29
LIF-MD6000 Master Link Board Bill of Materials (Continued)
Item
Reference
Quantity
Part
PCB
Footprint
Comments
Part_
Number
Manufacturer
Description
40
VCC_DPHY1,
VCC_CORE1,
VCCIO1, GND1,
VCCIO2, GND2,
GND3, GND4,
GND5, 1K_VCCIO0,
1K_VCC_CORE1,
1K_VCCIO1, 1V2,
1K_VCCIO2,
1K_VCCIO3, TP18,
TP23, TP24, TP25,
2V5, 3V3, 5V0,
12V0, VCCIO0
24
TP_S_40_
63
tp_s_
40_63
DNI
—
—
Square test point,
40 mil inner
diameter,
63 mil outer
diameter
41
J1
1
header_
1x8
hdr_amp_
87220_8_
1x8_100
—
22-28-4081
Molex
CONN HEADER
8POS .100 VERT TIN
42
J2
1
SKT_MINI
USB_B_R
A
skt_miniu
sb_b_ra
—
5075BMR-05-
SM-CR
Neltron
CONN MINI USB
RCPT RA TYPE B SMD
43
J3
1
PJ-032A
PJ-032A
—
PJ-032A
CUI Inc.
CON PWR JCK
2.0 X 6.5 M VERT
44
J4, J22
2
73391-
0060
73391-
0060
—
73391-0060
Molex
CONN SMA JACK STR
50 OHM PCB
45
J7, J19, J20
3
CON2
CON2
REGULAR
100 MIL
HEADER
—
—
General 100 mils
2 Position header
46
J8, J9
2
2 Position
Terminal
Block_0
TERM_BL
OCK_2PO
S_10A
—
1727010
Phoenix
Contact
TERM BLOCK 2POS
3.81 mm PCB GRN
47
J18
1
HEADER
5X2
HEADER
2X5
REGULAR
100 MIL
HEADER
—
—
General 100 Mils
2*5 header
48
J23
1
4 HEADER
CON4
REGULAR
100 MIL
HEADER
—
—
General 100 Mils
4 Position Header
49
J24, J25, J26, J27
4
Tri-Con
TriCon
REGULAR
100 MIL
HEADER
—
—
General 100 Mils
Header
50
J28
1
CON6
HDR1X6
REGULAR
100 MIL
HEADER
—
—
—
51
J29
1
CON3
HDR1X3
REGULAR
100 MIL
HEADER
—
—
—
52
L1, L2, L3, L4, L5, L6,
L7
7
600 Ω
500 mA
FB0603
—
BLM18AG601
SN1D
Murata
Ferrite Bead 600 Ω
@100 MHz 500 mA
0603
53
L8
1
4.7 uH
MPLC073
0L4R7
—
MPLC0730L4
R7
Kemet
INDUCTOR POWER
4.7 uH 20% SMD
54
MH1, MH2, MH3,
MH4, MH5, MH6,
MH7, MH8, MH9,
MH10
10
Thru Hole
MTG125
DNL
—
—
—
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30 EB105-1.1
LIF-MD6000 Master Link Board Bill of Materials (Continued)
Item
Reference
Quantity
Part
PCB
Footprint
Comments
Part_
Number
Manufacturer
Description
55
Q9, Q10, Q11
3
MMBT222
2A
SM_
SOT23-3
—
MMBT2222
A,215
NXP
Semiconductor
TRANS NPN 40 V 0.6
A SOT23
56
R1, R2, R3, R56,
R131, R175, R176,
R177, R178, R403,
R404, R405, R440,
R445, R477, R478,
R479, R480, R483,
R484
20
4.7K
R0603
—
CRCW06034
K70FKEA
Vishay
RES SMD
4.7 kΩ HM 1% 1/10
W 0603
57
R4, R5, R6, R7, R15,
R16, R26, R37, R39,
R51, R52, R53, R90,
R159, R165, R167,
R180, R181, R183,
R192, R431, R433,
R447
23
0
R0603
—
RC0603JR-
070RL
Yageo
Res 1/10 W 0.0 Ω 5%
0603
58
R9, R10
2
2K2
R0603
—
CRCW06032
K20FKEA
Vishay
RES SMD
2.2 kΩ 1% 1/10 W
0603
59
R11, R17
2
12K
R0603
—
RC0603FR-
0712KL
Yageo
RES SMD
12 kΩ 1% 1/10 W
0603
60
R12, R13, R14,
R123, R124, R125
6
10K
R0603
—
RMCF0603JT
10K0
Stackpole
Electronics Inc
RES SMD
10 kΩ 5%
1/10 W 0603
61
R18, R418, R419,
R422, R423
5
0
R0603
DNI
RC0603JR-
070RL
Yageo
Res 1/10 W 0.0 Ω 5%
0603
62
R19, R20, R21, R25,
R28, R33, R184,
R186, R188, R190,
R410, R417, R434,
R435, R448, R449
16
1
R0603
—
CRCW06031
R00JNEAHP
Vishay/Dale
RES SMD
1 Ω 5% 1/4W 0603
63
R22, R144
2
100E
R0603
DNI
CRCW06031
00RFKEAHP
Vishay / Dale
RES SMD 100 Ω 1%
1/4W 0603
64
R23
1
0
R0603
DNI
RC0603JR-
070RL
Yageo
Res 1/10 W 0.0 Ω 5%
0603
65
R24, R185, R187,
R189, R411
5
1
R0603
DNI
CRCW06031
R00JNEAHP
Vishay/Dale
RES SMD
1 Ω 5% 1/4W 0603
66
R36, R233
2
1K
R0603
—
RC0603FR-
071KL
Yageo
RES SMD
1 kΩ 1% 1/10 W
0603
67
R54, R55, R57, R59
4
680R
R0402
DNI
RMCF0402JT
680R
Stackpole
Electronics Inc
RES 680 Ω 1/16 W
5% 0402
68
R60, R61, R446,
R457, R458, R459,
R460, R461, R462,
R463, R464, R467,
R468, R469, R470,
R471, R472, R473,
R474, R475, R476
21
0
R0402
—
RC0402JR-
070RL
Yageo
RES SMD 0.0O HM
JUMPER 1/16 W
0402
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
EB105-1.1 31
LIF-MD6000 Master Link Board Bill of Materials (Continued)
Item
Reference
Quantity
Part
PCB
Footprint
Comments
Part_
Number
Manufacturer
Description
69
R76, R77
2
2K
R0402
—
ERJ-
2RKF2001X
Panasonic
RES SMD
2 kΩ 1% 1/10 W
0402
70
R78
1
10K
R0402
—
RMCF0402JT
10K0
Stackpole
Electronics
Inc
RES 10 kΩ 1/16 W
5% 0402
71
R80, R436, R437,
R438, R439
5
680R
R0402
—
RMCF0402JT
680R
Stackpole
Electronics
Inc
RES 680 Ω 1/16 W
5% 0402
72
R83
1
30E
R0603
—
RC0603FR-
0730RL
Yageo
RES SMD
30 Ω 1% 1/10 W
0603
73
R106, R107, R108,
R110, R111, R113,
R114, R117, R119,
R121
10
100
R0402
DNI
RC0402FR-
07100RL
Yageo
RES SMD 100 Ω
1% 1/16 W 0402
74
R160, R432
2
100K
R0402
—
RMCF0402JT
100K
Stackpole
Electronics
Inc
RES 100 kΩ 1/16 W
5% 0402
75
R166, R441, R442,
R443, R444
5
1K
R0402
—
RMCF0402JT
1K00
Stackpole
Electronics
Inc
RES 1 kΩ 1/16 W 5%
0402
76
R179
1
650
R0603
—
RC0603FR-
07649RL
Yageo
RES SMD 649 Ω 1%
1/10 W 0603
77
R229
1
15K
R0402
—
ERJ-
2RKF1502X
Panasonic
RES 15 kΩ 1/10 W
1% 0402 SMD
78
R230
1
34K
R0402
—
ERJ-
2RKF3402X
Panasonic
RES 34 kΩ 1/10 W
1% 0402 SMD
79
R231
1
536K
R0402
—
ERJ-
2RKF5363X
Panasonic
Electronic
Components
RES 536 kΩ 1/10 W
1% 0402 SMD
80
R232
1
100K
R0402
—
ERJ-
2RKF1003X
Panasonic
Electronic
Components
RES 100 kΩ 1/10 W
1% 0402 SMD
81
R395, R399, R400
3
10K
R0603
—
ERJ-
3EKF1002V
Panasonic
RES SMD
10 kΩ 1% 1/10 W
0603
82
R412, R413, R414,
R415, R416, R420,
R421, R424, R425,
R451, R452, R453,
R454, R455, R456,
R465, R466
17
0
R0603
—
RC0603JR-
070RL
Yageo
Res 1/10 W 0.0 Ω
5% 0603
83
R450
1
0
R0402
DNI
RC0402JR-
070RL
Yageo
RES SMD 0.0O HM
JUMPER 1/16 W
0402
84
R481, R482
2
0
R0603
DNL
RC0603JR-
070RL
Yageo
Res 1/10 W 0.0 Ω
5% 0603
85
SW1
1
PWR
TS01CQE_
switch
—
TS01CQE
C&K
Components
SWITCH SLIDE SPDT
3 A 120 V
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32 EB105-1.1
LIF-MD6000 Master Link Board Bill of Materials (Continued)
Item
Reference
Quantity
Part
PCB
Footprint
Comments
Part_
Number
Manufacturer
Description
86
SW2, SW3, SW4
3
SYS_
RST
2psmd_es
witch
—
TL1015AF160QG
E-Switch
SWITCH TACTILE SPST-
NO 0.05 A 12 V
87
SW5
1
WAKE_
UP
2psmd_es
witch
—
TL1015AF160QG
E-Switch
SWITCH TACTILE SPST-
NO 0.05 A 12 V
88
U1
1
FT2232HL
tqfp64_0p
5_12p2x1
2p2_h1p6
—
FT2232HL
FTDI
USB to UART / FIFO
89
U2
1
93LC56-SO8
so8_50_2
44
—
93LC56C-I/SN
Microchip
IC 93LC56 EEPROM
90
U3
1
FUSE
0154004D
RT
—
0154004.DRT
Littlefuse
Surface Mount Fuses
Fuseblock with fuse 4A
OMNI BLOK 154T
91
U5
1
NCP1117ST
33T3G
sot223_4p
—
NCP1117ST33T3G
On Semi
IC Reg LDO 3.3 V SOT-
223
92
U6
1
NCP1117ST
25T3G
sot223_4p
—
NCP1117ST25T3G
On Semi
IC Reg LDO 2.5 V SOT-
223
93
U7, U9, U11,
U12
4
Hirose -
FX12 - 40
Pos
Hirose-
FX12
—
FX12B-40P-0.4SV
Hirose Electric
Co Ltd
Conn Board to Board PL
40 POS
0.4 mm Solder ST SMD
T/R
94
U8
1
LIF-
MD6000-
csfBGA81
LIF-
MD6000-
csfBGA81
Customer
supplied
LIF-MD6000-
csfBGA81
Lattice
Semiconductor
Lattice Semiconductor
6K CrossLink FPGA
Family
95
U14
1
M25PX16-
VMW6TG
SOIC8
—
M25PX16-
VMW6TG
Micron
Technology Inc
IC FLASH
16 Mbit
75 MHz 8SO
96
U15
1
AP7313-
12SAG-7
SOT23
—
AP7313-12SAG-7
Diodes Inc
LDO Voltage Regulators
LDO SOT-23R
1.2 V/ 150 mA
97
U17
1
NCP1117ST
18T3G
sot223_4p
—
NCP1117ST18T3G
On Semi
IC Reg LDO 1.8 V SOT-
223
98
U18
1
LT3680
LT3680_1
0QFN
—
LT3680EDD#PBF
Linear
5 V Step down
converter
99
U19
1
LCMXO3LF-
1200E-
MG121
LCMXO3LF
-1200E-
MG121
Customer
supplied
LCMXO3LF-
1200E-MG121
Lattice
Semiconductor
CPLD MachXO3 Family
121-Pin CSFBGA-
0.5 mm Pitch
100
X1
1
12MHZ
crystal_4p
_3p2x2p5
—
7M-12.000MAAJ-
T
TXC
12 MHz Crystal
101
X3, X4
2
KC3225A27.
0000C30E0
A
27MHZ_O
SC
—
KC3225A27.0000
C30E0A
AVX
Corporation
Standard Clock
Oscillators 27.000 MHz
102
LIF-MD6000
MASTER LINK
BOARD PCB
1
—
—
—
305-PD-16-0154
PACTRON
—
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The
specifications and information herein are subject to change without notice.
EB105-1.1 33
Appendix C. SMA-IOL-EVN-BRD Schematics
SMA Debug Board
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TX Connector1
Note : Test point silk screen name should be same as the respective power rails
Note : Plae 0.01uF caps near each connector(U1)
Note : Plae 0.01uF caps near each connector(U1)
CH4_DATA3_TX_P
CH4_DATA3_TX_N
CH4_DATA2_TX_P
CH4_DATA2_TX_N
CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
CH4_DCK_TX_P CH4_DCK_TX_N
CH4_DATA0_TX_P CH4_DATA0_TX_N
CH4_DATA1_TX_P CH4_DATA1_TX_N
CH4_DATA2_TX_P CH4_DATA2_TX_N
CH4_DATA3_TX_P CH4_DATA3_TX_N
CH4_DATA4_TX_P
CH4_DATA4_TX_N
CH4_DATA5_TX_P
CH4_DATA5_TX_N
CH4_DATA4_TX_P
CH4_DATA4_TX_N
CH4_DATA5_TX_P
CH4_DATA5_TX_N
+5V +3.3V +1.8V
+5V +3.3V +1.8V
+3.3V
+1.8V
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
000444---MMMaaayyy---111555
BBB 111...000
111111
SSSMMMAAA DDDEEEBBBUUUGGG BBBOOOAAARRRDDD
LLLCCCMMMXXXOOO333LLL---444333000000---MMMGGG222555666 MMMIIIPPPIII BBBrrriiidddiiinnnggg sssooollluuutttiiiooonnn AAA
RESETN
1
1
SN
GND
1
C1
1uF
J12
73391-0060
1 2
3
4
5
C6
0.01uF
MOSI
1
J10
73391-0060
1 2
3
4
5
J2
73391-0060
1 2
3
4
5
SCL
1
J8
73391-0060
1 2
3
4
5
J6
73391-0060
1 2
3
4
5
J14
73391-0060
1 2
3
4
5
C2
0.1uF
J4
73391-0060
1 2
3
4
5
J9
73391-0060
1 2
3
4
5
MH1ThruHole
+1.8V
1
J7
73391-0060
1 2
3
4
5
C4
1uF
+5V
1
+3.3V
1
J11
73391-0060
1 2
3
4
5
J5
73391-0060
1 2
3
4
5
U1
Hirose - FX12 - 40 Pos
CH4_DCK_P
1
CH4_DCK_N
2
GND1
3
CH4_DATA0_P
4
CH4_DATA0_N
5
GND2
6
CH4_DATA1_P
7
CH4_DATA1_N
8
GND3
9
SN
10
SCLK
11
GND4
12
CH4_DATA2_P
13
CH4_DATA2_N
14
GND5
15
CH4_DATA3_P
16
CH4_DATA3_N
17
GND6
18
12V
19
12V
20
TBD 21
RESETN 22
PWR_5-0V 23
GND7 24
GND8 25
PWR_3-3V 26
GND9 27
GND10 28
PWR_1-8V 29
MOSI 30
MISO 31
PWR_1-8V 32
GND11 33
GND12 34
PWR_3-3V 35
GND13 36
GND14 37
PWR_5-0V 38
SDA 39
SCL 40
Shield1
41 Shield2 42
Shield3
43
Shield4
44 Shield5 45
Shield6 46
J3
73391-0060
1 2
3
4
5
SDA
1
J1
73391-0060
1 2
3
4
5
GND1
1
MH2ThruHole
1
SCLK
J13
73391-0060
1 2
3
4
5
C3
0.01uF
C5
0.1uF
MISO
1
CrossLink LIF-MD6000 Master Link BoardBoard
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34 EB105-1.1
Appendix D. SMA-IOL-EVN-BRD Bill of Materials
SMA IO Link Board Bill of Materials
Item
Reference
Quantity
Part
PCB
Footprint
Comments
Part_
Number
Manufacturer
Description
1
GND1, +5 V, +1.8 V,
+3.3 V, SN, SDA,
SCLK, SCL, RESETN,
MOSI, MISO, GND
12
TP_S_
40_63
tp_s_40_
63
DNI
—
—
Square test point,
40 mil inner
diameter, 63 mil
outer diameter
2
C1, C4
2
1 µF
C0402
—
C0402C105K
9PACTU
Kemet
CAP CERAMIC
1 µF 6.3 V X5R
0402
3
C2, C5
2
0.1 µF
C0402
—
C0402C104K
4RACTU
Kemet
CAP CERAMIC
0.1 µF 16 V X7R
0402
4
C3, C6
2
0.01
µF
C0402
—
C0402C103J
4RACTU
Kemet
CAP CERAMIC
10 nF 16 V 5% X7R
0402
5
J1, J2, J3, J4, J5, J6,
J7, J8, J9, J10, J11,
J12, J13, J14
14
73391
-0060
73391-
0060
—
73391-0060
Molex
Molex Straight 50O
Through Hole SMA
Connector, jack,
Solder Termination
6
MH1, MH2
2
Thru
Hole
MTG125
—
—
—
—
7
U1
1
Hirose
- FX12
- 40
Pos
Hirose-
FX12S
—
FX12B-40S-
0.4SV
Hirose Electric
Co Ltd
Conn Board to
Board PL 40 POS
0.4 mm Solder ST
SMD T/R
8
SMA IOLINK BOARD
PCB
1
—
—
—
305-PD-15-
0589
PACTRON
—
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The
specifications and information herein are subject to change without notice.
EB105-1.1 35
Appendix E. B-IOL-EVN-BRD Schematics
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TX Connector1
Note : Test point silk screen name should be same as the respective power rails
Note : Plae 0.01uF caps near each connector(1)
Note : Plae 0.01uF caps near each connector(1)
CH4_DATA3_TX_N
CH4_DATA3_TX_P
CH4_DATA2_TX_P
CH4_DATA2_TX_N
CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA4_TX_P
CH4_DATA4_TX_N
CH4_DATA3_TX_N
CH4_DATA3_TX_P
RESETN
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
RESETN
SDA
SCL
SDA
SCL
CH4_DATA4_TX_P
CH4_DATA4_TX_N
CH4_DATA5_TX_P
CH4_DATA5_TX_N
CH4_DATA5_TX_N
CH4_DATA5_TX_PCH4_DATA2_TX_N
CH4_DATA2_TX_P
+5V +3.3V +1.8V
+5V +3.3V +1.8V
+3.3V
+1.8V
+1.8V +3.3V
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
04-May-15
B1.0
11
100MILS_DEBUG HEADER
LCMXO3L-4300-MG256 MIPI Briding solution A
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
04-May-15
B1.0
11
100MILS_DEBUG HEADER
LCMXO3L-4300-MG256 MIPI Briding solution A
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
04-May-15
B1.0
11
100MILS_DEBUG HEADER
LCMXO3L-4300-MG256 MIPI Briding solution A
GND
1
SCLK
1
C3
1uF
C5
0.1uF
+3.3V
1
MISO
1
+1.8V
1
C6
0.01uF
C1
0.1uF
J2
HEADER 13X2
2
4
6
8
10
12
14
16
18
20
22
24
26
1
3
5
7
9
11
13
15
17
19
21
23
25
MH2ThruHole
+5V
1
MH1ThruHole
C2
0.01uF
MOSI
1
SN
1
GND1
1
U1
Hirose - FX12 - 40 Pos
CH4_DCK_P
1
CH4_DCK_N
2
GND1
3
CH4_DATA0_P
4
CH4_DATA0_N
5
GND2
6
CH4_DATA1_P
7
CH4_DATA1_N
8
GND3
9
SN
10
SCLK
11
GND4
12
CH4_DATA2_P
13
CH4_DATA2_N
14
GND5
15
CH4_DATA3_P
16
CH4_DATA3_N
17
GND6
18
12V
19
12V
20
TBD 21
RESETN 22
PWR_5-0V 23
GND7 24
GND8 25
PWR_3-3V 26
GND9 27
GND10 28
PWR_1-8V 29
MOSI 30
MISO 31
PWR_1-8V 32
GND11 33
GND12 34
PWR_3-3V 35
GND13 36
GND14 37
PWR_5-0V 38
SDA 39
SCL 40
Shield1
41 Shield2 42
Shield3
43
Shield4
44 Shield5 45
Shield6 46
C4
1uF
100MILS_DEBUG Header
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36 FPGA-EB-02010-1.2
Appendix F. B-IOL-EVN-BRD Bill of Materials
Breakout IO Link Board Bill of Materials
Item
Reference
Quantity
Part
PCB Footprint
Comments
Part_
Number
Manufacturer
Description
1
GND1, +5 V,
+1.8 V, +3.3 V,
SN, SCLK, MOSI,
MISO, GND
9
TP_S_40_
63
tp_s_40_63
DNL
—
—
Square test point, 40 mil
inner diameter,
63 mil outer diameter
2
C1, C5
2
0.1 µF
C0402
—
C0402C104
K4RACTU
Kemet
CAP CERAMIC 0.1 µF
16 V X7R 0402
3
C2, C6
2
0.01 µF
C0402
—
C0402C103
J4RACTU
Kemet
CAP CERAMIC
10 nF 16 V 5% X7R 0402
4
C3, C4
2
1 µF
C0402
—
C0402C105
K9PACTU
Kemet
CAP CERAMIC
1 µF 6.3 V X5R 0402
5
J2
1
HEADER
13X2
13X2_HDR
REGULAR
100 MIL
HEADER
—
—
—
6
MH1, MH2
2
ThruHole
MTG125
DNL
—
—
—
7
U1
1
Hirose -
FX12 - 40
Pos
Hirose-
FX12S
—
FX12B-40S-
0.4SV
Hirose
Electric Co Ltd
Conn Board to Board PL
40 POS 0.4 mm Solder
ST SMD T/R
8
BREAKOUT
IOLINK BOARD
PCB
1
—
—
—
305-PD-15-
0595
PACTRON
—
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.2 37
Revision History
Date
Version
Change Summary
September 2017
1.2
Changed document number from EB105 to FPGA-EB-02010.
Changed J25 from VCCIO1 to VCCIO2 in Table 2.1. Headers and Test Connectors.
Updated 100MILS_DEBUG Header in Appendix E. B-IOL-EVN-BRD Schematics.
April 2017
1.1
New sections:
SMA IO Link Board
Breakout IO Link Board
Ordering Information
Updated Appendix A. LIF-MD6000-ML-EVN-BRD Schematics:
Changed “SW4 SYS_RST” to “SW4 EXT_RST” in the Bank 1, 2 – LVDS Rx diagram.
Changed “EXTERNAL RESET” to “SYSTEM RESET” in the Bank0, Flash Interface
diagram.
May 2016
1.0
Initial release.
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Portland, OR 97204, USA
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