TB62713N/F
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TOSHIBA BiCMOS INTEGRATED CIRCUITS SILICON MONOLITHIC
TB62713N,TB62713F
7 × 5 DOT DISPLAY DECODER AND DRIVER
(COMMON CATHODE ROW CAPABILITY)
The TB62713N and TB62713F are multifunctional, compact, 7×5
dot matrix LED display drivers.
Each of these ICs can directly drive and control one 7×5 dot
matrix LED display.
The display shows the common cathode rows.
Row output uses a constant current, which is set using an
external resistor.
The column output is standard PNP output.
A synchronous serial port connects the IC to the CPU.
The different modes of control provided by this device, including
Duty Control Register Set, Digit Set, Decode Set and Standby Set,
are all based on every 16bit of serial data.
FEATURES
Control circuit power supply voltage
: VDD = 4.5 to 5.5 V
Digit output rating
: 17 V / 350 mA
Row output rating
: 17 V / 50 mA
Builtin decoder
: Decoding based on ASCII code.
Digit control function
: Automatically turns on column output OUTC0 to OUTC4 in sequence.
Maximum transmission frequency (for serial data transmission)
: fCLK = 15 MHz
Row output (OUTR0 to OUTR6)
Output current can be set to 50 mA using an external resistor.
Constant current tolerance (Ta = 25°C, VDD = 5.0 V)
: Variation between bits = ±7%, variation between devices (including variation between bits)
= ±15%, @VCE 0.7 V
Package
: 24pin SDIP (SDIP24P3001.78)
24pin SSOP (SSOP24P3001.00)
TB62713N
TB62713F
Weight
SDIP24-P-300-1.78: 1.62 g (typ.)
SSOP24-P-300-1.00: 0.32 g (typ.)
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PIN ASSIGNMENT (Top view)
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EQUIVALENT CIRCUIT DIAGRAM / BLOCK DIAGRAM
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PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
1 VDD 5 V power pin.
2 DATAIN (DI) Serial data input pin.
3 CLOCK (CK) Clock input pin. The shift register shifts data on the clock’s rising edge.
4 LOAD (LD)
Load signal input pin. The data in the D8 to D15 bits of the 16bit shift register.
A
re read on the rising edge of the load signal and the current load register is selected from
among the Duty Register, the Decode & Digit Register, or Data Registers 0 to 3. The D0to
D7 bits contain data corresponding to the same registers just described, which are read on
the load signal’s falling edge.
5~11 OUTR0 to R6 Row output pins. These pins output constant sink current. Connect these pins to the
LED’s cathode.
12 PGND Ground pin for row output.
13 TESTIN2 Product test pin. In normal use, be sure to connect to ground.
14 TESTIN1 Product test pin. In normal use, be sure to connect to ground.
15, 16, 17,
19, 20 OUTC0 to C4 Column output pins. These pins output the VCC pin voltage as a source current output.
Connect these pins to the LED common anodes.
18 VCC Power pin for column output.
21 TESTOUT Product test pin. In normal use, be sure to leave this pin open.
22 REXT Current setting pin for the OUTR0 to OUTR6 pins. Connect a resistor between this pin
and GND when setting the current.
23 DATAOUT (DO) Serial data output pin. Use this pin when TB62713N or TB62713F devices are
cascadeconnected.
24 LGND Ground pin for logic and analog circuits.
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TIMING DIAGRAM
DATA INPUT
Transfer data to the DATAIN pin on every 16bit including address (8 bits) and data (8 bits). After the 16th
clocksignal input following this data transfer, input a load signal from the LD pin.
Input the load signal using an Active High pulse. The register address is set on the rising edge of the load pulse.
On the subsequent falling edge, the data are read as data of the mode of the register.
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DESCRIPTION OF OPERATION
Data input (DATAIN, CLOCK, LOAD)
The data are input serially using the SERIALIN pin. The data input interface consists of a total of three
inputs : SERIALIN, LOAD, and CLOCK.
Binary code stored in the 16bit shift register offers control modes including Duty Control Register Set, Digit
Set, Decode Set and Standby Set.
The data are shifted, starting from the MSB, on the rising edge of the clock. Cascadeconnecting TB62713N or
TB62713F devices provides capability for controlling a larger number of digits extensibility.
The serial data in the 16bit shift register are used as follows : the four bits D15 (MSB) to D12 select the IC
operating mode (Table 1), while bits D11 to D8 select the register corresponding to the operating mode (Table 2).
Bits D7 to D0 (LSB) are used for detail settings such as number of digits in use, character settings in each digit,
and light intensity of these.
The internal registers are loaded on the rising edge of the LOAD signal, which causes loading of data from an
external some into the D15 (MSB) to D8 bits of the shift register, operating mode and the corresponding register
selection data. On the subsequent falling edge, the detail setting data of D7 to D0 (LSB) are loaded.
Normally LOAD is Low. After a serial transfer of 16bits, the input of a Highlevel pulse loads the data.
Note the following caution. Use the D15 to D8 setting and the D7 to D0 detail data setting as a pair. If just the
D7 to D0 data are input without setting D15 to D8 an error condition may result, in which the device will not
operate normally. The register settings will not be normal. If the current mode is set again by a new signal, the
data for D15 to D8 must also be reinput.
Operating precautions
At poweron or after operation in Clear mode (in initial state), the data are reset. If the IC enters Normal mode
after data are input and characters are specified, LEDs are lit according to the input data.
Operating the IC in Blank mode (all lights off) or in All ON mode (all lights lit) does not affect the internal data.
Setting the IC to Normal mode again continues the LED lighting in the state governed by the settings made
immediately before mode change.
Normal mode (not Shut Down, Clear, Blank, or All On mode) continues the operations set in Load Register mode.
In Normal mode, operations are governed by any new settings msde in the Load register, as soon as the changed
setting values are loaded.
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OPERATING MODE SETTINGS
Operating modes (Table 1)
These ICs support the following five operating modes :
1. Blank : Forcibly turns OFF the constantcurrent output both for data and digit setting.
This mode is not affected by the values in bits D11 to D0.
2. Normal : Used for display operations after the settings of the digits are complete.
This mode is not affected by D11 to D0. Note that setting this mode without making
any other settings results in a blank display (all lights off).
3. Load Register : Used for the detail settings of the Duty Control Register and for inputting display data.
D
11 to D0 of the shift register are used for the detail settings of the digits currently
being driven. (Table 2).
4. All On : Forcibly turns ON the constantcurrent data output. This mode is not affected by
D
11 to D0.
5. Standby : Used to set Standby state (in which internal data are not cleared) and to clear
data (initialization).
The settings in D3 to D0 determine the choice between standby state or initialization.
Table 1 Operating mode settings
REGISTER DATA
D15 D14 D13 D12 D11~D8 D7~D4 D3~D0 HEX CODE
INITIAL
SETTING
BLANK
(OUTn & OUTRn ALLOFF) 0 0 0 0 0−−−H
NORMAL (OPERATION) 0 0 0 1 1−−−H
LOAD REGISTER
(DUTY & CHARACTERDATA) 0 0 1 0 X X X 2XXXH
ALL ON (OUTCn ALL ON) 0 0 1 1 3−−−H
STANDBY 0 1 0 0 X 4−−XH
X = Input H or L. ” = Are not affected by the truth table.
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LOAD REGISTER SELECTION
Load Register Selection modes (Table 2)
These modes select the register to provide the data to control the IC operation. The Load Register selection
mode is determined by the settings of D15 to D12 and D11 to D8 of the shift register
1. Duty Register : Sets the digit output duty cycle. Duty Settings can be made in 16 steps from
0 / 16 to 15 / 16. (Table 3)
2. Data Register : Sets 7 × 5 display characters. D7 to D0 are used to set the display characters.
Table 2 Load register selection
REGISTER DATA
D15~D12 D11 D10 D9 D8 D7~D4 D3~D0 HEX CODE
LOAD DUTY REGISTER 2H 0 0 0 0 X X 20XXH
LOAD CHARACTERDATA
REGISTER 2H 0 0 0 1 X X 21XXH
X = Input H or L.
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DUTY CONTROL REGISTER SETTINGS
Duty Control Register detail settings and operation (Table 3)
Writing 20H to D15~D8 and writing 0~FH to D3~D0 sets the duty cycle shown in the following table for the
digitside source driver output. The duty cycle can be set in 16 steps.
The initial setting is 15 / 16. After Data Clear, the setting is also 15 / 16.
The current settings remain in force until changed (to the initial state, Data Clear state, standby state, or by
reset execution).
Table 3 Duty control register settings
REGISTER DATA
DUTY CYCLE D15~D8 D7~D4 D3 D2 D1 D0 HEX CODE
INITIAL
SETTING
0 / 16 20H 0 0 0 0 20X0H
1 / 16 20H 0 0 0 1 20X1H
2 / 16 20H 0 0 1 0 20X2H
3 / 16 20H 0 0 1 1 20X3H
4 / 16 20H 0 1 0 0 20X4H
5 / 16 20H 0 1 0 1 20X5H
6 / 16 20H 0 1 1 0 20X6H
7 / 16 20H 0 1 1 1 20X7H
8 / 16 20H 1 0 0 0 20X8H
9 / 16 20H 1 0 0 1 20X9H
10 / 16 20H 1 0 1 0 20XAH
11 / 16 20H 1 0 1 1 20XBH
12 / 16 20H 1 1 0 0 20XCH
13 / 16 20H 1 1 0 1 20XDH
14 / 16 20H 1 1 1 0 20XEH
15 / 16 20H 1 1 1 1 20XFH
X = Input H or L. ” = Are not affected by the truth table.
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STANDBY MODE SETTINGS
Standby mode settings and operation (Table 4)
Writing 4H to D15~D8 and writing 0001 to D3~D0 sets Standby mode. Writing 4H to D15~D8 and writing 0001
to D3D0 sets All Data Clear mode.
Standby mode maintains the settings made immediately before this mode came in force, turns the output
current OFF, and controls the bias current the internal circuits. Resets all settings to their initial states.
Table 7 Standby mode settings
REGISTER DATA
D15~D8 D7~D4 D3 D2 D1 D0 HEX CODE
STANDBY (NO DATA CLEAR) 4H 0 0 0 0 4XX0H
ALL DATA CLEAR 4H 0 0 0 1 4XX1H
X = Input H or L. = Are not affected by the truth table.
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Character (ASCII) genetator decoding
As the following table show,the characters are decoded using combinations of the data in D0 to D7.
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DATA INPUT
(Example 1: Displays A to G, blinks F and G, and adjusts luminance.)
STEP D15
~D12
D11
~D8
D7
~D4
D3
~D0
OUTR0~R6OUTC0~C4MODE DISPLAY
INFORMATION
0 OFF OFF At poweron
(= CLEAR MODE) ALL BLANK
1 0010 0000 XXXX 1111 OFF OFF DUTY = 15 / 16 ALL BLANK
2 0010 0001 0100 0001 OFF OFF CHARACTERDATA = A ALL BLANK
3 0001 XXXX XXXX XXXX OFF ON NORMAL A
4 0010 0001 0100 0010 ON ON CHARACTERDATA = B B
5 0010 0001 0100 0011 ON ON CHARACTERDATA = C C
6 0010 0001 0100 0100 ON ON CHARACTERDATA = D D
7 0010 0001 0100 0101 ON ON CHARACTERDATA = E E
8 0010 0000 0100 0110 ON ON CHARACTERDATA = F F
9 0000 XXXX XXXX XXXX OFF OFF BLANK ALL BLANK
10 0010 0000 XXXX 1000 OFF OFF DUTY = 8 / 16 ALL BLANK
11 0001 XXXX XXXX XXXX ON ON NORMAL F (MIDDLE BLIGHT)
11 0000 XXXX XXXX XXXX OFF OFF BLANK ALL BLANK
12 0010 0000 0100 0111 ON OFF CHARACTERDATA = G ALL BLANK
13 0001 XXXX XXXX XXXX ON ON NORMAL G (MIDDLE BLIGHT)
15 0100 XXXX XXXX 0000 OFF OFF STANDBY
(SHUT DOWN) ALL BLANK
STATE TRANSITION DIAGRAM
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ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage for Logic Circuits VDD 7.0 V
Supply Voltage VCC 17 V
OUTC0 to OUTC3 Output Current ICO 420 mA
OUTR0 to OUTR6 Output Current IRO 60 mA
Output Current for Logic Block IOH / IOL ±5 mA
Input Voltage VIN 0.3~VDD+0.3 V
Operating Frequency fCK 15.0 MHz
Total Supply Current IVDD 420 mA
TB62713N 1.78
Power Dissipation
TB62713F
PD 0.62
W
Operating Temperature Topr 40~85 °C
Storage Temperature Tstg 55~150 °C
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, VDD = 5.0 V, VCC = 5.0 V, REXT = 580 , Ta = 40 to 85°C)
CHARACTERISTIC SYMBOL
TEST
CIR
CUIT
TEST CONDITION MIN TYP. MAX UNIT
ICC1 1
SET NORMAL OPE. MODE,
REXT = 590 @OUTR0~R6
ALL ON, Ta = 25°C
370
Perating Power Supply Current for
Output Block
ICC2 1
SET NORMAL OPE. MODE,
REXT = 590 @OUTR0~R6
ALL ON, VCC = 12 V, Ta = 25°C
390
mA
OUTC0 to OUTC4 Scan
Frequency fOSC 2 NORMAL OPE. MODE,
VDD = 4.5~5.5 V 300 600 1200 Hz
OUTR0 to OUTR6 Output Sink
Current IRO 3 NORMAL OPE. MODE,
VCE = 0.7 V, REXT = 590 36.5 43.0 49.4 mA
OUTC0 to C4 Output Leakage
Current Ileak1 4 ALL OFF MODE, VCC = 17 V 20 µA
OUTR0 to R6 Output Leakage
Current Ileak2 4 ALL OFF MODE, VCC = 17 V 20 µA
OUTC0 to C4 Output Voltage VOUT 5 NORMAL OPE. MODE,
IOUTCn = 350 mA 3.0 V
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Logic block
CHARACTERISTIC SYMBOL
Test
Cir
cuit
TEST CONDITION MIN TYP. MAX UNIT
IDD1 6 STANDBY MODE, Ta = 25°C 200 µA
Static Power Supply Current for
Logic Circuits IDD2 6 BLANK MODE, Ta = 25°C 12.5 mA
Operating Power Supply Current for
Logic Circuits IDD3 6
NORMAL OPE. MODE,
fCLK = 10 MHz,
DATAIN : OUTR0~R6 = ON,
Ta = 25°C
20.5 mA
High Input Current for Logic Circuits IIH DATAIN, LOAD & CLOCK :
VIN = 5 V 1 µA
Low Input Current for Logic Circuits IIL DATAIN, LOAD & CLOCK :
VIN = 0 V 1 µA
VOH1 6 DATAOUT, IOH = 1.0 mA 4.6
High Output Voltage for Logic
Circuits VOH2 6 DATAOUT, IOH = 1.0 µA V
DD
V
VOL1 6 DATAOUT, IOL = 1.0 mA 0.4
Low Output Voltage for Logic Circuits
VOL2 6 DATAOUT, IOH = 1.0 µA 0.1
V
Clock Frequency fCLK 6 CASCADE CONNECTED,
Ta = 40~85°C 10 MHz
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SWITCHING CHARACTERISTICS
(Unless otherwise stated, VDD = 5.0 V, VCC = 5.0 V, Ta = 25°C)
CHARACTERISTIC SYMBOL
Test
Cir
cuit
TEST CONDITION MIN TYP. MAX UNIT
Data Hold Time (DINCLOCK) tDHO 10 ns
Data Setup Time (DINCLOCK) tDST 20 ns
Serial Output Delay Time
(CLOCKDOUT) tPDSO C
L = 10 pF 25 ns
High Clock Pulse Width tCKH 30 ns
Low Clock Pulse Width tCKL 30 ns
Load Pulse Width twLD 100 ns
Load Clock Time (CLOCKLOAD) tCLKLD 50 ns
Clock Load Time (LOADCLOCK) tLDCLK 50 ns
OUTC0 to OUTC6 Output Delay Time
(LOADOUTCn) tPD CO C
L = 10 pF 5.0 µs
OUTC0 to OUTC6 Output Rise
Time(OUTCn) tr CO C
L = 10 pF 0.2 1.0 µs
OUTC0 to OUTC6 Output Fall Time
(OUTCn) tf CO C
L = 10 pF 0.2 1.0 µs
OUTR0 to OUTR4 Output Delay Time
(LOADOUTRn) tPD RO C
L = 10 pF 10.0 µs
OUTR0 to OUTR4 Output Rise Time
(OUTRn) tr RO C
L = 10 pF 0.4 2.0 µs
OUTR0 to OUTR4 Output Fall Time
(OUTRn) tf RO CL = 10 pF 0.4 2.0 µs
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RECOMMENDED OPERATING CONDITIONS
(Unless otherwise stated, VDD = 5.0 V, VCC = 5.0 V, Ta = 40 to 85°C)
CHARACTERISTIC SYMBOL
Test
Cir
cuit
TEST CONDITION MIN TYP. MAX UNIT
Supply Voltage for Output Block VCC 4.0 15.0 V
OUTR0 to R4 Output Source Current ICO V
OUT = 3.0 V 280 mA
OUTC0 to C6 Output Sink Current IRO V
CE = 0.7 V 50 mA
Logic block
CHARACTERISTIC SYMBOL
Test
Cir
cuit
TEST CONDITION MIN TYP. MAX UNIT
Supply Voltage for Logic Block VDD 4.5 5.5 V
High Input Current for Logic Circuits IIH DATAIN, LOAD & CLOCK,
VIN = VDD
1 µA
Low Input Current for Logic Circuits IIL DATAIN, LOAD & CLOCK,
VIN = 0 V 1 µA
High Input Voltage for Logic Circuits VIH 0.7
VDD
V
Low Input Voltage for Logic Circuits VIL 0.3
VDD V
SWITCHING CONDITIONS
CHARACTERISTIC SYMBOL
Test
Cir
cuit
TEST CONDITION MIN TYP. MAX UNIT
Data Hold Time (DINCLOCK) tDHO 30 ns
Data Setup Time (DINCLOCK) tDST 50 ns
Serial Output Delay Time
(CLOCKDOUT) tPDSO C
L = 10 pF 50 ns
High Clock Pulse Width tCKH 30 ns
Low Clock Pulse Width tCKL 30 ns
Load Pulse Width twLD 150 ns
Load Clock Time (CLOCKLOAD) tCLKLD 100 ns
Clock Load Time (LOADCLOCK) tLDCLK 100 ns
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TEST CIRCUITS
(1) ICC1, ICC2
(2) fOSC
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(3) ISEG
(4) Ileak1, Ileak2
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(5) VOUT
(6) IDD1, IDD2, IDD3, VOH1, VOH2, VOL1, VOL2, fCLK
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EXTERNAL RESISTANCE AND OUTPUT CURRENT VALUES
The following diagram shows the application circuit.
Because operation may be unstable due to influences such as the electromagnetic induction of the wiring, the IC
should be located as close as possible to the LED.
The LGND and PGND of this IC are connected to the substrate in the IC.
Take care to avoid a potential difference exceeding 0.4 V at two pins.
When executing the pattern layout, Toshiba recommends not including inductance components in the GND or
output pin lines, and not inserting capacitance components exceeding 50 pF between the REXT pin and GND.
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APPLICATION CIRCUIT EXAMPLE (Connection example)
PRECAUTIONS for USING
Utmost care is necessary in the design of the output line, VCC (VDD) and GND (LGND, PGND) line since IC
may be destroyed due to shortcircuit between outputs, air contamination fault, or fault by improper
grounding.
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Package Dimensions
Weight: 1.62 g (typ.)
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Package Dimensions
Weight: 0.32 g (typ.)
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only.
Thorough evaluation is required, especially at the mass production design stage.
Toshiba does not grant any license to any industrial property rights by providing these examples of
application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
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IC Usage Considerations
Notes on Handling of ICs
(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
(2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in
case of over current and/or IC failure. The IC will fully break down when used under conditions that
exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal
pulse noise occurs from the wiring or load, causing a large current to continuously flow and the
breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of
breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are
required.
(3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current resulting from the inrush
current at power ON or the negative current resulting from the back electromotive force at power OFF.
IC breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable,
the protection function may not operate, causing IC breakdown. IC breakdown may cause injury,
smoke or ignition.
(4) Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and
exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
In addition, do not use any device that is applied the current with inserting in the wrong orientation
or incorrectly even just one time.
(5) Carefully select external components (such as inputs and negative feedback capacitors) and load
components (such as speakers), for example, power amp and regulator.
If there is a large amount of leakage current such as input or negative feedback condenser, the IC
output DC voltage will increase. If this output voltage is connected to a speaker with low input
withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause
smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied
Load (BTL) connection type IC that inputs output DC voltage to a speaker directly.
Points to Remember on Handling of ICs
(1) Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the
device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at
any time and condition. These ICs generate heat even during normal use. An inadequate IC heat
radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In
addition, please design the device taking into considerate the effect of IC heat radiation with
peripheral components.
(2) Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to
the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power
supply is small, the device’s motor power supply and output pins might be exposed to conditions
beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in
system design.
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RESTRICTIONS ON PRODUCT USE 060116EBA
The information contained herein is subject to change without notice. 021023_D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc. 021023_A
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk. 021023_B
The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others. 021023_C
The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E