FEATURES
PMC
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev:1.4
Pm49FL002 / Pm49FL004
1
• Single Power Supply Operation
- Low voltage range: 3.0 V - 3.6 V
• Standard Intel Firmware Hub/LPC Inter-
face
- Read compatible to Intel® 82802 Firmware
Hub devices
- Conforms to Intel LPC Interface Specification
Revision 1.1
• Memory Configuration
-Pm49FL002: 256K x 8 (2 Mbit)
- Pm49FL004: 512K x 8 (4 Mbit)
•Cost Effective Sector/Block Architecture
-Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
-Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
•T op Boot Block
-Pm49FL002: 16 Kbyte top Boot Block
- Pm49FL004: 64 Kbyte top Boot Block
•Automatic Erase and Program Operation
-Build-in automatic program verification for
extended product endurance
-T ypical 25 µs/byte programming time
- T ypical 50 ms sector/block/chip erase time
•Two Configurable Interfaces
-In-System hardware interface: Auto detection
of Firmware Hub (FWH) or Low Pin Count
(LPC) memory cycle for in-system read and
write operations
- Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
•Firmware HUB (FWH)/Low Pin Count
(LPC) Mode
- 33 MHz synchronous operation with PCI bus
-5-signal communication interface for in-
system read and write operations
- Standard SDP Command Set
- Data# Polling and T oggle Bit features
- Register-based read and write protection for
each block (FWH mode only)
- 4 ID pins for multiple Flash chips selection
(FWH mode only)
- 5 GPI pins for General Purpose Input Register
- TBL# pin for hardware write protection to Boot
Block
- WP# pin for hardware write protection to whole
memory array except Boot Block
•Address/Address Multiplexed (A/A Mux)
Mode
- 1 1-pin multiplexed address and 8-pin data I/O
interface
- Supports fast programming on EPROM
programmers
- Standard SDP Command Set
- Data# Polling and T oggle Bit features
•Lower Power Consumption
-T ypical 2 mA active read current
- Typical 7 mA program/erase current
•High Product Endurance
-Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
•Compatible Pin-out and Packaging
-32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
•Hardware Data Protection
PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
2
GENERAL DESCRIPTION
The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 V olt-only Flash Memories used as BIOS in PCs and Notebooks. These
devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in-
system or off-system read, erase and program operations. The 12.0 V olt VPP power supply are not required for the
program and erase operations of devices. The devices conform to Intel® Low Pin Count (LPC) Interface specification
revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applica-
tions. The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic
detect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed
(A/A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both
Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great
flexibility and simplicity for design, procurement, and material inventory .
The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector
group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors,
or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature
allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase
operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one
single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera-
tion.
The program operation of Pm49FL002/004 is executed by issuing the program command code into command
register . The internal control logic automatically handles the programming voltage ramp-up and timing. The erase
operation of the devices is executed by issuing the sector, block, or chip erase command code into command
register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming
on the array which has not been programmed is not required before an erase operation. The devices offer Data#
Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and
erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6.
The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The
Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled
by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The
rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers
(FWH mode only).
The Pm49FL002/004 are manufactured on PMC’s advanced nonvolatile technology , P-FLASH™. The devices are
offered in 32-pin VSOP and PLCC packages with optional environmental friendly lead-free package.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
3
CONNECTION DIAGRAMS
20
19
18
1716
15
14
5
6
7
8
9
10
11
12
13
1234323130
A8
A9
RST#
V
CC
R/C#
A10
I/O1
GND
I/O2
I/O3
I/O4
I/O5
I/O6
I/O0
A0
A1
A2
A3
A4
A5
A6
A7 29
28
27
26
25
24
23
22
21
IC
GND
NC
V
CC
OE#
WE#
I/O7
INIT#
RES
IC
LAD1
GND
RES
FWH1
GND
LAD0
RES
TBL#
WP#
GPI1
FWH0
ID0
GPI1
GPI2
GPI3
V
CC
CLK
GPI4
NC NC
GPI2
GPI3
V
CC
CLK
RST#
GPI4
NC
A/A Mux LPC FWH
FWH LPC A/A Mux
RST#
GND GND
NC
NC
NC NC
NC
V
CC
V
CC
INIT#
LFRAME# FWH4
NC NC
NC
RES
LAD2FWH2
LAD3
FWH3
RES
RES
RES
RES
RES
GPI0
GPI0
WP#
TBL#
RES
RES
RES
ID1
ID2
ID3
IC
A/A Mux LPC FWH
FWH LPC A/A Mux
OE# INIT# INIT#
WE# LFRAME# FWH4
NC NC NC
I/O7 RES RES
I/O6 RES RES
I/O5 RES RES
I/O4 RES RES
I/O3 LAD3 FWH3
G N D GND GND
I/O2 LAD2 FWH2
I/O1 LAD1 FWH1
I/O0 LAD0 FWH0
A0 RES ID0
A1 RES ID1
A2 RES ID2
A3 RES ID3
V
CC
V
CC
V
CC
NC NC NC
NC NC NC
GND GND GND
IC IC IC
GPI4 GPI4 A10
CLK CLK R/C#
V
CC
V
CC
V
CC
NC NC NC
RST# RST# RST#
GPI3 GPI3 A9
GPI2 GPI2 A8
GPI1 GPI1 A7
GPI0 GPI0 A6
WP# WP# A5
TBL# TBL# A4
32-PIN (8mm x 14mm) VSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A/A Mux LPC FWH
FWH LPC A/A Mux
32-PIN PLCC
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
4
PRODUCT ORDERING INFORMATION
Pm49FL00x T -33 J C E
Temperature Range
C = Commercial (0°C to +70°C)
Package Type
J = 32-pin Plastic J-Leaded Chip Carrier (32J)
V = 32-pin (8 mm x 14 mm) VSOP (32V)
Speed Option
Boot Block Location
T = Top Boot Block
PMC Device Number
Pm49FL002 (2 Mbit)
Pm49FL004 (4 Mbit)
rebmuNtraPzHM kcolBtooB noitacoL egakcaP erutarepmeT egnaR
ECJ33-T200LF94mP
33poT
J23 laicremmoC )C°07+otC°0(
CJ33-T200LF94mP
ECV33-T200LF94mP V23
CV33-T200LF94mP
ECJ33-T400LF94mP
33poT
J23 laicremmoC )C°07+otC°0(
CJ33-T400LF94mP
ECV33-T400LF94mP V23
CV33-T400LF94mP
Environmental Attribute
E = Lead-free (Pb-free) Package
Blank = Standard Package
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
5
PIN DESCRIPTIONS
LOBMYSEPYT ecafretnI NOITPIRCSED
PPHWFCPL
]0:01[AIX nisdnammocdnasesserddaxelpitlumehtgnitupniroF:stupnIsserddA rodaeragniruddehctalerasesserddanmulocdnawoR.edomPP .nip#C/Rybdellortnocelcycetirw
#C/RIX PPnisserddanmulocroworehtetacidnioT:tceleSnmuloC/woR sihtnehW.dehctalsisserddaworeht,wolseognipsihtnehW.edom .dehctalsisserddanmuloceht,hgihseognip
]0:7[O/IO/IX tupniot,ylnoedomxuMA/ArofdesU:stuptuO/stupnIataD daergnirudatadtuptuootdnanoitarepoetirwgnirudatad/dnammoc .delbasidsi#EOnehwetats-irtottaolfsnipatadehT.noitarepo
#EWIX .wolevitcasi#EW.noitarepoetirwrofecivedehtetavitcA:elbanEetirW
#EOIX .elcycdaeragnirudsreffubtuptuos'ecivedehtlortnoC:elbanEtuptuO .wolevitcasi#EO
CI I XXX
siedomhcihwsenimretednipsihT:tceleSnoitarugifnoCecafretnI nehW.edomxuMA/Aotnisretneecivedeht,hgihsllupnehW.detceles gnirudputesebtsumnipsihT.detcelessiedomCPL/HWF,wolsllup sihT.noitarepognirudegnahconsyatsdna,tesermetsysropu-rewop K001-02neewtebrotsiserahtiwnwoddellupyllanretnisinip .Ω
#TSR I XXX .edomybdnatsotnruterdnaecivedehtfonoitarepoehtteseroT:teseR
#TINIIXX nip#TSRro#TINI.esumetsys-nirofnipteserdnocesasisihT:ezilaitinI .teserecivedaetaitinilliwwolsllup
]0:4[IPGIXX
rofGER_IPGehttesotdesU:stupnIesopruPlareneGCPL/HWF daerebnacGER_IPGfoeulavehT.ylnoesoprupngisedmetsys etatsderisedtatesebdluohssnipesehT.ecafretniHWFhguorht dluohsdnanoitarepodaerrofelcyckcolcICPehtfotratsehterofeb tsumsnipIPGdesunU.elcycdaerehtfodneehtlitnuegnahconniamer .detaolfebton
#LBTIXX noitcetorpetirwerawdrahehtselbaneti,wolsllupnehW:kcoLkcolBpoT etirwerawdrahehtselbasidti,hgihsllupnehW.kcolbtoobpotrof .noitcetorp
#PWIXX noitcetorpetirwerawdrahehtselbaneti,wolsllupnehW:tcetorPetirW ti,hgihsllupnehW.kcolbtoobpotehttpecxeyarrayromemehtot .noitcetorpetirwerawdrahselbasid
]0:3[HWFO/IX ,atadgnittimsnartrofsnipO/IrojamehT:ataDdnasserddAHWF .edomHWFniedocdnammocdnasesserdda
4HWFIX .noitarepoelcycyromemHWFafotratsehtetacidnioT:tupnIHWF .ssergorpnielcycyromemWHFatrobaotdesuoslA
]0:3[DALO/IX ,atadgnittimsnartrofsnipO/IrojamehT:ataDdnasserddACPL .edomCPLniedocdnammocdnasesserdda
#EMARFLI X .noitarepoelcycyromemCPLafotratsehtetacidnioT:emarFCPL .ssergorpnielcycyromemCPLatrobaotdesuoslA
KLCIXX CPLdnaHWFrofkcolcsuonorhcnysaedivorpoT:kcolCCPL/HWF .snoitarepoedom
]0:3[DIIX
tahtmsinahcemehtfotraperasnipruofesehT:stupnInoitacifitnedI ehT.subemasehtotdehcattaebotsecivedHWFelpitlumswolla toobehT.tnenopmocehtyfitnediotdesusisnipesehtfognipparts llatahtdednemmocersitidnab0000=]0:3[DIevahtsumecived esehT.gnippartstnuoc-pulaitneuqesesudluohssecivedtneuqesbus K001-02neewtebrotsiserahtiwnwod-dellupyllanretnierasnip .Ω
V
CC
XXX ylppuSrewoPeciveD
DNG XXX dnuorG
CN XXX noitcennoCoN
SERXX .esuerutufrofsnipnoitcnufdevreseR:devreseR
Note: I = Input, O = Output
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
6
DEVICE OPERATION
MODE SELECTION
The Pm49FL002/004 can operate in two configurable
interfaces: The In-System Hardware interface and Ad-
dress/Address Multiplexed (A/A Mux) interface con-
trolled by IC pin. If the IC pin is set to logic high (VIH),
the devices enter into A/A Mux interface mode. If the IC
pin is set logic low (VIL), the devices will be in in-system
hardware interface mode. During the in-system hard-
ware interface mode, the devices can automatically de-
tect the Firmware Hub (FWH) or Low Pin Count (LPC)
memory cycle sent from host system and response to
the command accordingly. The IC pin mus t be setup
during power-up or system reset, and stays no change
during device operation.
When working in-system, typically on a PC or Note-
book, the Pm49FL002/004 are connected to the host
system through a 5-pin communication interface oper-
ated based on a 33-MHz synchronous clock. The 5-pin
interface is defined as FWH[3:0] and FWH4 pins under
FWH mode or as LAD[3:0] and LFRAME# pins under
LPC mode for easy understanding as to those existing
compatible products. When working off-system, typi-
cally on a EPROM Programmer , the devices are oper-
ated through 11-pin multiplexed address - A[10:0] and
8-pin data I/O - I/O[7:0] interfaces. The memory ad-
dresses of devices are input through two bus cycles as
row and column addresses controlled by a R/C# pin.
BLOCK DIAGRAM
WE#
OE#
PP MODE
INTERFACE CONTROL
LOGIC
A[10:0]
ERASE/PROGRAM
VOLTAGE
GENERATOR
HIGH VOLTAGE
SWITCH
I/O[7:0]
I/O BUFFERS
DATA
LATCH SENSE
AMP
Y-GATING
MEMORY
ARRAY
ADDRESS
LATCH
Y-DECODER
X-DECODER
R/C#
FWH/LPC
MODE
INTERFACE
FWH[3:0] or
LAD[3:0]
CLK
FWH4 or LFRAME#
GPI[4:0]
WP#
TBL#
INIT#
RST#
IC
noitpircseDsserddAataD
DIrerutcafunaM h00000 h20000 hD9 hF7
DIeciveD 200LF94mP 400LF94mP bM2 bM4 h10000hD6 hE6
Table 1: Product Identification
PRODUCT IDENTIFICA TION
The product identification mode can be used to read the
Manufacturer ID and the Device ID by a software Prod-
uct ID Entry command in both in-system hardware in-
terface and A/A Mux interface modes. The product
indentification mode is activated by three-bus-cycle com-
mand. Refer to Table 1 for the Manufacturer ID and De-
vice ID of Pm49FL00x and Table 14 for the SDP Com-
mand Definition.
In FWH mode, the product identification can also be
read directly at FFBC0000h for Manufacturer ID - “9Dh”
and FFBC0001h for Device ID in the 4 GByte system
memory map.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
7
The Pm49FL002/004 provide three levels of data protec-
tion for the critical BIOS code of PC and Notebook. It
includes memory hardware write protection, hardware
data protection and software data protection.
MEMORY HARDWARE WRITE PROTECTION
The Pm49FL002 has a 16 Kbyte top boot block and the
Pm49FL004 has a 64 Kbyte top boot block. When work-
ing in-system, the memory hardware write protection fea-
ture can be activated by two control pins - Top Block
Lock (TBL#) and Write Protection (WP#) for both FWH
and LPC modes. When TBL# is pulled low (VIL), the boot
block is hardware write protected. A sector erase, block
erase, or byte program command attempts to erase or
program the boot block will be ignored. When WP# is
pulled low (VIL), the Block 0 ~ Block 14 of Pm49FL002,
or the Block 0 ~ Block 6 of Pm49FL004 (except the boot
block) are hardware write protected. Any attemp to erase
or program a sector or block within this area will be ig-
nored.
Both TBL# and WP# pins must be set low (VIL) for pro-
tection or high (VIH) for un-protection prior to a program
or erase operation. A logic level change on TBL# or WP#
pin during a program or erase operation may cause un-
predictable results.
The TBL# and WP# pins work in combination with the
block locking registers. When active, these pins write
protect the appropriate blocks regardless of the associ-
ated block locking registers setting.
HARDWARE DA TA PROTECTION
Hardware data protection protects the devices from un-
intentional erase or program operation. It is performed
by the devices automatically in the following three ways:
(a) VCC Detection: if VCC is below 1.8 V (typical), the
program and erase functions are inhibited.
(b) Write Inhibit Mode: holding any of the signal OE#
low, or WE# high inhibits a write cycle (A/A Mux mode
only).
(c) Noise/Glitch Protection: pulses of less than 5 ns (typi-
cal) on the WE# input will not initiate a write cycle (A/A
Mux mode only).
DEVICE OPERATION (CONTINUED)
SOFTWARE DAT A PROTECTION
The devices feature a software data protection function
to protect the device from an unintentional erase or pro-
gram operation. It is performed by JEDEC standard Soft-
ware Data Protection (SDP) command sequences. See
Table 14 for SDP Command Definition. A program op-
eration is initiated by three memory write cycles of un-
lock command sequence. A chip (only available in A/A
Mux mode), sector or block erase operation is initiated
by six memory write cycles of unlock command se-
quence. During SDP command sequence, any invalid
command or sequence will abort the operation and force
the device back to standby mode.
BYTE PROGRAMMING
In program operation, the data is programmed into the
devices (to a logical “0”) on a byte-by-byte basis. In FWH
and LPC modes, a program operation is activated by
writing the three-byte command sequence and program
address/data through four consecutive memory write
cycles. In A/A Mux mode, a program operation is acti-
vated by writing the three-byte command sequence and
program address/data through four consecutive bus
cycles. The row address (A10 - A0) is latched on the
falling edge of R/C# and the column address (A21 - A1 1)
is latched on the rising edge of R/C#. The data is latched
on the rising edge of WE#. Once the program operation
is started, the internal control logic automatically handles
the internal programming voltages and timing.
A data “0” can not be programmed back to a “1”. Only
erase operation can convert “0”s to “1”s. The Data# Poll-
ing on I/O7 or Toggle Bit on I/O6 can be used to detect
when the programming operation is completed in FWH,
LPC, and A/A Mux modes.
CHIP ERASE
The entire memory array can be erased by chip erase
operation available under the A/A Mux mode operated
by EPROM Programmer only . Pre-programs the device
is not required prior to the chip erase operation. Chip
erase starts immediately after a six-bus-cycle chip erase
command sequence. All commands will be ignored once
the chip erase operation has started. The Data# Polling
on I/O7 or Toggle Bit on I/O6 can be used to detect the
progress or completion of erase operation. The devices
will return back to standy mode after the completion of
chip erase.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
8
SECTOR AND BLOCK ERASE
The Pm49FL002 contains sixty-four uniform 4 Kbyte sec-
tors, or sixteen uniform 16 Kbyte blocks (sector group -
consists of four adjecent sectors). The Pm49FL004 con-
tains one hundred and twenty-eight uniform 4 Kbyte sec-
tors, or eight uniform 64 Kbyte blocks (sector group -
consists of sixteen adjecent sectors). A sector erase
command is used to erase an individual sector . A block
erase command is used to erase an individual block.
See Table 12 - 13 for Sector/Block Address Tables.
In FWH/LPC mode, an erase operation is activated by
writing the six-byte command sequence through six con-
secutive write memory cycles. In A/A Mux mode, an
erase operation is activated by writing the six-byte com-
mand in six consecutive bus cycles. Pre-programs the
sector or block is not required prior to an erase opera-
tion.
I/O7 DA T A# POLLING
The devices provide a Data# Polling feature to indicate
the progress or the completion of a program or erase
operation in all modes. During a program operation, an
attempt to read the device will result in the complement
of the last loaded data on I/O7. Once the program cycle
is complete, the true data of the last loaded data is valid
on all outputs. During an erase operation, an attempt to
read the device will result a “0” on I/O7. After the erase
cycle is complete, an attempt to read the device will
result a “1” on I/O7.
DEVICE OPERATION (CONTINUED)
I/O6 TOGGLE BIT
The Pm49FL002/004 also provide a T oggle Bit feature to
detect the progress or the completion of a program or
erase operation. During a program or erase operation,
an attempt to read data from the devices will result in I/
O6 toggling between “1” and “0”. When the program or
erase operation is complete, I/O6 will stop toggling and
valid data will be read. Toggle bit may be accessed at
any time during a program or erase operation.
RESET
Any read, program, or erase operation to the devices
can be reset by the INIT# or RST# pins. INIT# and RST#
pins are internally hard-wired and have same function to
the devices. The INIT# pin is only available in FWH and
LPC modes. The RST# pin is available in all modes. It
is required to drive INIT# or RST# pins low during sys-
tem reset to ensure proper initialization.
During a memory read operation, pulls low the INIT# or
RST# pin will reset the devices back to standby mode
and then the FWH[3:0] of FWH interface or the LAD[3:0]
of LPC interface will go to high impedance state. During
a program or erase operation, pulls low the INIT# or RST#
pin will abort the program or erase operation and reset
the devices back to standby mode. A reset latency will
occur before the devices resume to standby mode when
such reset is performed. When a program or erase op-
eration is reset before the completion of such opera-
tion, the memory contents of devices may become
invalid due to an incomplete program or erase opera-
tion.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
9
FWH MODE MEMORY READ/WRITE OPERA TION
In FWH mode, the Pm49FL002/004 are connected
through a 5-pin communication interface - FWH[3:0] and
FWH4 pins to work with Intel® Family of I/O Controller
Hubs (ICH) chipset platforms. The FWH mode also sup-
port JEDEC standard Software Data Protection (SDP)
product ID entry , byte program, sector erase, and block
erase command sequences. The chip erase command
sequence is only available in A/A Mux mode.
The addresses and data are transmitted through the 4-
bit FWH[3:0] bus synchronized with the input clock on
CLK pin during a FWH memory cycle operation. The
address or data on FWH[3:0] bus is latched on the ris-
ing edge of the clock. The pulse of FWH4 pin inserted
for one clock indicates the start of a FWH memory read
or memory write cycle.
Once the FWH memory cycle is started, asserted by
FWH4, a START value “11xxb” is expected by
Pm49FL002/004 as a valid command cycle and is used
to indicates the type of memory cycle (“1101b” for FWH
memory read cycle or “1110b” for FWH memory write
cycle). Addresses and data are transferred to and from
the device decided by a series of “fields”. Field sequences
and contents are strictly defined for FWH memory read
and write operations. Refer to Table 2 and 3 for FWH
Memory Read Cycle Definition and FWH Memory Write
Cycle Definition.
There are 7 clock fields in a FWH memory cycle that
gives a 28 bit memory address A27 - A0 through
FWH[3:0] pins, but only the last five address fields will
be decoded by the FWH devices. The Pm49FL002 de-
codes A17 - A0 with A19 and A18 ignored. The
Pm49FL004 decodes A18 - A0 with A19 ignored. The
address A22 has the special function of directing reads
and writes to the Flash array when A22 = 1 or to the
register space with A22 = 0. The A27 - A23 and A21 -
A20 are don’t care for the devices under FWH mode.
The Pm49FL002/004 are mapped within the top 4 Mbyte
address range devoted to the FWH devices in the 4 Gbyte
system memory space. Please see Table 1 1 for System
Memory Map.
FWH MODE OPERATION
FWH ABORT OPERA TION
The FWH4 signal indicates the start of a memory cycle
or the termination of a cycle in FWH mode. Asserting
FWH4 for one or more clock cycle with a valid START
value on FWH[3:0] will initiate a memory read or memory
write cycle. If the FWH4 is driven low again for one or
more clock cycles during this cycle, this cycle will be
terminated and the device will wait for the ABORT com-
mand “1111b” to release the FWH[3:0] bus. If the abort
occurs during the program or erase operation such as
checking the operation status with Data# Polling (I/O7)
or Toggle Bit (I/O6) pins, the read status cycle will be
aborted but the internal program or erase operation will
not be affected. Only the reset operation initiated by RST#
or INIT# pin can terminate the program or erase opera-
tion.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
10
elcyCkcolCdleiF]0:3[HWFnoitceriDnoitpircseD
1TRATS1011NIyromemafotratsehtetacidniot"b1011":elcyCfotratS .elcycdaer
2LESDI ot0000 1111 NI
.dnopserdluohsecivedHWFhcihwsetacidnI:elcyCtceleSDI neht,snip]0:3[DInoteseulavehtsehctamdleifLESDIehtfI tneuqesbusotdnopserlliwecivedHWFralucitrapeht .sdnammoc
9-3RDDAMIYYYYNI
ehT.sserddayromemtib-82ehtsisihT:selcyCsserddA -tsaeldnatsrifelbbintnacifingis-tsomrefsnartsesserdda dna,tsrif]0:3[HWFno42-72A,.e.i(.tsalelbbintnacifingis .)tsal]0:3[HWFno0A-3A
01EZISMI0000NIroeblliwsetybynamwohsetacidnI:elcyCeziSyromeM ylnox00LF94mPehT.snoitarepoetyb-itlumgnirudderrefsnart .noitarepoetybenorof"b0000"troppus
110RAT1111 nehtNI taolF nehtsubehtnevirdsahHCIletnIehT:0elcyCdnuorA-nruT .subehtstaolfnehtdnas"1"llaottitaolf
211RAT 1111 )taolf( nehttaolF TUO subehtfolortnocsekatecivedehT:1elcyCdnuorA-nruT .elcycsihtgnirud
31CNYSR 0000 )YDAER( TUO tnacifingis-tsaelehtsetacidniecivedHWFehT:cnySydaeR .elcyckcolctxenniydaereblliwetybatadfoelbbin
51-41ATADYYYYTUO tnacifingis-tsaelhtiwderrefsnartatadstib-8ehT:selcyCataD no0O/I-3O/I,.e.i(.tsalelbbintnacifingis-tsomdnatsrifelbbin .)tsal]0:3[HWFno4O/I-7O/Ineht,tsrif]0:3[DAL
610RAT1111 nehtTUO taolF subehtnevirdsahecivedHWFehT:0elcyCdnuorA-nruT .subehtstaolfnehtdnas"1"llaottitaolfneht
711RAT 1111 )taolf( nehttaolF NI subehtfolortnocsemuserHCIletnIehT:1elcyCdnuorA-nruT .elcycsihtgnirud
Table 2: FWH Memory Read Cycle Definition
FWH MODE OPERATION (CONTINUED)
FWH MEMORY READ CYCLE WA VEFORMS
CLK
RST# or INIT#
FWH4
FWH[3:0]
1101b ID[3:0] xxxxb A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b D[3:0] D[7:4] 1101b
Next Start
Memory
Read
Start IDSEL
1 Clock 1 Clock Load Address in 7 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 1 Clock
Data
RSYNC
TAR
Address
x1xxb 1111b Tri-State
2 Clocks
TAR
From Device to HostFrom Host to Device
0000b
IMSIZE
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
11
elcyCkcolCdleiF]0:3[HWFnoitceriDnoitpircseD
1TRATS0111NIyromemafotratsehtetacidniot"b0111":elcyCfotratS .elcycetirw
2LESDI ot0000 1111 NI
.dnopserdluohsecivedHWFhcihwsetacidnI:elcyCtceleSDI neht,snip]0:3[DInoteseulavehtsehctamdleifLESDIehtfI tneuqesbusotdnopserlliwecivedHWFralucitrapeht .sdnammoc
9-3RDDAMIYYYYNI
ehT.sserddayromemtib-82ehtsisihT:selcyCsserddA -tsaeldnatsrifelbbintnacifingis-tsomrefsnartsesserdda dna,tsrif]0:3[HWFno42-72A,.e.i(.tsalelbbintnacifingis .)tsal]0:3[HWFno0A-3A
01EZISMI0000NIroeblliwsetybynamwohsetacidnI:elcyCeziSyromeM ylnox00LF94mPehT.snoitarepoetyb-itlumgnirudderrefsnart .noitarepoetybenorof"b0000"troppus
21-11ATADYYYYNItnacifingis-tsaelhtiwderrefsnartatadstib-8ehT:selcyCataD no0O/I-3O/I,.e.i(.tsalelbbintnacifingis-tsomdnatsrifelbbin .)tsal]0:3[HWFno4O/I-7O/Ineht,tsrif]0:3[DAL
310RAT1111 nehtNI taolF nehtsubehtnevirdsahHCIletnIehT:0elcyCdnuorA-nruT .subehtstaolfnehtdnas"1"llaottitaolf
411RAT 1111 )taolf( nehttaolF TUO subehtfolortnocsekatecivedehT:1elcyCdnuorA-nruT .elcycsihtgnirud
51CNYSR 0000 )YDAER( TUO deviecersahtitahtsetacidniecivedHWFehT:cnySydaeR .dnammocroatadeht
610RAT1111 nehtTUO taolF subehtnevirdsahecivedHWFehT:0elcyCdnuorA-nruT .subehtstaolfnehtdnas"1"llaottitaolfneht
711RAT 1111 )taolf( nehttaolF NI subehtfolortnocsemuserHCIletnIehT:1elcyCdnuorA-nruT .elcycsihtgnirud
Table 3: FWH Memory Write Cycle Definition
FWH MODE OPERATION (CONTINUED)
CLK
RST# or INIT#
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] 1111b Tri-State 0000b
TAR
1110b
Next Start
Memory
Write
Start IDSEL
1 Clock 1 Clock Load Address in 7 Clocks Load Data in 2 Clocks 1 Clock2 Clocks 1 Clock
x1xxb D[7:4]
TAR RSYNCDataAddress
1111b Tri-State
2 Clocks
From Device to HostFrom Host to Device
0000b
IMSIZE
1 Clock
FWH MEMORY WRITE CYCLE WA VEFORMS
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
12
CLK
RST# or INIT#
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
Memory
Write
Cycle IDSEL
1 Clock 1 Clock Load "5555h" in 7 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
0101b 0101b
0101b 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb 1010b 1111b Tri-State 0000b
2nd Start
1 Clock 1 Clock Load "2AAAh" in 7 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0101b
1010b 0101b
0010b 1010b 0000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
3rd Start
1 Clock 1 Clock Load "5555h" in 7 Clocks Load "A0h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
0101b 0101b
0101b 1010b0000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb A[19:16] 1111b Tri-State 0000b
4th Start
1 Clock 1 Clock Load Address in 7 Clocks Load Data in 2 Clocks 1 Clock
2 Clocks
x1xxb
TAR RSYNCDataAddress
D[7:4]
A[15:12] D[3:0]
A[11:8] A[7:4]
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
A[3:1]
RST# or INIT#
RST# or INIT#
RST# or INIT#
IMSIZE
IDSEL IMSIZE
IMSIZE
IDSEL
IDSEL IMSIZE
0000b
1 Clock
1 Clock
1 Clock
1 Clock
FWH BYTE PROGRAM W AVEFORMS
FWH MODE OPERATION (CONTINUED)
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
13
CLK
RST# or INIT#
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
Memory
Write Cycle IDSEL
1 Clock 1 Clock Load "5555h" in 7 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
0101b 0101b
0101b 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
1110b ID[3:0] xxxxb 1010b 1111b Tri-State 0000b
2nd Start
1 Clock 1 Clock Load "2AAAh" in 7 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0101b
1010b 0101b0010b 1010b 0000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb
SA[19:16]
1111b Tri-State 0000b
IDSEL
6th Start
1 Clock 1 Clock Load Sector Address in 7 Clocks Load "30h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0011b0000bxxxxb xxxxb
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b
SA = Sector Address
Internal Erase
Start
1110b ID[3:0] xxxxb 0010b 1111b Tri-State 0000b
IDSEL
5th Start
1 Clock 1 Clock Load "2AAAh" in 7 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
1010b 1010b
0010b 0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
IDSEL
4th Start
1 Clock 1 Clock Load "5555" in 7 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
1010b0101b 0101b0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
IDSEL
3rd Start
1 Clock 1 Clock Load "5555h" in 7 Clocks Load "80h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
0101b 0101b
0101b 0000b 1000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
SA[15:12]
IMSIZE
1 Clock
IDSEL IMSIZE
1 Clock
1 Clock
IMSIZE
1 Clock
IMSIZE
1 Clock
IMSIZE
1 Clock
IMSIZE
FWH SECTOR ERASE W A VEFORMS
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
14
CLK
RST# or INIT#
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
Memory
Write Cycle IDSEL
1 Clock 1 Clock Load "5555h" in 7 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
0101b 0101b
0101b 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
1110b ID[3:0] xxxxb 1010b 1111b Tri-State 0000b
2nd Start
1 Clock 1 Clock Load "2AAAh" in 7 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0101b
1010b 0101b0010b 1010b 0000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
FWH4
FWH[3:0]
CLK
FWH4
FWH[3:0]
1110b ID[3:0] xxxxb
BA[19:16]
1111b Tri-State 0000b
IDSEL
6th Start
1 Clock 1 Clock Load Block Address in 7 Clocks Load "50h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0101b0000bxxxxb xxxxb
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b
BA = Block Address
Internal Erase
Start
1110b ID[3:0] xxxxb 0010b 1111b Tri-State 0000b
IDSEL
5th Start
1 Clock 1 Clock Load "2AAAh" in 7 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
1010b 1010b
0010b 0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
IDSEL
4th Start
1 Clock 1 Clock Load "5555" in 7 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
1010b0101b 0101b0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b
1110b ID[3:0] xxxxb 0101b 1111b Tri-State 0000b
IDSEL
3rd Start
1 Clock 1 Clock Load "5555h" in 7 Clocks Load "80h" in 2 Clocks 1 Clock
2 Clocks
x1xxb xxxxb
TAR RSYNCDataAddress
0000b
0101b 0101b
0101b 0000b 1000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
BA[15:14]
+ xxb
IMSIZE
1 Clock
IDSEL IMSIZE
1 Clock
1 Clock
IMSIZE
1 Clock
IMSIZE
1 Clock
IMSIZE
1 Clock
IMSIZE
FWH BLOCK ERASE WAVEFORMS
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
15
FWH GPI REGISTER READ WA VEFORMS
CLK
RST# or INIT#
FWH4
FWH[3:0]
1101b ID[3:0] xxxxb 0000b 0001b 0000b 0000b 0000b 1111b Tri-State 0000b D[3:0] D[7:4]
TAR
1101b
Next Start
Memory
Read
Cycle IDSEL
1 Clock 1 Clock Load Address "xBC0100h" in 7 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 1 Clock
Data
RSYNC
TARAddress
x0xxb 1100b 1111b Tri-State
2 Clocks
From Device to Host
From Host to Device
IMSIZE
1 Clock
FWH MODE OPERATION (CONTINUED)
FWH BLOCK LOCKING REGISTER READ WA VEFORMS
CLK
RST# or INIT#
FWH4
FWH[3:0]
1101b ID[3:0] xxxxb 0000b 0000b 0000b 0010b 0000b 1111b Tri-State 0000b D[3:0] D[7:4]
TAR
1101b
Next Start
Memory
Read
Cycle IDSEL
1 Clock 1 Clock Load Address "xBx0002h" in 7 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 1 Clock
Data
RSYNC
TARAddress
x0xxb A[19:16] 1111b Tri-State
2 Clocks
From Device to Host
From Host to Device
IMSIZE
1 Clock
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
16
LPC MODE OPERATION
LPC MODE MEMORY READ/WRITE OPERATION
In LPC mode, the Pm49FL002/004 use the 5-pin LPC
interface includes 4-bit LAD[3:0] and LFRAME# pins to
communicate with the host system. The addresses and
data are transmitted through the 4-bit LAD[3:0] bus syn-
chronized with the input clock on CLK pin during a LPC
memory cycle operation. The address or data on LAD[3:0]
bus is latched on the rising edge of the clock. The pulse
of LFRAME# signal inserted for one or more clocks
indicates the start of a LPC memory read or write cycle.
Once the LPC memory cycle is started, asserted by
LFRAME#, a START value “0000b” is expected by the
devices as a valid command cycle. Then a CYCTYPE +
DIR value (“010xb” for memory read cycle or “011xb” for
memory write cycle) is used to indicates the type of
memory cycle. Refer to Table 4 and 5 for LPC Memory
Read and Write Cycle Definition.
There are 8 clock fields in a LPC memory cycle that
gives a 32 bit memory address A31 - A0 through LAD[3:0]
with the most-significant nibble first. The memory space
of Pm49FL002/004 are mapped directly to top of 4 Gbyte
system memory space. See T able 1 1 for System Memory
Map.
The Pm49FL002 is mapped to the address location of
(FFFFFFFFh - FFFC0000h), the A31- A18 must be
loaded with “1” to select and activate the device during a
LPC memory read or write operation. Only A17 - A0 is
used to decode and access the 256 Kbyte memory . The
I/O7 - I/O0 data is loaded onto LAD[3:0] in 2 clock cycles
with least-significant nibble first and most-significant
nibble last.
The Pm49FL004 is mapped to the address location of
(FFFFFFFFh - FFF80000h), the A31- A19 must be
loaded with “1” to select and activate the device during a
LPC memory operation. Only A18 - A0 is used to de-
code and access the 512 Kbyte memory.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
17
elcyCkcolCdleiF]0:3[DALnoitceriDnoitpircseD
1TRATS0000NIyromemCPLafotratsehtsetacidni"b0000":elcyCfotratS .elcyc
2EPYTCYC +RID x010NI
.elcycdaeryromemCPLafoepytehtsetacidnI:epyTelcyC :RID.elcycyromemrof"b10"ebtsum2-3stiB:EPYTCYC si0tiB.daeRrofelcycfoepytehtsetacidni"b0"=1tiB .devreser
01-3RDDAYYYYNI
ehT.sserddayromemtib-23ehtsisihT:selcyCsserddA -tsaeldnatsrifelbbintnacifingis-tsomrefsnartsesserdda 3Adna,tsrif]0:3[DALno82-13A,.e.i(.tsalelbbintnacifingis .)tsal]0:3[DALno0A-
110RAT1111 nehtNI taolF llaotsubehtnevirdsahtespihCehT:0elcyCdnuorA-nruT .subehttaolfnehtdnas"1"
211RAT 1111 )taolf( nehttaolF TUO subehtfolortnocsekatecivedehT:1elcyCdnuorA-nruT .elcycsihtgnirud
31CNYS0000TUO atadfoelbbintnacifingis-tsaelehtsetacidniecivedehT:cnyS .elcyckcolctxenniydaereblliwetyb
51-41ATADYYYYTUO tnacifingis-tsaelhtiwderrefsnartatadstib-8ehT:selcyCataD no0O/I-3O/I,.e.i(.tsalelbbintnacifingis-tsomdnatsrifelbbin .)tsal]0:3[DALno4O/I-7O/Ineht,tsrif]0:3[DAL
610RAT1111 nehtTUO taolF llaotsubehtnevirdsahecivedehT:0elcyCdnuorA-nruT .subehtstaolfnehtdnas"1"
711RAT 1111 )taolf( nehttaolF NI subehtfolortnocsemusertespihCehT:1elcyCdnuorA-nruT .elcycsihtgnirud
Table 4: LPC Memory Read Cycle Definition
LPC MODE OPERATION (CONTINUED)
LPC MEMORY READ CYCLE WA VEFORMS
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
0000b 010Xb 1111b 11b +
A[17:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b D[3:0] D[7:4] 0000b
Next Start
Memory
Read
Cycle
Start
1 Clock 1 Clock Load Address in 8 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 1 Clock
Data
SYNC
TARAddress
1111b 1111b 1111b Tri-State
2 Clocks
TAR
From Device to HostFrom Host to Device
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
18
LPC MODE OPERATION (CONTINUED)
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
0000b 011Xb 1111b A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] 1111b Tri-State 0000b
TAR
0000b
Next Start
Memory
Write
Cycle
Start
1 Clock 1 Clock Load Address in 8 Clocks Load Data in 2 Clocks 1 Clock2 Clocks 1 Clock
1111b 1111b D[7:4]
TAR SYNC
DataAddress
1111b Tri-State
2 Clocks
From Device to HostFrom Host to Device
LPC MEMORY WRITE CYCLE WA VEFORMS
elcyCkcolCdleiF]0:3[DALnoitceriDnoitpircseD
1TRATS0000NICPLafotratsehtetacidniot"b0000":elcyCfotratS .elcycyromem
2EPYTCYC +RID x110NI
.elcycetirwyromemCPLafoepytehtsetacidnI:epyTelcyC :RID.elcycyromemrof"b10"ebtsum2-3stiB:EPYTCYC si0tiB.etirWrofelcycfoepytehtsetacidni"b1"=1tiB .devreser
01-3RDDAYYYYNI
ehT.sserddayromemtib-23ehtsisihT:selcyCsserddA -tsaeldnatsrifelbbintnacifingis-tsomrefsnartsesserdda 3Adna,tsrif]0:3[DALno82-13A,.e.i(.tsalelbbintnacifingis .)tsal]0:3[DALno0A-
21-11ATADYYYYNItnacifingis-tsaelhtiwderrefsnartatadstib-8ehT:selcyCataD no0O/I-3O/I,.e.i(.tsalelbbintnacifingis-tsomdnatsrifelbbin .)tsal]0:3[DALno4O/I-7O/Ineht,tsrif]0:3[DAL
310RAT1111 nehtNI taolF llaotsubehtnevirdsahtespihCehT:0elcyCdnuorA-nruT .subehttaolfnehtdnas"1"
411RAT 1111 )taolf( nehttaolF TUO subehtfolortnocsekatecivedehT:1elcyCdnuorA-nruT .elcycsihtgnirud
51CNYS0000TUO roatadehtdeviecersahtitahtsetacidniecivedehT:cnyS .dnammoc
610RAT1111 nehtTUO taolF llaotsubehtnevirdsahecivedehT:0elcyCdnuorA-nruT .subehtstaolfnehtdnas"1"
711RAT 1111 )taolf( nehttaolF NI subehtfolortnocsemusertespihCehT:1elcyCdnuorA-nruT .elcycsihtgnirud
Table 5: LPC Memory Write Cycle Definition
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
19
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
0000b 011Xb 1111b 0101b 1111b Tri-State 0000b
Memory
Write
Cycle
1st Start
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
0101b 0101b
11xxb 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
LFRAME#
LAD[3:0]
0000b 011Xb 1111b 0010b 1111b Tri-State 0000b
Memory
Write
Cycle
2nd Start
1 Clock 1 Clock Load "2AAAh" in 8 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
1010b 0101b
11xxb 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
LFRAME#
LAD[3:0]
0000b 011Xb 1111b 0101b 1111b Tri-State 0000b
Memory
Write
Cycle
3rd Start
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "A0h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
0101b 0101b
11xxb 1010b0000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
LFRAME#
LAD[3:0]
0000b 011Xb 1111b A[19:16] 1111b Tri-State 0000b
Memory
Write
Cycle
4th Start
1 Clock 1 Clock Load Address in 8 Clocks Load Data in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
D[7:4]A[15:12] D[3:0]A[11:8] A[7:4]
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
A[3:1]
RST# or INIT#
RST# or INIT#
RST# or INIT#
LPC BYTE PROGRAM WAVEFORMS
LPC MODE OPERATION (CONTINUED)
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
20
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
0000b 011Xb 1111b 0101b 1111b Tri-State 0000b
Memory
Write
Cycle
1st Start
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
0101b 0101b
11xxb 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b 011Xb 1111b 0010b 1111b Tri-State 0000b
Memory
Write
Cycle
2nd Start
1 Clock 1 Clock Load "2AAAh" in 8 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
1010b 0101b11xxb 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
0000b 011Xb 1111b
SA[19:16]
1111b Tri-State 0000b
Memory
Write
Cycle
6th Start
1 Clock 1 Clock Load Sector Address in 8 Clocks Load "30h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0011b0000bxxxxb xxxxb
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
xxxxb
SA = Sector Address
Internal Erase
Start
0000b 011Xb 1111b 0010b 1111b Tri-State 0000b
Memory
Write
Cycle
5th Start
1 Clock 1 Clock Load "2AAAh" in 8 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
1010b
1010b 1010b
11xxb 0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b 011Xb 1111b 11xxb 1111b Tri-State 0000b
Memory
Write
Cycle
4th Start
1 Clock 1 Clock Load "5555" in 8 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
1010b0101b 0101b0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0101b
0000b 011Xb 1111b 0101b 1111b Tri-State 0000b
Memory
Write
Cycle
3rd Start
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "80h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
0101b 0101b
11xxb 0000b 1000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
SA[15:12]
LPC SECTOR ERASE W AVEFORMS
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
21
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
0000b 011Xb 1111b 0101b 1111b Tri-State 0000b
Memory
Write
Cycle
1st Start
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
0101b 0101b
11xxb 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b 011Xb 1111b 0010b 1111b Tri-State 0000b
Memory
Write
Cycle
2nd Start
1 Clock 1 Clock Load "2AAAh" in 8 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
1010b 0101b11xxb 1010b 1010b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
CLK
LFRAME#
LAD[3:0]
CLK
LFRAME#
LAD[3:0]
0000b 011Xb 1111b 1111b Tri-State 0000b
Memory
Write
Cycle
6th Start
1 Clock 1 Clock Load Block Address in 8 Clocks Load "50h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
BA[15:14]
+ xxb
0000bxxxxb xxxxb
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
xxxxb
BA = Block Address
Internal Erase
Start
0000b 011Xb 1111b 0010b 1111b Tri-State 0000b
Memory
Write
Cycle
5th Start
1 Clock 1 Clock Load "2AAAh" in 8 Clocks Load "55h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
1010b
1010b 1010b
11xxb 0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0000b 011Xb 1111b 11xxb 1111b Tri-State 0000b
Memory
Write
Cycle
4th Start
1 Clock 1 Clock Load "5555" in 8 Clocks Load "AAh" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
1010b0101b 0101b0101b 0101b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
0101b
0000b 011Xb 1111b 0101b 1111b Tri-State 0000b
Memory
Write
Cycle
3rd Start
1 Clock 1 Clock Load "5555h" in 8 Clocks Load "80h" in 2 Clocks 1 Clock
2 Clocks
1111b 1111b
TAR SyncDataAddress
0101b
0101b 0101b
11xxb 0000b 1000b
Host to Device
1111b Tri-State
TAR
2 Clocks
Device to Host
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
RST# or INIT#
BA[19:16]
LPC BLOCK ERASE WA VEFORMS
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
22
LPC GPI REGISTER READ WA VEFORMS
CLK
RST# or INIT#
LFRAME#
LAD[3:0]
0000b 010Xb 1111b 1100b 0000b 0001b 0000b 0000b 1111b Tri-State 0000b D[3:0] D[7:4]
TAR
0000b
Next Start
Memory
Read
Cycle
Start
1 Clock 1 Clock Load Address "FFBC0100h" in 8 Clocks 2 Clocks 1 Clock Data Out 2 Clocks 1 Clock
Data
SYNC
TARAddress
1111b 1011b 1111b Tri-State
2 Clocks
From Device to Host
From Host to Device
LPC MODE OPERATION (CONTINUED)
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
23
The Pm49FL002/004 have two registers include the Gen-
eral Purpose Inputs Register (GPI_REG - available in
FWH and LPC modes) and the Block Locking Register
(BL_REG - available in FWH mode only). The GPI_REG
can be read at FFBC0100h in the 4 Gbyte system
memory map. And the BL_REG can be read through
FFBx0002h where x = F - 0h. See Table 8 and 9 for the
address of BL_REG.
GENERAL PURPOSE INPUTS REGISTER
The Pm49FL002/004 contain an 8-bit General Purpose
Inputs Register (GPI_REG) available in FWH and LPC
modes. Only Bit 4 to Bit 0 are used in current version
and Bit 7 to Bit 5 are reserved for future use. The
GPI_REG is a pass-through register with the value set
by GPI[4:0] pin during power-up. The GPI_REG is used
for system design purpose only , the devices do not use
this register . This register is read only and can be read
at address location FFBC0100h in the 4 GByte system
memory map through a memory read cycle. Refer to
Table 6 for General Purpose Input Register Definition.
Table 6. General Purpose Inputs Register Definition
tiBemaNtiBnoitcnuF#niPCCLP-23#niPPOSV-23
5:7devreseR--
44IPG4tiBGER_IPG036
33IPG3tiBGER_IPG311
22IPG2tiBGER_IPG421
11IPG1tiBGER_IPG531
00IPG0tiBGER_IPG641
BLOCK LOCKING REGISTERS
The devices support block read-lock, write-lock, and lock-
down features through a set of Block Locking Registers.
Each memory block has an associated 8-bit read/writ-
able block locking register. Only Bit 2 to Bit 0 are used
in current version and Bit 7 to Bit 3 are reserved for future
use. The default value of BL_REG is “01h” at power up.
The definition of BL_REG is listed in Table 7. The FWH
Register Configuration Map of Pm49FL002 is shown in
Table 8. The FWH Register Configuration Map of
Pm49FL004 is shown in Table 9. Unused register will be
read as 00h.
REGISTERS
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
24
Table 7. Block Locking Register Definition
tiBnoitcnuF
3:7 devreseR
2kcoL-daeR .teserehwkcolbehtnisnoitarepodaerstneverP="1" .etatstluafeD.raelcerehwkcolbehtnisdaerrofnoitarepolamroN="0"
1
nwoD-kcoL -kcoL.stibkcoL-daeRdnakcoL-etirWehtotsnoitareporaelcrotesrehtrufstneverP="1" htiw(teserlitnunwod-dekcolniamerlliwkcolbehT.deraelctontub,tesebnacylnonwoD .teserno-rewopsiecivedehtlitnuro,)#TINIro#TSR .raelcerehwkcolbehtnigniretlatibkcoL-daeRdnakcoL-etirWrofnoitarepolamroN="0" .etatstluafeD
0kcoL-etirW .etatstluafeD.teserehwkcolbehtnisnoitarepoesareromargorpstneverP="1" .raelcerehwkcolbehtniesarednagnimmargorprofnoitarepolamroN="0"
ataD]3:7[tiB2tiB1tiB0tiBetatSkcolBgnitluseR
h0000000000 .sseccalluF
h1000000001 .pu-rewoptaetatstluafeD.dekcoletirW
h2000000010 .)nwoddekcolsseccalluf(nepodekcoL
h3000000011 .nwoddekcol-etirW
h4000000100 .dekcoldaeR
h5000000101 .dekcoletirwdnadaeR
h6000000110 .nwoddekcol-daeR
h7000000111 .nwoddekcol-etirwdnadekcol-daeR
REGISTERS (CONTINUED)
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
25
REGISTERS (CONTINUED)
retsigeR eziSkcolB )setybK( kcolBdetcetorP egnaRsserddA sserddApaMyromeM
KL_KCOLB_T61hFFFF3-h000C3h2008FBFF
KL_10SUNIM_T 616161
hFFFB3-h00083 hFFF73-h00043 hFFF33-h00003 h2000FBFF
KL_20SUNIM_T 6161 hFFFF2-h000C2 hFFFB2-h00082 h2008EBFF
KL_30SUNIM_T 6161 hFFF72-h00042 hFFF32-h00002 h2000EBFF
KL_40SUNIM_T 6161 hFFFF1-h000C1 hFFFB1-h00081 h2008DBFF
KL_50SUNIM_T 6161 hFFF71-h00041 hFFF31-h00001 h2000DBFF
KL_60SUNIM_T 6161 hFFFF0-h000C0 hFFFB0-h00080 h2008CBFF
KL_70SUNIM_T 6161 hFFF70-h00040 hFFF30-h00000 h2000CBFF
T able 8. Pm49FL002 Block Locking Register Address
retsigeR eziSkcolB )setybK( kcolBdetcetorP egnaRsserddA sserddApaMyromeM
KL_KCOLB_T46hFFFF7-h00007h2000FBFF
KL_10SUNIM_T46hFFFF6-h00006h2000EBFF
KL_20SUNIM_T46hFFFF5-h00005h2000DBFF
KL_30SUNIM_T46hFFFF4-h00004h2000CBFF
KL_40SUNIM_T46hFFFF3-h00003h2000BBFF
KL_50SUNIM_T46hFFFF2-h00002h2000ABFF
KL_60SUNIM_T46hFFFF1-h00001h20009BFF
KL_70SUNIM_T46hFFFF0-h00000h20008BFF
T able 9. Pm49FL004 Block Locking Register Address
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
26
A/A MUX MODE OPERA TION
A/A MUX MODE READ/WRITE OPERA TION
The Pm49FL002/004 offers a Address/Address Multi-
plexed (A/A Mux) mode for off-system operation, typi-
cally on an EPROM Programmer , similar to a traditional
Flash memory except the address input is multiplexed.
In the A/A Mux mode, the programmer must drive the
OE# pin to low (VIL) for read or WE# pins to low for write
operation. The devices have no Chip Enable (CE#) pin
for chip selection and activation as traditional Flash
memory . The R/C#, OE# and WE# pins are used to ac-
tivate the device and control the power . The 1 1 multiplex
address pins - A[10:0] and a R/C# pin are used to load
the row and column addresses for the target memory
location. The row addresses (internal address A10 - A0)
Notes:
1. X can be VIL or VIH.
2. Refer to T able 1 for the Manufacturer ID and Device ID of devices.
Table 10. A/A Mux Mode Bus Operation Modes
edoM#TSR#EO#EWsserddAO/I
daeRV
HI
V
LI
V
HI
X
)1(
D
TUO
etirWV
HI
V
HI
V
LI
XD
NI
ybdnatSV
HI
V
HI
V
HI
XZhgiH
elbasiDtuptuOV
HI
V
HI
XX ZhgiH
teseRV
LI
XX X ZhgiH
noitacifitnedItcudorPV
HI
V
LI
V
HI
=12A-2A,X
V=1A
LI
V=0A,
LI
dna
V=1A
HI
V=0A,
HI
DIrerutcafunaM
)2(
,X=12A-2A V=1A
LI
V=0A,
HI
DIeciveD
)2(
are latched on the falling edge of R/C# pin. The column
addresses (internal address A21 - A1 1) are latched on
the rising edge of R/C# pin. The Pm49FL002 uses A17
- A0 internally to decode and access the 256 Kbytes
memory space. The Pm49FL004 use A18 - A0 respec-
tively.
During a read operation, the OE# signal is used to con-
trol the output of data to the 8 I/O pins - I/O[7:0]. During
a write operation, the WE# signal is used to latch the
input data from I/O[7:0]. See Table 10 for Bus Operation
Modes.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
27
SYSTEM MEMORY MAP
System Memory
(Top 4 MBytes)
Pm49FL002
(2 Mbits)
Pm49FL004
(4 Mbits)
Pm49FL008
(8 Mbits)
FFFFFFFFh
FFFC0000h
FFF80000h
FFF00000h
FFC00000h
Range for other
FWH Devices
Table 11. System Memory Map
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
28
T able 12. Pm49FL002 Sector/Block Address Table
MEMORY BLOCKS AND ADDRESSES
erawdraH noitcetorP kcolB eziSkcolB )setybK( rotceS eziSrotceS )setybK( egnaRsserddA
#LBT tooB(51kcolB )kcolB 61
""
hFFFF3-h000C3
#PW
41kcolB61
""
hFFFB3-h00083
31kcolB61
""
hFFF73-h00043
21kcolB61
""
hFFF33-h00003
11kcolB61
""
hFFFF2-h000C2
01kcolB61
""
hFFFB2-h00082
9kcolB61
""
hFFF72-h00042
8kcolB61
""
hFFF32-h00002
7kcolB61
""
hFFFF1-h000C1
6kcolB61
""
hFFFB1-h00081
5kcolB61
""
hFFF71-h00041
4kcolB61
""
hFFF31-h00001
3kcolB61
""
hFFFF0-h000C0
2kcolB61
""
hFFFB0-h00080
1kcolB61
""
hFFF70-h00040
0kcolB61
3rotceS4 hFFF30-h00030
2rotceS4 hFFF20-h00020
1rotceS4 hFFF10-h00010
0rotceS4 hFFF00-h00000
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
29
erawdraH noitcetorP kcolB eziSkcolB )setybK( rotceS eziSrotceS )setybK( egnaRsserddA
#LBT tooB(7kcolB )kcolB 46
""
hFFFF7-h00007
#PW
6kcolB46
""
hFFFF6-h00006
5kcolB46
""
hFFFF5-h00005
4kcolB46
""
hFFFF4-h00004
3kcolB46
""
hFFFF3-h00003
2kcolB46
""
hFFFF2-h00002
1kcolB46
""
hFFFF1-h00001
0kcolB46
51rotceS4 hFFFF0-h000F0
:: :
1rotceS4 hFFF10-h00010
0rotceS4 hFFF00-h00000
Table 13. Pm49FL004 Sector/Block Address T able
MEMORY BLOCKS AND ADDRESSES (CONTINUED)
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
30
COMMAND DEFINITION
Table 14. Software Data Protection Command Definition
dnammoC ecneuqeS suB elcyC
suBts1 elcyC
rddA
)2(
ataD
suBdn2 elcyC ataDrddA
suBdr3 elcyC ataDrddA
suBht4 elcyC ataDrddA
suBht5 eclyC ataDrddA
suBht6 elcyC ataDrddA
daeR1DrddA
TUO
esarEpihC
)1(
6hAAh5555h55hAAA2h08h5555hAAh5555h55hAAA2h01h5555
esarErotceS6hAAh5555h55hAAA2h08h5555hAAh5555h55hAAA2AS
)3(
h03
esarEkcolB6hAAh5555h55hAAA2h08h5555hAAh5555h55hAAA2AB
)4(
h05
margorPetyB4hAAh5555h55hAAA2h0Ah5555DrddA
NI
yrtnEDItcudorP3hAAh5555h55hAAA2h09h5555
tixEDItcudorP
)5(
3hAAh5555h55hAAA2h0Fh5555
tixEDItcudorP
)5(
1h0FhXXXX
Notes:
1. Chip erase is available in A/A Mux Mode only.
2. Address A[15:0] is used for SDP command decoding internally and A15 must be “0” in FWH/LPC and A/A
Mux modes. AMS - A16 = Don’t care where AMS is the most-significant address of Pm49FL00x.
3. SA = Sector address to be erased.
4. BA = Block address to be erased.
5. Either one of the Product ID Exit command can be used.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
31
Start
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data A0h
to
Address 5555h
Load Program
Data to
Program Address
I/O7 = Data?
or
I/O6 Stop Toggle?
Last Address?
Programming
Completed
No
No
Yes
Yes
Address
Increment
DEVICE OPERATIONS FLOWCHARTS
AUTOMATIC PROGRAMMING
Chart 1. Automatic Programming Flowchart
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
32
AUTOMA TIC ERASE
Chart 2. Automatic Erase Flowchart
SECTOR ERASE COMMAND
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
Start
Write Chip, Sector,
or Block
Erase Command
Data = FFh?
or
I/O6 Stop Toggle?
Erasure
Completed
Yes
No
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data 80h
to
Address 5555h
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data 10h
to
Address 5555h
(3)
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data 80h
to
Address 5555h
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data 30h
to
SA
(1,2,3)
Notes:
1. Please see Table 12 to Table 13 for
Sector/Block Address Tables.
2. Only erase one sector or one block per
erase operation.
3. When the TBL# pin is pulled low (VIL),
the boot block will not be erased.
CHIP ERASE COMMAND BLOCK ERASE COMMAND
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data 80h
to
Address 5555h
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data 50h
to
BA
(1,2,3)
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
33
SOFTWARE PRODUCT IDENTIFICATION EXIT
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data 90h
to
Address 5555h
Enter Product
Identification
Mode
(1,2)
Load Data AAh
to
Address 5555h
Load Data 55h
to
Address 2AAAh
Load Data F0h
to
Address 5555h
Exit Product
Identification
Mode
(3)
Load Data F0h
to
Address XXXXh
Exit Product
Identification
Mode
(3)
or
Chart 3. Software Product Identification Entry/Exit Flowchart
SOFTWARE PRODUCT IDENTIFICATION ENTRY
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
Notes:
1. After entering Product Identification Mode, the Manufacturer ID and the Device ID of Pm49FL00x can be read.
2. Product Identification Exit command is required to end the Product Identification mode and return to standby mode.
3. Either Product Identification Exit command can be used, the device returns to standby mode.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
34
saiBrednUerutarepmeT 55-
o
521+otC
o
C
erutarepmeTegarotS 56-
o
051+otC
o
C
erutarepmeTgniredloSdaeLtnuoMecafruS egakcaPdradnatS042
o
sdnoceS3C
egakcaPeerf-daeL062
o
sdnoceS3C
sniPllAnodnuorGottcepseRhtiwegatloVtupnI
)2(
VotV5.0-
CC
V5.0+
dnuorGottcepseRhtiwegatloVtuptuOllA VotV5.0-
CC
V5.0+
V
CC )2(
V0.6+otV5.0-
DC AND AC OPERATING RANGE
rebmuNtraP200LF94mP400LF94mP
erutarepmeTgnitarepO0
o
07otC
o
C0
o
07otC
o
C
ylppuSrewoPccVV6.3-V0.3V6.3-V0.3
ABSOLUTE MAXIMUM RATINGS (1)
Notes:
1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only. The functional operation of the device
or any other conditions under those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating condition for extended periods
may affected device reliability.
2. Maximum DC voltage on input or I/O pins are +6.25 V . During voltage transitioning period,
input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum
DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O
pins may undershoot GND to -2.0 V for a period of time up to 20 ns.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
35
DC CHARACTERISTICS
lobmySretemaraPnoitidnoCniMpyTxaMstinU
I
I
roftnerruCegakaeLtupnI snip]0:3[DI,CI V
NI
VotV0=
CC
V,
CC
V=
xamCC
001Aµ
I
IL
tnerruCegakaeLtupnIV
NI
VotV0=
CC
V,
CC
V=
xamCC
1±Aµ
I
OL
tnerruCegakaeLtuptuOV
O/I
VotV0=
CC
V,
CC
V=
xamCC
1±Aµ
I
BS
VybdnatS
CC
tnerruC )edoMCPL/HWF( V=#EMARFLro4HWF
HI
,
;zHM33=fV
CC
V=
xamCC
005Aµ
I
YR
VedoMydaeR
CC
tnerruC
)edoMCPL/HWF(
V=#EMARFLro4HWF
LI
,
I;zHM33=f
TUO
,Am0=
V
CC
V=
xamCC
01Am
I
1CC
V
CC
tnerruCdaeRevitcA )edoMCPL/HWF(
V=#EMARFLro4HWF
LI
,
I;zHM33=f
TUO
,Am0=
V
CC
V=
xamCC
251Am
I
2CC )1(
V
CC
tnerruCesarE/margorP 702Am
V
LI
egatloVwoLtupnI5.0-V3.0
CC
V
V
HI
egatloVhgiHtupnIV7.0
CC
V
CC
5.0+V
V
LO
egatloVwoLtuptuOI
LO
V,Am0.2=
CC
V=
nimCC
V1.0
CC
V
V
HO
egatloVhgiHtuptuOI
HO
001-= µV,A
CC
V=
nimCC
V9.0
CC
V
Note: 1. Characterized but not 100% tested.
AC CHARACTERISTICS
PIN IMPEDANCE (VCC = 3.3 V, f = 1 MHz, T = 25°C )
pyTxaMstinUsnoitidnoC
C
O/I )1(
ecnaticapaCniPO/I21FpV
O/I
V0=
C
NI )1(
ecnaticapaCtupnI21FpV
NI
V0=
L
NIP )2(
ecnatcudnIniP02Hn
Notes:
1. These parameters are characterized but not 100% tested.
2. Refer to PCI specification.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
36
AC CHARACTERISTICS (CONTINUED)
FWH/LPC INTERFACE AC INPUT/OUTPUT CHARACTERISTICS
lobmySretemaraPnoitidnoCniMxaMstinU
I
HO
)CA( tnerrucgnihctiwS hgih
V<0
TUO
<V3.0
CC
V21-
CC
Am
V3.0
CC
V<
TUO
V9.0<
CC
V(1.71-
CC
V-
TUO
)Am
V7.0
CC
V<
TUO
V<
CC
CnoitauqE
)1(
)tnioptseT(V
TUO
V7.0=
CC
V23-
CC
Am
I
LO
)CA(woltnerrucgnihctiwS
V
CC
V>
TUO
>V6.0
CC
V61
CC
Am
V6.0
CC
V>
TUO
V1.0>
CC
V(1.71-
CC
V-
TUO
)Am
V81.0
CC
V>
TUO
0>DnoitauqE
)1(
)tnioptseT(V
TUO
V81.0=
CC
V83
CC
Am
I
LC
tnerrucpmalcwoLV<3-
NI
<1-V(+52-
NI
510.0/)1+Am
I
HC
tnerrucpmalchgiHV
CC
V>4+
NI
>V
CC
1+ V(+52
NI
V-
CC
/)1-
510.0 Am
rwels
)2(
etarwelsesirtuptuOV2.0
CC
V6.0-
CC
daol14sn/V
fwels
)2(
etarwelsllaftuptuOV6.0
CC
V2.0-
CC
daol14sn/V
Notes:
1. See PCI specification.
2. PCI specification output load is used.
FWH/LPC INTERFACE CLOCK CHARACTERISTICS
lobmySretemaraPniMxaMstinU
t
CYC
emiTelcyCkcolC03sn
t
HGIH
emiThgiHkcolC11sn
t
WOL
emiTwoLkcolC11sn
etaRwelSkcolC14sn/V
etaRwelS#TSRro#TINI05sn/Vm
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
37
AC CHARACTERISTICS (CONTINUED)
lobmySretemaraPniMxaMstinU
T
CYC
emiTelcyCkcolC03sn
T
US
emiTpUteStupnI7sn
T
H
emiTdloHtupnI0sn
T
LAV
tuOataDotkcolC211sn
T
NO
)yaledevitcaottaolf(emiTevitcAotkcolC2sn
T
FFO
)yaledtaolfotevitca(emiTevitcanIotkcolC82sn
FWH/LPC MEMORY READ/WRITE OPERA TIONS CHARACTERISTICS
tLOW
tHIGH
tCYC
0.5 V
CC
0.4 V
CC
0.3 V
CC
0.4 V
CC
p-to-p
(minimum)
0.6 V
CC
0.2 V
CC
FWH/LPC INTERFACE CLOCK WA VEFORM
FWH/LPC INTERFACE MEASUREMENT CONDITION PARAMETERS
lobmySeulaVstinU
V
HT 1
V6.0
CC
V
V
LT 1
V2.0
CC
V
V
TSET
V4.0
CC
V
V
XAM 1
V4.0
CC
V
etaRegdElangiStupnIsn/V1
Note: 1. The input test environment is done with 0.1 VCC of overdrive over VIH and VIL. Timing parameters must
be met with no more overdrive that this. VMAX specifies the maximum peak-to-peak waveform allowed
for measuring input timing. Production testing may use different voltage values, but must correlate
results back to these parameter .
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
38
AC CHARACTERISTICS (CONTINUED)
V
TEST
V
TL
V
TH
t
VAL
t
OFF
t
ON
CLK
FWH[3:0] or
LAD[3:0]
(Valid Output Data)
FWH[3:0] or
LAD[3:0]
(Float Output Data)
FWH/LPC OUTPUT TIMING P ARAMETERS
tH
tSU
INPUT VALID
V
TH
V
TL
V
TEST
V
MAX
FWH[3:0] or
LAD[3:0]
(Valid Input Data)
CLK
FWH/LPC INPUT TIMING P ARAMETERS
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
39
T
PRST
T
KRST
T
RSTP
T
RST
T
RSTF
V
CC
CLK
RST#/INIT#
FWH[3:0] or
LAD[3:0]
FWH4 or
LFRAME#
FWH/LPC RESET AC WA VEFORMS
lobmySretemaraPniMxaMstinU
T
TSRP
VotemiTevitcAteseR
CC
elbatS 1sm
T
TSRK
otemiTevitcAteseRkcolCelbatS 001sµ
T
PTSR
htdiWesluPteseR001sn
T
FTSR
yaleDtaolFtuptuOotevitcAteseR05sn
T
TSR )1(
evitcAtupnIotemiTevitcanIteseR1sµ
FWH/LPC RESET OPERA TION CHARACTERISTICS
AC CHARACTERISTICS (CONTINUED)
A/A MUX MODE TEST LOAD CONDITION
TO TESTER
30 pF
C
L
TO DUT
A/A MUX MODE INPUT TEST MEASUREMENT CONDITION P ARAMETERS
3.0 V
0.0 V
1.5 V AC
Measurement
Level
Input
Note: 1. There will be a 10 µs reset latency if a reset procedure is performed during a programming or erase
operation.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
40
AC CHARACTERISTICS (CONTINUED)
A/A MUX MODE READ OPERA TIONS CHARACTERISTICS
lobmySretemaraPniMxaMstinU
t
CR
emiTelcyCdaeR072sn
t
CCA
yaleDtuptuOotsserddA 021sn
t
TSR
emiTpu-teSsserddAwoRothgiH#TSR1sm
t
SA
emiTpu-teSsserddA#C/R54sn
t
HA
emiTdloHsserddA#C/R54sn
t
EO
yaleDtuptuOot#EO 05sn
t
FD
ZhgiHtuptuOot#EO003sn
t
HO
tsrifderuccorevehcihw,sserddAro#EOmorfdloHtuptuO0sn
t
SCV
V
CC
emiTpu-teS05sµ
A/A MUX MODE READ OPERA TIONS AC WAVEFORMS
ROW ADDRESS
t
RC
t
ACC
t
OE
t
DF
t
OH
OUTPUT
VALID
HIGH Z
ADDRESS
OE#
WE#
OUTPUT
V
CC
t
VCS
RST#
t
RST
COLUMN ADDRESS
t
AS
t
AH
t
AS
t
AH
R/C#
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
41
A/A MUX MODE WRITE OPERA TIONS AC W A VEFORMS
ROW ADDRESS
t
RC
t
CWH
t
OEH
t
DS
t
DH
INPUT
DATA
HIGH Z
ADDRESS
OE#
WE#
OUTPUT
V
CC
t
VCS
RST#
t
RST
COLUMN ADDRESS
t
AS
t
AH
t
AS
t
AH
R/C#
t
OES
AC CHARACTERISTICS (CONTINUED)
A/A MUX MODE WRITE (PROGRAM/ERASE) OPERA TIONS CHARACTERISTICS
lobmySretemaraPniMxaMstinU
t
TSR
emiTpu-teSsserddAwoRothgiH#TSR1sm
t
SA
emiTpu-teSsserddA#C/R05sn
t
HA
emiTdloHsserddA#C/R05sn
t
HWC
emiThgiH#EWot#C/R05sn
t
SEO
emiTpu-teShgiH#EO02sn
t
HEO
emiTdloHhgiH#EO02sn
t
SD
emiTpu-teSataD05sn
t
HD
emiTdloHataD5sn
t
PW
htdiWesluPetirW001sn
t
HPW
hgiHhtdiWesluPetirW001sn
t
PB
emiTgnimmargorPetyB04sµ
t
CE
emiTelcyCesarEkcolBrorotceS,pihC08sm
t
SCV
V
CC
emiTpu-teS05sµ
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
42
A/A MUX MODE BYTE PROGRAM OPERA TIONS AC WA VEFORMS
A/A MUX MODE CHIP ERASE OPERA TIONS AC WA VEFORMS
t
WP
t
WPH
t
EC
AA 55
DATA IN
ADDRESS
OE#
WE#
R/C#
6-Byte Chip Erase Command
t
DH
t
DS
t
CWH
5555 5555
2AAA 5555 5555
2AAA
AA 55
80 10
AC CHARACTERISTICS (CONTINUED)
t
WP
t
WPH
t
BP
5555 5555 BYTE ADDRESS
2AAA
AA 55 A0
INPUT
DATA VALID
DATA
DATA
ADDRESS
OE#
WE#
R/C#
4-Byte Program Command
t
DH
t
DS
t
CWH
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
43
A/A MUX MODE SECTOR/BLOCK ERASE OPERA TIONS AC W AVEFORMS
t
WP
t
WPH
t
EC
AA 55
DATA IN
ADDRESS
OE#
WE#
R/C#
6-Byte Block Erase Command
t
DH
t
DS
t
CWH
5555 5555
2AAA 5555
SECTOR OR
BLOCK ADDRESS
2AAA
AA 55
80 30/50
A/A MUX MODE TOGGLE BIT AC W A VEFORMS
t
OEH
WE#
R/C#
OE#
I/O6
t
OE
DD
ADDRESS ROW COLUMN
Note: 1. T oggling OE# will operate Toggle Bit.
2. I/O6 may start and end from “1” or “0” in random.
AC CHARACTERISTICS (CONTINUED)
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
44
A/A MUX MODE DA T A# POLLING AC W A VEFORMS
t
OEH
WE#
R/C#
OE#
I/O7
t
OE
DD
ADDRESS ROW COLUMN
D#D#D#
Note: Toggling OE# will operate Data# Polling.
AC CHARACTERISTICS (CONTINUED)
retemaraPtinUpyTxaMskrameR
emiTesarEkcolB/rotceSsm0508noitelpmocesareotdnammocesaregnitirwmorF
emiTesarEpihCsm0508noitelpmocesareotdnammocesaregnitirwmorF
emiTgnimmargorPetyB µs5204dnammocmargorpelcyc-ruoffoemitehtsedulcxE noitucexe
PROGRAM/ERASE PERFORMANCE
Note: These parameters are characterized but not 100% tested.
RELIABILITY CHARACTERISTICS (1)
retemaraPniMpyTtinUdohteMtseT
ecnarudnE000,001
)2(
selcyC711AdradnatSCEDEJ
noitneteRataD02sraeY301AdradnatSCEDEJ
ledoMydoBnamuH-DSE000,2000,4>stloV411AdradnatSCEDEJ
ledoMenihcaM-DSE002004>stloV511AdradnatSCEDEJ
pU-hctaL I+001
1CC
Am87dradnatSCEDEJ
Notes: 1. These parameters are characterized but not 100% tested.
2. Preliminary specification only and will be formalized after cycling qualification test.
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
45
PACKAGE TYPE INFORMATION
TOP VIEW SIDE VIEW
32V
32-Pin Thin Small Outline Package (VSOP - 8 mm x 14 mm)( measure in millimeters)
0.50
BSC
1.05
0.95
0.27
0.17
0.15
0.05
Pin 1 I.D.
12.50
12.30
14.20
13.80
8.10
7.90
1.20
MAX
0.25 0°
5°
0.20
0.10
0.70
0.50
32J
32-Pin Plastic Leaded Chip Carrier (measured in millimeters)
Pin 1 I.D.
15.11
14.86
14.05
13.89
1.27 Typ.
0.81
0.66
11.51
11.35
12.57
12.32
0.74X30°
13.46
12.45
0.53
0.33
2.41
1.93
3.56
3.18
SEATING
PLANE
Programmable Microelectronics Corp. Issue Date: December, 2003 Rev: 1.4
PMC Pm49FL002 / 004
46
REVISION HISTORY
etaD.oNnoisiveRsegnahCfonoitpircseD.oNegaP
2002,enuJ0.1noitacilbupyranimilerPllA
2002,yluJ1.1noitacilbuplamroFllA
3002,yraunaJ2.1 noitacificepsemitesarednamargorpdesiveR44,14,1
gnikcoLkcolBrofrebmuntrapehtnoopytdetcerroC retsigeR 32
3002,rebmevoN3.1 noitamrofni800LF94mPdevomeRllA
epytegakcaproftnemerusaemhcnidevomeR noitamrofni 54
3002,rebmeceD4.1
eerf-daelrofnoitamrofnigniredrotcudorpdegnahC noitpoegakcap 43,4,1
morfselcycesare/margorpdeetnarugdedargpU )yranimilerp(000,001ot000,05 44,1
