SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
High Speed
D
Standard Supply Voltage
D
Dual Channels
D
High Common-Mode Rejection Ratio
D
High Input Impedance
D
High Input Sensitivity
D
Differential Common-Mode Input Voltage
Range of ±3 V
D
Strobe Inputs for Receiver Selection
D
Gate Inputs for Logic Versatility
D
TTL Drive Capability
D
High dc Noise Margin
D
Totem-Pole Outputs
D
B Version Has Diode-Protected Input for
Power-Off Condition
description
These circuits are TTL-compatible, high-speed
line receivers. Each is a monolithic dual circuit
featuring two independent channels. They are
designed for general use, as well as for such
specific applications as data comparators and
balanced, unbalanced, and party-line transmis-
sion systems. These devices are unilaterally
interchangeable with and are replacements for
the SN55107, SN75107, and SN75108, but offer
diode-clamped strobe inputs to simplify circuit
design.
The essential difference between the A and B versions can be seen in the schematics. Input-protection diodes
are in series with the collectors of the differential-input transistors of the B versions. These diodes are useful
in certain party-line systems that have multiple VCC+ power supplies and can be operated with some of the VCC+
supplies turned off. In such a system, if a supply is turned of f and allowed to go to ground, the equivalent input
circuit connected to that supply would be as follows:
Input
A Version
Input
B Version
This would be a problem in specific systems that might have the transmission lines biased to some potential
greater than 1.4 V.
The SN55107A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN75107A, SN75107B, and SN75108A are characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1A
1B
NC
1Y
1G
S
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC+
VCC–
2A
2B
NC
2Y
2G
SN55107A ... J OR W PACKAGE
SN75107A, SN75107B, SN75108A ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2A
NC
2B
NC
NC
NC
NC
1Y
NC
1G
SN55107A . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
2Y
S
GND
NC
NC – No internal connection
CC +
V
2G CC –
V
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
DIFFERENTIAL INPUTS STROBES OUTPUT
A – B G S Y
VID ≥ 25 mV X X H
X L H
–25 mV < VID < 25 mV L X H
H H Indeterminate
X L H
VID ≤ –25 mV L X H
H H L
H = high level, L = low level, X = irrelevant
logic symbol†
2G
2B
2A
1G
1B
1A
S
8
11
12
5
2
6
2Y
1Y
9
4
&
EN
SN75108A
1
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2G
2B
2A
1G
1B
1A
S
8
11
12
5
2
1
6
2Y
1Y
9
4
&
EN
SN55107A, SN75107A, and SN75107B
logic diagram (positive logic)
2B
2A
2G
1G
1B
1A
S
11
12
8
5
2
1
6
2Y
1Y
9
4
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each receiver)
13
2, 11
14
1, 12
See
Note 2
To Other Receiver
Output Y
GND
Strobe G
Strobe S
4, 9
7
5, 8
6
800 Ω
Common
to Both
Receivers
1 kΩ1 kΩ400 Ω4 kΩ1.6 kΩ120 Ω
4.8 kΩ
760 ΩR†
4.25 kΩ
3 kΩ3 kΩ
VCC +
A
B
Inputs
VCC –
Pin numbers shown are for D, J, N, and W packages.
†R = 1 kΩ for ’107A and SN75107B, 750 Ω for SN75108A.
NOTES: 1. Resistor values shown are nominal.
2. Components shown with dashed lines in the output circuitry are applicable to the ’107A and SN75107B only . Diodes in series with
the collectors of the differential input transistors are short circuited on ’107A and SN75108A.
See
Note 2
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC+ (see Note 3) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, VCC– –7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 4) ±6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common-mode input voltage, VIC (see Note 5) ±5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Strobe input voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, Tc: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package 300°C. . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or W package 260°C. . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 3. All voltage values, except differential voltages, are with respect to network ground terminal.
4. Differential voltage values are at the noninverting (A) terminal with respect to the inverting (B) terminal.
5. Common-mode input voltage is the average of the voltages at the A and B inputs.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING F ACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 125°C
POWER RATING
D950 mW 7.6 mW/°C608 mW —
FK 1375 mW 11.0 mW/°C 880 mW 275 mW
J1375 mW 11.0 mW/°C 880 mW 275 mW
N1150 mW 9.2 mW/°C 736 mW —
W1000 mW 8.0 mW/°C640 mW 200 mW
recommended operating conditions (see Note 6)
SN55107A
SN75107A, SN75107B,
SN55107A
,,
SN75108A UNIT
MIN NOM MAX MIN NOM MAX
Supply voltage, VCC+ 4.5 5 5.5 4.75 5 5.25 V
Supply voltage, VCC– –4.5 –5 –5.5 –4.75 –5 –5.25 V
High-level input voltage between differential inputs, VIDH (see Note 7) 0.025 5 0.025 5 V
Low-level input voltage between differential inputs, VIDL (see Note 7) –5‡–0.025 –5‡–0.025 V
Common-mode input voltage, VIC (see Notes 7 and 8) –3‡3–3‡3 V
Input voltage, any differential input to GND (see Note 8) –5‡3–5‡3 V
High-level input voltage at strobe inputs, VIH(S) 2 5.5 2 5.5 V
Low-level input voltage at strobe inputs, VIL(S) 0 0.8 0 0.8 V
Low-level output current, IOL –16 –16 mA
Operating free-air temperature, TA–55 125 0 70 °C
‡The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for input voltage
levels only.
NOTES: 6. When using only one channel of the line receiver, the strobe input (G) of the unused channel should be grounded and at least one
of the differential inputs of the unused receiver should be terminated at some voltage between –3 V and 3 V.
7. The recommended combinations of input voltages fall within the shaded area in Figure 1.
8. The common-mode voltage may be as low as –4 V provided that the more positive of the two inputs is not more negative than
–3 V.
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
–1
–3
–4
–5
–5 –4 –3 –2 –1 0
Input A to GND Voltage – V
1
2
Input B to GND Voltage – V
RECOMMENDED COMBINATIONS
OF INPUT VOLTAGES
3
123
0
–2
NOTE A: Recommended input-voltage combinations are in the shaded area.
Figure 1. Recommended Combinations of Input Voltages
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS†
’107A, SN75107B SN75108A
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VOH
High level out
p
ut voltage
VCC± = MIN,
VIDH 25 mV
VIL(S) = 0.8 V,
IOH 400 µA
24
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
V
IDH =
25
m
V
,
VIC = –3 V to 3 V
I
OH = –
400
µ
A
,
2
.
4
V
VOL
Low level out
p
ut voltage
VCC± = MIN,
VIDL 25 mV
VIH(S) = 2 V,
IOL 16 mA
04
04
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
V
IDL = –
25
m
V
,
VIC = –3 V to 3 V
I
OL =
16
m
A
,
0
.
4
0
.
4
V
IIH
High level in
p
ut current
A
VCC±= MAX
VID = 5 V 30 75 30 75
µA
I
IH
High
-
le
v
el
inp
u
t
c
u
rrent
B
V
CC± =
MAX
VID = –5 V 30 75 30 75 µ
A
IIL
Low-level input current A
VCC±= MAX
VID = –5 V –10 –10
µA
I
IL B
V
CC± =
MAX
VID = 5 V –10 –10 µ
A
IIH
High-level input current into VCC± = MAX, VIH(G) = 2.4 V 40 40 µA
I
IH
g
1G or 2G VCC± = MAX, VIH(G) = MAX VCC+ 1 1 mA
IIL
Low-level input current
VCC±= MAX
VIL(G) =04V
16
16
mA
I
IL into 1G or 2G
V
CC± =
MAX
,
V
IL(G) =
0
.
4
V
–
1
.
6
–
1
.
6
mA
IIH
High level in
p
ut current into S
VCC± = MAX, VIH(S) = 2.4 V 80 80 µA
I
IH
High
-
le
v
el
inp
u
t
c
u
rrent
into
S
VCC± = MAX, VIH(S) = MAX VCC+ 2 2 mA
IIL Low-level input current into S VCC± = MAX, VIL(S)= 0.4 V –3.2 –3.2 mA
IOH High-level output current VCC± = MIN, VOH = MAX VCC+ 250 µA
IOS Short-circuit output current§VCC± = MAX –18 –70 mA
ICCH
Supply current from V
CC+
,
VCC±= MAX
TA=25
°
C
18
30
18
30
mA
I
CCH+
yCC+,
outputs high
V
CC± =
MAX
,
T
A =
25°C
18
30
18
30
mA
ICCH– Supply current from VCC–,
outputs high VCC± = MAX, TA = 25°C –8.4 –15 –8.4 –15 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC+ = 5 V, VCC– = –5 V, TA = 25°C.
§Not more than one output should be shorted at a time.
switching characteristics, VCC± = ±5 V, TA = 25°C, RL = 390 Ω (see Figure 2)
PARAMETER
TEST ’107A, SN75107B SN75108A
UNIT
PARAMETER
CONDITIONS MIN TYP MAX MIN TYP MAX
UNIT
tPLH(D)
Propagation delay time, low- to high-level output, CL = 50 pF 17 25
ns
t
PLH(D)
gy,g ,
from differential inputs A and B CL = 15 pF 19 25
ns
tPHL(D)
Propagation delay time, high- to low-level output, CL = 50 pF 17 25
ns
t
PHL(D)
gy,g ,
from differential inputs A and B CL = 15 pF 19 25
ns
tPLH(S)
Propagation delay time, low- to high-level output, CL = 50 pF 10 15
ns
t
PLH(S)
gy,g ,
from strobe input G or S CL = 15 pF 13 20
ns
tPHL(S)
Propagation delay time, high- to low-level output, CL = 50 pF 8 15
ns
t
PHL(S)
gyg
from strobe input G or S CL = 15 pF 13 20
ns
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
Pulse
Generator
(see Note A)
Differential
Input VCC–
1G S 2G VCC+
50 Ω
390 Ω
390 Ω
Output
‘107A, SN75107B
(see Note D)
(see Note C)
50 pF
50 Ω
Vref
100 mV
1A
1B
2A
2B
1Y
2Y
15 pF
Output
SN75108A,
CL
Strobe
Input
(see Note B)
TEST CIRCUIT
VOLTAGE WAVEFORMS
1.5 V 1.5 V
1.5 V
100 mV 100 mV 200 mV
0 V
3 V
VOH
VOL
1.5 V 1.5 V
tPLH(S) tPHL(S)
tPLH(D) tPHL(D)
Output Y
Input A
Strobe Input
G or S
CL
Pulse
Generator
(see Note A)
(see Note C)
tp2
tp1
NOTES: A. The pulse generators have the following characteristics: ZO = 50 Ω, tr = 10 ± 5 ns, tf = 10 ± 5 ns, tpd1 = 500 ns, PRR ≤ 1 MHz,
tpd2 = 1 µs, PRR ≤ 500 kHz.
B. Strobe input pulse is applied to Strobe 1G when inputs 1A-1B are being tested, to Strobe S when inputs 1A-1B or 2A-2B are being
tested, and to Strobe 2G when inputs 2A-2B are being tested.
C. CL includes probe and jig capacitance.
D. All diodes are 1N916.
Figure 2. Test Circuit and Voltage Waveforms
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 3
–40
VID – Differential Input Voltage – mV
6
40
0–30 –20 –10 0 10 20 30
1
2
3
4
5
VCC± = ±5 V
RL = 400 Ω
TA = 25°C
SN75108A
Inverting
Inputs Inputs
Noninverting
’107A,
SN75107B
VO – Output Voltage – V
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
ÁÁÁ
ÁÁÁ
VO
Figure 4
–75
TA – Free-Air Temperature – °C
100
125
0–25 0 25 50 75 100
20
40
60
80
VCC± = ±5 V
IIH – High-Level Input Current –
HIGH-LEVEL INPUT CURRENT (1A OR 2A)
vs
FREE-AIR TEMPERATURE
–50
IIH Aµ
Figure 5
30
0
5
10
15
20
25
1007550250–25–50 125
TA – Free-Air Temperature – °C
–75
VCC± = ±5 V
ICC+
ICC–
– Supply Current – mA
SUPPPLY CURRENT (OUTPUTS HIGH)
vs
FREE-AIR TEMPERATURE
| ICCH |
Figure 6
40
0
5
10
15
20
25
30
35
–75
TA – Free-Air Temperature – °C
125–50 –25 0 25 50 75 100
tPLH(D)
tPHL(D)
Propagation Delay Time – ns
PROPAGATION DELAY TIME
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
CL = 50 pF
RL = 390 Ω
VCC± = ±5 V
tpd –
†Values below 0°C and above 70°C apply to SN55107A only.
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 7
–75
TA – Free-Air Temperature – °C
120
125
0–50 –25 0 25 50 75 100
20
40
100
60
RL = 1950 Ω
RL = 390 Ω
tPLH(D) – Propagation Delay Time – ns
PROPAGATION DELAY TIME (LOW-T O-HIGH LEVEL)
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
PLH(D)
t
VCC ± = ±5 V
CL = 15 pF
RL = 3900 Ω
80
Figure 8
RL = 390 Ω
RL = 1950 Ω
–75
TA – Free-Air Temperature – °C
40
125
0–50 –25 0 25 50 75 100
5
10
15
20
25
30
35
PROPAGATION DELAY TIME (LOW-T O-HIGH LEVEL)
(DIFFERENTIAL INPUTS)
vs
FREE-AIR TEMPERATURE
CL = 15 pF
VCC± = ±5 V
tPLH(D) – Propagation Delay Time – ns
PLH(D)
t
RL = 3900 Ω
Figure 9
1007550250–25–50 125
TA – Free-Air Temperature – °C
–75
35
30
25
20
15
10
5
0
40
– Propagation Delay Time – ns
SN75108A
PROPAGATION DELAY TIME (STROBE INPUTS)
vs
FREE-AIR TEMPERATURE
tPLH(S)
tPHL(S)
tpd
VCC± = ±5 V
RL = 390 Ω
CL = 50 pF
Figure 10
1007550250–25–50 125
TA – Free-Air Temperature – °C
–75
35
30
25
20
15
10
5
0
40
SN75108A
PROPAGATION DELAY TIME (STROBE INPUTS)
vs
FREE-AIR TEMPERATURE
tPLH(S)
tPHL(S)
– Propagation Delay Time – ns
tpd
VCC± = ±5 V
RL = 390 Ω
CL = 15 pF
†Values below 0°C and above 70°C apply to SN55107A only.
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
basic balanced-line transmission system
The ’107A, SN75107B, and SN75108A dual line devices are designed specifically for use in high-speed
data-transmission systems that utilize balanced terminated transmission lines, such as twisted-pair lines. The
system operates in the balanced mode, so noise induced on one line is also induced on the other. The noise
appears common mode at the receiver input terminals, where it is rejected. The ground connection between
the line driver and receiver is not part of the signal circuit; therefore, system performance is not affected by
circulating ground currents.
The unique driver-output circuit allows terminated transmission lines to be driven at normal line impedances.
High-speed system operation is ensured because line reflections are virtually eliminated when terminated lines
are used. Crosstalk is minimized by low signal amplitudes and low line impedances.
The typical data delay in a system is approximately 30 + 1.3 L ns, where L is the distance in feet separating the
driver and receiver. This delay includes one gate delay in both the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output current.
The driven line is selected by appropriate driver-input logic levels. The voltage difference is approximately:
VDIFF ≈ 1/2IO(on) • RT
High series line resistance causes degradation of the signal. However, the receivers detect signals as low as
25 mV. For normal line resistances, data can be recovered from lines of several thousand feet in length.
Line-termination resistors (RT) are required only at the extreme ends of the line. For short lines, termination
resistors at the receiver only may be adequate. The signal amplitude is then approximately:
VDIFF ≈ IO(on) • RT
Transmission Line Having
Characteristic Impedance ZO
RT = ZO/2
L
RT
RT
A
B
C
DStrobes
RT
RT
Y
Receiver
‘107A, SN75107B,
SN75108A
Driver
SN55110A, SN75110A,
SN75112
Data Input
Inhibit
Figure 11. Typical Differential Data Line
data-bus or party-line system
The strobe feature of the receivers and the inhibit feature of the drivers allow these dual line devices to be used
in data-bus or party-line systems. In these applications, several drivers and receivers can share a common
transmission line. An enabled driver transmits data to all enabled receivers on the line while other drivers and
receivers are disabled. Data is time multiplexed on the transmission line. The device specifications allow widely
varying thermal and electrical environments at the various driver and receiver locations. The data-bus system
offers maximum performance at minimum cost.
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
C
RT
RT
RT
RT
Drivers
SN55110A, SN751 10A,
SN75112 Receiver 1 Receiver 2 Receiver 4
Driver 1 Driver 3 Driver 4
Location 1 Location 3 Location 4
Strobes
Receivers
‘107A, SN75107B,
SN75108A
Location 2
Data
Input
Inhibit
A
B
C
D
A
BB
A
C
DD
YY Y
Strobes Strobes
Figure 12. Typical Differential Party Line
unbalanced or single-line systems
These dual line circuits also can be used in unbalanced or single-line systems. Although these systems do not
offer the same performance as balanced systems for long lines, they are adequate for very short lines where
environmental noise is not severe.
The receiver threshold level is established by applying a dc reference voltage to one receiver input terminal.
The signal from the transmission line is applied to the remaining input. The reference voltage should be
optimized so that signal swing is symmetrical about it for maximum noise margin. The reference voltage should
be in the range of –3 V to 3 V. It can be provided by a voltage supply or by a voltage divider from an available
supply voltage.
A single-ended output from a driver can be used in single-line systems. Coaxial or shielded line is preferred for
minimum noise and crosstalk problems. For large signal swings, the high output current (typically 27 mA) of the
SN75112 is recommended. Drivers can be paralleled for higher current. When using only one channel of the
line drivers, the other channel should be inhibited and/or have its outputs grounded.
Input
Vref
Input
Inhibit
SN55110A, SN751 10A, SN75112
A
B
C
D
Output
VO = –IO • R
R‘107A, SN75107B, SN75108A
Strobes
Output
Figure 13. Single-Ended Operation
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN75108A dot-AND output connections
The SN75108A line receiver features an open-collector-output circuit that can be connected in the dot-AND
logic configuration with other similar open-collector outputs. This allows a level of logic to be implemented
without additional logic delay.
Output
SN75108A
SN75108A
SN5401/SN7401 or
Equivalent Dot-AND
Connection
Figure 14. Dot-AND Connection
increasing common-mode input voltage range of receiver
The common-mode voltage range (CMVR) is defined as the range of voltage applied simultaneously to both
input terminals that, if exceeded, does not allow normal operation of the receiver.
The recommended operating CMVR is ±3 V, making it useful in all but the noisiest environments. In extremely
noisy environments, common-mode voltage can easily reach ±10 V to ±15 V if some precautions are not taken
to reduce ground and power supply noise, as well as crosstalk problems. When the receiver must operate in
such conditions, input attenuators should be used to decrease the system common-mode noise to a tolerable
level at the receiver inputs. Differential noise is also reduced by the same ratio. These attenuators were omitted
intentionally from the receiver input terminals so the designer can select resistors that are compatible with his
particular application or environment. Furthermore, the use of attenuators adversely affects the input sensitivity ,
the propagation delay time, the power dissipation, and in some cases (depending on the selected resistor
values) the input impedance; thereby reducing the versatility of the receiver.
The ability of the receiver to operate with approximately ±15 V common-mode voltage at the inputs has been
checked using the circuit shown in Figure 15. Resistors R1 and R2 provide a voltage-divider network. Dividers
with three different values presenting a 5-to-1 attenuation were used to operate the differential inputs at
approximately ±3 V common-mode voltage. Careful matching of the two attenuators is needed to balance the
overdrive at the input stage. The resistors used are shown in Table 1.
Table 1
Attenuator 1: R1 = 2 kΩ,R2 = 0.5 kΩ
Attenuator 2: R1 = 6 kΩ, R2 = 1.5 kΩ
Attenuator 3: R1 = 12 kΩ,R2 = 3 kΩ
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
increasing common-mode input voltage range of receiver (continued)
Table 2 shows some of the typical switching results obtained under such conditions.
Table 2. Typical Propagation Delays for Receiver
With Attenuator Test Circuit Shown in Figure 15
DEVICE PARAMETERS INPUT
ATTENUATOR TYPICAL
(NS)
t
1 20
t
PLH 2 32
’107A 3 42
SN75107B
t
1 22
t
PHL 2 31
3 33
t
1 36
t
PLH 2 47
SN75108A
3 57
SN75108A
t
1 29
t
PHL 2 38
3 41
R1 R2
Receiver
One Attenuator
on Each Input
16 V
– 14 V
or
14 V
– 16 V 15 V or –15 V
R2
5 V
RL = 390 Ω
R1
5 V
Figure 15. Common-Mode Circuit for Testing Input Attenuators With Results Shown in Table 2
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
T wo methods of terminating a transmission line to reduce reflections are shown in Figure 16. The first method
uses the resistors as the attenuation network and line termination. The second method uses two additional
resistors for the line terminations.
APPLICATION INFORMATION
R3
R3R3
R1
(see Note A)
R2
(see Note A)
R2
R1
R3 = R1 + R2 = ZO/2
Method 2
R2
R1
R3
R1 + R2 > ZO
R3 = ZO/2
R2
(see Note A)
R3
R3
R1
Method 1
NOTE A: To minimize the loading, the values of R1 and R2 should be fairly large. Examples of possible values are shown in Table 1.
Figure 16. Termination Techniques
For party-line operation, method 2 should be used as shown in Figure 17.
Attenuation Network
R3
+
ZO
2R3
+
ZO
2R3
+
ZO
2R3
+
ZO
2
Figure 17. Party-Line Termination Technique
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
furnace control using the SN75108A
The furnace control circuit in Figure 18 is an example of the possible use of the SN75108A series in areas other
than what would normally be considered electronic systems. A description of the operation of this control
follows. When the room temperature is below the desired level, the resistance of the room temperature sensor
is high and channel 1 noninverting input is below (less positive than) the reference level set on the input
differential amplifier. This situation causes a low output, operating the heat-on relay and turning on the heat.
The channel 2 noninverting input is below the reference level when the bonnet temperature of the furnace
reaches the desired level. This causes a low output, thus operating the blower relay. Normally the furnace is
shut down when the room temperature reaches the desired level and the channel 1 output goes high, turning
the heat off. The blower remains on as long as the bonnet temperature is high, even after the heat-on relay is
off. There is also a safety switch in the bonnet that shuts down the furnace if the temperature there exceeds
desired limits. The types of temperature-sensing devices and bias-resistor values used are determined by the
particular operating conditions encountered.
1 Y
+ T Room
Temp.
Sensor – T
Blower on Control
Room
Temp.
Setting
A
B
2A
2B
2 Y
To Heat-on
Relay Return
To Blower
Relay Return
Bonnet Upper
Limit Switch
Channel 1
Channel 2
Bonnet
Temp.
Sensor
5 V
Figure 18. Furnace Control Using SN75108A
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
repeaters for long lines
In some cases, the driven line may be so long that the noise level on the line reaches the common-mode limits
or the attenuation becomes too large and results in poor reception. In such a case, a simple application of a
receiver and a driver as repeaters [shown in Figure 19(a)] restores the signal level and allows an adequate
signal level at the receiving end. If multichannel operation is desired, then proper gating for each channel must
be sent through the repeater station using another repeater set as in Figure 19(b).
Driver
Strobe
Ckt
P
Receiver
P
P P
P P
Data In
Clock In
Data Out
(a) SINGLE-CHANNEL LINE
(b) MULTICHANNEL LINE WIDTH WITH STROBE
Repeaters
Data In
Driver Receiver
Driver Receiver Driver Receiver
Receiver Driver Receiver
Data Out
Figure 19. Receiver-Driver Repeaters
receiver as dual differential comparator
There are many applications for differential comparators, such as voltage comparison, threshold detection,
controlled Schmitt triggering, and pulse-width control.
As a differential comparator, a ’107A or SN75108A can be connected to compare the noninverting input terminal
with the inverting input as shown in Figure 20. The output is high or low , resulting from the A input being greater
or less than the reference. The strobe inputs allow additional control over the circuit so that either output, or both,
can be inhibited.
Strobe 1, 2
Reference 1
Reference 2
Strobe 2
Strobe 1
Output 1
Output 2
1A
1B
2A
2B
Figure 20. SN75107A Series Receiver as a Dual Differential Comparator
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
window detector
The window detector circuit in Figure 21 has a large number of applications in test equipment and in determining
upper limits, lower limits, or both at the same time, such as detecting whether a voltage or signal has exceeded
its window limits. Illumination of the upper-limit (lower-limit) indicator shows that the input voltage is above
(below) the selected upper (lower) limit. A mode selector is provided for selecting the desired test. For window
detecting, the upper-and-lower-limits test position is used.
Mode
Selector
1
2
3
4
500 Ω
500 Ω
5 V –5 V
1 kΩ1 kΩ
Set
Upper
Limit
Set
Lower
Limit
5 kΩ
1 kΩ
Upper-Limit
Indicator
Lower-Limit
Indicator
MODE SELECTOR LEGEND
POSITION CONDITION
1Off
2 Test for Upper Limit
3 Test for Lower Limit
4 Test for Upper and Lower Limits
5 V
Input From
Test Point
4.7 kΩ
4.7 kΩ
4.7 kΩ
Figure 21. Window Detector Using SN75108A
SN55107A, SN75107A, SN75107B, SN75108A
DUAL LINE RECEIVERS
SLLS069D – JANUARY 1977 – REVISED APRIL 1998
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
temperature controller with zero-voltage switching
The circuit in Figure 22 switches an electric-resistive heater on or off by providing negative-going pulses to the
gate of a triac during the time interval when the line voltage is passing through zero. The pulse generator is the
2N5447 and four diodes. This portion of the circuit provides negative-going pulses during the short time
(approximately 100 µs) when the line voltage is near zero. These pulses are fed to the inverting input of one
channel of the SN75108A. If the room temperature is below the desired level, the resistance of the thermistor
is high and the noninverting input of channel 2 is above the reference level determined by the thermostat setting.
This provides a high-level output from channel 2. This output is ANDed with the positive-going pulses from the
output of channel 1, which are reinverted in the 2N5449.
Heater
Load
2B
120 V to
220 V, 60 Hz
5-V
Zener
– T
Thermostat
Setting
GND
Channel 1
Channel 2
10-V
Zener
250 µF
2N5449
2N5447
250 µF
VCC +VCC –
1A
1B
2A
+
+
SN75108A
Figure 22. Zero-Voltage Switching Temperature Controller
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9690301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9690301Q2A
SNJ55
107AFK
5962-9690301QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9690301QC
A
SNJ55107AJ
5962-9690301QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9690301QD
A
SNJ55107AW
JM38510/10401BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10401BCA
M38510/10401BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10401BCA
SN55107AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN55107AJ
SN75107AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107AN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN75107AN
SN75107ANE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN75107AN
SN75107ANSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN75107ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107A
SN75107BD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BDE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BDRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN75107BN
SN75107BNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN75107BN
SN75107BNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75107BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75107B
SN75108AD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75108A
SN75108ADE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75108A
SN75108ADG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75108A
SN75108ADR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75108A
SN75108ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75108A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN75108ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN75108A
SNJ55107AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9690301Q2A
SNJ55
107AFK
SNJ55107AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9690301QC
A
SNJ55107AJ
SNJ55107AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9690301QD
A
SNJ55107AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55107A, SN75107A, SN75107B, SN75108A :
•Catalog: SN75107A
•Military: SN55107A, SN55107B, SN55108A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75107ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN75107ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN75107BDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN75107BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN75108ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75107ADR SOIC D 14 2500 367.0 367.0 38.0
SN75107ANSR SO NS 14 2000 367.0 367.0 38.0
SN75107BDR SOIC D 14 2500 367.0 367.0 38.0
SN75107BNSR SO NS 14 2000 367.0 367.0 38.0
SN75108ADR SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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