Description
The PBL 386 30/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in Digital Loop Carrier, FITL and other telecommunications equipment.
The PBL 386 30/2 has been optimized for low total line interface cost and a high
degree of flexibility in different applications.
The PBL 386 30/2 emulates resistive loop feed, programmable between 2x50 Ω
and 2x900 Ω, with short loop current limiting adjustable to max 45 mA. In the current
limited region the loop feed is nearly constant current with a slight slope
corresponding to 2x30kΩ.
A second lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current and ring trip detection functions.
The PBL 386 30/2 is compatible with loop start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
two-wire impendance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet the DLC requirements.
The PBL 386 30/2 package options are 24-pin SSOP, 24-pin SOIC and
28-pin PLCC.
Figure 1. Block diagram.
March 2000
PBL 386 30/2
Subscriber Line
Interface Circuit
Key Features
• 24-pin SSOP package
• High and low battery supply with
automatic switching
• 65 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• Programmable signal headroom
• 43V open loop voltage @ -48V battery
feed
• Constant loop voltage for line leakage
<5 mA (RLeak ~ >10 kΩ @ -48V)
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Integrated Ring Relay Driver
• -40°C to +85°C ambient temperature
range
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
1
RRLY
C1
C2
DET
PSG
REF
LP
PLD
PLC
VTX
RSN
PTG
BGND
AGND
VBAT
VBAT2
VCC
HP
RINGX
TIPX
DR
DT
Ring Relay
Driver
Input
Decoder
and
Control
Ring Trip
Comparator
Line Feed
Controller
and
Longitudinal
Signal
Suppression
Off-hook
Detector
VF Signal
Transmission
Two-wire
Interface
POV
PBL 386 30/2
PBL
38630/2
PBL 386 30/2
PBL 386 30/2
2
Maximum Ratings
Parameter Symbol Min Max Unit
Temperature, Humidity
Storage temperature range TStg -55 +150 °C
Operating temperature range TAmb -40 +110 °C
Operating junction temperature range, Note 1 TJ-40 +140 °C
Power supply, -40 °C ≤ TAmb ≤ +85 °C
VCC with respect to A/BGND VCC -0.4 6.5 V
VBat2 with respect to A/BGND VBat2 VBat 0.4 V
VBat with respect to A/BGND, continuous VBat -75 0.4 V
VBat with respect to A/BGND, 10 ms VBat -80 0.4 V
Power dissipation
Continuous power dissipation at TAmb ≤ +85 °CP
D1.5 W
Ground
Voltage between AGND and BGND VG-0.3 0.3 V
Relay Driver
Ring relay supply voltage BGND+14 V
Ring trip comparator
Input voltage VDT, VDR VBat AGND V
Input current IDT, IDR -5 5 mA
Digital inputs, outputs (C1, C2, DET)
Input voltage VID -0.4 VCC V
Output voltage VOD -0.4 VCC V
TIPX and RINGX terminals, -40°C < TAmb < +85°C, VBat = -50V
Maximum supplied TIPX or RINGX current ITIPX, IRINGX -100 +100 mA
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 VTA, VRA -80 2 V
TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 VTA, VRA VBat -10 5 V
TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 VTA, VRA VBat -25 10 V
TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3 VTA, VRA VBat -35 15 V
Recommended Operating Condition
Parameter Symbol Min Max Unit
Ambient temperature TAmb -40 +85 °C
VCC with respect to AGND VCC 4.75 5.25 V
VBat with respect to AGND VBat -58 -8 V
AGND with respect to BGND VG-100 100 mV
Notes
1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability.
2. With the diodes DVB and DVB2 included, see figure 11.
3. RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.
PBL 386 30/2
3
VTX
Electrical Characteristics
-40 °C ≤ TAmb ≤ +85 °C, PTG = open (see pin description), VCC = +5V ±5 %, VBat = -58V to -40V, VBat2 = -32 V, RLC=32.4 kΩ,
IL = 27 mA. RL = 600 Ω, RF1= RF2 = 0, RRef = 49.9 kΩ, CHP = 47 nF, CLP=0.15 µF, RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ,
RR = 52.3 kΩ ROV = ∞, unless otherwise specified. Current definition: current is positive if flowing into a pin.
Ref
Parameter fig Conditions Min Typ Max Unit
Two-wire port
Overload level, VTRO ,ILdc > 18mA 2 Active state,
1% THD, ROV = ∞2.7 VPeak
On-Hook, ILdc < 5mA Note 1 1.1 VPeak
Input impedance, ZTR Note 2 ZT/200
Longitudinal impedance, ZLOT, ZLOR 0 < f < 100 Hz 20 35 Ω/wire
Longitudinal current limit, ILOT, ILOR active state 28 mArms /wire
Longitudinal to metallic balance, BLM IEEE standard 455-1985, ZTRX=736Ω
0.2 kHz < f < 1.0 kHz, Tamb 0-70°C63 66 dB
1.0 kHz < f < 3.4 kHz, Tamb 0-70°C60 66 dB
0.2 kHz < f < 1.0 kHz, Tamb -40-85°C60 66 dB
1.0 kHz < f < 3.4 kHz, Tamb -40-85°C55 66 dB
Longitudinal to metallic balance, BLME 3
Longitudinal to four wire balance BLFE 3 0.2 kHz < f < 1.0 kHz, Tamb 0-70°C63 66 dB
1.0 kHz < f < 3.4 kHz, Tamb 0-70°C60 66 dB
0.2 kHz ≤ f ≤ 1.0 kHz, Tamb -40-85°C60 66 dB
1.0 kHz < f < 3.4 kHz, Tamb -40-85°C55 66 dB
Metallic to longitudinal balance, BMLE 4 0.2 kHz < f < 3.4 kHz 40 50 dB
VTR
BMLE = 20 · Log ; ERX = 0
VLO
Figure 2. Overload level, VTRO , two-wire
port
1
<< RL, RL= 600 Ω
ωC
RT = 120 kΩ, RRX = 60 kΩ
Figure 3. Longitudinal to metallic (BLME)
and Longitudinal to four-wire (BLFE)
balance
1
<< 150 Ω, RLR =RLT =RL /2=300Ω
ωC
RT = 120 kΩ, RRX = 60 kΩ
BLME = 20 · Log
BLFE = 20 · Log
VTR
ELo
ELo
PBL 386 30/2
TIPX
RINGX RSN
VTX
RT
RRX
ERX
RLVTRO ILDC
C
PBL 386 30/2
TIPX
RINGX RSN
VTX
R
T
R
RX
V
TX
R
LT
C
V
TR
R
LR
E
Lo
PBL 386 30/2
4
Parameter fig Conditions Min Typ Max Unit
Four-wire to longitudinal balance, BFLE 4 0.2 kHz < f < 3.4 kHz 40 50 dB
ERX
BFLE = 20 · Log VLo
Two-wire return loss, r |ZTR + ZL|
r = 20 · Log |ZTR - ZL|
0.2 kHz < f < 1.0 kHz 30 35 dB
1.0 kHz < f < 3.4 kHz, Note 3 20 22 dB
TIPX idle voltage, VTi active, IL < 5 mA - 1.3 V
RINGX idle voltage, VRi active, IL < 5 mA VBat +3.0 V
VTR active, IL < 5 mA VBat +4.3 V
Four-wire transmit port (VTX)
Overload level, VTXO, IL > 18mA 5 Load impedance > 20 kΩ, 2.7 VPeak
1% THD, Note 4
On-hook, IL < 5mA 1.1 VPeak
Output offset voltage, ∆VTX -100 0 100 mV
Output impedance, zTX 0.2 kHz < f < 3.4 kHz 15 50 Ω
Four-wire receive port (RSN)
Receive summing node (RSN) DC voltage IRSN = -55 µA 1.15 1.25 1.35 V
Receive summing node (RSN) impedance 0.2 kHz < f < 3.4 kHz 8 20 Ω
Receive summing node (RSN) 0.3 kHz < f < 3.4 kHz
current (IRSN) to metallic loop current (IL) 200 ratio
gain,αRSN
Frequency response
Two-wire to four-wire, g2-4 6 relative to 0 dBm, 1.0 kHz. ERX = 0 V
0.3 kHz < f < 3.4 kHz -0.20 0.10 dB
f = 8.0 kHz, 12 kHz, 16 kHz -1.0 0.1 dB
Figure 4. Metallic to longitudinal and four-
wire to longitudinal balance
1
<< 150 Ω, RLT = RLR = RL /2 =300Ω
ωC
RT = 120 kΩ, RRX = 60 kΩ
Figure 5. Overload level, VTXO, four-wire
transmit port
1
<< RL, RL = 600 Ω
ωC
RT = 120 kΩ, RRX = 60 kΩ
Ref
PBL 386 30/2
TIPX
RINGX RSN
VTX
RT
RRX
RLILDC
C
EL
VTXO
PBL 386 30/2
TIPX
RINGX RSN
VTX
R
T
R
RX
E
RX
R
LT
CV
TR
R
LR
V
Lo
PBL 386 30/2
5
Four-wire to two-wire, g4-2 6 relative to 0 dBm, 1.0 kHz. EL=0 V
0.3 kHz < f < 3.4 kHz -0.2 0.1 dB
f = 8 kHz, 12 kHz, -1.0 0 dB
16 kHz -2.0 0 dB
Four-wire to four-wire, g4-4 6 relative to 0 dBm, 1.0 kHz, EL=0 V
0.3 kHz < f < 3.4 kHz -0.2 0.1 dB
Insertion loss
Two-wire to four-wire, G2-4 6 0 dBm, 1.0 kHz, Note 5
VTX
G2-4 = 20 · Log ; ERX = 0 -0.2 0.2 dB
VTR
PTG = AGND -6.22 -6.02 -5.82 dB
Four-wire to two-wire, G4-2 6 0 dBm, 1.0 kHz, Note 6
VTR
G4-2 = 20 · Log ; EL = 0 -0.2 0.2 dB
ERX
Gain tracking
Two-wire to four-wire 6 Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +3 dBm -0.1 0.1 dB
-55 dBm to -40 dBm -0.2 0.2 dB
Four-wire to two-wire 6 Ref. -10 dBm , 1.0 kHz
-40 dBm to +3 dBm -0.1 0.1 dB
-55 dBm to -40 dBm -0.2 0.2 dB
Noise
Idle channel noise at two-wire C-message weighting 12 dBrnC
(TIPX-RINGX) or four-wire (VTX) output Psophometrical weighting -78 dBmp
Note 8
Harmonic distortion
Two-wire to four-wire 6 0 dBm -67 -50 dB
Four-wire to two-wire 0.3 kHz < f < 3.4 kHz -67 -50 dB
Battery feed characteristics
Loop current, IL , in the current 12 18mA ≤ IL ≤ 45 mA 0.92 ILIL1.08 ILmA
limited region, reference A, B & C
Open circuit state loop current, ILOC RL = 0Ω-100 0 100 µA
Ref
Parameter fig Conditions Min Typ Max Unit
Figure 6.
Frequency response, insertion loss,
gain tracking.
1
<< RL, RL = 600 kΩ
ωC
RT = 120 kΩ, RRX = 60 kΩ
PBL 386 30/2
TIPX
RINGX RSN
VTX
RT
RRX
ERX
RLVTR ILDC
C
EL
VTX
PBL 386 30/2
6
Loop current detector
Programmable threshold, ILTh ILTh = 500 0.85·ILTh ILTh 1.15·ILTh mA
RLD
RLD in kΩ, ILTh ≥ 7 mA
Ring trip comparator
Offset voltage, ∆VDTDR Source resistance, RS = 0 Ω-20 0 20 mV
Input bias current, IBIB = (IDT + IDR)/2 -200 -20 200 nA
Input common mode range, VDT, VDR VBat+1 -1 V
Ring relay driver
Saturation voltage, VOL IOL = 50 mA 0.2 0.5 V
Off state leakage current, ILk VOH = 12 V 10 µA
Digital inputs (C1, C2)
Input low voltage, VIL 0 0.5 V
Input high voltage, VIH 2.5 VCC V
Input low current, IIL VIL = 0.5 -50 µA
Input high current, IIH VIH = 2.5 V 50 µA
Detector output (DET)
Output low voltage IOL = 0.5 mA 0.7 V
Internal pull-up resistor 15 kΩ
Power dissipation (VBat = -48V,VBat2 = -32V)
P1Open circuit state, C1, C2 = 0, 0 10 15 mW
Active state, C1, C2 = 0, 1
P2Longitudinal current = 0 mA, I L=0 mA (on-hook) 65 85 mW
P3RL =300Ω (off-hook) 730 mW
P4RL =800Ω (off-hook) 360 mW
Power supply currents (VBat = -48V)
VCC current, ICC Open circuit state 1.2 2.0 mA
VBat current, IBat -0.10 -0.05 mA
VCC current, ICC Active state 2.8 4.0 mA
VBat current, IBat On-hook, Long Current = 0 mA -1.5 -1.0 mA
Power supply rejection ratios
VCC to 2- or 4-wire port Active State 30 42 dB
VBat to 2- or 4-wire port f= 1kHz, Vn = 100mV 36 45 dB
VBat2 to 2- or 4-wire port 40 60 dB
Temperature guard
Junction threshold temperature, TJG 145 °C
Thermal resistance
28-pin PLCC, θJP28plcc 39 °C/W
24-pin SOIC, θJP24soic 43 °C/W
24-pin SSOP, θJP24ssop 55 °C/W
Parameter fig Conditions Min Typ Max Unit
Ref
PBL 386 30/2
7
Notes
1. The overload level can be adjusted with the ROV resistor
for higher levels e.g. min 3.1 VPeak and is specified at the
two-wire port with the signal source at the four-wire
receive port.
2. The two-wire impedance is programmable by selection of
external component values according to:
ZTRX = ZT/|G2-4S α RSN| where:
ZTRX = impedance between the TIPX and RINGX
terminals
ZT= programming network between the VTX and RSN
terminals
G2-4S = transmit gain, nominally = 1 (or 0.5 see pin PTG)
α RSN = receive current gain, nominally = 200 (current
defined as positive flowing into the receivesumm-
ing node, RSN, and when flowing from ring to tip).
3. Higher return loss values can be achieved by adding a
reactive component to RT, the two-wire terminating
impedance programming resistance, e.g. by dividing RT
into two equal halves and connecting a capacitor from the
common point to ground.
4. The overload level level can be adjusted with the ROV
resistor for higher levels e.g. min 3.1 VPeak and is specified
at the four-wire transmit port, VTX, with the signal source
at the two-wire port. Note that the gain from the two-wire
port to the four-wire transmit port is G2-4S = 1 (or 0.5 see
pin PTG)
5. Pin PTG = Open sets transmit gain to nom. 0.0dB
Pin PTG = AGND sets transmit gain to nom. -6.02 dB
Secondary protection resistors RF impact the insertion loss
as explained in the text, section Transmission. The
specified insertion loss is for RF = RP = 0.
6. The specified insertion loss tolerance does not include
errors caused by external components.
7. The level is specified at the two-wire port.
8. The two-wire idle noise is specified with the port
terminated in 600 Ω (RL) and with the four-wire receive
port grounded (ERX = 0; see figure 6).
The four-wire idle noise at VTX is specified with the two-
wire port terminated in 600 Ω (RL). The noise specification
is referenced to a 600 Ω programmed two-wire impedance
level at VTX. The four-wire receive port is grounded
(ERX = 0).
PBL 386 30/2
8
Pin Description
Figure 7. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view.
Refer to figure 7.
PLCC Symbol Description
1 PTG Prog. Transmit Gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB.
2 RRLY Ring Relay driver output. The relay coil may be connected to maximum +14V.
3 HP Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX.
4NCNo internal Connection
5 RINGX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
6 BGND Battery Ground, should be tied together with AGND.
7 TIPX The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
8 VBAT Battery supply Voltage. Negative with respect to AGND.
9 VBAT2 An optional second (2) Battery Voltage connects to this pin.
10 PSG Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a
resistor connected from this pin to VBAT.
11 NC No internal Connection
12 LP Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT.
13 DT Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
14 DR Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
1
2
3
4
5
6
7
8
9
10
11
24
23
22
21
20
19
18
17
16
15
14
RRLY
PTG
HP
RINGX
BGND
TIPX
VBAT
LP
POV
VTX
AGND
C2
RSN
REF
PLD
VCC
C1
DT
PSG
PLC
VBAT2
DET
12 13
DR NU
24-pin SOIC
and
24-pin SSOP
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4
3
2
1
28
27
26
12
13
14
15
16
17
18
PTG
RRLY
HP
NC
BGND
TIPX
VBAT
VBAT2
PSG
LP
NC
DT
DR
NU
C2
C1
DET
VCC
NC
PLD
POV
PLC
REF
NC
AGND
RSN
VTX
RINGX
28-pin PLCC
PBL 386 30/2
9
SLIC Operating States
State C2 C1 SLIC operating state Active detector
0 0 0 Open circuit -
1 0 1 Ringing state Ring trip detector (active low)
2 1 0 Active state Loop detector (active low)
3 1 1 Not applicable -
Table 1. SLIC operating states.
15 NU Pin Not Used. Must be connected to AGND.
16 C2 C1 and C2 are digital inputs (internal pull-up) controlling the SLIC operating states.
17 C1 Refer to section "Operating states" for details.
18 DET Detector output. Active low when indicating loop detection and ring trip.
19 NC No internal Connection
20 VCC +5 V power supply.
21 PLD Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
22 POV Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 2.7 V in
off-hook and min 1.1 V in On-hook. If a resistor is connected between this pin and AGND: the overhead
voltage can be set to higher values.
23 PLC Prog. Line Current, the current limit, reference C in figure 12, is programmed by a resistor connected from
this pin to AGND.
24 REF A Reference, 49.9 kΩ, resistor should be connected from this pin to AGND.
25 NC No internal Connection
26 RSN Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal)
AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain
connect to the receive summing node. A resistor should be connected from this pin to AGND.
27 AGND Analog Ground, should be tied together with BGND.
28 VTX Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin PTG).
The two-wire impedance programming network connects between VTX and RSN.
PBL 386 30/2
10
Functional Description
and Applications Informa-
tion
Transmission
General
A simplified ac model of the transmission
circuits is shown in figure 8. Circuit analysis
yields:
(1)
(2)
VTR = EL - IL · ZL(3)
where:
VTX is a ground referenced version of the
ac metallic voltage between the TIPX
and RINGX terminals.
G2-4S is the programmable SLIC two-wire
to four-wire gain (transmit direction).
See note below.
VTR is the ac metallic voltage between
tip and ring.
ELis the line open circuit ac metallic
voltage.
ILis the ac metallic current.
RFis a fuse resistor.
RPis part of the SLIC protection
ZLis the line impedance.
ZTdetermines the SLIC TIPX to RINGX
impedance at voice frequencies.
ZRX controls four- to two-wire gain.
V
ZV
ZI
TX
T
RX
RX
L
RSN
+=
α
VRX is the analog ground referenced re-
ceive signal.
αRSN is the receive summing node current
to metallic loop current gain = 200.
Note that the SLICs two-wire to four-wire
gain, G2-4S, is user programmable between
two fix values. Refer to the datasheets for
values on G2-4S.
Two-Wire Impedance
To calculate ZTR, the impedance presented
to the two-wire line by the SLIC including
the fuse and protection resistors RF and RP,
let: VRX = 0.
From (1) and (2):
Thus with ZTR, αRSN, G2-4S, RP and RF known:
Two-Wire to Four-Wire Gain
From (1) and (2) with VRX = 0:
Four-Wire to Two-Wire Gain
From (1), (2) and (3) with EL = 0:
For applications where
ZT/(αRSN·G2-4S) + 2RF + 2RP is chosen to be
equal to ZL the expression for G4-2 simplifies
to:
Four-Wire to Four-Wire Gain
From (1), (2) and (3) with EL = 0:
Hybrid Function
The hybrid function can easily be imple-
mented utilizing the uncommitted amplifier
in conventional CODEC/filter combinations.
Please, refer to figure 9. Via impedance ZB
a current proportional to VRX is injected into
the summing node of the combination
CODEC/filter amplifier. As can be seen
from the expression for the four-wire to
four-wire gain a voltage proportional to VRX
is returned to VTX. This voltage is converted
by RTX to a current flowing into the same
summing node. These currents can be
made to cancel by letting:
The four-wire to four-wire gain, G4-4, in-
cludes the required phase shift and thus
the balance network ZB can be calculated
from:
Figure 8. Simplified ac transmission circuit.
V
RV
ZE
TX
TX
RX
BL
+==00()
GZ
ZG
T
RX S
42 24
1
2
−−
=− ⋅
VV
GIR R
TR TX
SLFP
=+⋅+
−24 22()
ZZGRR
TR T
RSN S FP
=⋅++
−
α24 22
ZGZRR
T RSN S TR F P
=⋅ ⋅−−
−
α24 22()
GV
VZ
ZGRR
TX
TR
T RSN
T
RSN S FP
24
24
22
−
−
==
⋅++
/α
α
GV
V
Z
ZZ
ZGZRR
TR
RX
T
RX
L
T
RSN SL F P
42
24
22
−
−
==
−⋅ +⋅++
α()
GV
V
Z
ZGZRR
ZGZRR
TX
RX
T
RX
SL F P
T
RSN SL F P
44
24
24
22
22
−
−
−
==
−⋅ ⋅+ +
+⋅++
()
()
α
ZR
V
V
RZ
Z
ZGZRR
GZRR
BTX
RX
TX
TX RX
T
T
RSN SL F P
SL F P
=− ⋅ =
⋅⋅ +⋅++
⋅++
−
−
α24
24
22
22
()
()
PBL 386 30/2
+
-
+
-
VTX
RSN
IL/αRSN
TIPX
RINGX
+
-
EL
+
-
TIP
RING
RF
RF
ZTR
ZT
VTX
VRX
ZRX
IL
IL
RHP
+
-
ZL
VTR
RP
G2-4S
RP
PBL 386 30/2
11
When choosing RTX, make sure the output
load of the VTX terminal is >20 kΩ.
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is recom-
mended. Contact Ericsson Microelectron-
ics for assistance.
The PBL 386 30/2 SLIC may also be
used together with programmable CODEC/
filters. The programmable CODEC/filter
allows for system controller adjustment of
hybrid balance to accommodate different
line impedances without change of hard-
ware. In addition, the transmit and receive
gain may be adjusted. Please, refer to the
programmable CODEC/filter data sheets
for design information.
Longitudinal Impedance
A feed back loop counteracts longitudinal
voltages at the two-wire port by injecting
longitudinal currents in opposing phase.
Thus longitudinal disturbances will ap-
pear as longitudinal currents and the TIPX
and RINGX terminals will experience very
small longitudinal voltage excursions, leav-
ing metallic voltages well within the SLIC
common mode range.
The SLIC longitudinal impedance per
wire, ZLoT and ZLoR, appears as typically
20Ω to longitudinal disturbances. It should
be noted that longitudinal currents may
exceed the dc loop current without disturb-
ing the vf transmission.
Capacitors CTC and CRC
The capacitors designated CTC and CRC
in figure 11, connected between TIPX
and ground as well as between RINGX
and ground, can be used for RFI filtering.
The recommended value for CTC and CRC
is 2200 pF. Higher capacitance values
may be used, but care must be taken to
prevent degradation of either longitudinal
balance or return loss. CTC and CRC
contribute to a metallic impedance of
1/(π⋅f⋅CTC) = 1/(π⋅f⋅CRC), a TIPX to ground
impedance of 1/(2⋅π⋅f⋅CTC) and a RINGX
to ground impedance of 1/(2⋅π⋅f⋅CRC).
Figure 9. Hybrid function.
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HP and TIPX provides
the separation of the ac signal from the dc
part. CHP positions the low end frequency
response break point of the ac loop in the
SLIC. Refer to table 1 for recommended
values of CHP.
Example: A CHP value of 150 nF will posi-
tion the low end frequency response 3dB
break point of the ac loop at 1,8 Hz (f3dB)
according to f3dB = 1/(2⋅π⋅RHP⋅CHP) where
RHP = 600 kΩ.
High-Pass Transmit Filter
The capacitor CTX in figure 11 connected
between the VTX output and the CODEC/
filter forms, together with RTX and/or the
input impedance of a programmable
CODEC/filter, a high-pass RC filter. It is
recommended to position the 3 dB break
point of this filter between 30 and 80 Hz to
get a faster response for the dc steps that
may occur at DTMF signalling.
Capacitor CLP
The capacitor CLP, which connects between
the terminals CLP and VBAT, positions
together with the resistive loop feed resis-
tor RSG (see section Battery Feed), the high
end frequency break point of the low pass
filter in the dc loop in the SLIC. CLP together
with RSG, CHP and ZT (see section Two-Wire
Impedance) forms the total two wire output
impedance of the SLIC. The choise of
these programmable components have an
influence on the power supply rejection
ratio (PSRR) from VBAT to the two wire
side at sub-audio frequencies. At these
frequencies capacitor CLP also influences
the transversal to longitudinal balance in
the SLIC. Table 1 suggests suitable values
on CLP for different feeding characteristics.
Typical values of the transversal to longitu-
dinal balance (T-L bal.) at 200Hz is given in
table 1 for the chosen values on CLP.
RFeed RSG CLP T-L bal. CHP
@200Hz
[
Ω
][k
Ω
] [nF] [dB] [nF]
2⋅50 0 150 -46 47
2⋅200 60,4 100 -46 150
2⋅400 147 47 -43 150
2⋅800 301 22 -36 150
Table 1. RSG , CLP and CHP values for differ-
ent feeding characteristics.
V
T
Combination
CODEC/Filter
R
TX
R
FB
Z
B
Z
RX
Z
T
VTX
RSN
V
RX
PBL
386 30/2
PBL 386 30/2
12
tions and to fit both single and dual battery
feed CODECs. The RSN terminal, con-
necting to the CODEC receive output via
the resistor RRX, is dc biased with +1,25V.
This makes it possible to compensate for
currents floating due to dc voltage differ-
ences between RSN and the CODEC out-
put without using any capacitors. This is
done by connecting a resistor RR between
the RSN terminal and ground. With current
directions defined as in figure 13, current
summation gives:
where VCODEC is the reference voltage of the
CODEC at the receive output.
From this equation the resistor RR can be
calculated as
For values on IRSN, see table 3.
The resistor RR has no influence on the ac
transmission.
SLIC IRSN [
µ
A]
PBL 386 30/2 -55
Table 3. The SLIC internal bias current with
the direction of the current defined as posi-
tive when floating into the terminal RSN.
Battery Feed
The PBL 386 30/2 SLIC emulate resistive
loop feed, programmable between 2·50 Ω
and 2·900 Ω, with adjustable current limita-
tion. In the current limited region the loop
current has a slight slope corresponding to
2·30 kΩ, see figure 12 reference B.
The open loop voltage measured be-
tween the TIPX and RINGX terminals is
tracking the battery voltage VBat. The sig-
nalling headroom, or overhead voltage VTRO,
is programmable with a resistor ROV con-
nected between terminal POV on the SLIC
and ground. Please refer to section “Pro-
grammable overhead voltage(POV)”.
The battery voltage overhead, VOH, de-
pends on the programmed signal overhead
voltage. VOH defines the TIP to RING volt-
age at open loop conditions according to
VTR(at IL = 0 mA) = |VBat| - VOH.
Refer to table 2 for typical values on VOH
and VOHVirt. The overhead voltage is changed
when the line current is approaching open
loop conditions. To ensure maximum open
loop voltage, even with a leaking telephone
line, this occurs at a line current of approxi-
mately 6 mA. When the overhead voltage
has changed, the line voltage is kept nearly
constant with a steep slope corresponding
to 2·25 Ω(reference G in figure 12).
The virtual battery overhead, VOHvirt, is
defined as the difference between the bat-
tery voltage and the crossing point of all
possible resistive feeding slopes, see fig-
ure 12 reference J. The virtual battery over-
head is a theoretical constant needed to be
able to calculate the feeding characteris-
tics.
SLIC VOH(typ) VOHvirt(typ)
(V) (V)
PBL 386 30/2 3.0 +VTRO 4.9 +VTRO
Table 2. Battery overhead.
The resistive loop feed (reference D in
figure 12) is programmed by connecting a
resistor, RSG, between terminals PSG and
VBAT according to the equation:
RFeed = RSG + 2 · 104 + 2RF
200
where RFeed is in Ω for RSG and RF in Ω.
The current limit (reference C in figure
12) is adjusted by connecting a resistor,
RLC, between terminal PLC and ground
according to the equation:
RLC = 1000
ILProg + 4
where RLC is in kΩ for ILProg in mA.
A second, lower battery voltage may be
connected to the device at terminal VBAT2
to reduce short loop power dissipation. The
SLIC automatically switches between the
two battery supply voltages without need
for external control. The silent battery
switching occurs when the line voltage
passes the value
|VB2| - 40·IL - (VOHVirt -1,3), if IL > 6mA.
For correct functionality it is important to
connect the terminal VBAT2 to the second
power supply via the diode DVB2 in figure 11.
An optional diode DBB connected be-
tween terminal VB and the VB2 power
supply, see figure 11, will make sure that
the SLIC continues to work on the second
battery even if the first battery voltage dis-
appears.
If a second battery voltage is not used,
VBAT2 is connected to VBAT on the SLIC
and CVB2, DBB and DVB2 are removed.
Metering applications
For designs with metering applications
please contact Ericsson Microelectronics
for assistance.
CODEC Receive Interface
The PBL 386 30/2 SLIC have got a com-
pletely new receive interface at the four
wire side which makes it possible to reduce
the number of capacitors in the applica-
−=+ +=
+−+
IIII
RV
RR
RSN RT RRX RR
T
CODEC
RX R
125 125 125,, ,
RIRV
R
R
RSN T
CODEC
RX
=−−−−
125
125 125
,
,,
Figure 10. Programmable overhead voltage (POV). RL = 600
Ω
or
∞
.
0 102030405060
0
1
2
3
4
5
6
7
off-hook
on-hook
VTRO (V
Peak
)
Rov (KΩ)
PBL 386 30/2
13
Figure 11. Single-channel subscriber line interface with PBL 386 30/2 and combination CODEC/filter.
RESISTORS: (Values according to IEC E96
series)
RSG = 0 Ω1% 1/10 W
RLD = 49,9 kΩ1% 1/10 W
ROV = User programmable
RLC = 32,4 kΩ1% 1/10 W
RREF = 49,9 kΩ1% 1/10 W
RR= 64,9 kΩ1% 1/10 W
RT= 105 kΩ1% 1/10 W
RTX = 24,9 kΩ1% 1/10 W
RB= 22,1 kΩ1% 1/10 W
RRX = 52,3 kΩ1% 1/10 W
RFB Depending on CODEC / filter
R1= 604 kΩ1% 1/10 W
R2= 604 kΩ1% 1/10 W
R3= 249 kΩ1% 1/10 W
R4= 280 kΩ1% 1/10 W
RRT = 330 Ω5% 2 W
RF1, RF2 = Line resistor, 40 Ω 1% match
RP1, RP2 = 10 Ω1% 1/10 W,(Note 1)
CAPACITORS: (Values according to IEC
E96 series)
CVB = 100 nF 100 V 10%
CVB2 = 150 nF 100 V 10%
CVCC = 100 nF 10 V 10%
CTC = 2,2 nF 100 V 10%
CRC = 2,2 nF 100 V 10%
CHP = 47 nF 100 V 10%
CLP = 150 nF 100 V 10%
CTX = 100 nF 10 V 10%
CGG = 220 nF 100 V 10%
C1= 330 nF 63 V 10%
C2= 330 nF 63 V 10%
DIODES:
DVB = 1N4448
DVB2 = 1N4448
DBB = 1N4448
OVP:
Secondary protection ( e. g. Power
Innovations TISPPBL2). The ground
terminals of the secondary protection should
be connected to the common ground on the
Printed Board Assembly with a track as
short and wide as possible, preferable a
groundplane.
R
LC
R
RX
R
REF
R
LD
C
VCC
C
TX
PBL 386 30/2
R
TX
0
-
+
0
CODEC/
Filter
R
FB
SYSTEM CONTROL
INTERFACE
R
R
R
T
R
B
-
+
VCC
VCC
BGND
TIPX
VBAT
VBAT2
PLC
POV
PLD
VCC
PSG
NC
LP
DT
NC
DET
C1
C2
RRLY
HP
NC
RINGX
AGND
RSN
NC
REF
PTG VTX
DR NU
PBL 386 30/2
R
OV
R
SG
C
LP
C
1
R
4
C
2
R
3
C
HP
VB2
SLIC No. 2 etc.
C
RC
R
P2
R
P1
R
F2
R
F1
TIP
RING
OVP
C
GG
C
TC
VB
+12 V /+5V
K
R
C
VB
D
VB2
C
VB2
D
BB
VB D
VB
R
RT
E
RG
R
2
R
1
Programmable overhead
voltage(POV)
With the POV function the overhead
voltage can be increased.
If the POV pin is left open the overhead
voltage is internally set to 3,2 VPeak in off-
hook and 1,3 VPeak on-hook. If a resistor
ROV is connected between the POV pin
and AGND, the overhead voltage can be
set to higher values, typical values can
be seen in figure 10. The ROV and
corresponding VTRO (signal headroom)
are typical values for THD <1% and the
signal frequency 1000Hz.
Observe that the 4-wire output terminal
VTX can not handle more than 3,2 VPeak.
So if the gain 2-wire to 4-wire is 0dB,
3,2 VPeak is maximum also for the 2-wire
side. Signal levels between 3,2 and
6,4 VPeak on the 2-wire side can be
handled with the PTG shorted so that the
gain G2-4S become -6,02dB. Please note
that the two-wire impedance, RR and the
4-wire to 4-wire gain has to be recalcu-
lated if the PTG is shorted.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 9 mA.
How to use POV:
1. Decide what overhead voltage(VTRO) is
needed. The POV function is only
needed if the overhead voltage
exceeds 3,2 VPeak
2. In figure 10 the corresponding ROV for
the decided VTRO can be found.
3. If the overhead voltage exceeds
3,2 VPeak, the G2-4S gain has to be
changed to -6,02dB by connecting the
PTG pin to AGND. Please note that
the two-wire impedance, RR and the 4-
wire to 4-wire gain has to be recalcu-
lated.
NOTE:
1. RP1 and RP2 may be omitted if DVB is in place.
PBL 386 30/2
14
Analog Temperature Guard
The widely varying environmental condi-
tions in which SLICs operate may lead to
the chip temperature limitations being ex-
ceeded. The PBL 386 30/2 SLIC reduce
the dc line current when the chip tempera-
ture reaches approximately 145°C and in-
creases it again automatically when the
temperature drops. Accordingly transmis-
sion is not lost under high ambient tem-
perature conditions.
The detector output, DET, is forced to a
logic low level when the temperature guard
is active.
Loop Monitoring Functions
The loop current and ring trip detector
report their status through a common out-
put, DET. The detector to be connected to
DET is selected via the two bit wide control
interface C1 and C2. Please refer to sec-
tion Control Inputs for a description of the
control interface.
Loop Current Detector
The loop current detector is indicating
that the telephone is off hook and that
current is flowing in the loop by putting the
output DET to a logical low level when
selected.The loop current threshold value,
ILTh, at which the loop current detector
changes state is programmable by select-
ing the value of resistor RLD. RLD connects
between pin PLD and ground and is calcu-
lated according to
RLD = 500
ILTh
The current detector is internally filtered
and is not influenced by the ac signal at the
two wire side.
Ring Trip Detector
Ring trip detection is accomplished by con-
necting an external network to a compara-
tor in the SLIC with inputs DT and DR. The
ringing source can be balanced or unbal-
anced superimposed on VB or GND. The
unbalanced ringing source may be applied
to either the ring lead or the tip lead with
return via the other wire. A ring relay driven
by the SLIC ring relay driver connects the
ringing source to tip and ring.
Figure 12. Battery feed characteristics (without the protection resistors on the line).
C
D
B
A
E
G
FF
J
H
CB
D
A
V
TR
[V]
I
L
[mA]
DC characteristics
A: IL (@ VTR = 0V) = ILProg + |VBat| - VOHVirt - RFeed · (ILProg + 4·10-3)
60 · 103
B: RfeedB = 2 · 30 kΩ
C: ILConst(typ)= ILProg = 103 - 4·10-3
RLC
VTR = |VBat| - VOHvirt - RFeed · (ILProg + 4·10-3)
D: RFeed = RSG + 2 · 104
200
E: IL ≈ 6 mA
F: Apparent battery VBat(@ IL = 0) =|VBat| - VOHvirt - RFeed · 4·10-3)
G: RfeedG = 2 · 25 Ω
H: VTROpen = |VBat| - VOH
J: Virtual battery VBatVirt (@ IL = 4 mA) = |VBat| - VOHVirt
PBL 386 30/2
15
The ring trip function is based on a polar-
ity change at the comparator input when
the line goes off-hook. In the on-hook state
no dc current flows through the loop and
the voltage at comparator input DT is more
positive than the voltage at input DR. When
the line goes off-hook, while the ring relay
is energized, dc current flows and the
comparator input voltage reverses polarity.
Figure 11 gives an example of a ring trip
detection network. This network is applica-
ble, when the ring voltage is superimposed
on VB and is injected on the ring lead of the
two-wire port. The dc voltage across sense
resistor RRT is monitored by the ring trip
comparator input DT and DR via the net-
work R1, R2, R3, R4, C1 and C2. With the line
on-hook (no dc current) DT is more positive
than DR and the DET output will report
logic level high, i.e. the detector is not
tripped. When the line goes off-hook, while
ringing, a dc current will flow through the
loop including sense resistor RRT and will
cause input DT to become more negative
than input DR. This changes output DET to
logic level low, i.e. tripped detector condi-
tion. The system controller (or line card
processor) responds by de-energizing the
ring relay, i.e. ring trip.
Complete filtering of the 20 Hz ac com-
ponent at terminal DT and DR is not neces-
sary. A toggling DET output can be exam-
ined by a software routine to deter-mine the
duty cycle. When the DET output is at logic
level low for more than half the time, off-
hook condition is indicated.
Relay driver
The PBL 386 30/2 SLIC incorporates a
ring relay driver designed as open
collector (npn) with a current sinking
capability of 50 mA. The drive transistor
emitter is connected to BGND. The relay
driver has an internal zener diode clamp
for inductive kick-back voltages. Care
must be taken when using the relay
driver together with relays that have high
impedance.
Control Inputs
The PBL 386 30/2 SLIC have two digital
control inputs, C1 and C2.
A decoder in the SLIC interprets the
control input condition and sets up the
commanded operating state.
C1 and C2 are internal pull-up inputs.
Open Circuit State
In the Open Circuit State the TIPX and
RINGX line drive amplifiers as well as other
circuit blocks are powered down. This
causes the SLIC to present a high imped-
ance to the line. Power dissipation is at a
Figure 13. CODEC receive interface.
PBL386 30/2
CODEC
+
_
VTX
RSN R
RX
R
T
R
R
I
RRX
I
RSN
I
RT
I
RR
U
REFcodec
+1.25 V
I
DC-GND
minimum and no detectors are active.
Ringing State
The ring relay driver and the ring trip detec-
tor are activated and the ring trip detector is
indicating off hook with a logic low level at
the detector output.
The SLIC is in the active normal state.
Active State
TIPX is the terminal closest to ground and
sources loop current while RINGX is the
more negative terminal and sinks loop cur-
rent. Vf signal transmission is normal and
the loop current detector is activated. The
loop current detector is indicating off hook
with a logic low level present at the detector
output.
Overvoltage Protection
The PBL 386 30/2 SLIC must be protected
against overvoltages on the telephone line
caused by lightning, ac power contact and
induction. Refer to Maximum Ratings, TIPX
and RINGX terminals, for maximum allow-
able continuous and transient currents that
PBL 386 30/2
16
Ordering Information
Package Temp. Range Part No.
24 pin SSOP Tape & Reel -40° - +85° C PBL 386 30/2SHT
24 pin SOIC Tube -40° - +85° C PBL 386 30/2SOS
24 pin SOIC Tape & Reel -40° - +85° C PBL 386 30/2SOT
28 pin PLCC Tube -40° - +85° C PBL 386 30/2QNS
28 pin PLCC Tape & Reel -40° - +85° C PBL 386 30/2QNT
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third parties
which may result from its use. No license is granted by
implication or otherwise under any patent or patent
rights of Ericsson Microelectronics. These products
are sold only according to Ericsson Microelectronics'
general conditions of sale, unless otherwise confirmed
in writing.
Specifications subject to change without
notice.
1522-PBL 386 30/2 Uen Rev. B
© Ericsson Microelectronics AB 2000
Ericsson Microelectronics AB
SE-164 81 Kista-Stockholm, Sweden
Telephone: +46 8 757 50 00
This product is an original Ericsson
product protected by US, European and
other patents.
may be applied to the SLIC.
Secondary Protection
The circuit shown in figure 11 utilizes series
resistors together with a programmable
overvoltage protector
(e.g. Power Innovations TISPPBL2), serv-
ing as a secondary protection.
The TISPPBL2 is a dual forward-con-
ducting buffered p-gate overvoltage pro-
tector. The protector gate references the
protection (clamping) voltage to negative
supply voltage (i e the battery voltage, VB).
As the protection voltage will track the
negative supply voltage the overvoltage
stress on the SLIC is minimized.
Positive overvoltages are clamped to
ground by a diode. Negative overvoltages
are initially clamped close to the SLIC nega-
tive supply rail voltage and the protector will
crowbar into a low voltage on-state condi-
tion, by firing an internal thyristor.
A gate decoupling capacitor, C GG, is
needed to carry enough charge to supply a
high enough current to quickly turn on the
thyristor in the protector. C GG shall be
placed close to the overvoltage protection
device. Without the capacitor even the low
inductance in the track to the VBat supply will
limit the current and delay the activation of
the thyristor clamp.
The fuse resistors RF serve the dual
purposes of being non- destructive energy
dissipators, when transients are clamped
and of being fuses, when the line is ex-
posed to a power cross.
If a PTC is chosen for RF, note that it is
important to always use PTC´s in series
with resistors not sensitive to temperature,
as the PTC will act as a capacitance for fast
transients and therefore will not protect the
SLIC.
Power-up Sequence
No special power-up sequence is neces-
sary except that ground has to be present
before all other power supply voltages.
Printed Circuit Board Layout
Care in PCB layout is essential for proper
function. The components connecting to
the RSN input should be placed in close
proximity to that pin, so that no interference
is injected into the RSN pin. Ground plane
surrounding the RSN pin is advisable.
Analog ground (AGND) should be con-
nected to battery ground (BGND) on the
PCB in one point.
The capacitors for the battery should be
connected with short wide leads of the
same length.
