Dynamic Shift Registers MM4012/MM5012 dual 256-bit dynamic shift register general description The MM4012/MM5012 dual 256-bit dynamic shift register is a monolithic MOS integrated circuit using P-channel enhancement mode technology to achieve bipolar compatibility. The device pro- vides full read/write control, recirculate logic and an independent wire-OR-able TRI-STATET out- put which aitows a common output bus-line to be connected between several registers. The input logic allows recirculating both registers or recirculating either register while loading the other from the data bus input, which along with the TAI-STATE bus output, is enabled by a 2. input NOR gate which allows multiple address decoding. N-bits may be added to the recirculate loop by connecting additional shift registers be- tween outputs A or B and data inputs A or 8. features @ Bipolar compatibility +5V, -12V operation No pull-up or pull-down. resistors required finn = 400 Hz at 25C tinax ~ 2.6 MHz over temperature guaranteed Wide frequency range TRISTATE output Common bus systems may be built using wire-OR Output System flexibility Chip cantains af! recir- culate logic, contrai logic and shift register for disc and drum replacement memories applications @ Disc and drum memory replacement = CRT refresh memory Serial and parallel data storage logic and connection diagrams typical application tO eemes Dual-in-Line Package sara 1 fot Yon 8 se wervts 1d ba mers aeuce | | P sonra aus autewr cvrnus conse 4 4 by putrut cuamce mus a 4 p02 sats ot meus mw ed fas varus emanie sarameete pt bre meer cuanis poy erect =I conrnen vee yew TTL/MOS Interface 21 ZLOSWW/ZLOPIAW 4 i { gtk gree sy remem5 wo absolute maximum ratings = Vottage at Any Pin Vgg + 0.3 to Ves ~ 22 2 3 = Operating Temperature MM4012 65C to +125C ~s MM5012 -28C to +70C N Storage Temperature Range ~65C to + 150C Oo Lead Temperature (Sotdering, 10 sec) 300C = electrical characteristics = T, within operating temperature range, Vsg = +5.0V #5%, Vag = -12.0V * 10%, unless otherwise noted. PARAMETER CONDITIONS MIN vr MAX UNITS: Data topes Levers Logical HIGH Level {Vial Ves -20 Ves 03 v Lopecai LOW Levet iV) Veg 42 v Dats Input Leexage ny -200V. Ta + 28 0.07 O68 A All Other Pins GNGO Data Input Capacitance Vin = DOV, 5.0 pF Ab Other P Note? Contiot input Levels Logica! HIGH Level Wen! Vis 20 Vs 103 v Logical LOW Level (Vou) Ves 42 v Gomtrot Input Leakage Vin -200V Ta 26 C. oo as 4a All Other Puss GND Cantrol input Capacitance Vin O0V. 4 = Met, 10 100 pF Hy AW Ornae Pros GND. Note 2 Clock bnput Levets, H Logwal HIGH Level Vga! Veg- 15 V55 103 v Logical LOW Level (Vo! Vgg - 18.6 Ves - 145 v Crock Input Leakage Vg> -20V Tat WC. 008 1.0 rr All Other Pins GND Clock tnpur Capacitance Vos GOV t+ 1 MHz, 110. 175 pF : Data Output Levels Logicat HIGH Level (Wor? Igounce * -O5 mA 24 Vss v . Logrcal LOW Level (Voy) Ign = 16 A, a4 v fe Data Bus Output Leakage Vg VS Bus Vuur Ven 10 BA li Bus Output Desabled. Ty = 25C : Power Supply Current tos. Tat 129C. Voy 2 12 Ore" 150 Ms, Veg 7 SOV Ve? 12 Oa 01.01 B01 Mir <0,0.1 MHz 40 50 ma os DOME: 78 9s mA r+ 25 Mer 130 160 ma Clack Frequency 4) Ot, + Oty + Wwe. Mote F oor 25 MHz Clock Pultewidth (Opy,) et, Oty * Qn 150 100 us Clock Phase Delay Times (G5. Ost 100 m Chock Transinon Times (et, Ot) 10 as Portal Bit Tunes (T) Note 1 Anput Par tut Bt Tome (Tay! 02 100 us Output Parad Br Tome Tour? 02 400, us Data Joput Setup Tome (to! Note 4 BO oO * Data Input Hod Teme Ion) Now 4 2 a om Output Controls Setup Time Hogs! Note Sand 4 0 n ns Output Controts Hold Time toca) Note 3 and 4 20 o ms Output Propagetion Delay wt Delay to HIGH Level (tyne! 180 250 ns Delay to LOW Level (pau) 180 250 ms Gus Output Propagation Detay { from our Delay to HIGH Impedance State from LOW Level Iga! 150 200 os trom HIGH Leval (14 10 200 ns Delay to HIGH Level [togrs) 180 260 a Delay fo LOW Lovet ito) 180 250 ms Nowe 1 Minimum clock Frequency is @ funcbon of temperature and Kbit umes Try and TOUT. se ihawn by tne oy vernon wermperature eee! Th, TOUT versus temoeratuce curves The lowest gust ciieed clock Wrequenty for any temperature can be attained Dy making TiN equal te TOUT The fmunmum guranieed clock Wrequency HOO Fa nga ante Tan 40d TQUT ey 01 tnGeE Ihe Quranic anemia Note 2. Capacitance i guaranteed by perc testing y Note 3) The vulpul controls are sampled ny din The FRE STATE output must be enabled ur disatied sens ine orm Cock time poor te the oguyT clock Vume pl mich the Ouipul 1 HRpeLIed Lo BE True OF ; ae igs atcomice state, See ting diapan Two but connertad devices may We 1: Opposite 1Um venpedaice states umultancously without Oateyeng ether Now Date input an Input Control Setup aod Holl Tomes are referenced ta the tieing evge of Me the Output Contror Timing w reterenced ta the leading sige of Gy See temang deagiar 22performance characteristics Guaranteed Maximum Partral Bit Times vs Temperature (Note 1) 1 AXEMUM Tig, Tout TIME (mes) a1 o -4 n o 1. a AMBIENT TEMPERATURE { C} Typical Data Output Sink Current vs Voltage 1 +56 OUTPUT HK CURRENT (mA) Vour () Typical Gus Output Capacitance vs Voltage Ty = 778 6 Ves = .0 OUTPUT CAPACITANCE ipF) se o38 8-100 -200 88 Your {) timing diagram 3 epee = Z 10 i z 3 = 3 z z Fan QUTPUT SOURCE CURRENT (maj Guaranteed Minimum Clock Frequency vs Temperature (Note 1} AMBIENT TEMPERATURE (C} Typical Data Output Source Curcent vs Voltage T,*2C as 1280 AVERAGE Igg mA) Veg +6.0 av Vous {) ac test circuit o weet Typical Power Supply Current vs Clock Frequency i il Fab He aan att it li ' 1 10 10008 OPERATING FREQUENCY (ine) Typical Power Supply Current vs Voltage TRISTATE Output Enabted ow = 158 me = ema we me We me we Ves ~ Yoo (} Ver * Yaa Decay | rtf cr tea | 354 | 20 pF tom =| 35% | 20 pF tor | 254 | S00F tue | 258 | 800 tors 00d Cy Only Fested an TRISTATE bus output . Yay ean / Vi Cine ote Saar a 7 We wow saat a r i | i 1 1 1 I 4, ' i ZLOSWW/ZLOPWAlogic table (notes 3, 4) MM4012/MM5012 i REGISTER enaset SELECT CONTROLS FUNCTION : CONTROL H rine pinto | ein INPUT 1 : 1 A Rigpster ts A at B Register OB anbt SELECTION 0 , 1 A Regstes tor A opt B Aegister Go ong ' 0 1 A Regier tos A nynil B Register (0 8 ingnat o o 1 A Hrgester bs A saipct B Register tee Bb argnal ' 1 o A Heyeter Ge A npat B Regstn ty B orguat . o 1 0 A Hegter te Asnpul B Reyeter to B nwa 1 a 0 8 Ragoter ty Dale Bars cpet A Regisiet A vepul 0 a 0 A Reiter to Data Bus ait B Regsiee to Bingrat PINS pina ona OUTPUT 1 + 1 TRISTATE output in ngh wmpedaner state Pg SELECTION o 1 1 TRISTATE suatpiat so Hag urpeatance state B 1 6 ' TAY ST ASE stotaaer or tig umpextany state i : 0 1 TRL STATE saatjst oe tg nnipasdince state 1 1 0 TAL STATE output ss thighs anpertann state o U o TAL STATE oettast an bigh sonpeadueie state 1 o o TRISTATE outpat connet txt ta A Regeter a 9 o FRI STATE uutpuet suerte to B Register Note 3: The output controls ave sampled by cin, The TAI STATE output must be enabled or ussabled during the @ity clock me prior to the @OUT clock time at which the Gutput 1s expected 0 be trus oF 4 in the hugh impedance state. See Liming disgeam Two bus-connected deviers may be in opposite low ; unpedance states smulteneoutly without damaging either: Note 4: Date Input and input Cantro Setup and Hold Times are referenced to the trailing edge of 4 : O1N. Wheres the Quiput Control Timing 1s referenced to the teacing edge of 11y. See timung dagram. 24Channel Matching Channel matching and crosstalk efficiency are largely dependent on board layout. The layout of Nationals dual amplifier evaluation boards are optimized to produce maximum channel matching and isolation. Typical channel matching for the CLC417 is shown in Figure 3. Channel (Bap) eseyd Channel A Magnitude (0.5dB/div) 1 10 100 Frequency (MHz) Figure 3: Channel Matching The CLC417s channel-to-channel isolation is better than 70dB for input frequencies of 4MHz. Input referred crosstalk vs. frequency is illustrated in Figure 4. -20 & @ & 3 3 s Crosstalk (dB) 2 S nN oS 1 10 100 Frequency (MHz) Figure 4: Input Referred Crosstalk vs. Frequency Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC417 will improve stability. The A, vs. Capacitive Load plot, in the Typical Performance section, gives the recommended series resistance value for optimum flatness at various capacitive loads. Power Dissipation The power dissipation of an amplifier can be described in two conditions: = Quiescent Power Dissipation - Pg (No Load Condition) = Total Power Dissipation - P+ (with Load Condition) The following steps can be taken to determine the power consumption for each CLC417 amplifier: 1. Determine the quiescent power Pa = (Vcc - Vee) * Ice 2. Determine the RMS power at the output stage Po = (Voc - Vioad) (lioad) WHETE Vicad aNd load are the RMS voltage and current across the external load. 3. Determine the total RMS power Py = Pa + Po Add the total RMS powers for both channels to determine the power dissipated by the dual. The maximum power that the package can dissipate at a given temperature is illustrated in the Power Derating curves in the Typical Performance section. The power derating curve for any package can be derived by utiliz- ing the following equation: (175 Tamb) Aja where: Tamb = Ambient temperature (C) 034 = Thermal resistance, from junction to ambient, for a given package (C/W) P= Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC417 (CLC730038 - DIP, CLC730036 - SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. Supply bypassing is required for best performance. The bypass capacitors provide a low impedance return current path at the supply pins. They also provide high frequency filtering on the power supply traces. Other layout factors play a major role in high frequency performance. The following are recommended as a basis for high frequency layout: 1. Include 6.8uF tantalum and 0.1pF ceramic capacitors on both supplies. 2. Place the 6.8uF capacitors within 0.75 inches of the power pins. 3. Place the 0.1uF capacitors less than 0.1 inches from the power pins. 4. Remove the ground plane near the input and output pins to reduce parasitic capacitance. 5. Minimize all trace lengths to reduce series inductances. Additional information is included in the evaluation board literature. Special Evaluation Board Considerations To optimize off-isolation of the CLC417, cut the R; trace on both the 730038 and 730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and output. Figure 5 indicates the alterations recommended to improve off-isolation. http:/Avww.national.com730036 Top Cut traces here 730038 Bottom e * Le e e ee? m e ee ? e eaui@u 730038 e REV B e Cut traces here Figure 5: Optional Evaluation Board Alterations SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for Nationals monolithic amplifiers that: = Support Berkeley SPICE 2G and its many derivatives m Reproduce typical DC, AC, Transient, and Noise performance = Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parame- ters. The application note OA-18, Simulation SPICE Models for Nationals Op Amps, contains schematics and a reproduction of the readme file. http:/Avww.national.com Applications Circuits Video Cable Driver The CLC417 was designed to produce exceptional video performance at all three closed-loop gains. A typical cable driving configuration is shown in Figure 6. In this example, the amplifier is configured with a gain of 2. ao ou < a IL u AML a fo) co - a V7 NOTE: i con The same technique can | 2 er also be applied . to Channel A. | | 3 PF) 250936 [6 bw, -5V a1 : L4 | 4 6.8uF >= ==0.1uF v Figure 6: Typical Cable Driver Single to Differential Line Driver The topology in Figure 7 accomplishes a single-ended to differential conversion with no external components. With this configuration, the value of Vin is limited to the common mode input range of the CLC417. +5V Voutt 7-2 VY ra | O.1NF a= 75 6.8HF i 2502 [z 2500 [pr 7] Vout2 3 ! 25008 0 1/6 HK -5V Mm : 14) [5 ty 6.8nF == ==0.1nF v Ay, = 1V/V Avy = -1V/V Vout = Vin Vin Voutz = -Vin Figure 7: Single to Differential Line Driver