ANALOG DEVICES AN-394 APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 @ 617/329-4700 An Outboard Digital-to-Analog Converter for Digital Audio Sources by Hank Zumbahlen INTRODUCTION This application note describes an AES/EBU receiver and outboard digital-to-analog converter (DAC) for use with digital audio sources. Due to the use of the AD1891 Asynchronous Sample Rate Converter (ASRC), which is at the heart of the design, the sample rate of the input signal can vary from 24 kSPS to 48 kSPS. The interpola- tion filter is implemented using the ADSP-2115 Digital Signal Processor (DSP). Great care has also been taken in the design of the analog section and power supplies. The block diagram of the complete system is shown in Figure 1. INPUT 7 AES/EBU RECEIVER ASYNCHRONOUS SAMPLE RATE CONVERTER INTERPOLATING FILTER on Fone RECONSTRUCTION RECONSTRUCTION FILTER FILTER OUT OUT Figure 1. Block Diagram BACKGROUND As the performance level of CD players has improved over the years, we have seen the separation of the trans- port and the conversion functions into two physically separate units. Separate DAC converters first appeared as performance enhancements to commercial CD play- ers, the idea being that the analog section in most CD player designs were limited in some manner, usually by cost constraints. The external DAC would also free from the power supply modulation resulting from the electro- mechanical demands of the positioning systems on the power supply in the CD or DAT transport. The use of the AD1891 ASRC chip in this design yields several benefits. First, it allows the optimization of the reconstruction filter. Since the sample rate of the output is fixed, regardless of the sample rate of the input, the reconstruction filter design need not accommodate a range of output sample rates. Secondly, the sample rate conversion process reduces the jitter on the digital signals applied to the D/A converter chip. This outboard DAC is implemented on three boards. The first board contains the digital functions, which in- clude the AES receiver and the interpolation filter. The second board contains the analog functions, the D/A converter chip, reconstruction filters and balanced out- put drivers. The power supply occupies the third board. By separating the analog function from the digital func- tion, we effectively isolate the analog ground from the digital ground, reducing coupled noise. THE DIGITAL BOARD The AES/EBU Receiver The first section of the outboard DAC converter is the AES/EBU (Audio Engineering Society/ European Broad- cast Union) receiver. The AES/EBU interface has been adopted as the standard interface linking the digital inputs and outputs of audio components. The AES/EBU interface is primarily intended for profes- sional applications. A very similar standard is the S/P DIF (Sony/Philips Digital Interface Format) which is pri- marily intended for consumer applications. There are some small differences in the channel status bits, but the main difference is that the AES/EBU interface is bal- anced (RS-422 compatible) and the S/P DIF is single ended. Impedance levels and signal amplitudes are also different.+VLI 1000 100k RESEBUIN O.1uF 14w 5% 1/4W 5% 1502 ew AWA? AW 5% U2 5 YM3623B $ 3f> 17 S750 S750 tp! 28 pout t= DATA OUT 2 ae DIN cLk Fe BIT CLOCK 8 aw UR LEFT/RIGHT y ur 5 | our emp 18 EMPHASIS 2 PLL FILTER | aps - 3) co HLDR ~ 7 fe | KMODE/ HLDL a 2000 | eal? p[]tp | 7 4700pF | 9 | @B 22 1MQ L | SEL 23 aw 5%| L st Wr POWER ON RESET) __ S2 4VL! ERR }2! MUTE 14 | 9 ~ 10pF 4s 10pF >= | | | 4Eo & 1N4148 Oo 1k i 292627] ["s 18 | AW 5% I AAA | VV | 0.01 pF >5 | vu | WORD CLOCK | | 18MHz Figure 2. The standard digital audio format consists of four sig- nals. They are the output data, which alternates between left and right channels, a bit clock, a left/right channel identification signal and a word sync (frame sync) signal. For convenience of transmission, these four signals are encoded into one composite signal and the composite signal is transmitted asynchronously down a single wire or optical conductor. The receiver takes this composite signal and through the use of a phase lock loop (PLL) separates the four signals back out. ; It is this reconstruction of the clock signal in the PLL that is one source of jitter in the recovered signal. Jitter of the word clock is a source of one form of sonic degrada- tion. Simply stated: the correct signal at the wrong time is the wrong signal. Jitter can cause spurious tones by mixing in a nonlinear fashion with the sample rate which could produce tones in the audio band. This is a form of intermodulation distortion (IMD). Much discus- sion has taken place on the audibility of jitter." 2 + 4 The receiver is implemented in a single LSI chip (U2 of Figure 2). The main function of this chip is to implement the PLL for clock and data recovery. It also strips off the header information and provides a mute signal if an er- ror is detected. A crystal oscillator provides a signal for the PLL to lock onto in the absence of an input. A preamplifier function is provided to amplify the input signal to the TTL levels required by the receiver chip. This function is implemented with a comparator (U1 of Figure 2) rather than the usual CMOS gate as an attempt to minimize the jitter of the signal. ASYNCHRONOUS SAMPLE RATE CONVERSION The next section of the design is the block made up of the AD1891 Asynchronous Sample Rate Converter {ASRC). This block serves two major purposes: it pro- vides for sample rate conversion and also de-jitters the output. The AD1891 was chosen over the AD1890 because we assume that the input data word is a fixed 16-bit length and the sample rate would not be variable short term. The AD1890 allows for variable length and variable rate. There are several standard sample rates in the audio world. The most common is undoubtedly the 44.1 kHz sample rate used by the Compact Disk (CD). Other stan- dards include 48 kHz used in Digital Audio Tape (DAT) and the 32 kHz used in film and direct digital satellite broadcast. The output data rate in this design is set to 48 kHz. This allows a little more room for the transition band of the reconstruction filter. An output rate of 48 kHz allows an input range of 24 kHz to 48 kHz. If the input rate were to be over 48 kHz (the maximum allowable rate is 60 kHz), the AD1891 would adjust the bandwidth of the FIR filters downward to avoid aliasing effects. The AD1891 takes the standard four signal set (data, bit and word clocks, and the L/R signal) from-the AES/EBU receiver as its input. On the output side are a new bit clock, word clock and L/R signals that are generated by a crystal oscillator and a divider string. Note that there is no requirement for the input and output signals to haveany particular phase relationship. They are completely independent. This is also why the sample rate conver- sion process is said to be asynchronous. Note that the only output of the AD1891 is the data out, all other signals are inputs. The process of sample rate conversion is most easily thought of as asynchronous resampling of the data. In this process the input data stream is interpolated to a very high sample rate. The data is then passed througha FIR filter to limit the bandwidth so that the resampling will not produce aliases. The data stream would then be resampled at the output data rate. By using a high effec- tive interpolation rate (65,536) and a high number of taps and filter coefficients (approximately 4 million) in- sures that the distortion in the audio band is kept below the 16-bit level. A visual representation of this process is shown in Figure 3. IN * ANALOG ~%. OUT | LOW-PASS }- | | FILTER A | B c D | E Foyy = 1/71 Fgour = 1/T2 ORIGINAL SIGNAL lt ft tt SAMPLED AT Fay tt FREQ RESPONSE OF LOW-PASS FILTER t SPECTRUM AT LOW-PASS FILTER OUTPUT ft + +f {| SPECTRUM OF Feouy SAMPLING FUNCTION It tt ft tt DO CONVOLVED WITH E Figure 3. Two Samplers with Analog Filter al This model is an oversimplification. If we assume a 48 kSPS sample rate and a 65,536 times oversample rate, the required clock rate would be over 3 GHz, which is beyond the operating frequency of the DSP engine. A more correct model (see Figure 4) is one of a bank of filters with uniform amplitude response and incremen- tally different group delays. Flat amplitude response with a fixed group delay is a characteristic of the all pass filter. Each filter has a different fixed delay. The larger the time difference between input and output samples the shorter the delay added by the filter used (see Figure 5). The group delay of each of these filters is uniform so that the resulting response has the desirable feature of linear phase across the audio band. There are the equivalent of 65,356 of these filters in the AD1891, each with nominaily 64 taps for a total of approximately 4 Meg words of 22 bits of coefficients for the FIR filters. We can therefore model the ASRC as a digital filter where the filter coefficients change on a sample by sample basis. This lowers the required clock rate of the ASRC to the tens of MHz, which is much more practical. For a more complete description of the polyphase model, please refer to the AD1890/AD1891 data sheet and the references in the bibliography. 7 PARALLEL POLYPHASE FILTER BANK POLYPHASE FILTER 1 > POLYPHASE FILTER 2 > POLYPHASE FILTER 3 > POLYPHASE FILTER 4 POLYPHASE FILTER 5 > POLYPHASE FILTER 6 > Not oer POLYPHASE FILTER 7 >| MUX | QUTBUT e e e POLYPHASE FILTER N-1 > POLYPHASE FILTER N | SELECT a SAMPLE CLOCK TRACKING CIRCUIT Figure 4. Polyphase Filter Bank Model-Conceptual Block Diagram I | wh DELAY = NOMINAL u | | | l lo g ~~ ~= { tt T] =| FREQ ~~ Fs LOW Wty IT} ul DELAY = NOMINAL | | 3) ~~ I | zyFAee ~~ HW] DELAY = NOMINAL > _ a | I | WeLow wl _928 Ff, LOW i| T | z FREQ = DELAY = NOMINAL | | | un 05F, LOW ' | 2 > T /FREQ == | DELAY = NOMINAL wh 0.75'F, LOW | 1 g =~ l =| FREQ a Figure 5. Subfilters Realigned with Coarse Time Grid There is an unexpected side benefit from this process. Since the output data rate is determined by an external crystal oscillator, there is a very low jitter in the output clock. The jitter being only the inherent jitter of the oscil- lator and the jitter of the divider string, which will be al- most nonexistent. Of course, to take advantage of this jitter reduction, care must be taken to minimize the amount of circuitry the clocks, especially the word clock, pass through. The word clock is most critical since it controls the updating of the D/A converter. There is also a digital servoing in the clock circuit that reduces jitter of the internal clock. This circuit determines the ratio be- tween the input and output clocks and therefore the ap- propriate set of filter coefficients. The block diagram of the AD1890/AD1891 is shown if Figure 6.BCLK_I WeLKI LRA LRU 1 i VveVvVoV FIFO WRITE DATA! SERIAL DATA GENERATOR FIFO READ ( 2 OO 1 t WCLK_O _ SAMPLE CLOCK RATIO onenator [I | "o | Beto ee SERVO CONTROL LOOP START I | V_V_Vv A ADDRESS I ACCUMULATOR [1 SERIAL DATA Lgepata 0 T T POLEHASESLTER | 1] ouput UNIT - = A I I LAL! LR_O ; Fon) sour) QM ADDRESS | To) COEPRGIENT t t F De ee J F, < FREQUENCY FIR CONVOLVER RESPONSE COMPRESSION A T T LR LR_O Figure 6. AD1890/AD1891 Functional Block Diagram The audio performance of the AD1891 is consistent with 0.0 eo high quality audio reproduction. The passband ripple of the polyphase filters is less than .01 dB. The transition ~20.00 band is 4.1 kHz at a 44.1 kHz sample rate. The stopband 40.00 attenuation is greater than 110 dB. The dynamic range of the filter (referred to full scale using a -60 dB input) is 60.00 96 dB. The THD+N is a minimum of 96 dB below full iz ss scale (108 dB typical at 1 kHz). The amplitude of the 80.00 distortion and noise components scale with input ampli- 100.0 tude, being 20 dB down for an input signal that is 20 dB . down. Typical performance is shown if Figures 7 through 120.0 11 i 9, The internal accumulator is 27 bits, which is important in maintaining the audio performance of the system. ~140.0 20 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 0.0 Ap 20.00 60.00 dBi | -80.00 -100.0 Y -120.0 ., HERI Wh 20.00 1.02 2.02 3.01 4.01 5.01 6.01 7.01 8.00 9.00 10.0 FREQUENCY kHz Figure 7. AD1890/AD1891-5 kHz Tone at 0 dB FS with 100 ns p-p Binomial Jitter on L/R Clocks, Fast Settling Mode, 48 kHz Input Sample Frequency, 44.1 kHz Output Sample Frequency, 16 K-Point FFT, BH4 Window FREQUENCY - Hz Figure 8. AD1891-Twintone, 10 kHz and 11 kHz, 44.1 kHz Input Sample Frequency, 48 kHz Output Sample Frequency, 16 K-Point FFT, BH4 Window $0.00 Ap 91.00 92.00 93.00 94.00 dBFS 95.00 96.00 97.00 98.00 99.00 -100.00 -100 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 ~20.0 -10.0 0.0 AMPLITUDE - dBFS Figure 9. AD1891-THD+N vs. Input Amplitude, 44.1 kHz Input Sample Frequency, 48 kHz Output Sample Frequency, 1 kHz and 20 kHz TonesAD1891 DATAIN 3 DATA DATA_O - DATA OUT BIT CLOCK . SCLK_| SCLK_O 2 BIT CLOCK LEFTRIGHT vu 5] UR uALOT LEFT/RIGHT WORD CLOCK ! t MCLK_I MCLK_O r----_ WORD CLOCK 4 | 10 19 | 2tcrn aD | 2 p PR g/s 77 | BKPOL BKPOL_O 18 eck + a +vLIi] TRGLRI = TRGLR OL yyy I ha 98 cK sg} 2] wseoty1 msapty_o L17 aa cL % MUTE_O . | 74Hc393_s| ira Vv o = MUTE 2h CLOCKS TO PAL Lt # g i % | ache + 10 BaHG 2 | ha oe pa | 0 r a| vanessa | | fctkour I oh vu | OSC 12.288 MHz l Loe _ OUTPUT SAMPLE RATE CLOCK -4--1 MUTE | 2 100k | | ssw I O.1pF | | v I | POWER ON RESET 18 MHz Figure 10. Asynchronous Sample Rate Converter Even though the input data word length is 16 bits, the word length is 32 bit clocks, for a total of 64 bit times for the combined left and right channels. This allows for higher resolution data streams in the AES/EBU interface along with header information such as whether the emphasis is on or off and an indication of the sample rate. The interface between the AES/EBU receiver and the AD1891 is complicated slightly by the fact that the receiver right justifies the data and the AD1891 expects to see left justified data. To get around this, the word clock is used to delay the L/R signal. This delays the L/R signal by 1/4 of the word time which in effect left justifies the data. The schematic for the AD1891 block is shown in Figure 10. INTERPOLATION FILTER it has become accepted procedure in the design of CD players and DAT recorders to use interpolation, which is effectively oversampling the output data. The reason we would want to use oversampling is to increase the transition band and, in turn, reduce the required order, of the output reconstruction filters. There is the added benefit that through the averaging effects of the interpo- lation filter the resolution of the output can be in- creased. In this case we are going to a 20-bit, 4x oversampled system. A 20 MHz ADSP-2115 digital signal processor is used as the DSP engine. A complete schematic is shown in Figure 11. The primary purpose of the DSP engine is to provide the interpolation of the data word to the oversampling rate. It also provide the FIR (Finite Impulse Response) filtering function to band limit the resultant output to 20 kHz. The averaging of the data by the filter also allows us to in- crease the resolution of data stream. An FIR filter is used so that the filter can have a linear phase response. This means that the group delay is uniform across the audio band. This preserves the phase relationship of the audio signal components. A 4x oversample rate was chosen as the highest practi- cal rate. It is desirable to move the sample rate as far out in frequency as possible to reduce the requirements of the analog reconstruction filter. The upper limit is set by the number of instruction cycles between output samples at the 4x rate and the number of taps in the fil- ter. The number of taps in the filter in turn determines the width of the transition band and the minimum stopband attenuation. Several other features were incorporated into the digital filter. First, we provide for digital dither. Dither is adding a low level random signal to the output word. This signal ran- domizes the roundoff error of the digital filter which pro- duces as apparent improvement in low level linearity with a slight decrease in S/N ratio. Subjectively, the in- creased noise level is less objectionable than the har- monic distortion of the roundoff error and therefore is a reasonable tradeoff for the increased linearity. A calibration signal is also provided to facilitate adjust- ment of the low level linearity trim of the AD1862 DAC. This signal is a low level sine wave which allows trim- ming the MSB transition of the AD1862. This also im- proves the low level linearity. Another control line allows for pglarity inversion of the signal. The audibility of absolute polarity is still widely discussed in the audio world. It is especially hard to prove or disprove since little source material is available that takes polarity into account. This function is provided for those instances where it is useful.z Ed? ~ % MP/L ME Stidpl 9 old s Wo a tdt 3S AAPL aL wa 01 s490]9 t Seid. . IL 39079 GYOM 4AHDIH/14371 9019 Lid NI Vivo ab YsHLid i | isis | zs ! ! --_~-4 hse TANVd INOW NO %S MPs ab stave | e z ALIYY10d 43019 Ova HOLlV1 Vd Vive 1437 vivd LHOIW Anos 4G tayLua Oowild {OBViSSL oOultS4y LwTOs: Figure 11. qmoowwor a oua ola osal OSs onToS OL dtlop 2 6 %S MPL NOSE uM za aA Ea au Stlae. ATAt+ SG Siizdsav anovowa cr xmoouwugor q@Noowwgr 40S. ZHWEZ dg)The output of the DSP chip connects to the D/A convert- ers. The data out of the ADSP-2115 is parallel instead of serial due to bandwidth limitations of the serial port. It is much easier for the DSP to work with word lengths that are binary numbers. Therefore, a 20 bit word will be rounded up to 32 bits. Left channel data + right channel data equals 64 bits. At 4x oversampling at 48 kSPS we then need a serial clock of 12.288 MHz. This does not al- low much time for the overhead required to run the se- rial port. Also, we would still have to synchronize the serial port to the operation of the filter since we are out- putting two words. And we need to gate off the clock after the 20th bit so as not to overflow the input shift register of the D/A. We have to count the clock pulses into the D/A converter and limit them to 20 or the MSB will clock past the D/A converters shift register. The counter string also forms the word clock pulse, generat- ing a pulse at the 20th bit. Since the input word is 16 bits at 48 kSPS we use the serial port for the data input. A programmable logic device (PAL) is used to generate all the gating pulses. The PAL programming is available on the Analog Devices BBS (617) 461-4258. THE ANALOG BOARD Digital-to-Analog Conversion The next section of the design is the analog section, which is contained on a separate board. It is comprised of the digital to analog converter (DAC) chip, a de- emphasis circuit, reconstruction filters and output driv- ers. The purpose of the reconstruction filter is to smooth the output of the DAC by band limiting the signal. This turns the stairstep output of the D/A converter to a smoothly varying analog waveform. The D/A converter used is the AD1862. It is a con- ventional multibit 20-bit converter. Although the current trend in consumer audio is toward single bit converters, they dont seem to provide top of the line performance. ' While they have theoretically perfect linearity, they seem to be lacking in noise and_ transient performance. The AD1862 uses a digital offset technique to minimize the nonlinearity at center scale. An adjustment for further optimizing the low level linearity (commonly referred to as the MSB trim) is provided. The I/V converter IC has been set up to allow a variety of op amps. Space for compensation caps and feedback resistors have been provided which allow for just about any single amplifier (with the standard pinout) to be ac- commodated. Suggested op amps are the AD797, AD829 or the AD811. Note that this includes both voltage feedback and current feedback {transimpedance) types. See Figure 12. NOTE: Not all passive components used for all op amps. _7_ ANALOG OUT 1000 T v 82pF =~ 75pF tz by 3.01kO Wy 5 Ui6 ; 50pF i DAC CLOCK CLK AFL onle eH DATA {PATA our 6 DAC LATCH LE t 3 AD1962 2200pF 4 ADS29/797 1 5 OR AD8t11 CBIAS 33pF 2 ==-an g MSBTRM | Qe 100k 464k |3 {14 [13/15 + iIpF ms Figure 12. 464k -12V RECONSTRUCTION FILTER The next amplifier section (see Figure 13) has a dual purpose. First, it provides compensation for the pass- band rolloff of the Bessel or Equiripple reconstruction filter. This is about 1 dB at 20 kHz, assuming a cutoff frequency of 30 kHz. The second is to provide a comple- mentary de-emphasis function for the emphasis which is an option in the CD format. The de-emphasis curve is shown in Figure 14. An LED is provided for indication of the activation of this circuit. 13 SSM2402 EMPHASIS 24.3kQ 220pF 3300pF 1 g ANALOG Ww|t-e of ote enatoa IN 4.64kQ Wy 1 0kQ 10k Wy 1000 AMPLITUDE i = o tg = 15ps FREQUENCY Figure 14. De-Emphasis CurveIt is common practice in most CD systems for the com- plexity of the output filter to be three poles, usually of the Bessel type. While this does a reasonable job of at- tenuating the undesirable spectral components, it does not really go far enough. Let us look at the graphs of attenuation vs. frequency (Figure 15). Using an oversample rate of 4 and a sample rate of 48 kSPS (kilo-samples per second) the DACs data rate is 192 kSPS. If we assume that 30 kHz is the edge of the passband of the filter, this equates to Q of 6.4. We use 30 kHz as the passband edge to minimize the attenu- ation of the filter at 20 kHz and to insure the flat phase response extends well past the audible frequency range. 140 ie vn a w N STOPBAND ATTENUATION - dB n=1 n=310 Ve \eANAGNS WA s \ PASSBAND ATTENUATION - dB N of a 0.2 04 0608 1 2 4 oo Figure 15. Attenuation Characteristics for Maximally Flat Delay (Bessel) Filters (Used with Permission John Wiley & Co.) Since we are trying to develop a high quality system with better than 16 bit performance, the spurs should be attenuated by more than 96 dB. We also want Bessel re- sponse since it has flat group delay, which will insure that we maintain the phase integrity of the signal. The standard three-pole Bessel filter will be in the area of 40 dB45 dB attenuation at 2 of 6.4 (Q = frequency/cutoff frequency). Seven pole Bessel filters will approach 90 dB, eight poles will surpass it. On further investigation we find that an equiripple filter gives almost equivalent performance in the passband but improved attenuation in the stopband. A seventh order Equiripple filter will give us the desired response (see Figure 16). a ua 1 z 9 - < 2 E <{ a? a i z 1 ea a 2 252 5 ae e ae b ae1 aw E <9 0 0.1 0.2 0.4 06 08 1 2 4 6 810 o> Figure 16. Attenuation Characteristics for Linear Phase with Equiripple Error Filter (Phase Error = 0.05) (Used with Permission John Wiley & Co.) Now that we have chosen the type of filter that we are going to build, we must choose the topology of the filter. We choose the FDNR (Frequency Dependent Negative Resistor) topology for several reasons. First, the FDNR has become popular in the audio world because the signal does not pass directly through an op amp. The attractiveness of not passing a signal through an active device is based on the assumption that any active device will distort the signal and, therefore, should be avoided. Secondly, although it does increase the number of com- ponents, the sensitivity of the filter response to the accu- racy of the component value is decreased. The design of the filter section appears in Appendix A. The schematic of the filter section is shown in Figure 17. FILTER IN FILTER Doyy L 210M Figure 17.INPUT 3 aD . PKs of L 2kQ AAA V certe ee a | $100k 1.5mo 1 4 14W 5% > | AD711 2 | | I | | ! The AD712 op amp was chosen for use in this circuit for two reasons. First, since it is a FET input device, its high input impedance will not load down the rest of the circuit. Also the high input impedance means that the input bias currents are low, which will also reduce er- rors. The second reason for using the AD712 is that by virtue of the fact that it is a dual monolithic device the inputs will be inherently well matched, which will im- prove the performance of the circuit. OUTPUT DRIVERS The output of the unit is available as either balanced or single ended signals. The balanced format is preferable in that it minimizes ground loops between stereo com- ponents. It also has the potential of providing a cleaner signal because the signal is not referred to the local ground but to the inverse of itself. Single-ended outputs are provided simply by using only one side of the bal- anced output. Single ended are used simply because the vast majority of audio systems will be set up for this type of output. The output of the driver circuit is shorted to ground by the mute relay at power up and anytime an error is detected by the AES receiver or the sample rate converter. The schematic of the output section is shown in Figure 18. APPENDIX A FILTER DESIGN We choose to use a Bessel type filter for the reconstruc- tion filter because of its superiority in the time domain. As stated earlier we actually use an equiripple filter that has slightly better attenuation but with still good tran- sient response. The price we pay is for slightly greater, although still flat, group delay. Figure 19 compares the Equiripple filter response to Bessel and Butterworth filter responses. The reason we give up the better attenuation of the Butterworth filter types is for the transient performance and flat phase response, as Figure 18. demonstrated by the Impulse and _ step responses. Figures 20 and 21 show the transient response of Equiripple filter compared to Bessel and Butterworth response filters. 0 =<] m ~20 A Zs 1 BUTTERWORTH 2 A 5 BESSEL a 8 EQUIRIPPLE = 60 \ \ . \ \\ -100 100m 300m 1 3 10 FREQUENCY Hz Figure 19. Normalized Filter Comparison Frequency Response 400 BESSEL 300 a7 | EQUIRIPPLE > E | 200 f\ wl 2 BUTTERWORTH 2 @ 100 : \ ~\ -100 0 1.0 2.0 3.0 4.0 5.0 TIME - sec Figure 20. Normalized Filter Comparison Impulse Response12 T T BUTTERWORTH Lo MA BESSEL an, aul 0.2 RESPONSE - V 0 1.0 2.0 3.0 40 5.0 TIME sec Figure 21. Normalized Filter Comparison Step Response We choose the single terminated (Rs = 0) version of the filter rather than the double terminated so that we eliminate a capacitor in the signal path. Going to the charts"' we get the following values: 1.4988 0.8422 0.6441 0.1911 1v T 1.0071 T 0.7421 T 0.4791 ? o ? Figure 22. Normalized Filter Prototype We now perform the transformation by s to transform the filter into the Frequency Dependent Negative Resistor (FDNR) form, , = Sr are => $n te Figure 23. Frequency Dependent Negative Resistor 1/S Impedance Transformation We now must denormalize the filter by frequency and impedance. We have chosen a cutoff frequency of 30 kHz. Therefore we define a frequency scaling factor (FS) of 2 Fe = 1.884 x 10>. Next we choose a normalized capacitor value of 1000 pF. This allows us to then define a impedance normalizing factor of Z=C/{(FS C). All capacitor values are then multiplied by Z x FS. All resis- tors are then multiplied by Z. When calculating the val- ues of the resistors in the filter we find that they do not fall on a standard value. We now modify the center fre- quency to allow for a standard value for the 5.305 kQ resistor that shows up twice in each section. The stan- an dard value is 5.36 kQ. This results in a center frequency of 29.693 kHz. For the rest of the resistor values we par- allel two values to allow us to get an accurate response as possible. The frequency and group delay of the filter are shown in Figure 24 and Figure 25. o -20 \ ~ AMPLITUDE a a i 40 \ wi a z o ; \ iy 60 \ c 80 \ -100 1.0k 3.0k 10k 30k 100k 300k 1M FREQUENCY - Hz Figure 24. Reconstruction Filter 20 . 12 GROUP DELAY \ 4 YS J 1.0k 3.0k 10k 30k 100k 300k 1.0M FREQUENCY ~ Hz DELAY - ps Filter 25. Reconstruction Filter APPENDIX B POWER SUPPLIES One of the most overlooked aspects of audio design is the power supply. It is an essential part of the circuit. If there is noise on the power supplies to an op amp, it will be passed on to the rest of the circuit. All op amps have a power supply rejection ratio (PSRR) specified. Although the PSRR is generally large at low frequency, it falls as the frequency is increased. Therefore, we use de- coupling capacitors to shunt high frequency noise from the circuit. As has been discussed many time in the lit- erature, these decoupling caps must have good high fre- quency performance (low ESR, etc.) and must be located as close to the amplifiers as possible. We also can improve the voltage regulator that we use to provide the power. Standard regulators, such as the LM78XxX series, do a good job of stabilizing the voltage at dc, their output impedance rises with frequency. This is because they are based on an amplifier with limited gain bandwidth product. We can make significant improvements in the performance of the system as awhole by designing a regulator using more modern am- plifiers with higher gain-bandwidth products. The circuit simple amplifies the difference between the reference, which is provided by a Zener diode and its own output, buffered by a pass transistor. A complete schematic of the regulator is provided in Figure 26. In addition high speed soft recovery diodes are used as rectifiers in the power supply. This results in reduced RFI."3 2 al. MJE181 AD847 4+12V AY ' VV + t pa re 46402 AAA Wy Stk Figure 26. Positive Regulator CONCLUSION We have presented a complete, state of the art outboard DAC. Full schematics, copies of the PAL program and copies of the Gerber files for the project are available on the Anaiog Devices DSP BBS (617) 461-4258. -11- BIBLIOGRAPHY 1. 10. 11. 12. 13. 14. 15. 16. 17. Hartley, Robert. The Jitter Game, Stereophile, Janu- ary 1993 Fourre, Remy. Jitter and the Digital Interface, Stereophile, October 1993 . Fourre, Remy. Jitter, Jitter, Jitter. .., Ultra Ana- log Inc. Application Note AP-103 . Adams, Bob. Clock Jitter, D/A Converters, and Sample-Rate Conversion, The Audio Critic Issue No. 21 Adams, Bob. Theory & VLSI Architecture for Asyn- chronous Sample Rate Converters, Journal of the Audio Engineering Society, October 1992 . Wood, Maury. An Integrated Circuit Asynchro- nous Sample Rate Converter for Professional Audio Application, Analog Devices . Adams, Bob. Asynchronous Sample Rate Con- verter, Analog Dialogue, 28-1 . Shandle, Jack. Incompatible Audio Sources Matched by Digital IC, Electronic Design, July 22, 1993 . Johnson, R.C. "The Wood Effect, The Modern Audio Association, 1988 Benjamin, Eric. Effects of DAC Nonlinearity on Re- production of Noise Shaped Signals, AES Preprint 3778 Williams, Arthur. Electronic Filter Design Hand- book, McGraw-Hill, 1981 Giesberts, T. A.F. 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