CY62126DV30 MoBL 1 Mb (64K x 16) Static RAM Features * * * * * * * * Very high speed: 55 and 70 ns Wide voltage range: 2.2V to 3.6V Pin compatible with CY62126BV Ultra-low active power -- Typical active current: 0.85 mA @ f = 1 MHz -- Typical active current: 5 mA @ f = fMAX Ultra-low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected Packages offered in a 48-ball FBGA and a 44-lead TSOP Type II Functional Description[1] The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable (CE) HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable (CE) HIGH, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable (CE) LOW and Write Enable (WE) LOW). Writing to the device is accomplished by taking Chip Enable (CE) LOW and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/Oh A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) LOW and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Logic Block Diagram 64K x 16 RAM Array 2048 x 512 SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 - I/O7 I/O8 - I/O15 A13 BHE WE CE OE BLE A14 A15 A12 A11 COLUMN DECODER Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05230 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised August 29, 2003 CY62126DV30 MoBL Pin Configuration[2,3] FBGA (Top View) 4 5 3 6 A1 A2 NC A A3 A4 CE I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 DNU NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 1 2 BLE OE A0 I/O8 BHE I/O9 NC TSOP II (Forward) Top View H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Notes: 2. 3. NC pins are not connected to the die. E3 (DNU) can be left as NC or Vss to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M). Document #:38-05230 Rev.*C Page 2 of 11 CY62126DV30 MoBL DC Input Voltage[4] ................................ -0.3V to VCC + 0.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA Operating Range Supply Voltage to Ground Potential........................................................... -0.3V to 3.9V DC Voltage Applied to Outputs in High-Z State[4] ....................................-0.3V to VCC + 0.3V Range Ambient Temperature (TA) VCC[5] Industrial -40C to +85C 2.2V to 3.6V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range (V) Product CY62126DV30L f = 1 MHz Min. Typ. Max. Speed (ns) 2.2 3.0 3.6 55/70 0.85 1.5 55/70 0.85 1.5 CY62126DV30LL Typ. [6] f = fMAX Max. Standby, ISB2 (A) Max. Typ.[6] Max. 5 10 1.5 5 5 10 1.5 4 Typ. [6] DC Electrical Characteristics (Over the Operating Range) CY62126DV30-55/70 Parameter Description Test Conditions Min. VOH Output HIGH Voltage 2.2 < VCC < 2.7 IOH = -0.1 mA 2.0 2.7 < VCC < 3.6 IOH = -1.0 mA 2.4 VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 2.7 < VCC < 3.6 IOL = 2.1 mA VIH Input HIGH Voltage 2.2 < VCC < 2.7 VIL Input LOW Voltage IIX Input Leakage Current IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fMAX = 1/tRC ISB1 ISB2 Typ.[6] Max. V 0.4 V 0.4 1.8 VCC + 0.3 2.7 < VCC < 3.6 2.2 VCC + 0.3 2.2 < VCC < 2.7 -0.3 0.6 2.7 < VCC < 3.6 -0.3 0.8 GND < VI < VCC -1 +1 f = 1 MHz Unit -1 Vcc = 3.6V, IOUT = 0 mA, CMOS level V V A +1 A 5 10 mA 0.85 1.5 Automatic CE Power-down Current - CMOS Inputs CE > VCC - 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) L 1.5 5 LL 1.5 4 Automatic CE Power-down Current - CMOS Inputs CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC=3.6V L 1.5 5 LL 1.5 4 A A Notes: 4. VIL(min.) = -2.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.75V for pulse durations less than 20 ns. 5. Full device Operation Requires linear Ramp of Vcc from 0V to Vcc(min) & Vcc must be stable at Vcc(min) for 500 s. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. Document #:38-05230 Rev.*C Page 3 of 11 CY62126DV30 MoBL Capacitance[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ) Max. Unit 8 pF 8 pF Thermal Resistance Parameter Description Test Conditions JA Thermal Resistance (Junction to Ambient)[7] JC Thermal Resistance (Junction to Case)[7] Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board TSOP FBGA Unit 55 76 C/W 12 11 C/W AC Test Loads and Waveforms R1 V CC OUTPUT ALL INPUT PULSES V CC Typ 10% GND R2 C L= 50 pF 90% 10% 90% Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: Fall Time: 1 V/ns TH EVENIN EQUIVALENT R TH OUTPUT Parameters R1 R2 R TH V TH V TH 3.0V (2.7 - 3.6V) 1103 1554 645 1.75 2.5V (2.2 - 2.7V) 16600 15400 8000 1.2 Unit V Data Retention Characteristics Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[7] Chip Deselect to Data Retention Time tR[8] Operation Recovery Time Conditions Min. Typ.[6] Max. 1.5 VCC=1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Unit V L 4 LL 3 A 0 ns 100 s Data Retention Waveform VCC V CC(min.) DATA RETENTION MODE VDR > 1.5V tCDR V CC(min.) tR CE Notes: 7. Tested initially and after any design or proces changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 us. Document #:38-05230 Rev.*C Page 4 of 11 CY62126DV30 MoBL Switching Characteristics (Over the Operating Range)[9] CY62126DV30-55 Parameter Description Min. Max. CY62126DV30-70 Min. Max. Unit Read Cycle tRC Read Cycle Time 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns Z[10] tLZOE OE LOW to Low tHZOE OE HIGH to High Z[10,11] [10] tLZCE CE LOW to Low Z tHZCE CE HIGH to High Z[10,11] tPU CE LOW to Power-up tPD CE HIGH to Power-down tDBE BLE/BHE LOW to Data Valid tLZBE BLE/BHE LOW to Low Z[10] Write 55 10 ns 70 10 5 10 ns 25 10 20 0 25 5 ns ns 70 ns ns 70 5 20 ns 25 0 55 ns ns 5 20 BLE/BHE HIGH to High-Z[10,11] tHZBE 70 ns ns 25 ns Cycle[12] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 40 60 ns tAW Address Set-up to Write End 40 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tBW BLE/BHE LOW to Write End 40 60 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[10,11] tLZWE WE HIGH to Low Z[10] 0 20 10 ns 25 5 ns ns Notes: 9. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signal. Document #:38-05230 Rev.*C Page 5 of 11 CY62126DV30 MoBL Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13,14] t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14,15] ADDRESS t RC CE t ACE OE BHE , BLE t DBE t HZBE t LZBE t HZOE t DOE t LZOE DATA OUT t HZCE HIGH IMPEDANCE DATA VALID t LZCE V CC SUPPLY CURRENT HIGH IMPEDANCE t PD t PU 50% I CC 50% I SB Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #:38-05230 Rev.*C Page 6 of 11 CY62126DV30 MoBL Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [11,12, 16, 17, 18] t WC ADDRESS t SCE CE t AW t HA t SA t PWE WE t BW BHE / BLE OE t SD DATA I/O DATA DON'T CARE t HD IN VALID t HZOE Write Cycle No. 2 (CE Controlled) [11,12, 16, 17, 18] t WC ADDRESS t SCE CE tSA t AW t HA t PWE WE t BW BHE / BLE OE t SD DATA I/O DATA DON'T CARE t HD IN VALID t HZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #:38-05230 Rev.*C Page 7 of 11 CY62126DV30 MoBL Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18] t WC ADDRESS t SCE CE t BW BHE / BLE t AW t HA t SA t PWE WE t HD t SD DATA I/O DATA DON'T CARE IN VALID t LZWE t HZWE Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[17, 18] t WC ADDRESS CE t SCE t AW t HA t BW BHE / BLE t SA t PWE WE t SD DATA I/O DON'T CARE Document #:38-05230 Rev.*C DATA t HD IN VALID Page 8 of 11 CY62126DV30 MoBL Truth Table CE OE WE BLE BHE I/O 0 -I/O 7 I/O 8 - I/O 15 Mode Power H X X X X High Z High Z Power Down L L H L L Data Out Data Out Read All bits Active (I CC ) L L H L H Data Out High Z Read Lower bits only Active (I CC ) L L H H L High Z Data Out Read Upper bits only Active (I CC ) L X L L L Data In Data In Write All bits Active (I CC ) L X L L H Data In High Z Write Lower bits only Active (I CC ) L X L H L High Z Data In Write Upper bits only Active (I CC ) L H H X X High Z High Z Selected, Outputs Disabled Active (I CC ) L X X H H High Z High Z Output Disabled Active (I CC ) Standby (I SB ) Ordering Information Speed (ns) 55 Ordering Code CY62126DV30L-55BVI BV48A CY62126DV30LL-55BVI BV48A CY62126DV30L-55ZI 70 Package Name Package Type 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 44-Lead TSOP Type II 44-Lead TSOP Type II CY62126DV30LL-55ZI Z44 BV48A CY62126DV30LL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62126DV30L-70ZI Z44 44-Lead TSOP Type II CY62126DV30LL-70ZI Z44 44-Lead TSOP Type II Document #:38-05230 Rev.*C Industrial 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Z44 CY62126DV30L-70BVI Operating Range Page 9 of 11 CY62126DV30 MoBL Package Diagrams 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B 44-pin TSOP II Z44 51-85087-*A MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05230 Rev. *C Page 10 of 11 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62126DV30 MoBL Document History Page Document Title: CY62126DV30 MoBL(R) 1 Mb (64K x 16) Static RAM Document Number: 38-05230 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117689 08/27/02 JUI *A 127313 06/13/03 MPR Changed From Advanced Status to Preliminary. Changed Isb2 to 5 uA (L), 4 uA (LL) Changed Iccdr to 4 uA (L), 3 uA (LL) Changed Cin from 6 pF to 8 pF *B 128340 07/22/03 JUI Changed from Preliminary to Final Add 70-ns speed, updated ordering information *C 129002 08/29/03 CDY Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA Document #:38-05230 Rev.*C New Data Sheet Page 11 of 11