VBUS54FD-SD1 www.vishay.com Vishay Semiconductors 4-Line BUS-Port ESD Protection Array - Flow Through Design FEATURES * Compact chip level page CLP1007-5L * Length = 1 mm; width = 0.7 mm; height = 0.27 mm 5 4 * 4-lines, unidirectional ESD protection array 1 1 MM 3 2 p Ty * Low leakage current IR < 0.1 A e * Low capacitance at VR = 0 V = 0.9 pF (typ.) YY * Ideal for high speed data line like - HDMI, DisplayPort, eSATA - USB, 1394/firewire - Thunderbolt 22736 * ESD immunity acc. IEC 61000-4-2 15 kV contact discharge 15 kV air discharge MARKING MM YY * e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) 5F4 * Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 22738 Pin 1 5F4 = type code MM = date code month YY = date code year DESIGN SUPPORT TOOLS click logo to get started Models Available ORDERING INFORMATION DEVICE NAME ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VBUS54FD-SD1 VBUS54FD-SD1-G4-08 10 000 10 000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VBUS54FD-SD1 CLP1007-5L 5F4 0.1 mg MSL level 1 (according J-STD-020) Peak temperature max. 260 C ABSOLUTE MAXIMUM RATINGS (Tamb = 25 C, unless otherwise specified) PARAMETER Peak pulse current Peak pulse power ESD immunity Operating temperature Storage temperature Rev. 1.3, 04-Jan-2019 TEST CONDITIONS SYMBOL VALUE UNIT Acc. IEC 61000-4-5; tP = 8/20 s; single shot IPPM 3 A Acc. IEC 61000-4-5; tP = 8/20 s; single shot PPP 45 W Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature VESD 15 15 kV TJ -40 to +125 C TSTG -55 to +150 C Document Number: 82665 1 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54FD-SD1 www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS (pin 1, 3, 4 or 5 to pin 2) (Tamb = 25 C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 4 lines Max. reverse working voltage VRWM - - 5.5 V Reverse voltage at IR = 0.1 A VR 5.5 - - V Reverse current at VRWM = 5.5 V IR - < 1 nA 0.1 A at IR = 1 mA VBR 6.9 7.5 8.7 V Protection paths Reverse stand-off voltage Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage at IPP = 1 A VC - 9.5 11 V at IPP = IPPM = 3 A VC - 12.9 15 V at IPP = 1 A VF - 1.8 2.2 V at IPP = 3 A VF - 3 4 V - 0.9 1 pF - 0.9 1 pF at VR = 0 V; f = 1 MHz Capacitance at VR = 3.3 V; f = 1 MHz CD Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns, ITLP = 8 A VC-TLP - 18 - V Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns, ITLP = 16 A VC-TLP - 24 - V Transmission Line Pulse (TLP); tp = 100 ns VC-TLP - 0.93 - Dynamic resistance APPLICATION NOTE The VBUS54FD-SD1 is a four-line ESD protection device with the characteristic of a Z-diode with a high ESD immunity and a very low capacitance which makes it usable for high frequency applications like USB 2.0, USB 3.0 or HDMI. With the VBUS54FD-SD1 four high speed data lines can be protected against transient voltage signals like ESD (electro static discharge). Connected to the data line (pin 1, 3 and pin 4, 5) and to ground (pin 2) negative transients will be clamped close below the ground level while positive transients will be clamped close above the 5.5 V working range. The clamping behavior of the VBUS54FD-SD1 is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up to 5.5 V. Pin configuration: * Pin 2 is the central ground pin and has to be connected to ground * Pin 1, 3 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2- 5 4 2 D2- D1- D2+ 4 5 1 1 GND D1+ Receiver 2 3 3 D2- D2+ GND D1- D1+ 22736 Transmitter 22737 FLOW THROUGH DESIGN Modern digital transmission lines can be clocked up to 480 Mbit/s (USB 2.0) or 1.65 Gbit/s (HDMI). At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected to the data lines - like ESD protection devices - have to be connected with minimal changes in these trace dimensions and distances. With the package in the so called "Flow Through Design" this is possible. The lines are running straight along the PCB while the VBUS54FD-SD1 is placed on top without any vias or loops. Rev. 1.3, 04-Jan-2019 Document Number: 82665 2 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54FD-SD1 www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 C, unless otherwise specified) 1000 120 % Rise time = 0.7 ns to 1 ns 80 % 10 IF in mA 100 Discharge Current IESD 100 % 60 % 53 % 1 0.1 40 % 27 % 0.01 20 % 0% -10 0 10 20 30 40 50 60 70 80 90 100 0.001 0 Time (ns) 20557 0.5 1 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 1.5 2 VF in V 22780 Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF 9 8 s to 100 % 100 % 8 7 80 % VR in V 6 IPPM 60 % 20 s to 50 % 5 4 40 % 3 2 20 % 1 0 0.01 0% 0 10 20 30 40 Time (s) 20548 Fig. 2 - 8/20 s Peak Pulse Current Wave Form acc. IEC 61000-4-5 1 10 100 1000 10 000 IR in A Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 1.2 14 f = 1MHz Pin 1, 3, 4 or 5 to Pin 2 12 1.0 Pin 1, 3, 4 or 5 to Pin 2 10 VC in V 0.8 CD in pF 0.1 22781 0.6 8 6 0.4 4 Pin 2 to Pin 1, 3, 4 or 5 0.2 2 0.0 Measured acc. IEC 61000-4-5 (8/20 s - wave form) 0 0 22779 1 2 3 4 5 6 VR in V Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.3, 04-Jan-2019 0 22782 1 2 3 IPP in A Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Document Number: 82665 3 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54FD-SD1 www.vishay.com Vishay Semiconductors 45 TLP: tp = 100 ns 40 VC-TLP in V 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 ITLP in A 22783 Fig. 7 - Typical Clamping Performance at 100 ns Transmission Line Pulse (TLP) PACKAGE DIMENSIONS in millimeters: CLP1007-5L e 1 2 L 5 Package = chip dimensions in mm 3 4 d b A1 A e D MM Type YY E foot print recommendation: Millimeters b 0.25 0.29 - 0.02 0.15 0.13 D 0.68 0.73 E 0.98 1.03 e L Radius e 0.7 A1 max. 0.25 A 0.35 min. 0.155 0.35 0.27 0.23 0.35 0.075 0.03 0.855 Document no.:S8-V-3906.04-041 (4) Created - Date: 11. August 2015 22857 Footprint and soldering recommendation: please see Application Note: www.vishay.com/doc?85917 Rev. 1.3, 04-Jan-2019 Document Number: 82665 4 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VBUS54FD-SD1 www.vishay.com Vishay Semiconductors CARRIER TAPE in millimeters: CLP1007-5L 3.5 0.05 A A-A K0 See note 2 B0 +0.1 0 R 0.1 max. 2 R 0.1 typ. O 0.3 0.1 A A0 (5) 1.5 +0.3 4 2 0.05 8 -0.1 See note 2 1.75 0.1 See note 1 0.2 0.05 A0 = 0.82 0.05 B0 = 1.12 0.05 K0 = 0.40 0.05 Notes: 1. 10 Sprocket hole pitch cumulative tolerance 0.2 2. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole 3. A0 and B0 are calculated on a plane at a distance "R" above the bottom of the pocket Document no.: S8-V-3906.04-042 (3) Created - Date: 23. November 2015 22858 ORIENTATION IN CARRIER TAPE: CLP1007-5L Unreeling direction MM YY MM 5 YY 1 YY MM YY MM 3 Type 4 Type 2 Type Type Top view CLP1007 Pad layout - view from top seen at bottom side Document no.: S8-V-3906.04-043 (4) Created - Date: 17. August 2015 22859 Rev. 1.3, 04-Jan-2019 Document Number: 82665 5 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. (c) 2019 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 01-Jan-2019 1 Document Number: 91000