VBUS54FD-SD1
www.vishay.com Vishay Semiconductors
Rev. 1.3, 04-Jan-2019 1Document Number: 82665
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
4-Line BUS-Port ESD Protection Array - Flow Through Design
MARKING
5F4 = type code
MM = date code month
YY = date code year
DESIGN SUPPORT TOOLS
FEATURES
Compact chip level page CLP1007-5L
Length = 1 mm; width = 0.7 mm; height = 0.27 mm
4-lines, unidirectional ESD protection array
Low leakage current IR < 0.1 μA
Low capacitance at VR = 0 V = 0.9 pF (typ.)
Ideal for high speed data line like
- HDMI, DisplayPort, eSATA
- USB, 1394/firewire
- Thunderbolt
ESD immunity acc. IEC 61000-4-2
± 15 kV contact discharge
± 15 kV air discharge
e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
MM
YY
Type
1
22736
13
2
5 4
Pin 1
22738
MM
YY 5F4
click logo to get started
Available
Models
ORDERING INFORMATION
DEVICE NAME ORDERING CODE TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY
VBUS54FD-SD1 VBUS54FD-SD1-G4-08 10 000 10 000
PACKAGE DATA
DEVICE NAME PACKAGE
NAME
TYPE
CODE WEIGHT MOISTURE SENSITIVITY
LEVEL SOLDERING CONDITIONS
VBUS54FD-SD1 CLP1007-5L 5F4 0.1 mg MSL level 1
(according J-STD-020) Peak temperature max. 260 °C
ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified)
PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT
Peak pulse current Acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 3A
Peak pulse power Acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP 45 W
ESD immunity Contact discharge acc. IEC 61000-4-2; 10 pulses VESD
± 15 kV
Air discharge acc. IEC 61000-4-2; 10 pulses ± 15
Operating temperature Junction temperature TJ-40 to +125 °C
Storage temperature TSTG -55 to +150 °C
VBUS54FD-SD1
www.vishay.com Vishay Semiconductors
Rev. 1.3, 04-Jan-2019 2Document Number: 82665
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATION NOTE
The VBUS54FD-SD1 is a four-line ESD protection device with the characteristic of a Z-diode with a high ESD immunity and a
very low capacitance which makes it usable for high frequency applications like USB 2.0, USB 3.0 or HDMI.
With the VBUS54FD-SD1 four high speed data lines can be protected against transient voltage signals like ESD (electro static
discharge). Connected to the data line (pin 1, 3 and pin 4, 5) and to ground (pin 2) negative transients will be clamped close
below the ground level while positive transients will be clamped close above the 5.5 V working range. The clamping behavior
of the VBUS54FD-SD1 is bidirectional but asymmetrical (BiAs) and so it offers the best protection for applications running up
to 5.5 V.
Pin configuration:
Pin 2 is the central ground pin and has to be connected to ground
Pin 1, 3 and 4, 5 are the inputs for the data lines D1+ and D1- and D2+ and D2-
FLOW THROUGH DESIGN
Modern digital transmission lines can be clocked up to 480 Mbit/s (USB 2.0) or 1.65 Gbit/s (HDMI).
At such high data rates the transmission lines like cables or the line traces on the PCBs have to be very homogeneous regarding
their surge impedance. This requires well defined trace dimensions as trace width and distance which have to be calculated
depending on the requested surge impedance (e.g. 50 ) and the PCB material and layer dimensions. Any device connected
to the data lines - like ESD protection devices - have to be connected with minimal changes in these trace dimensions and
distances.
With the package in the so called “Flow Through Design” this is possible. The lines are running straight along the PCB while the
VBUS54FD-SD1 is placed on top without any vias or loops.
ELECTRICAL CHARACTERISTICS (pin 1, 3, 4 or 5 to pin 2)
(Tamb = 25 °C, unless otherwise specified)
PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT
Protection paths Number of lines which can be protected Nchannel --4lines
Reverse stand-off voltage Max. reverse working voltage VRWM --5.5V
Reverse voltage at IR = 0.1 μA VR5.5 - - V
Reverse current at VRWM = 5.5 V IR- < 1 nA 0.1 μA
Reverse breakdown voltage at IR = 1 mA VBR 6.9 7.5 8.7 V
Reverse clamping voltage at IPP = 1 A VC-9.511V
at IPP = IPPM = 3 A VC- 12.9 15 V
Forward clamping voltage at IPP = 1 A VF-1.82.2V
at IPP = 3 A VF-34V
Capacitance at VR = 0 V; f = 1 MHz CD
-0.91pF
at VR = 3.3 V; f = 1 MHz - 0.9 1 pF
Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns, ITLP = 8 A VC-TLP -18- V
Clamping voltage Transmission Line Pulse (TLP); tp = 100 ns, ITLP = 16 A VC-TLP -24- V
Dynamic resistance Transmission Line Pulse (TLP); tp = 100 ns VC-TLP -0.93-
22736
13
2
5 4
Receiver
Transmitter
D1+
D1-
GND
D2+
D2-
D1+
D1-
GND
D2+
D2-
1
2
3
4
22737
VBUS54FD-SD1
www.vishay.com Vishay Semiconductors
Rev. 1.3, 04-Jan-2019 3Document Number: 82665
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
Fig. 5 - Typical Reverse Voltage VR vs.
Reverse Current IR
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
0 %
20 %
40 %
60 %
80 %
100 %
120 %
-10 0 102030405060708090100
Time (ns)
Discharge Current I
ESD
Rise time = 0.7 ns to 1 ns
53 %
27 %
20557
0 %
20 %
40 %
60 %
80 %
100 %
010203040
Time (µs)
I
PPM
20 µs to 50 %
8 µs to 100 %
20548
C
D
in pF
V
R
in V
22779
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0123456
f = 1MHz
Pin 1, 3, 4 or 5 to Pin 2
0.001
0.01
22780
0.1
1
10
100
1000
0 0.5 1 1.5 2
V
F
in V
I
F
in mA
I
R
in µA
VR in V
0
22781
1
2
3
4
5
6
7
8
9
0.01 0.1 1 10 100 1000 10 000
I
PP
in A
V
C
in V
22782
0
2
4
6
8
10
12
14
0123
Pin 1, 3, 4 or 5 to Pin 2
Pin 2 to Pin 1, 3, 4 or 5
Measured acc. IEC 61000-4-5
(8/20 μs - wave form)
VBUS54FD-SD1
www.vishay.com Vishay Semiconductors
Rev. 1.3, 04-Jan-2019 4Document Number: 82665
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Clamping Performance at 100 ns
Transmission Line Pulse (TLP)
PACKAGE DIMENSIONS in millimeters: CLP1007-5L
Footprint and soldering recommendation:
please see Application Note: www.vishay.com/doc?85917
ITLP in A
VC-TLP in V
22783
0
5
10
15
20
25
30
35
40
45
0 5 10 15 20 25 30
TLP: tp = 100 ns
foot print recommendation:
Document no.:S8-V-3906.04-041 (4)
Package = chip dimensions in mm
Created - Date: 11. August 2015
be
123
45
e
E
d
L
D
A
A1
Type
MM
YY
Millimeters
A
A1
b
D
E
Radius
L
min. max.
0.25
0.68
0.98
0.23
0.29
0.15
0.73
1.03
0.075
e0.03
0.35
0.35
0.155
0.855
0.7
0.25
0.27
-0.02
0.13
e 0.35
22857
VBUS54FD-SD1
www.vishay.com Vishay Semiconductors
Rev. 1.3, 04-Jan-2019 5Document Number: 82665
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
CARRIER TAPE in millimeters: CLP1007-5L
ORIENTATION IN CARRIER TAPE: CLP1007-5L
See note 1
See note 2
2 ± 0.05 1.5 +0.1
0
8+0.3
-0.1
1.75 ± 0.13.5 ± 0.05
Ø 0.3 ± 0.1 0.2 ± 0.05
A0
A0 = 0.82 ± 0.05
B0 = 1.12 ± 0.05
K0 = 0.40 ± 0.05
B0
K0
R 0.1 max.
See note 2
R 0.1 typ.2
4
(5°)
A - A
A
A
Notes:
1. 10 Sprocket hole pitch cumulative tolerance ± 0.2
2. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
3. A0 and B0 are calculated on a plane at a distance “R”
above the bottom of the pocket
Document no.: S8-V-3906.04-042 (3)
Created - Date: 23. November 2015
22858
Unreeling direction
Top view Pad layout - view from top
seen at bottom side
CLP1007
Document no.: S8-V-3906.04-043 (4)
Created - Date: 17. August 2015
22859
MM
YY Type
MM
YY Type
MM
YY Type
MM
YY Type
123
45
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 01-Jan-2019 1Document Number: 91000
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