SN54LV00, SN74LV00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) 2-µ Process
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
D
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
These quadruple 2-input positive-NAND gates
are designed for 2.7-V to 5.5-V VCC operation.
The ’LV00 perform the Boolean function
Y = A • B or Y = A + B in positive logic.
The SN74LV00 is available in TI’s shrink
small-outline package (DB), which provides the
same I/O pin count and functionality of standard
small-outline packages in less than half the
printed-circuit-board area.
The SN54LV00 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV00 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H H L
LXH
X L H
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
SN54LV00 ...J OR W PACKAGE
SN74LV00 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
SN54LV00 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
3Y
3A V
4B
2Y
GND
NC
NC – No internal connection
CC
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV00, SN74LV00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†logic diagram, each gate (positive logic)
1
1A 2
1B 1Y
3
4
2A 5
2B 2Y
6
9
3A 10
3B 3Y
8
12
4A 13
4B 4Y
11
&A
BY
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for D, DB, J, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3):D package 1.25 W. . . . . . . . . . . . . . . . . . .
DB or PW package 0.5 W. . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
SN54LV00, SN74LV00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LV00 SN74LV00
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 5.5 2.7 5.5 V
VIH
High level in
p
ut voltage
VCC = 2.7 V to 3.6 V 2 2
V
V
IH
High
-
le
v
el
inp
u
t
v
oltage
VCC = 4.5 V to 5.5 V 3.15 3.15
V
VIL
Low level in
p
ut voltage
VCC = 2.7 V to 3.6 V 0.8 0.8
V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
VCC = 4.5 V to 5.5 V 1.65 1.65
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
IOH
High level out
p
ut current
VCC = 2.7 V to 3.6 V –6 –6
mA
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 4.5 V to 5.5 V –12 –12
mA
IOL
Low level out
p
ut current
VCC = 2.7 V to 3.6 V 6 6
mA
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 4.5 V to 5.5 V 12 12
mA
∆t/∆vInput transition rise or fall rate 0 100 0 100 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC†
SN54LV00 SN74LV00
UNIT
PARAMETER
TEST
CONDITIONS
V
CC
†
MIN TYP MAX MIN TYP MAX
UNIT
IOH = –100 µAMIN to MAX VCC – 0.2 VCC – 0.2
VOH IOH = –6 mA 3 V 2.4 2.4 V
IOH = –12 mA 4.5 V 3.6 3.6
IOL = 100 µAMIN to MAX 0.2 0.2
VOL IOL = 6 mA 3 V 0.4 0.4 V
IOL = 12 mA 4.5 V 0.55 0.55
II
VI=V
CC or GND
3.6 V ±1±1
µA
I
I
V
I =
V
CC
or
GND
5.5 V ±1±1µ
A
ICC
VI=V
CC or GND
IO=0
3.6 V 20 20
µA
I
CC
V
I =
V
CC
or
GND
I
O =
0
5.5 V 20 20 µ
A
n
ICC One input at
VCC – 0.6 V Other inputs at
VCC or GND 3 V to 3.6 V 500 500 µA
Ci
VI=V
CC or GND
3.3 V 2.5 2.5 p
F
C
i
V
I =
V
CC
or
GND
5 V 1.5 1.5
pF
†For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN54LV00
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN TYP MAX MIN MAX
tpd A Y 6 11 9 15 18 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV00, SN74LV00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
TO
SN74LV00
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN TYP MAX MIN MAX
tpd A Y 6 11 9 15 18 ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cd
p
p
p
CL=50
p
F
f=10MHz
3.3 V 23 p
F
C
pd
w
C
L =
50
pF
,
f
=
10
MH
z5 V 23
pF
SN54LV00, SN74LV00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Vm
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 VzOpen
GND
1 kΩ
1 kΩ
Data Input
Timing Input Vm
Vi
0 V
VmVm
Vi
0 V
Vi
0 V
VmVm
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VmVm
Vi
0 V
Vm
Vm
Input
Vm
Output
Control
Output
W aveform 1
S1 at Vz
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
Vm
Vm
0.5 × Vz
0 V
VmVOL + 0.3 V
VmVOH – 0.3 V
[
0 V
Vi
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
TEST S1
0.5 ×VCC
VCC
2 ×VCC
1.5 V
2.7 V
6 V
WAVEFORM
CONDITION VCC = 4.5 V
to 5.5 V VCC = 2.7 V
to 3.6 V
Vm
Vi
Vz
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV00D OBSOLETE SOIC D 14 TBD Call TI Call TI
SN74LV00DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74LV00DR OBSOLETE SOIC D 14 TBD Call TI Call TI
SN74LV00PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
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